A Crosstalk Suppression Circuit, Method and Device for a Field Effect Transistor

Abstract

An embodiment of the present application provides a crosstalk suppression circuit, method and device for a field effect transistor. The crosstalk suppression circuit includes a suppression module and an auxiliary capacitor. The suppression module and the auxiliary capacitor are connected in parallel between the gate and the source of the field effect transistor. Among them, the suppression module is configured to receive a first driving signal and control the conduction state of the suppression module according to the first driving signal, so as to control the access time of the auxiliary capacitor connected in parallel between the gate and the source of the field effect transistor. In this way, based on the suppression module, the auxiliary capacitor can be connected between the gate and the source of the field effect transistor before crosstalk occurs in the field effect transistor, so that the crosstalk phenomenon generated between the field effect transistors can be suppressed, and the risk of mis-turn-on or device damage of the field effect transistor is reduced.

Description

Technical Field

[0001] This application relates to the field of electronic circuit technologies, and in particular, to a crosstalk suppression circuit, method, and device for a field effect transistor. Background Art

[0002] Silicon carbide metal-oxide-semiconductor field effect transistors (MOSFETs) (hereinafter simply referred to as: field effect transistors) have high switching speeds, high operating frequencies, low on-resistance, and smaller volumes, and thus become ideal switches for high-frequency, high-power density, and high-efficiency power electronic converters, and are increasingly applied to mid- to high-end converters.

[0003] In related technologies, compared with traditional insulated gate bipolar transistors (IGBTs) or silicon-based devices, the crosstalk phenomenon of silicon carbide MOSFETs is more serious. When the state of a field effect transistor changes (for example, from an off state to an on state or from an on state to an off state), the field effect transistor bridged thereto may experience a crosstalk phenomenon, which may further lead to the risk of mis-turn-on of the field effect transistor or device damage. Summary of the Invention

[0004] Embodiments of this application provide a crosstalk suppression circuit, method, and device for a field effect transistor, which can control the access timing of an auxiliary capacitor before crosstalk occurs, thereby suppressing the crosstalk phenomenon generated between field effect transistors due to state changes.

[0005] The technical solution of the embodiments of this application is implemented as follows:

[0006] In a first aspect, embodiments of this application provide a crosstalk suppression circuit for a field effect transistor. The crosstalk suppression circuit includes a suppression module and an auxiliary capacitor, and the suppression module and the auxiliary capacitor are connected in parallel between the gate and source of the field effect transistor; wherein,

[0007] The suppression module is configured to receive a first drive signal, control the conduction state of the suppression module according to the first drive signal, so as to control the access time when the auxiliary capacitor is connected in parallel between the gate and source of the field effect transistor; wherein, the access time is earlier than the crosstalk current generation time of the field effect transistor.

[0008] In some embodiments, the suppression module includes a first auxiliary module and a second auxiliary module; wherein,

[0009] The first auxiliary module is configured to receive the first drive signal, perform drive reverse processing according to the first drive signal, and generate a second drive signal;

[0010] The second auxiliary module is configured to receive the second driving signal and control the conduction state of the second auxiliary module according to the second driving signal, so as to control the access time when the auxiliary capacitor is connected in parallel between the gate and the source of the field effect transistor.

[0011] In some embodiments, the first auxiliary module includes a first auxiliary switch tube and a first driving resistor, and the second auxiliary module includes a second auxiliary switch tube and a second driving resistor; wherein,

[0012] The gate of the first auxiliary switch tube is connected to the first driving resistor for receiving the first driving signal; the drain of the first auxiliary switch tube and one end of the second driving resistor are both connected to a first connection point, the other end of the second driving resistor is connected to the gate of the second auxiliary switch tube, and the first connection point is used for outputting the second driving signal;

[0013] The source of the first auxiliary switch tube and the source of the second auxiliary switch tube are both connected to the source of the field effect transistor;

[0014] The drain of the second auxiliary switch tube is connected to one end of the auxiliary capacitor, and the other end of the auxiliary capacitor is connected to the gate of the field effect transistor.

[0015] In some embodiments, the suppression module further includes a delay module, and the delay module is connected to the connection point of the first auxiliary module and the second auxiliary module; wherein,

[0016] The delay module is configured to perform a delay process on the second driving signal, so as to control the access time when the auxiliary capacitor is connected in parallel between the gate and the source of the field effect transistor.

[0017] In some embodiments, the delay module includes a delay resistor and a delay capacitor; wherein,

[0018] One end of the delay resistor is connected to a power supply, one end of the delay capacitor is connected to the source of the field effect transistor, and the other end of the delay resistor and the other end of the delay capacitor are both connected to the first connection point.

[0019] In some embodiments, the suppression module is configured to, when the level of the first driving signal changes from a second level to a first level, turn off the first auxiliary switch tube, charge the delay capacitor through the power supply and the delay resistor, so that the level of the second driving signal changes from the first level to the second level; or, when the level of the first driving signal changes from the first level to the second level state, turn on the first auxiliary switch tube, discharge through the delay capacitor, so that the level of the first driving signal changes from the second level to the first level;

[0020] The suppression module is further configured to, when the level of the second driving signal changes from the first level to the second level, turn on the second auxiliary switch tube, so that the auxiliary capacitor is connected between the gate and the source of the field effect transistor; or, when the level of the second driving signal changes from the second level to the first level, turn off the second auxiliary switch tube, so that the auxiliary capacitor is not connected between the gate and the source of the field effect transistor.

[0021] In some embodiments, the first level is a low level and the second level is a high level.

[0022] In some embodiments, the crosstalk suppression circuit further includes a first driving module; wherein,

[0023] The first driving module is configured to receive an initial driving signal, perform driving control on the initial driving signal, and generate a target driving signal; wherein, the target driving signal is used to control the conduction and turn-off of the field effect transistor.

[0024] In some embodiments, the first driving signal is the same as the initial driving signal.

[0025] In some embodiments, the first driving signal is different from the initial driving signal, and the crosstalk suppression circuit further includes a second driving module; wherein,

[0026] The second driving module is configured to generate the first driving signal.

[0027] In a second aspect, an embodiment of the present application provides a bridge arm driving circuit, which includes a bridge arm module and at least one crosstalk suppression circuit according to any one of the first aspect.

[0028] In some embodiments, the bridge arm module includes a first field effect transistor and a second field effect transistor, and the number of the crosstalk suppression circuits is two; wherein,

[0029] The first crosstalk suppression circuit includes a first suppression module and a first auxiliary capacitor, and is configured to control the conduction state of the first suppression module to control the access time when the first auxiliary capacitor is connected in parallel between the gate and the source of the first field-effect transistor earlier than the crosstalk current generation time of the first field-effect transistor, where the crosstalk current is generated when the second field-effect transistor is turned on;

[0030] The second crosstalk suppression circuit includes a second suppression module and a second auxiliary capacitor, and is configured to control the conduction state of the second suppression module to control the access time when the second auxiliary capacitor is connected in parallel between the gate and the source of the second field-effect transistor earlier than the crosstalk current generation time of the second field-effect transistor, where the crosstalk current is generated when the first field-effect transistor is turned on.

[0031] In some embodiments, the first crosstalk suppression circuit is further configured to control the conduction state of the first suppression module to control the first auxiliary capacitor to be connected between the gate and the source of the first field-effect transistor before the second field-effect transistor is turned on;

[0032] The second crosstalk suppression circuit is further configured to control the conduction state of the second suppression module to control the second auxiliary capacitor to be connected between the gate and the source of the second field-effect transistor before the first field-effect transistor is turned on.

[0033] In a third aspect, an embodiment of the present application provides a method for suppressing crosstalk of a field-effect transistor, the method including:

[0034] Receiving a first drive signal;

[0035] Controlling the conduction state of the suppression module according to the first drive signal to control the access time when the auxiliary capacitor is connected in parallel between the gate and the source of the field-effect transistor; where the access time is earlier than the crosstalk current generation time of the field-effect transistor.

[0036] In a fourth aspect, an embodiment of the present application provides an electronic device, and the electronic device at least includes the bridge arm drive circuit according to any one of the second aspect.

[0037] The embodiments of the present application provide a crosstalk suppression circuit, method and device for a field effect transistor. The crosstalk suppression circuit includes a suppression module and an auxiliary capacitor. The suppression module and the auxiliary capacitor are connected in parallel between the gate and the source of the field effect transistor. Among them, the suppression module is configured to receive a first driving signal and control the conduction state of the suppression module according to the first driving signal, so as to control the access time of the auxiliary capacitor connected in parallel between the gate and the source of the field effect transistor. In this way, the auxiliary capacitor is connected between the gate and the source of the field effect transistor through the suppression module to achieve the crosstalk suppression effect. Moreover, the access time of the auxiliary capacitor connected between the gate and the source of the field effect transistor can be controlled, so that the auxiliary capacitor is connected between the gate and the source of the field effect transistor before crosstalk occurs, thereby being able to better suppress the crosstalk phenomenon generated between field effect transistors, not only without affecting the switching speed of the field effect transistor, but also reducing the risk of mis-turn-on or device damage of the field effect transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 FIG. is a schematic circuit diagram of a field effect transistor bridge connection structure provided by the related art;

[0039] Figure 2 FIG. is a waveform diagram of a field effect transistor bridge connection structure provided by the related art during the turn-on process of the bridge connection circuit;

[0040] Figure 3 FIG. is a waveform diagram of a field effect transistor bridge connection structure provided by the related art during the turn-off process of the bridge connection circuit;

[0041] Figure 4 FIG. is a schematic circuit diagram of a circuit for suppressing crosstalk between field effect transistors provided by the related art;

[0042] Figure 5 FIG. is a schematic circuit diagram of another circuit for suppressing crosstalk between field effect transistors provided by the related art;

[0043] Figure 6 FIG. is a schematic circuit diagram of yet another circuit for suppressing crosstalk between field effect transistors provided by the related art;

[0044] Figure 7 FIG. is a schematic circuit diagram of still another circuit for suppressing crosstalk between field effect transistors provided by the related art;

[0045] Figure 8 FIG. is a schematic structural diagram of a crosstalk suppression circuit for a field effect transistor provided by an embodiment of the present application;

[0046] Figure 9 FIG. is a schematic structural diagram of another crosstalk suppression circuit for a field effect transistor provided by an embodiment of the present application;

[0047] Figure 10Schematic diagram of another crosstalk suppression circuit for a field effect transistor provided by an embodiment of the present application;

[0048] Figure 11 Schematic diagram of a leg drive circuit provided by an embodiment of the present application;

[0049] Figure 12 Flow chart of a crosstalk suppression method for a field effect transistor provided by an embodiment of the present application;

[0050] Figure 13 Schematic diagram of the specific structure of a leg drive circuit provided by an embodiment of the present application;

[0051] Figure 14 Schematic diagram of the specific structure of another leg drive circuit provided by an embodiment of the present application;

[0052] Figure 15 Schematic diagram of the change curve of voltages at different positions in a leg drive circuit provided by an embodiment of the present application;

[0053] Figure 16 Schematic diagram of the specific structure of another leg drive circuit provided by an embodiment of the present application;

[0054] Figure 17 Schematic diagram of the change curves of drain-source voltage and gate-source voltage of a non-clamped circuit provided by the related art;

[0055] Figure 18 Schematic diagram of the change curves of drain-source voltage and gate-source voltage in a leg drive circuit with a clamping circuit provided by an embodiment of the present application;

[0056] Figure 19a Schematic diagram of the vds change curve when the non-clamped circuit is turned off provided by the related art;

[0057] Figure 19b Schematic diagram of the id change curve when the non-clamped circuit is turned off provided by the related art;

[0058] Figure 20a Schematic diagram of the vds change curve when the clamping circuit is turned off provided by an embodiment of the present application;

[0059] Figure 20b Schematic diagram of the id change curve when the clamping circuit is turned off provided by an embodiment of the present application;

[0060] Figure 21a Schematic diagram of the vds change curve when the non-clamped circuit is turned on provided by the related art;

[0061] Figure 21b Schematic diagram of the id change curve when the non-clamped circuit is turned on provided by the related art;

[0062] Figure 22a It is a schematic diagram of the vds change curve when the clamping circuit is turned on provided by the embodiment of the present application;

[0063] Figure 22b It is a schematic diagram of the id change curve when the clamping circuit is turned on provided by the embodiment of the present application;

[0064] Figure 23 It is a schematic diagram of the composition structure of an electronic device provided by the embodiment of the present application. Detailed implementation manners

[0065] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. It can be understood that the specific embodiments described herein are only used to explain the related application, rather than limiting the application. In addition, it should be noted that, for the sake of convenience of description, only the parts related to the related application are shown in the drawings.

[0066] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0067] In the following description, "some embodiments" are involved, which describe a subset of all possible embodiments. However, it can be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments, and can be combined with each other without conflict.

[0068] It should be noted that the terms "first / second / third" involved in the embodiments of the present application are only used to distinguish similar objects and do not represent a specific order for the objects. It can be understood that "first / second / third" can be interchanged with a specific order or sequence when permitted, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.

[0069] It can be understood that due to the characteristics of fast switching speed and low loss of silicon carbide MOSFETs, they are used more and more in power electronic circuits. However, compared with traditional IGBTs or silicon-based MOSFETs, the crosstalk phenomenon of silicon carbide MOSFETs has become obvious. Especially for silicon carbide MOSFETs connected in a bridge structure, due to the very fast turn-on speed of silicon carbide MOSFETs, the rate of change of the drain-source voltage dv / dt is very large. The crosstalk problem is more difficult to solve compared with traditional silicon-based devices.

[0070] See Figure 1 , which shows a schematic diagram of the circuit structure of a field-effect transistor bridge connection structure, asFigure 1 As shown, it shows a basic circuit in which the upper transistor and the lower transistor are connected through a bridge structure. Among them, Q1 is the upper transistor, Q2 is the lower transistor, Cgd1, Cgs1, and Cds1 are the self-parasitic capacitances of Q1; Cgd2, Cgs2, and Cds2 are the self-parasitic capacitances of Q2.

[0071] See Figure 2 , which shows a waveform diagram during the conduction process of the field effect transistor in the bridge connection circuit based on Figure 1 . See Figure 3 , which shows a waveform diagram during the turn-off process of the field effect transistor in the bridge connection circuit based on Figure 1 . Among them, Vgs1 is the gate-source drive voltage of the upper transistor, Vds1 is the drain-source voltage of the upper transistor, Vgs2 is the gate-source drive voltage of the lower transistor, and Vds2 is the drain-source voltage of the lower transistor.

[0072] Specifically, combining the waveform comparison in Figure 2 and Figure 3 , when the lower transistor is in the off state, if the arm current is outward, that is, the current flows through the body diode of the lower transistor, at this time, Vds of the lower transistor is approximately 0, and Vds of the upper transistor is approximately Vdc. If the upper transistor changes from the off state to the on state, the current will commutate from the lower transistor to the upper transistor, the Vds voltage of the lower transistor will quickly rise to Vdc, and the Vds voltage of the upper transistor will drop to 0. Since the turn-on speed of the silicon carbide MOSFET is very fast, the voltage rise rate dv / dt is very large. This dv / dt will generate a current from the drain (D) to the gate (G) in the parasitic capacitance Cgd of the lower transistor. This current will charge Cgd and raise its voltage. The flow path of this current is either through the parasitic capacitance Cgs or through the drive loop. The part of this current passing through Cgs will charge Cgs and cause the Vgs voltage to rise. Therefore, even when the lower transistor is in the off state, the Vgs voltage will also rise. If the rise of Vgs exceeds the threshold voltage Vth, it will cause the lower transistor to mis-turn on, and then lead to arm breakdown. When the lower transistor is in the off state and the upper transistor is in the on state, Vds of the lower transistor is approximately Vdc, and Vds of the upper transistor is approximately 0. If the arm current direction is outward at this time, when the upper transistor turns off, the Vds of the upper transistor will quickly change from 0 to Vdc, and the Vds of the lower transistor will quickly change from Vdc to 0. This voltage change will also generate a very high dv / dt, generating a current that discharges through the Cgd of the lower transistor. The part of this current flowing through the Cgs of the lower transistor will cause the Vgs to drop. If the drop amplitude is too large, the Vgs voltage will be lower than the minimum voltage allowed by the device, resulting in device damage.

[0073] In the related art, there are several solutions to solve the crosstalk problem between field effect transistors as follows:

[0074] Exemplarily, see Figure 4, a capacitor C1 is connected in parallel between the gate and the source (gs). With the crosstalk current remaining unchanged, the dv / dt is reduced by increasing the gate capacitance, thereby achieving the effect of reducing voltage variation. This method has a good effect on crosstalk suppression. However, the additional parallel capacitor will slow down the switching speed, thus increasing the switching loss of the silicon carbide MOSFET, which is contrary to the original intention of using the silicon carbide MOSFET.

[0075] Exemplarily, refer to Figure 5 , a switching device is connected in parallel between the gate and the source to implement Miller clamping. When the device is turned off, this auxiliary transistor is always in the conducting state through an additional Vmiller driving signal, thereby pulling down the voltage between the gate and s1 (s), playing a clamping role. This switching device can be a PNP or NPN bipolar transistor, a P-type MOSFET, or an N-type MOSFET. However, due to the existence of the parasitic capacitance of the device itself, the clamping effect is not obvious, and this switching device requires an additional driving signal for driving, making the implementation relatively cumbersome.

[0076] Exemplarily, refer to Figure 6 and Figure 7 , a PNP bipolar transistor and a capacitor are connected in series between the gates to suppress crosstalk. When crosstalk occurs, since current flows through the driving loop (as shown by the dotted line in Figure 7 ), a voltage drop is generated between the emitter and the base of the auxiliary bipolar transistor. When this voltage exceeds the turn-on voltage of the bipolar transistor, the bipolar transistor conducts and connects the capacitor into the driving loop. The advantage of this method is that the capacitor is only connected into the circuit after crosstalk occurs, which will not affect the switching speed of the silicon carbide MOSFET and will not increase the loss.

[0077] In these above-mentioned schemes, the additional capacitor in the driving loop will cause the turn-on and turn-off times to become longer, resulting in an impact on the switching speed and an increase in the switching loss. The parasitic parameters of the auxiliary switching device itself will lead to a poor actual crosstalk suppression effect. The auxiliary switching device requires an additional driving signal to conduct, additionally increasing the complexity of the circuit. On the other hand, the auxiliary capacitor will only be connected into the circuit to play a crosstalk suppression effect after crosstalk has occurred and the gate voltage has risen to a certain level. During the dynamic process, the gate voltage will oscillate, and the bipolar transistor will turn off during the oscillation process, unable to play a role in suppressing crosstalk.

[0078] Based on this, an embodiment of the present application provides a crosstalk suppression circuit, method, and device for a field effect transistor. The crosstalk suppression circuit includes a suppression module and an auxiliary capacitor, and the suppression module and the auxiliary capacitor are connected in parallel between the gate and the source of the field effect transistor. Among them, the suppression module is configured to receive a first driving signal and control the conduction state of the suppression module according to the first driving signal to control the access time when the auxiliary capacitor is connected in parallel between the gate and the source of the field effect transistor. In this way, the auxiliary capacitor is connected between the gate and the source of the field effect transistor through the suppression module to achieve the crosstalk suppression effect. Moreover, the access time when the auxiliary capacitor is connected between the gate and the source of the field effect transistor can be controlled, so that the auxiliary capacitor is connected between the gate and the source of the field effect transistor before crosstalk occurs, thereby being able to better suppress the crosstalk phenomenon generated between field effect transistors, not only not affecting the switching speed of the field effect transistor, but also reducing the risk of mis-turn-on or device damage of the field effect transistor.

[0079] The following will further describe the embodiments of the present application in detail with reference to the accompanying drawings and specific embodiments.

[0080] In an embodiment of the present application, refer to Figure 8 , which shows a schematic structural diagram of a crosstalk suppression circuit for a field effect transistor provided by an embodiment of the present application. As Figure 8 shown, the crosstalk suppression circuit 80 may include a suppression module 801 and an auxiliary capacitor 802. Among them, the suppression module 801 and the auxiliary capacitor 802 are connected in parallel between the gate and the source of the field effect transistor. Among them,

[0081] The suppression module 801 is configured to receive a first driving signal and control the conduction state of the suppression module according to the first driving signal to control the access time when the auxiliary capacitor is connected in parallel between the gate and the source of the field effect transistor. Among them, the access time is earlier than the crosstalk current generation time of the field effect transistor.

[0082] It should be noted that the crosstalk suppression circuit provided by the embodiment of the present application can be applied to a bridge arm driving circuit, or can be applied to an electronic device integrated with this circuit or having a crosstalk suppression requirement. Here, the electronic device may be integrated with a Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) / Junction Field-effect Transistor (JFET) / Insulated Gate Bipolar Translator (IGBT) or other controllable switching tubes, which is not specifically limited here.

[0083] It should also be noted that a crosstalk suppression circuit 40 of a field effect transistor provided by an embodiment of the present application can be a part of a leg drive circuit. The crosstalk suppression circuit 40 is used to connect an auxiliary capacitor between the gate and the source of the field effect transistor in the leg drive circuit before crosstalk occurs in the field effect transistor, so as to improve the crosstalk problem of the field effect transistor in the leg drive circuit.

[0084] In some embodiments, the suppression module includes a first auxiliary module and a second auxiliary module; wherein,

[0085] The first auxiliary module is configured to receive the first drive signal, perform drive reverse processing according to the first drive signal, and generate a second drive signal;

[0086] The second auxiliary module is configured to receive the second drive signal, control the conduction state of the second auxiliary module according to the second drive signal, so as to control the access time when the auxiliary capacitor is connected in parallel between the gate and the source of the field effect transistor.

[0087] It should be noted that the first drive signal is used to drive the field effect transistor to turn on or off. The first auxiliary module reverses the direction of the first drive signal, so that the direction of the second drive signal is opposite to that of the first drive signal. In this way, when the state of the field effect transistor changes, the crosstalk suppression circuit does not take effect. When crosstalk occurs in the field effect transistor, the crosstalk suppression circuit takes effect, and the auxiliary capacitor is connected in parallel between the gate and the source of the field effect transistor, so as to suppress the crosstalk phenomenon and ensure the safe operation of the device.

[0088] It should also be noted that when the second auxiliary module is turned on, the auxiliary capacitor is connected in parallel between the gate and the source of the field effect transistor to suppress the crosstalk phenomenon. When the second auxiliary module is turned off, the auxiliary capacitor is open-circuited and cannot be connected in parallel between the gate and the source of the field effect transistor, so the suppression effect on crosstalk is invalid.

[0089] In some embodiments, the first auxiliary module includes a first auxiliary switch tube and a first drive resistor, and the second auxiliary module includes a second auxiliary switch tube and a second drive resistor; wherein,

[0090] The gate of the first auxiliary switch tube is connected to the first drive resistor for receiving the first drive signal; the drain of the first auxiliary switch tube and one end of the second drive resistor are both connected to a first connection point, and the other end of the second drive resistor is connected to the gate of the second auxiliary switch tube, and the first connection point is used to output the second drive signal;

[0091] The source of the first auxiliary switch tube and the source of the second auxiliary switch tube are both connected to the source of the field effect transistor;

[0092] The drain of the second auxiliary switching transistor is connected to one end of the auxiliary capacitor, and the other end of the auxiliary capacitor is connected to the gate of the field effect transistor.

[0093] It should be noted that the first auxiliary switching transistor and the second auxiliary switching transistor can be MOSFETs, bipolar junction transistors (BJTs), JFETs, IGBTs. The first auxiliary switching transistor and the first driving resistor are combined to reverse-process the first driving signal, and the second auxiliary switching transistor and the second driving resistor are combined to control the connection and disconnection of the auxiliary capacitor according to the second driving signal.

[0094] In some embodiments, the suppression module further includes a delay module, and the delay module is connected to the connection point between the first auxiliary module and the second auxiliary module; wherein,

[0095] The delay module is used to perform a delay process on the second driving signal to control the access time when the auxiliary capacitor is connected in parallel between the gate and the source of the field effect transistor.

[0096] It should be noted that the delay module is used to delay the time when the second driving signal is transmitted from the first auxiliary module to the second auxiliary module. During the process of crosstalk generated by the turn-on or turn-off of other field effect transistors, the transmission of crosstalk requires a certain amount of time. The delay module can delay the effective time of the second driving signal according to actual requirements, so that the auxiliary capacitor can be connected in parallel between the gate and the source of the field effect transistor at an appropriate time. The auxiliary capacitor can be connected between the gate and the source of the field effect transistor before the crosstalk causes the transistor to turn on, and the switching transistor will not turn off during the crosstalk process, and the capacitor always plays a role in suppression.

[0097] In some embodiments, the delay module includes a delay resistor and a delay capacitor; wherein,

[0098] One end of the delay resistor is connected to the power supply, one end of the delay capacitor is connected to the source of the field effect transistor, and the other end of the delay resistor and the other end of the delay capacitor are both connected to the first connection point.

[0099] It should be noted that the delay module can adopt an RC delay circuit to delay the time when the second driving signal is transmitted from the first auxiliary module to the second auxiliary module. Among them, the delay time of the circuit can be adjusted by the magnitudes of the delay resistor and the delay capacitor. In order to make the second driving signal be issued at an appropriate moment, the delay module can also adopt a relay delay circuit, a monostable delay circuit composed of a single operational amplifier, a transistor delay circuit or a simple long-delay circuit, and the present application does not make specific limitations thereto.

[0100] In some embodiments, the suppression module is configured to, when the level of the first drive signal changes from a second level to a first level, turn off the first auxiliary switch transistor, charge the delay capacitor through the power supply and the delay resistor, so that the level of the second drive signal changes from the first level to the second level; or, when the level of the first drive signal changes from the first level to the second level, turn on the first auxiliary switch transistor, discharge through the delay capacitor, so that the level of the first drive signal changes from the second level to the first level;

[0101] The suppression module is further configured to, when the level of the second drive signal changes from the first level to the second level, turn on the second auxiliary switch transistor, so that the auxiliary capacitor is connected between the gate and the source of the field effect transistor; or, when the level of the second drive signal changes from the second level to the first level, turn off the second auxiliary switch transistor, so that the auxiliary capacitor is not connected between the gate and the source of the field effect transistor.

[0102] In some embodiments, the first level is a low level and the second level is a high level.

[0103] It should be noted that when the first auxiliary switch transistor receives the first drive signal, the state of the first auxiliary switch transistor changes. Through the charging and discharging of the eye resistor and the delay capacitor, the high level of the first drive signal is converted to a low level, or the low level is converted to a high level. When the second auxiliary switch transistor receives the second drive signal, the state of the second auxiliary switch transistor changes, and the auxiliary capacitor is connected to or disconnected from between the gate and the source of the field effect transistor.

[0104] In some embodiments, referring to Figure 9 FIG., a schematic structural diagram of another crosstalk suppression circuit for a field effect transistor provided by the embodiments of the present application is shown. As Figure 9 shown, the crosstalk suppression circuit further includes a first drive module 803; wherein,

[0105] The first drive module 803 is configured to receive an initial drive signal, perform drive control on the initial drive signal, and generate a target drive signal; wherein, the target drive signal is used to control the conduction and turn-off of the field effect transistor.

[0106] In some embodiments, the first drive signal is the same as the initial drive signal.

[0107] It should be noted that the initial drive signal is used to generate the target drive signal to control the on and off of the field effect transistor. After the initial drive signal is input as the first drive signal to the first auxiliary switch transistor, the first replication switch transistor performs an inversion process on the first drive signal to obtain the second drive signal, which is used to control the on and off of the second auxiliary switch transistor, and further control the connection and disconnection of the auxiliary capacitor to suppress the crosstalk phenomenon occurring in the field effect transistor.

[0108] In some embodiments, referring to Figure 10 , which shows a schematic structural diagram of another crosstalk suppression circuit for a field effect transistor provided by an embodiment of the present application. As Figure 10 shown, the first drive signal is different from the initial drive signal, and the crosstalk suppression circuit further includes a second drive module 804; wherein,

[0109] The second drive module 804 is used to generate the first drive signal.

[0110] It should be noted that in the above embodiment, the second drive signal is obtained by inverting the initial drive signal for controlling the field effect transistor. In this embodiment, the second drive signal is obtained by inverting the first drive signal generated by the second drive module. In this case, the first drive signal and the initial drive signal have the same direction.

[0111] In some embodiments, the second drive module 804 is used to generate the second drive signal.

[0112] It should be noted that the second drive signal generated by the second drive module is directly used to control the turn-on and turn-off of the second auxiliary switch transistor, and the second drive signal generated by the second drive module has the opposite direction to the initial drive signal.

[0113] Referring to Figure 11 , which shows a schematic structural diagram of a bridge arm drive circuit provided by an embodiment of the present application. As Figure 11 shown, the bridge arm drive circuit 110 includes a bridge arm module 1101 and at least one crosstalk suppression circuit 80.

[0114] It should be noted that the bridge arm module 1101 includes field effect transistors that are mutually bridged. Each field effect transistor corresponds to a crosstalk suppression circuit. Exemplarily, if the bridge arm module includes two field effect transistors, then correspondingly two crosstalk suppression circuits are included, and the two crosstalk suppression circuits are respectively connected to the two field effect transistors to achieve the suppression of the crosstalk phenomenon of the field effect transistors.

[0115] In some embodiments, the bridge arm module 1101 includes a first field effect transistor and a second field effect transistor, and the number of crosstalk suppression circuits is two; wherein,

[0116] The first crosstalk suppression circuit includes a first suppression module and a first auxiliary capacitor, and is used to control the on-state of the first suppression module to control the access time of the first auxiliary capacitor connected in parallel between the gate and the source of the first field-effect transistor to be earlier than the crosstalk current generation time of the first field-effect transistor, where the crosstalk current is generated when the second field-effect transistor is turned on;

[0117] The second crosstalk suppression circuit includes a second suppression module and a second auxiliary capacitor, and is used to control the on-state of the second suppression module to control the access time of the second auxiliary capacitor connected in parallel between the gate and the source of the second field-effect transistor to be earlier than the crosstalk current generation time of the second field-effect transistor, where the crosstalk current is generated when the first field-effect transistor is turned on.

[0118] It should be noted that before the state of the first field-effect transistor changes from on to off or from off to on, the second auxiliary capacitor in the crosstalk suppression circuit corresponding to the second field-effect transistor is connected between the gate and the source of the second field-effect transistor, so that the crosstalk suppression circuit corresponding to the second field-effect transistor starts to work, avoiding the crosstalk influence of the state change of the first field-effect transistor on the second field-effect transistor. Similarly, before the state of the second field-effect transistor changes from on to off or from off to on, the first auxiliary capacitor in the crosstalk suppression circuit corresponding to the first field-effect transistor is connected between the gate and the source of the first field-effect transistor, so that the crosstalk suppression circuit corresponding to the first field-effect transistor starts to work, avoiding the crosstalk influence of the state change of the second field-effect transistor on the first field-effect transistor.

[0119] In some embodiments, the first crosstalk suppression circuit is further used to control the on-state of the first suppression module to control the first auxiliary capacitor to be connected between the gate and the source of the first field-effect transistor before the second field-effect transistor is turned on;

[0120] The second crosstalk suppression circuit is further used to control the on-state of the second suppression module to control the second auxiliary capacitor to be connected between the gate and the source of the second field-effect transistor before the first field-effect transistor is turned on.

[0121] It should be noted that the first crosstalk suppression circuit is connected to the second driving module, and the second driving module issues a second driving signal to control the on-state of the first suppression module through the second driving signal, and further controls the first auxiliary capacitor to be connected between the gate and the source of the first field-effect transistor before the second field-effect transistor is turned on; similarly, the second crosstalk suppression circuit is connected to the second driving module, and the second driving module issues a second driving signal to control the on-state of the second suppression module through the second driving signal, and further controls the second auxiliary capacitor to be connected between the gate and the source of the second field-effect transistor before the first field-effect transistor is turned on.

[0122] An embodiment of the present application provides a crosstalk suppression circuit for a field effect transistor. The crosstalk suppression circuit includes a power supply module, a voltage stabilization module, and a driving module. Among them, the power supply module is used to receive an input voltage and perform voltage conversion processing on the input voltage to obtain an output voltage. The voltage stabilization module is used to perform voltage stabilization processing on the output voltage to obtain a stable positive driving voltage and an adjustable negative driving voltage. The driving module is used to perform driving processing on the first control signal according to the positive driving voltage and the negative driving voltage to generate a target driving signal. Among them, the target driving signal is used to control the on and off of the field effect transistor. In this way, the auxiliary capacitor is connected between the gate and the source of the field effect transistor through the suppression module to achieve the crosstalk suppression effect. Moreover, the access time of the auxiliary capacitor connected between the gate and the source of the field effect transistor can also be controlled, so that the auxiliary capacitor is connected between the gate and the source of the field effect transistor before crosstalk occurs, thereby being able to better suppress the crosstalk phenomenon generated between field effect transistors, not only not affecting the switching speed of the field effect transistor, but also reducing the risk of mis-turn-on or device damage of the field effect transistor.

[0123] In another embodiment of the present application, refer to Figure 12 , which shows a schematic flowchart of a crosstalk suppression method for a field effect transistor provided by an embodiment of the present application. As Figure 12 shown, the method may include:

[0124] S1201: Receive a first driving signal;

[0125] S1202: Control the conduction state of the suppression module according to the first driving signal to control the access time of the auxiliary capacitor connected in parallel between the gate and the source of the field effect transistor. Among them, the access time is earlier than the crosstalk current generation time of the field effect transistor.

[0126] It should be noted that the crosstalk suppression method provided by the embodiment of the present application can be applied to a bridge arm driving circuit, or can be applied to an electronic device integrated with this circuit or having a crosstalk suppression requirement. Here, the electronic device may be integrated with a Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) / Junction Field-effect Transistor (JFET) / Insulated Gate Bipolar Translator (IGBT) or other controllable switching tubes, and no specific limitation is made here.

[0127] Further, the suppression module may include a first auxiliary module and a second auxiliary module. In some embodiments, for S1202, it may include:

[0128] Receiving a first driving signal through the first auxiliary module, and performing driving reverse processing according to the first driving signal to generate a second driving signal;

[0129] Receiving the second driving signal through the second auxiliary module, and controlling the conduction state of the second auxiliary module according to the second driving signal to control the access time when the auxiliary capacitor is connected in parallel between the gate and the source of the field effect transistor.

[0130] It should be noted that, in the embodiments of the present application, the first auxiliary module may include a first auxiliary switching tube and a first driving resistor, and the second auxiliary module may include a second auxiliary switching tube and a second driving resistor. Specifically, the circuit connection relationship of the suppression module is as follows: the gate of the first auxiliary switching tube is connected to the first driving resistor for receiving the first driving signal; the drain of the first auxiliary switching tube and one end of the second driving resistor are both connected to the first connection point, the other end of the second driving resistor is connected to the gate of the second auxiliary switching tube, and the first connection point is used for outputting the second driving signal; the source of the first auxiliary switching tube and the source of the second auxiliary switching tube are both connected to the source of the field effect transistor; the drain of the second auxiliary switching tube is connected to one end of the auxiliary capacitor, and the other end of the auxiliary capacitor is connected to the gate of the field effect transistor.

[0131] Further, the suppression module may further include a delay module, and the delay module is connected to the connection point between the first auxiliary module and the second auxiliary module. In some embodiments, the method may further include: delaying the second driving signal through the delay module to control the access time when the auxiliary capacitor is connected in parallel between the gate and the source of the field effect transistor.

[0132] It should be noted that, in the embodiments of the present application, the delay module may include a delay resistor and a delay capacitor; wherein, one end of the delay resistor is connected to the power supply, one end of the delay capacitor is connected to the source of the field effect transistor, and the other end of the delay resistor and the other end of the delay capacitor are both connected to the first connection point.

[0133] It should also be noted that the delay module may adopt an RC delay circuit to delay the time for the second driving signal to be transmitted from the first auxiliary module to the second auxiliary module. Among them, the delay time of the circuit can be adjusted by the magnitudes of the delay resistor and the delay capacitor. In order to make the second driving signal be sent at an appropriate moment, the delay module may also adopt a relay delay circuit, a monostable delay circuit composed of a single operational amplifier, a transistor delay circuit or a simple long-delay circuit, and the present application does not make specific limitations thereto.

[0134] Further, in some embodiments, for S1202, the method may further include:

[0135] When the level of the first driving signal changes from the second level to the first level, control the first auxiliary switching transistor to be in the off state, and charge the delay capacitor through the power supply and the delay resistor, so that the level of the second driving signal changes from the first level to the second level; or,

[0136] When the level of the first driving signal changes from the first level to the second level state, control the first auxiliary switching transistor to be in the on state, and discharge through the delay capacitor, so that the level of the first driving signal changes from the second level to the first level.

[0137] Correspondingly, the method may further include:

[0138] When the level of the second driving signal changes from the first level to the second level, control the second auxiliary switching transistor to be in the on state, so that the auxiliary capacitor is connected between the gate and the source of the field effect transistor; or,

[0139] When the level of the second driving signal changes from the second level to the first level, control the second auxiliary switching transistor to be in the off state, so that the auxiliary capacitor is not connected between the gate and the source of the field effect transistor.

[0140] It should be noted that in the embodiments of the present application, the first level may be a low level and the second level may be a high level, but there is no limitation here.

[0141] It should also be noted that when the first auxiliary switching transistor receives the first driving signal, the state of the first auxiliary switching transistor changes, and through the charging and discharging of the delay resistor and the delay capacitor, the high level of the first driving signal is converted into a low level, or the low level is converted into a high level. When the second auxiliary switching transistor receives the second driving signal, the state of the second auxiliary switching transistor changes, and the auxiliary capacitor is connected to or disconnected from between the gate and the source of the field effect transistor.

[0142] Further, the crosstalk suppression circuit may further include a first driving module. In some embodiments, the method may further include: receiving an initial driving signal, and performing driving control on the initial driving signal through the first driving module to generate a target driving signal. Here, the target driving signal is used to control the conduction and cutoff of the field effect transistor.

[0143] It should be noted that in the embodiments of the present application, the first driving signal and the initial driving signal may be the same, and both may be generated by the same driving circuit; or, the first driving signal and the initial driving signal may also be different. For example, the first driving signal is generated by a second driving module, and the initial driving signal is generated by a third driving module. There is no limitation in the embodiments of the present application.

[0144] It should also be noted that based on the same crosstalk suppression, this method can be applied to a single field-effect transistor or multiple field-effect transistors. It can be applied to a group of mutually bridged field-effect transistors or multiple groups of mutually bridged field-effect transistors. The embodiments of this application do not make any limitations.

[0145] Further, in some embodiments, when applied to a group of mutually bridged field-effect transistors, assuming it includes a first field-effect transistor and a second field-effect transistor, this method may further include:

[0146] Controlling the conduction state of the first suppression module according to a first driving signal to control the access time when the first auxiliary capacitor is connected in parallel between the gate and source of the first field-effect transistor earlier than the crosstalk current generation time of the first field-effect transistor;

[0147] Controlling the conduction state of the second suppression module according to a second driving signal to control the access time when the second auxiliary capacitor is connected in parallel between the gate and source of the second field-effect transistor earlier than the crosstalk current generation time of the second field-effect transistor.

[0148] It should be noted that for the first field-effect transistor, its corresponding crosstalk suppression circuit may include a first suppression module and a first auxiliary capacitor, and the signal for controlling the conduction state of the first suppression module is the first driving signal; for the second field-effect transistor, its corresponding crosstalk suppression circuit may include a second suppression module and a second auxiliary capacitor, and the signal for controlling the conduction state of the second suppression module is the second driving signal.

[0149] The embodiments of this application provide a crosstalk suppression method for a field-effect transistor. The crosstalk suppression method includes: receiving a first driving signal; controlling the conduction state of a suppression module according to the first driving signal to control the access time when an auxiliary capacitor is connected in parallel between the gate and source of the field-effect transistor; wherein the access time is earlier than the crosstalk current generation time of the field-effect transistor. In this way, the auxiliary capacitor is connected between the gate and source of the field-effect transistor through the suppression module to achieve the crosstalk suppression effect; moreover, the access time when the auxiliary capacitor is connected between the gate and source of the field-effect transistor can also be controlled, so that the auxiliary capacitor is connected between the gate and source of the field-effect transistor before crosstalk occurs, thereby being able to better suppress the crosstalk phenomenon generated between field-effect transistors, not only not affecting the switching speed of the field-effect transistor, but also reducing the risk of mis-turn-on or device damage of the field-effect transistor.

[0150] In another embodiment of this application, refer to Figure 13 , which shows a specific structural schematic diagram of a bridge arm driving circuit provided by the embodiments of this application. As Figure 13 shown, the bridge arm driving circuit 130 may include a crosstalk suppression circuit 80.

[0151] Further, in some embodiments, as Figure 13 shown, taking two field effect transistors connected in a bridging manner as an example, the bridge arm driving circuit may further include a first auxiliary circuit 1301, a first auxiliary capacitor 1302, a second auxiliary circuit 1303, a second auxiliary capacitor 1304, a first driving circuit 1305, and a second driving circuit 1306; the bridge arm driving circuit may further include a first field effect transistor and a second field effect transistor;

[0152] The first auxiliary circuit 1301 is configured to receive a driving signal, control the conduction state of the first auxiliary circuit 1301 according to the driving signal, so as to control the access time when the first auxiliary capacitor 1302 is connected in parallel between the gate and the source of the first field effect transistor;

[0153] The first auxiliary capacitor 1302 is configured to be connected in parallel between the gate and the source of the first field effect transistor to suppress the crosstalk phenomenon of the first field effect transistor;

[0154] The second auxiliary circuit 1303 is configured to receive a driving signal, control the conduction state of the second auxiliary circuit 703 according to the driving signal, so as to control the access time when the second auxiliary capacitor 704 is connected in parallel between the gate and the source of the second field effect transistor;

[0155] The second auxiliary capacitor 1304 is configured to be connected in parallel between the gate and the source of the second field effect transistor to suppress the crosstalk phenomenon of the second field effect transistor;

[0156] It should be noted that the auxiliary circuit is the suppression module in the foregoing embodiments.

[0157] Referring to Figure 14 , which shows a schematic structural diagram of another bridge arm driving circuit provided by an embodiment of the present application. As Figure 14 shown, the bridge arm driving circuit includes a field effect transistor Q1 (also called the upper transistor) and a field effect transistor Q2 (also called the lower transistor). The dashed part in the figure is the crosstalk suppression circuit provided by the embodiment of the present application; among them, Q3 and Q4 are auxiliary switching transistors, C1 is an auxiliary capacitor, C2 is a delay capacitor, and R1 is a delay resistor.

[0158] Taking the lower transistor Q2 as an example, the auxiliary capacitor C1 is connected in series with Q3, and R1 is connected in series with C2 and connected to the positive electrode Vcc of the driving power supply and the source S1 / S of the silicon carbide field effect transistor Q2. The connection point of R1 and C2 is connected to the gate of Q3 through the driving resistor of Q3 and is also connected to the drain of Q4. The driving signal Vg2 of the silicon carbide field effect transistor Q2 is connected to the gate of Q4 through the driving resistor of Q4.

[0159] It should be noted that Q3, as the first switching transistor, is used to control whether the auxiliary capacitor C1 is connected in parallel between the gate and source of the field effect transistor Q2; R1 and C2 are connected in series to form a delay circuit, which is used to control the access time of the auxiliary capacitor C1, so that the auxiliary capacitor C1 is connected between the gate and source of the field effect transistor Q2 before crosstalk occurs. Q4, as the second switching transistor, is used to invert the drive signal to control the on and off of Q3.

[0160] It should also be noted that Q3 and Q4 can be replaced with other switching transistors, such as BJT, JFET, IGBT, etc. The auxiliary circuit can be replaced with other circuits that can play a delaying role.

[0161] See Figure 15 , which shows a schematic diagram of the change curve of voltages at different positions in a bridge arm drive circuit provided by an embodiment of the present application. As Figure 15 shown, taking the following transistor as an example, the working principle of this bridge arm drive circuit is as follows:

[0162] Stage 1 (t0 - t1): The drive signal Vg2 of the following transistor changes from high level to low level. Therefore, the gate voltage of Q4 is lower than its threshold voltage, Q4 turns off, and the Vds voltage of Q4 starts to rise. On the other hand, the voltage between g and s1 drops. When it is lower than the threshold voltage of the silicon carbide MOSFET, the device turns off. Since Q3 is in the off state at this time, C1 will not affect the turn-off speed.

[0163] Stage 2 (t1 - t2): During the process of the Vds of the following transistor rising, Vcc needs to charge its Cds capacitor and C2 capacitor through R1. This charging time depends on the RC time constant R1 * (Cds4 + C2). Select an appropriate C2 to end before t4.

[0164] Stage 3 (t2 - t3): Since the Vds voltage gradually rises from 0 to Vcc and exceeds the gate threshold voltage of Q3, Q3 conducts, and C1 is connected in parallel between the gate g and s1.

[0165] Stage 4 (t3 - t4): At this time, the drive signal Vg1 of Q1 changes from low to high, and Q1 turns on. Crosstalk current appears and charges Cgd2. Since Q3 is in the conducting state at this time and C1 is connected in parallel with Cgs2, the change amplitude of the gate voltage of Q2 is smaller.

[0166] Stage 5 (t4 - t5): During this time period, Q1 is in the conducting state and Q2 is in the off state. At time t5, the gate drive of Q1 changes from high level to low level, and the crosstalk current discharges Cgd2. Since C1 is connected in parallel with Cgs2 at this time, the decrease amplitude of the gate voltage of Q2 is smaller.

[0167] Stage 6 (t5 - t6): This time period is within the dead time, and the oscillation of the gate voltage of Q2 caused by crosstalk ends. At time t6, the dead time ends, and the gate voltage of Q2 changes from low level to high level.

[0168] Stage 7 (t6 - t7): When Vg2 exceeds the threshold voltage of Q4, Q4 conducts. Since Q4 is a low-voltage MOS and its threshold voltage < 1V, it conducts quickly, and Vds_Q4 drops to 0. After Q4 conducts, it quickly discharges C2, and the voltage of C2 drops rapidly. Therefore, the gate voltage of Q3 quickly drops below its threshold voltage, and Q3 turns off. Since this process is very fast, when Q3 turns off, the gate voltage of Q2 has just exceeded the threshold voltage, and at this time, C1 is no longer in parallel with Cgs2. In the subsequent turn-on process, Vg2 only charges Cgs2, so the rising speed of the current of Q2 and the falling speed of the voltage will not slow down.

[0169] Based on the above analysis, C1 is in parallel with Cgs2 during the time periods of t3 and t6, and the turn-on and turn-off of Q1 also occur during this time, so it can play a role in suppressing crosstalk. During the turn-on and turn-off processes of Q2, C1 is not in parallel with Cgs2, so the switching speed of Q2 is not affected.

[0170] In some embodiments, refer to Figure 16 , which shows a specific structural schematic diagram of another bridge arm driving circuit provided by the embodiments of the present application. As Figure 16 shown, on the basis of the bridge arm circuit shown in Figure 13 , this bridge arm driving circuit may further include an auxiliary driving signal. The auxiliary driving signal is independent of the driving signal, reducing the complexity of the auxiliary circuit. The on and off of the auxiliary circuit are controlled by an additional auxiliary driving signal to determine the time when the auxiliary capacitor is connected to the circuit. When keeping the auxiliary driving signal and the driving signal opposite, it can be achieved that when the driving signal drives the field effect transistor, the auxiliary capacitor will not be connected to the field effect transistor, that is, the crosstalk suppression circuit of the field effect transistor will not take effect.

[0171] To verify the beneficial effects of the present invention, refer to Figure 17 , which shows a schematic diagram of the change curves of the drain-source voltage and gate-source voltage of a non-clamped circuit provided by the related art. Refer to Figure 18 , which shows a schematic diagram of the change curves of the drain-source voltage and gate-source voltage of a bridge arm driving circuit with a clamping circuit provided by the embodiments of the present application. Among them, the clamping circuit is the crosstalk suppression circuit in the foregoing embodiments. Taking the lower transistor as an example, the double-pulse simulation analysis is respectively carried out on the bridge structure circuit without using the crosstalk suppression circuit provided by the embodiments of the present application and using the crosstalk suppression circuit provided by the embodiments of the present application, and the Vgs and Vds waveform diagrams of the field effect transistor are observed. Among them, Vgs is the gate-source voltage, and Vds is the drain-source voltage, and the differences between the traditional driving scheme and the embodiments of the present application are compared.

[0172] Figure 17 It is a schematic diagram of the waveform of the gate-source voltage Vgs of the lower transistor when using the traditional driving scheme. It can be seen that when the upper transistor turns on and turns off, there are obvious oscillations in the gate-source voltage Vgs of the lower transistor, and the oscillation amplitude is relatively high. Figure 18 It is a schematic diagram of the waveform of the gate-source voltage Vgs of the lower transistor when using the embodiment of the present application. It can be seen that when the upper transistor turns on and off, the oscillation of the gate-source voltage Vgs of the lower transistor is significantly reduced. Therefore, this scheme has a great effect on suppressing crosstalk.

[0173] Furthermore, the turn-on and turn-off speeds of the devices in the traditional scheme and the embodiment of the present application are compared. Among them, Vds is the drain-source voltage and Id is the drain current

[0174] See Figure 19a and Figure 19b , Figure 19a shows a schematic diagram of the change curve of vds when a non-clamped circuit provided by the related art turns off; Figure 19b shows a schematic diagram of the change curve of id when a non-clamped circuit provided by the related art turns off. By comparing 19a and Figure 19b , the turn-off speed of the lower transistor in the traditional non-clamped circuit scheme can be obtained.

[0175] See Figure 20a and Figure 20b , Figure 20a shows a schematic diagram of the change curve of vds when there is a clamping circuit in a bridge arm driving circuit provided by the embodiment of the present application when it turns off; Figure 20b shows a schematic diagram of the change curve of id when there is a clamping circuit in a bridge arm driving circuit provided by the embodiment of the present application when it turns off; By comparing 20a and Figure 20b , the turn-off speed of the lower transistor in a bridge arm driving circuit provided by the embodiment of the present application when there is a clamping circuit can be obtained.

[0176] See Figure 21a and Figure 21b , Figure 21a shows a schematic diagram of the change curve of vds when a non-clamped circuit provided by the related art turns on; Figure 21b shows a schematic diagram of the change curve of id when a non-clamped circuit provided by the related art turns on. By comparing 21a and Figure 21b , the turn-on speed of the lower transistor in the traditional non-clamped circuit scheme can be obtained.

[0177] See Figure 22a and Figure 22b , Figure 22a shows a schematic diagram of the change curve of vds when there is a clamping circuit in another bridge arm driving circuit provided by the embodiment of the present application when it turns on; Figure 22bIt shows a schematic diagram of the id variation curve when the clamping circuit is turned on in another arm driving circuit provided by the embodiment of the present application. Through the comparison with 22a and Figure 22b the turn-on speed of the lower transistor in an arm driving circuit provided by the embodiment of the present application when there is a clamping circuit can be obtained.

[0178] Figure 19a , Figure 19b and Figure 21a , Figure 21b It can be seen the turn-on and turn-off speeds of the lower transistor in the traditional non-clamping circuit scheme. Among them, the upper dotted curve is the Vds of the lower transistor, and the lower solid curve is the Id of the lower transistor. In the simulation, the rise time of Id is about 24 ns, and the fall time is about 16 ns;

[0179] Figure 20a , Figure 20b and Figure 22a Figure 22b It can be seen the simulation results of an arm driving circuit provided by the embodiment of the present application with a clamping circuit. Among them, the upper dotted curve is the Vds of the lower transistor, and the lower solid curve is the Id of the lower transistor. In the simulation, the rise time of Id is about 24 ns, and the fall time of Id is about 16 ns. The turn-on or turn-off speed of the embodiment of the present application has no difference from that of the traditional scheme. The above simulation results verify that: this scheme can not only suppress crosstalk, but also will not reduce the switching speed of the device.

[0180] The embodiment of the present application provides an arm driving circuit. According to the driving signal, the auxiliary capacitor is timely connected in parallel between the gate and source of the field effect transistor. The arm driving circuit provided by this embodiment will not affect the switching speed of the silicon carbide MOSFET and will not affect the efficiency; by connecting the capacitor between the gate gs, the crosstalk suppression effect is achieved, and the suppression effect is obvious; the switching tube used does not require an additional driving signal for driving, and the implementation method is simple; before the crosstalk pair is turned on, the capacitor has been connected, and the switching tube will not turn off during the crosstalk process, and the capacitor always plays a role in suppression. In this way, through the suppression module, the auxiliary capacitor is connected between the gate and source of the field effect transistor to achieve the crosstalk suppression effect; moreover, the access time of the auxiliary capacitor connected between the gate and source of the field effect transistor can be controlled, so that the auxiliary capacitor is connected between the gate and source of the field effect transistor before crosstalk occurs, thereby being able to better suppress the crosstalk phenomenon generated between the field effect transistors, not only will not affect the switching speed of the field effect transistor, but also reduce the risk of mis-turn-on or device damage of the field effect transistor.

[0181] In another embodiment of the present application, referring to Figure 23 , it shows a schematic diagram of the structure of an electronic device provided by the embodiment of the present application. As Figure 23As shown, the electronic device 230 at least includes the leg driving circuit 110 described in the foregoing embodiments.

[0182] In this way, for the electronic device 230, since the leg driving circuit therein includes a crosstalk suppression circuit, according to the specific description of the foregoing embodiments, the crosstalk suppression circuit includes a suppression module and an auxiliary capacitor, and the suppression module and the auxiliary capacitor are connected in parallel between the gate and the source of the field effect transistor; wherein, the suppression module is configured to receive a first driving signal and control the conduction state of the suppression module according to the first driving signal, so as to control the access time of the auxiliary capacitor connected in parallel between the gate and the source of the field effect transistor. In this way, by connecting the auxiliary capacitor between the gate and the source of the field effect transistor through the suppression module, the crosstalk suppression effect is achieved; moreover, the access time of the auxiliary capacitor connected between the gate and the source of the field effect transistor can also be controlled, so that the auxiliary capacitor is connected between the gate and the source of the field effect transistor before crosstalk occurs, thereby being able to better suppress the crosstalk phenomenon generated between the field effect transistors, not only not affecting the switching speed of the field effect transistors, but also reducing the risk of mis-turn-on or device damage of the field effect transistors.

[0183] It should be noted that in this application, the terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including one..." does not exclude the existence of additional identical elements in the process, method, article or device including the element.

[0184] The serial numbers of the embodiments of the present application above are only for description and do not represent the superiority or inferiority of the embodiments.

[0185] The methods disclosed in the several method embodiments provided by the present application can be arbitrarily combined without conflict to obtain new method embodiments.

[0186] The features disclosed in the several product embodiments provided by the present application can be arbitrarily combined without conflict to obtain new product embodiments.

[0187] The features disclosed in the several method or device embodiments provided by the present application can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0188] As described above, it is only the specific implementation manner of the present application. However, the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of changes or substitutions, which should all be covered within the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the said claims.

Claims

1. A crosstalk suppression circuit for a field effect transistor, characterized in that, the crosstalk suppression circuit includes a suppression module and an auxiliary capacitor. The suppression module and the auxiliary capacitor are connected in parallel between the gate and the source of the field effect transistor. The suppression module includes a first auxiliary module, a second auxiliary module and a delay module. The delay module is connected to the connection point of the first auxiliary module and the second auxiliary module; wherein, the first auxiliary module is configured to receive a first driving signal, perform a driving reverse process according to the first driving signal, and generate a second driving signal; the delay module is configured to perform a delay process on the second driving signal; the second auxiliary module is configured to receive the second driving signal, control the conduction state of the second auxiliary module according to the second driving signal, so as to control the access time when the auxiliary capacitor is connected in parallel between the gate and the source of the field effect transistor; wherein, the access time is earlier than the crosstalk current generation time of the field effect transistor.

2. The crosstalk suppression circuit according to claim 1, characterized in that, the first auxiliary module includes a first auxiliary switch tube and a first driving resistor, and the second auxiliary module includes a second auxiliary switch tube and a second driving resistor; wherein, the gate of the first auxiliary switch tube is connected to the first driving resistor for receiving the first driving signal; the drain of the first auxiliary switch tube and one end of the second driving resistor are both connected to a first connection point, the other end of the second driving resistor is connected to the gate of the second auxiliary switch tube, and the first connection point is used for outputting the second driving signal; the source of the first auxiliary switch tube and the source of the second auxiliary switch tube are both connected to the source of the field effect transistor; the drain of the second auxiliary switch tube is connected to one end of the auxiliary capacitor, and the other end of the auxiliary capacitor is connected to the gate of the field effect transistor.

3. The crosstalk suppression circuit according to claim 2, characterized in that, the delay module includes a delay resistor and a delay capacitor; wherein, one end of the delay resistor is connected to a power supply, one end of the delay capacitor is connected to the source of the field effect transistor, and the other end of the delay resistor and the other end of the delay capacitor are both connected to the first connection point.

4. The crosstalk suppression circuit according to claim 3, characterized in that, the suppression module is configured to, when the level of the first driving signal changes from a second level to a first level, the first auxiliary switch tube is in an off state, and the delay capacitor is charged through the power supply and the delay resistor, so that the level of the second driving signal changes from the first level to the second level; or, when the level of the first driving signal changes from the first level to the second level state, the first auxiliary switch tube is in an on state, and the delay capacitor is discharged, so that the level of the first driving signal changes from the second level to the first level; The suppression module is further configured to, when the level of the second driving signal changes from the first level to the second level, turn on the second auxiliary switching transistor so that the auxiliary capacitor is connected between the gate and the source of the field effect transistor; or, when the level of the second driving signal changes from the second level to the first level, turn off the second auxiliary switching transistor so that the auxiliary capacitor is not connected between the gate and the source of the field effect transistor.

5. The crosstalk suppression circuit according to claim 4, wherein, the first level is a low level and the second level is a high level.

6. The crosstalk suppression circuit according to any one of claims 1 to 5, wherein, the crosstalk suppression circuit further includes a first driving module; wherein, the first driving module is configured to receive an initial driving signal, perform driving control on the initial driving signal, and generate a target driving signal; wherein the target driving signal is used to control the conduction and cutoff of the field effect transistor.

7. The crosstalk suppression circuit according to claim 6, wherein, the first driving signal is the same as the initial driving signal.

8. The crosstalk suppression circuit according to claim 6, wherein, the first driving signal is different from the initial driving signal, and the crosstalk suppression circuit further includes a second driving module; wherein, the second driving module is configured to generate the first driving signal.

9. A bridge arm driving circuit, wherein, the bridge arm driving circuit includes a bridge arm module and at least one crosstalk suppression circuit according to any one of claims 1 to 8.

10. The bridge arm driving circuit according to claim 9, wherein, the bridge arm module includes a first field effect transistor and a second field effect transistor, and the number of the crosstalk suppression circuits is two; wherein, The first crosstalk suppression circuit includes a first suppression module and a first auxiliary capacitor, and is configured to control the conduction state of the first suppression module to control the access time of the first auxiliary capacitor in parallel between the gate and the source of the first field effect transistor earlier than the crosstalk current generation time of the first field effect transistor, and the crosstalk current is generated when the second field effect transistor conducts; The second crosstalk suppression circuit includes a second suppression module and a second auxiliary capacitor, and is configured to control the conduction state of the second suppression module to control the access time of the second auxiliary capacitor in parallel between the gate and the source of the second field effect transistor earlier than the crosstalk current generation time of the second field effect transistor, and the crosstalk current is generated when the first field effect transistor conducts.

11. The bridge arm driving circuit according to claim 10, wherein, the first crosstalk suppression circuit is further configured to control the conduction state of the first suppression module to control the first auxiliary capacitor to be connected between the gate and the source of the first field effect transistor before the second field effect transistor conducts; The second crosstalk suppression circuit is further configured to control the on-state of the second suppression module, so as to control the second auxiliary capacitor to be connected between the gate and the source of the second field-effect transistor before the first field-effect transistor is turned on.

12. A method for suppressing crosstalk of a field-effect transistor, characterized in that the method includes: receiving a first drive signal, performing a drive reverse process according to the first drive signal, and generating a second drive signal; performing a delay process on the second drive signal; receiving the second drive signal, and controlling the on-state of the second auxiliary module according to the second drive signal, so as to control the access time when the auxiliary capacitor is connected in parallel between the gate and the source of the field-effect transistor; wherein, the access time is earlier than the crosstalk current generation time of the field-effect transistor.

13. An electronic device, characterized in that the electronic device at least includes the leg drive circuit according to any one of claims 9 to 11.

Images