Three-way switch array structure and switch array substrate based on non-volatile memory

Abstract

The present invention discloses a three-way switch array structure and a switch array substrate based on a non-volatile memory, wherein the three-way switch array structure comprises N first wirings, M second wirings, N×M third wirings and N×M three-way switches, each three-way switch has a first contact, a second contact, a third contact, a first switch and a second switch, wherein each first contact is arranged on one of these first wirings, each second contact is arranged on one of these second wirings, each third contact is arranged on one of these third wirings, the first switch is arranged between the first contact and the third contact, and the second switch is arranged between the second contact and the third contact, wherein N and M are positive integers greater than or equal to 1.

Description

Technical Field

[0001] The invention relates to a three-way switch array structure and a switch array substrate based on a non-volatile memory. Background Art

[0002] Solderless universal circuit boards (commonly known as "breadboards") are used to allow electronic components to be repeatedly inserted and disassembled on an electronic component configuration carrier to lay out electronic circuits with specific functions. However, the electronic component configuration carrier only has two-dimensional circuits connecting the electronic components, so the space utilization rate of the electronic components cannot be improved.

[0003] In addition, for the electronic circuit layout of the memory array, the memory can be manufactured as an array composed of a plurality of memory cells to read the data stored in the memory cells or write the data in the memory cells. The data of the memory cells can be configured to store two or more levels or states (e.g., 0 or 1). Common memory cells access data in a combination of transistors and capacitors, wherein the transistors are used to selectively access the capacitors and can be referred to as access devices, and the capacitors electrostatically store energy in the form of an electric field in the capacitor dielectric between the two capacitor plates to represent the state of the memory cell.

[0004] In order to construct a three-dimensional wiring electronic circuit and stack electronic components vertically, it is necessary to develop or newly design an electronic component configuration carrier with a three-way switch array structure for use. At the same time, in order to construct a three-dimensional memory array, stack memory cells vertically and control the level or state stored in each memory cell, it is also necessary to develop or newly design a semiconductor substrate with a three-way switch array structure for use. Summary of the invention

[0005] The invention relates to a three-way switch array structure and a switch array substrate based on a non-volatile memory.

[0006] According to one aspect of the present invention, a three-way switch array structure is proposed, comprising N first wirings, M second wirings, N×M third wirings and N×M three-way switches, each three-way switch having a first contact, a second contact, a third contact, a first switch and a second switch, wherein each first contact is arranged on one of the first wirings, each second contact is arranged on one of the second wirings, each third contact is arranged on one of the third wirings, the first switch is arranged between the first contact and the third contact, and the second switch is arranged between the second contact and the third contact, wherein N and M are positive integers greater than or equal to 1.

[0007] According to another aspect of the present invention, a switch array substrate based on a non-volatile memory is provided, comprising N first wirings, M second wirings, N×M third wirings, N×M three-way switches and a semiconductor substrate, each three-way switch having a first contact, a second contact, a third contact, a first memory unit and a second memory unit, wherein each first contact is arranged on one of the first wirings, each second contact is arranged on one of the second wirings, each third contact is arranged on one of the third wirings, the first memory unit is arranged between the first contact and the third contact, and the second memory unit is arranged between the second contact and the third contact, wherein N and M are positive integers greater than or equal to 1. The semiconductor substrate is used to arrange the first wirings, the second wirings, the third wirings and the three-way switches.

[0008] In order to better understand the above and other aspects of the present invention, embodiments are given below and described in detail with reference to the accompanying drawings: BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 A schematic diagram of a three-way switch array structure according to an embodiment of the present invention is shown;

[0010] Figure 2A and Figure 2B Draw separately Figure 1 Schematic diagram of a three-way switch;

[0011] Figure 3 A schematic diagram of a three-way switch array structure according to another embodiment of the present invention is shown;

[0012] Figure 4 A schematic diagram of a switch array substrate based on a non-volatile memory according to an embodiment of the present invention is shown;

[0013] Figure 5 Draw Figure 4 Schematic diagram of a three-way switch;

[0014] Figure 6 Draw Figure 5 A cross-sectional schematic diagram of a memory cell in FIG.

[0015] Figure 7 Draw Figure 5 A schematic cross-sectional view of a memory cell and a vertical conductive structure thereof; and

[0016] Figure 8 Draw according to Figure 5 A top view of a 2×2 three-way switch.

[0017]

Explanation of symbols

[0018] 100, 101: Three-way switch array structure

[0019] 110: First connection

[0020] 120: Second connection

[0021] 130: Third connection

[0022] 140: Three-way switch

[0023] X: First direction

[0024] Y: Second direction

[0025] Z: Third direction

[0026] X1-X4: first to fourth row

[0027] Y1-Y4: first to fourth columns

[0028] 141: First contact

[0029] 142: Second contact

[0030] 143: The third contact

[0031] 144: First switch

[0032] 145: Second switch

[0033] 146: The third switch

[0034] 150: First terminal switch

[0035] 160: Second terminal switch

[0036] Z(1,1), Z(1,4), Z(4,1), Z(4,4): coordinates

[0037] W1-W4: first to fourth columns

[0038] R1-R4: first to fourth row

[0039] 200: Switch array substrate

[0040] 210: First connection

[0041] 211: First drain line

[0042] 212: First word line

[0043] 222: Second word line

[0044] 220: Second connection

[0045] 221: Second drain line

[0046] 230: Third connection

[0047] 240: Three-way switch

[0048] 241: First contact

[0049] 242: Second contact

[0050] 243: The third contact

[0051] 244: First memory unit

[0052] 245: Second memory unit

[0053] 246: Conductive plug

[0054] 247: Substrate conduction structure

[0055] 250: Semiconductor substrate

[0056] S1: First source

[0057] D1: First drain

[0058] G1: First gate

[0059] S2: Second source

[0060] D2: Second drain

[0061] G2: Second gate

[0062] F1, F2: floating gate

[0063] G1, G2: Gate

[0064] M1: First metal layer

[0065] M2: Second metal layer DETAILED DESCRIPTION

[0066] The following embodiments are provided for detailed description. The embodiments are only used as examples and are not intended to limit the scope of the invention. The following are explanations of the same / similar elements represented by the same / similar symbols. The directional terms mentioned in the following embodiments, such as up, down, left, right, front or back, etc., are only referenced to the directions of the accompanying drawings. Therefore, the directional terms used are used to illustrate and are not intended to limit the invention.

[0067] Please refer to Figure 1 , Figure 2A and Figure 2B ,in Figure 1 FIG. 1 is a schematic diagram of a three-way switch array structure 100 according to an embodiment of the present invention. Figure 2A and Figure 2B Schematic diagrams of a three-way switch 140 according to an embodiment of the present invention are respectively shown.

[0068] According to one embodiment of the present invention, a three-way switch array structure 100 includes a plurality of first wirings 110, a plurality of second wirings 120, a plurality of third wirings 130, and a plurality of three-way switches 140. The first wiring 110 is a wire extending along a first direction X, the second wiring 120 is a wire extending along a second direction Y, and the third wiring 130 is a wire extending along a third direction Z. Any two of the first wiring 110, the second wiring 120, and the third wiring 130 are perpendicular to each other or intersect at a predetermined angle, and any two of the first wiring 110, the second wiring 120, and the third wiring 130 are connected to each other via the three-way switch 140 to form N first wirings 110, M second wirings 120, N×M third wirings 130, and N×M three-way switches 140 arranged in a three-dimensional space, wherein N and M are positive integers greater than or equal to 1. Figure 1 , X1 to X4 represent first wiring lines 110 of first to fourth rows, respectively, and Y1 to Y4 represent second wiring lines 120 of first to fourth columns, respectively.

[0069] Please refer to Figure 1 , Figure 2A and Figure 2B Taking the array of 4×4 three-way switches 140 as an example, each three-way switch 140 has a first contact 141, a second contact 142, a third contact 143, a first switch 144, and a second switch 145. The first switch 144 is disposed between the first contact 141 and the third contact 143, and the second switch 145 is disposed between the second contact 142 and the third contact 143. Each first contact 141 is disposed on the corresponding first wiring 110, and each second contact 142 is disposed on the corresponding second wiring 120. Each third contact 143 is disposed on the corresponding third wiring 130. The position of the third connection point 143 is represented by the coordinates Z(X, Y), wherein Z(1, 1) represents the coordinates of the third connection point 143 connected to the first connection point 110 (X1) and the second connection point 120 (Y1) respectively, Z(1, 4) represents the coordinates of the third connection point 143 connected to the first connection point 110 (X1) and the second connection point 120 (Y4) respectively, Z(4, 1) represents the coordinates of the third connection point 143 connected to the first connection point 110 (X4) and the second connection point 120 (Y1) respectively, and Z(4, 4) represents the coordinates of the third connection point 143 connected to the first connection point 110 (X4) and the second connection point 120 (Y4) respectively.

[0070] In one embodiment, the first switch 144 and the second switch 145 are, for example, mechanical or electronic switches. The electronic switch is, for example, a two-stage electronic switch, and common ones include transistor switches, capacitive touch switches, and resistive switches. The mechanical switch is, for example, a micro-electromechanical element, and common ones include piezoelectric switches, photointerrupter switches, reed switches, and Hall switches. In order to reduce the size of the element and the wiring space, the first switch 144 and the second switch 145 are, for example, made of semiconductor elements, and common ones include metal-oxide-semiconductor field-effect transistors (MOSFET) or silicon controlled switches.

[0071] Please refer to Figure 2A The first switch 144 has two states (0 or 1), and the second switch 145 has two states (0 or 1), where 0 represents that the switch is open (Open) and 1 represents that the switch is closed (Close). The above states of the first switch 144 and the second switch 145 are arranged and combined to obtain the following four signal states (0, 0) (0, 1) (1, 0) and (1, 1), where (0, 0) represents that both the first switch 144 and the second switch 145 are open, so that the three-way switch 140 is in a completely disconnected state; (0, 1) represents that the first switch 144 is open and the second switch 145 is closed, so that the three-way switch 140 is in a single-way conducting state; (1, 0) represents that the first switch 144 is closed and the second switch 145 is open, so that the three-way switch 140 is in a single-way conducting state; and (1, 1) represents that both the first switch 144 and the second switch 145 are closed, so that the three-way switch 140 is in a fully conducting state.

[0072] Please refer to Figure 2B In addition to the first switch 144 and the second switch 145, each three-way switch 140 may further include a third switch 146 disposed on the third connection 130. The third switch 146 is, for example, a mechanical or electronic switch, and its function is similar to that of the first switch 144 and the second switch 145, which will not be described in detail herein.

[0073] exist Figure 2B, the first switch 144 has two states (0 or 1), the second switch 145 has two states (0 or 1), and the third switch 146 has two states (0 or 1), where 0 represents the switch is open and 1 represents the switch is closed. Combining the states of the first switch 144, the second switch 145, and the third switch 146, the following eight signal states can be obtained: (0, 0, 0) (0, 1, 0) (0, 1, 1) (0, 0, 1) (1, 0, 0) (1, 0, 1) (1, 1, 0) and ( 1, 1, 1), where (0, 0, 0) means that all three switches are open, so that the three-way switch 140 is in a completely disconnected state, (0, 1, 0) (0, 0, 1) (1, 0, 0) means that two switches are open and one switch is closed, so that the three-way switch 140 is in a single-way on state, (0, 1, 1) (1, 0, 1) (1, 1, 0) means that two switches are closed and one switch is open, so that the three-way switch 140 is in a two-way on state, and (1, 1, 1) means that all three switches are closed, so that the three-way switch 140 is in a fully on state.

[0074] Please refer to Figure 3 , which is a schematic diagram of a three-way switch array structure 101 according to another embodiment of the present invention. The three-way switch array structure 101 of this embodiment is Figure 2A and Figure 2B The three-way switch array structure 100 is similar to that of FIG. 1 , except that it includes a plurality of first terminal switches 150 and a plurality of second terminal switches 160, wherein the first terminal switches 150 are respectively disposed on the corresponding first wirings 110 to control the signal states (0 or 1) of the M first contacts 141 located in the same row, and the second terminal switches 160 are respectively disposed on the corresponding second wirings 120 to control the signal states (0 or 1) of the N second contacts 142 located in the same column, wherein 0 indicates that the terminal switch is in an open state, and 1 indicates that the terminal switch is in a closed state.

[0075] In one embodiment, the first terminal switch 150 and the second terminal switch 160 are, for example, mechanical or electronic switches, and their functions are similar to those of the first switch 144 and the second switch 145, which are not described in detail herein. In addition, the first terminal switch 150 and the second terminal switch 160 are, for example, multiplexers or demultiplexers. The multiplexer is used for selecting data at the data transmitting end to determine which line the data is to be sent, and is also called a data selector. The demultiplexer is used for distributing data at the data receiving end to determine which line the data is to be received, and is also called a data distributor.

[0076] In addition to the plurality of first terminal switches 150 and the plurality of second terminal switches 160, the three-way switch array structure 101 of the present embodiment may further include the following configurations: Figure 2B The third switch 146 shown has the same function as the first switch 144 and the second switch 145 , which will not be described in detail herein.

[0077] Compared to the conventional solder-free universal circuit board (commonly known as "breadboard"), the three-way switch array structures 100 and 101 of the above two embodiments can be applied to the electronic component configuration carrier to construct a three-dimensional wiring electronic circuit. The difference from the conventional solder-free universal circuit board is that the first switch 144, the second switch 145, the third switch 146, the first terminal switch 150, and the second terminal switch 160 can be wireless switch components, for example, controlling the corresponding circuit to be turned on or off by Bluetooth or WiFi communication.

[0078] Please refer to Figure 4 and Figure 5 ,in Figure 4 FIG. 1 is a schematic diagram of a switch array substrate 200 based on a non-volatile memory according to an embodiment of the present invention. Figure 5 Draw Figure 4 The switch array substrate 200 is, for example, a silicon wafer or an interposer, and includes a plurality of first wires 210, a plurality of second wires 220, a plurality of third wires 230, a plurality of three-way switches 240, and a semiconductor substrate 250 (see Figure 6 ). The first wiring 210 is a wire extending along the first direction X, the second wiring 220 is a wire extending along the second direction Y, and the third wiring 230 is a wire extending along the third direction Z. Any two of the first wiring 210, the second wiring 220, and the third wiring 230 are perpendicular to each other or intersect at a predetermined angle, and any two of the first wiring 210, the second wiring 220, and the third wiring 230 are connected to each other via the three-way switch 240 to form N first lines, M second lines, N×M third lines, and N×M three-way switches 140 arranged in a three-dimensional space, wherein N and M are positive integers greater than or equal to 1.

[0079] Please refer to Figure 4 and Figure 5Taking the array of 4×4 three-way switches 240 as an example, each three-way switch 240 has a first contact 241, a second contact 242, a third contact 243, a first memory unit 244, and a second memory unit 245. The first memory unit 244 is disposed between the first contact 241 and the third contact 243, and the second memory unit 245 is disposed between the second contact 242 and the third contact 243. Each first contact 241 is disposed on the corresponding first wiring 210, and each second contact 242 is disposed on the corresponding second wiring 220. Each third contact 243 is disposed on the corresponding third wiring 230.

[0080] The first memory cell 244 can be used as a transistor with a variable threshold voltage, and the second memory cell 245 can also be used as a transistor with a variable threshold voltage. The first memory cell 244 and the second memory cell 245 can be distinguished as PMOS transistors or NMOS transistors according to the difference in majority carriers (holes or electrons) doped in the semiconductor substrate 250.

[0081] In addition to the first memory unit 244 and the second memory unit 245, each three-way switch 240 may further include a switch disposed on the third connection 230. This switch is, for example, a mechanical or electronic switch, and its function is similar to the third switch 146 (see Figure 2B In another embodiment, the switch may also be a memory unit, that is, the three-way switch 240 may further include a third memory unit, such as a transistor with a variable threshold voltage, whose function is the same as the first memory unit 244 and the second memory unit 245, which will not be described in detail here.

[0082] Please refer to Figure 5 The first memory cell 244 has two states (0 or 1) according to the threshold voltage of the stored charge, and the second memory cell 245 has two states (0 or 1) according to the threshold voltage of the stored charge, where 0 represents a high potential and 1 represents a low potential. The above states of the three-way switch 240 are arranged and combined to obtain the following four signal states (0, 0), (0, 1), (1, 0) and (1, 1), where (0, 0) indicates that both transistors in the first memory cell 244 and the second memory cell 245 are in a data storage state, (0, 1) and (1, 0) indicate that one memory cell is at a high potential and the other memory cell is at a low potential, so that one transistor is in a data storage state and the other transistor is in an erase state, and (1, 1) indicates that both transistors in the first memory cell 244 and the second memory cell 245 are in an erase state.

[0083] In addition, the third memory cell can also have two states (0 or 1) according to the threshold voltage of the stored charge. By arranging and combining the states of the first memory cell 244, the second memory cell 245 and the third memory cell, the following eight data states can be obtained: (0, 0, 0) (0, 1, 0) (0, 1, 1) (0, 0, 1) (1, 0, 0) (1, 0, 1) (1, 1, 0) and (1, 1, 1).

[0084] Please refer to Figure 5 The first memory unit 244 includes a first source S1, a first drain D1 and a first gate G1, wherein the first source S1 is connected to the third contact 243, the first drain D1 is connected to the first contact 241, and the first gate G1 is connected to a voltage source (not shown) via a first word line 212. In addition, the second memory unit 245 includes a second source S2, a second drain D2 and a second gate G2, wherein the second source S2 is connected to the third contact 243, the second drain D2 is connected to the second contact 242, and the second gate G2 is connected to a voltage source (not shown) via a second word line 222. The first source S1 and the second source S2 can be connected to the third contact 243 at the same time. Based on the connection requirements, the first memory unit 244 and the second memory unit 245 can be in an open circuit (0, 0) state, a partially open circuit / partially closed circuit (1, 0) / (0, 1) state, or a closed circuit (1, 1) state at the same time. In one embodiment, the channel width is, for example, greater than 10 micrometers, but is not limited thereto.

[0085] The first gate G1 and the second gate G2 are respectively electrically connected to the first word line 212 and the second word line 222 of different layers in the vertical direction, and the first word line 212 and the second word line 222 are perpendicular to each other, and the intersection of the first word line 212 and the second word line 222 is separated by an insulating layer (not shown). Figure 4 , W1 to W4 represent first word lines 212 of first to fourth columns, respectively, and R1 to R4 represent second word lines 222 of first to fourth rows, respectively.

[0086] The materials of the first gate G1 and the second gate G2 may include any suitable conductive material, such as one or more materials selected from metals (e.g., titanium, tungsten, cobalt, nickel, platinum, etc.), metal compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.) and / or conductively doped semiconductor materials (e.g., conductively doped silicon, conductively doped germanium, etc.). In addition, the channel material in the first memory cell 244 and the second memory cell 245 is, for example, gallium phosphide (GaP), which can provide a semiconductor material with a large band gap and charge carrier mobility superior to, for example, silicon, and is compatible with the lattice of the semiconductor substrate 250.

[0087] Please refer to Figure 6, which shows Figure 5 2 is a cross-sectional schematic diagram of a memory cell 240 in FIG. The first memory cell 244 and the second memory cell 245 are, for example, flash memories, which are formed on a semiconductor substrate 250. Since the flash memory is a non-volatile memory, a floating gate F1, F2 made of polysilicon or silicon nitride is added to the gates G1, G2 of the transistors, and the state (0 or 1) of the memory cells is determined by the presence or absence of charge in the floating gates F1, F2. Since the floating gates F1, F2 are surrounded by an insulator, when the power supply of the gates G1, G2 disappears, the charge is confined in the floating gates F1, F2 and will not dissipate, so that the state (0 or 1) can be maintained.

[0088] In addition to flash memory, Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) memory and hafnium dioxide-based ferroelectric field effect transistor (FeFET) may also be used as the first memory unit 244 and the second memory unit 245 .

[0089] In addition, this embodiment may also use magnetoresistive RAM (MRAM), phase change RAM (PCRAM) and resistive RAM (RRAM) as the first memory unit 244 and the second memory unit 245 .

[0090] Please refer to Figure 6The semiconductor substrate 250 may be made of any suitable basic semiconductor (e.g., crystalline silicon or germanium), compound semiconductor (e.g., silicon carbide, gallium arsenide, gallium phosphide, iodine phosphide, iodine arsenide and / or iodine antimonide), or a combination thereof. The semiconductor substrate 250 is, for example, a P-type substrate, and the impurity polarity doped in the first source S1 and the first drain D1 is N-type. When a positive voltage is applied to the first gate G1, negatively charged electrons are attracted to the surface of the semiconductor substrate 250, forming a channel, allowing the majority carriers (electrons) of the semiconductor substrate 250 to flow from the first source S1 to the first drain D1. If the positive voltage is removed from the first gate G1, or a negative voltage is applied, the channel cannot be formed, and the majority carriers (electrons) cannot flow between the first source S1 and the first drain D1. Similarly, when a positive voltage is applied to the second gate G2, negatively charged electrons are attracted to the surface of the semiconductor substrate 250, forming a channel, allowing the majority carriers (electrons) of the semiconductor substrate 250 to flow from the second source S2 to the second drain D2. If the positive voltage is removed from the second gate G2, or a negative voltage is applied, the channel cannot be formed, and the majority carriers (electrons) cannot flow between the second source S2 and the second drain D2. In another embodiment, the semiconductor substrate 250 is, for example, an N-type substrate. In this case, the impurity polarity doped in the first source S1 and the first drain D1 is P-type, and the majority carriers are holes.

[0091] Please refer to Figure 7 , which shows Figure 5 Schematic cross-sectional view of a memory cell and its vertical conductive structure in FIG. In the present embodiment, the first contact 241, the second contact 242 and the third contact 243 may include a suitable conductive material, such as tungsten. The first contact 241 is, for example, a conductive plug, which is electrically connected to the vertically stacked first metal layer M1, and the second contact 242 is, for example, a conductive plug, which can be connected to the vertically stacked first metal layer M1 and the second metal layer M2 via another conductive plug 246, and the first metal layer M1 and the second metal layer M2 are isolated from each other by an insulating layer (not shown). In addition, the third contact 243 is, for example, a conductive plug, and the semiconductor substrate 250 has a substrate conductive structure 247, such as a through silicon via (TSV), which is vertically stacked and electrically connected to the third contact 243, so that the third contact 143 can be electrically connected to the chip (chiplet) of the wafer-level package in the vertical direction through the substrate conductive structure 247 to form a wafer-level three-dimensional IC packaging structure.

[0092] It can be seen that, through the vertical conductive structure, the first contact 241 and the second contact 242 are electrically connected to the first metal layer M1 and the second metal layer M2 of different layers in the vertical direction, respectively, wherein the first metal layer M1 is, for example, the first drain line (i.e., the first wiring 210), and the second metal layer M2 is, for example, the second drain line (i.e., the second wiring 220). The first metal layer M1 and the second metal layer M2 are perpendicular to each other, and the intersection of the first metal layer M1 and the second metal layer M2 is separated by an insulating layer (not shown).

[0093] Figure 8 Draw according to Figure 5 2×2 three-way switch 240 is a top view schematic diagram. Figure 8 , the position of each third contact 243 is represented by the coordinate Z (X, Y), the first gate G1 is connected to a first word line 212, and the second gate G2 is connected to a second word line 222, wherein the first word line 212 and the second word line 222 are not parallel to each other and are located in different conductor layers. Figure 6 , Figure 7 and Figure 8 , the first drain D1 can be connected to a first drain line 211 (i.e., the first wiring 210 or the first metal layer M1) via the first contact 241, and the second drain D2 can be connected to a second drain line 221 (i.e., the second wiring 220 or the second metal layer M2) via the second contact 242, wherein the first drain line 211 and the second drain line 221 are not parallel to each other and are located in different wiring layers. In this embodiment, the first drain line 211 and the second word line 222 are substantially parallel to each other, and the second drain line 221 and the first word line 212 are substantially parallel to each other.

[0094] In addition, please refer to Figure 8 The three-way switches 240 in the same row are arranged along the extension direction of the first wiring 210 and are commonly connected to one of the first wirings 210 , and the three-way switches 240 in the same column are arranged along the extension direction of the second wiring 220 and are commonly connected to one of the second wirings 220 .

[0095] The three-way switch array structure and the switch array substrate based on non-volatile memory of the above-mentioned embodiment of the present invention can be applied to the electronic component configuration carrier to construct a three-dimensional wiring electronic circuit. For the electronic circuit of the memory array, through the three-way switch composed of multiple memory units, the switch array substrate and the chip (chiplet) of the wafer-level package can be stacked and electrically connected in the vertical direction to form a wafer-level three-dimensional IC packaging structure.

[0096] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A three-way switch array structure, wherein: include: N first wirings; M second wirings; N×M third wirings; N×M three-way switches, each of which has a first contact, a second contact, a third contact, a first switch and a second switch, wherein each of the first contacts is disposed on one of the first connections, each of the second contacts is disposed on one of the second connections, each of the third contacts is disposed on one of the third connections, the first switch is disposed between the first contact and the third contact, and the second switch is disposed between the second contact and the third contact, wherein N and M are positive integers greater than or equal to 1; and N terminal switches are respectively arranged on the N first connecting lines.

2. The array structure according to claim 1, wherein: It also includes M terminal switches, which are respectively arranged on the M second wirings.

3. The array structure according to claim 1, wherein: It also includes N×M third switches, which are respectively arranged on the N×M third wirings.

4. A switch array substrate based on non-volatile memory, wherein: include: N first wirings; M second wirings; N×M third wirings; N×M three-way switches, each of which has a first contact, a second contact, a third contact, a first memory unit and a second memory unit, wherein each of the first contacts is disposed on one of the first connections, each of the second contacts is disposed on one of the second connections, each of the third contacts is disposed on one of the third connections, the first memory unit is disposed between the first contact and the third contact, and the second memory unit is disposed between the second contact and the third contact, wherein N and M are positive integers greater than or equal to 1; and A semiconductor substrate is used to set the first wirings, the second wirings, the third wirings and the three-way switches.

5. The substrate according to claim 4, wherein The first memory cell includes a first source, a first drain and a first gate, wherein the first source is connected to the third contact, the first drain is connected to the first contact, and the first gate is connected to a first word line; the second memory cell includes a second source, a second drain and a second gate, wherein the second source is connected to the third contact, the second drain is connected to the second contact, and the second gate is connected to a second word line.

6. The substrate according to claim 4, wherein The first memory unit and the second memory unit are flash memories.

7. The substrate according to claim 5, wherein The first word line and the second word line are not parallel to each other.

8. The substrate according to claim 5, wherein The first word line and the second word line are located in different conductive line layers.

9. The substrate according to claim 5, wherein The first drain is connected to a first drain line, the second drain is connected to a second drain line, and the first drain line and the second drain line are located in different wiring layers.

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