Memory device, method of operating the same, and semiconductor device

Abstract

The present application relates to a memory device, an operation method thereof, and a semiconductor device. A memory device includes: a clock generator that generates a data processing clock signal based on an external clock signal; and an input / output circuit that performs a data transmission / reception operation of transmitting / receiving data to / from an external device based on the data processing clock signal, wherein the clock generator includes a warm-up operation controller that generates a warm-up enable signal for identifying a part of a period of the external clock signal as a dummy signal, and when detecting a pause period in which switching of the external clock signal is temporarily stopped, the warm-up operation controller resets the warm-up enable signal.

Description

Technical Field

[0001] Various embodiments generally relate to an electronic device, and more particularly, to a storage device and a method of operating the storage device. Background Art

[0002] A storage device is configured to store data in response to control of a host device (e.g., a computer or a smart phone). The storage device may include a memory device that stores data and a storage controller that controls the memory device. The memory device may be classified into a volatile memory device and a non-volatile memory device.

[0003] A volatile memory device can hold data as long as power is supplied and can lose the stored data when power is not supplied. Types of the volatile memory device may include a static random access memory (SRAM), a dynamic random access memory (DRAM), and the like.

[0004] A non-volatile memory device does not lose data even when power is not supplied. Types of the non-volatile memory device may include a read only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), and a flash memory. Summary of the Invention

[0005] Various embodiments of the present disclosure relate to a memory device capable of implementing an improved warm-up cycle operation in a data transmission / reception operation.

[0006] According to one embodiment, a memory device may include: a clock generator that generates a data processing clock signal based on an external clock signal; and an input / output circuit that performs a data transmission / reception operation of transmitting / receiving data to / from an external device based on the data processing clock signal, wherein the clock generator includes a warm-up operation controller that generates a warm-up enable signal for identifying a part of a period of the external clock signal as a dummy signal and resets the warm-up enable signal when detecting a pause period in which switching of the external clock signal is temporarily stopped.

[0007] According to one embodiment, a method of operating a memory device to transmit / receive data to / from an external device may include the steps of: receiving an external clock signal; generating a warm-up enable signal to identify a part of a period of the external clock signal as a dummy signal; generating a data processing clock signal based on the warm-up enable signal and the external clock signal; detecting a pause period in which switching of the external clock signal is temporarily stopped; and resetting the warm-up enable signal when detecting the pause period.

[0008] According to one embodiment, a semiconductor device may include: an operation control circuit configured to perform an operation according to a first clock signal; and a clock generation circuit configured to, in response to enabling of a second clock signal, enable a warm-up enable signal at a predetermined amount of time after the enabling to enable the first clock signal, the second clock signal having a leading disable time period and the first clock signal having a trailing disable time period, and disable the warm-up enable signal when the trailing disable time period is detected. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a block diagram showing a storage device according to an embodiment of the present disclosure;

[0010] Figure 2 is a block diagram showing a memory device according to an embodiment of the present disclosure;

[0011] Figure 3 is a block diagram showing a storage block according to an embodiment of the present disclosure;

[0012] Figure 4 is a diagram showing a pattern of an external clock signal according to an embodiment of the present disclosure;

[0013] Figure 5 is a diagram showing a warm-up cycle operation according to an embodiment of the present disclosure;

[0014] Figure 6 is a diagram showing a conventional warm-up cycle operation after a pause period;

[0015] Figure 7 is a timing diagram showing a warm-up cycle operation including a pause period according to an embodiment of the present disclosure;

[0016] Figure 8 is a block diagram showing a clock generator according to an embodiment of the present disclosure;

[0017] Figure 9 is a block diagram showing a pause detector according to an embodiment of the present disclosure;

[0018] Figure 10 is a block diagram showing a counter controller according to an embodiment of the present disclosure;

[0019] Figure 11 is a diagram showing a ring oscillator according to an embodiment of the present disclosure;

[0020] Figure 12 is a timing diagram showing a counter controller according to an embodiment of the present disclosure;

[0021] Figure 13 is a block diagram showing a storage controller according to another embodiment of the present disclosure;

[0022] Figure 14 is a block diagram showing a memory card system according to an embodiment of the present disclosure;

[0023] Figure 15 is a block diagram showing a solid state drive (SSD) system according to an embodiment of the present disclosure; and

[0024] Figure 16 is a block diagram showing a user system according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0025] Descriptions of structures or functions showing embodiments according to concepts disclosed in this specification describe embodiments in terms of how the concepts according to various embodiments can be implemented. The following description does not limit the present invention.

[0026] According to the concepts and embodiments shown in the drawings and described in the specification, various modifications and changes can be applied to the embodiments. However, the various embodiments of the present disclosure are not limited to the disclosure herein and include all changes, equivalents, or alternatives that do not depart from the scope of the present disclosure. When describing those embodiments, descriptions of technologies well-known in the field to which the present disclosure pertains are omitted, and descriptions of technologies not directly related to the present disclosure are omitted.

[0027] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the drawings.

[0028] Figure 1 is a block diagram showing a storage device 1000 according to an embodiment of the present disclosure.

[0029] Referring to Figure 1 , the storage device 1000 may include a memory device 100 and a storage controller 200.

[0030] The storage device 1000 may be configured to store data in response to the control of a host 2000. Examples of the storage device 1000 may include a cellular phone, a smart phone, an MP3 player, a laptop computer, a desktop computer, a game console, a display device, a tablet PC, and an in-vehicle infotainment system.

[0031] The storage device 1000 can be manufactured as one of various types of storage devices according to a host interface corresponding to a communication method with the host 2000. For example, the storage device 1000 can be configured as any one of various types of storage devices, such as a solid state drive (SSD), multimedia cards in the form of MMC, eMMC, RS-MMC, and micro-MMC, secure digital cards in the form of SD, mini-SD, and micro-SD, universal serial bus (USB) storage devices, universal flash storage (UFS) devices, Personal Computer Memory Card International Association (PCMCIA) card-type storage devices, Peripheral Component Interconnect (PCI) card-type storage devices, high-speed PCI (PCI-E) card-type storage devices, compact flash (CF) cards, smart media cards, and / or memory sticks.

[0032] The storage device 1000 can be manufactured as any one of various types of packages. For example, the storage device 1000 can be manufactured in any one of various types of package types, such as a package on package (POP), system in package (SIP), system on chip (SOC), multi-chip package (MCP), chip on board (COB), wafer-level fabricated package (WFP), and wafer-level stacked package (WSP).

[0033] The memory device 100 can store data or utilize the stored data. More specifically, the memory device 100 can operate in response to the control of the storage controller 200. Additionally, the memory device 100 can include a plurality of memory dies, which include a memory cell array having a plurality of memory cells for storing data.

[0034] The memory cells can be single-level cells (SLCs) that store 1 bit of data, multi-level cells (MLCs) that store 2 bits of data, triple-level cells (TLCs) that store 3 bits of data, and quad-level cells (QLCs) that store 4 bits of data.

[0035] The memory cell array can include a plurality of storage blocks. The storage blocks can include a plurality of memory cells. The storage blocks can include a plurality of pages. A page can be a unit for storing data in the memory device 100 or a unit for reading data stored in the memory device 100.

[0036] Examples of the memory device 100 may include Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Low Power Double Data Rate 4 (LPDDR4) SDRAM, Graphics Double Data Rate (GDDR) SDRAM, Low Power DDR (LPDDR), Rambus Dynamic Random Access Memory (RDRAM), NAND flash memory, vertical NAND flash memory, NOR flash memory, Resistive Random Access Memory (RRAM), Phase Change Random Access Memory (PRAM), Magnetoresistive Random Access Memory (MRAM), Ferroelectric Random Access Memory (FRAM), and Spin Transfer Torque Random Access Memory (STT-RAM). For convenience of illustration, it is assumed that the memory device 100 is a NAND flash memory.

[0037] The memory device 100 may receive commands and addresses from the storage controller 200. The memory device 100 may be configured to access a region selected in response to the received address in the memory cell array. When the memory device 100 accesses the selected region, the memory device 100 may perform an operation on the selected region corresponding to the received command. For example, the memory device 100 may perform a write (programming) operation, a read operation, and an erase operation. The programming operation may refer to an operation in which the memory device 100 writes data to a region selected by an address. The read operation may refer to an operation in which the memory device 100 reads data from a region selected by an address. The erase operation may refer to an operation in which the memory device 100 erases data stored in a region selected by an address.

[0038] According to one embodiment, the memory device 100 may include a clock generator 300. The clock generator 300 may receive an external clock signal from an external device (e.g., the storage controller 200 or the host 2000), and may use the received external clock signal to generate an internal clock. The clock generator 300 may generate a data processing clock signal based on the internal clock, and the memory device 100 uses the data processing clock signal when sending / receiving data to / from an external device. The memory device 100 may perform a data sending / receiving operation of sending / receiving data to / from an external device based on the data processing clock signal.

[0039] The storage controller 200 may control general operations of the storage device 1000. More specifically, when power is applied to the storage device 1000, the storage controller 200 may execute firmware FW. The firmware FW may include: a Host Interface Layer (HIL) that receives requests input from the host 2000 or outputs responses to the host 2000; a Flash Translation Layer (FTL) that manages operations between the interface of the host 2000 and the interface of the memory device 100; and a Flash Interface Layer (FIL) that provides commands to the memory device 100 or receives responses from the memory device 100.

[0040] The storage controller 200 can receive data and a logical address LA from the host 2000, and convert the logical address LA into a physical address PA indicating the address of the memory cell storing the data in the memory device 100. The logical address LA may be a logical block address LBA, and the physical address PA may be a physical block address PBA.

[0041] The storage controller 200 can control the memory device 100 to perform a programming operation, a read operation, or an erase operation in response to a request from the host 2000. During the programming operation, the storage controller 200 can provide a programming command, a physical block address, and data to the memory device 100. During the read operation, the storage controller 200 can provide a read command and a physical block address to the memory device 100. During the erase operation, the storage controller 200 can provide an erase command and a physical block address to the memory device 100.

[0042] According to an embodiment of the present disclosure, the storage controller 200 can control the memory device 100 to perform a read operation in response to a read request from the host 2000. Additionally, when the read operation fails, the storage controller 200 can control the memory device 100 to perform a read retry operation to retry the read operation by changing the voltage level of the read voltage.

[0043] The storage controller 200 can control the memory device 100 to perform a programming operation, a read operation, or an erase operation in response to a request from the host 2000 regardless of the request from the host 2000. For example, the storage controller 200 can control the memory device 100 to perform a programming operation, a read operation, or an erase operation during background operations such as wear leveling, garbage collection, and read reclaim.

[0044] The host 2000 can communicate with the storage device 1000 using at least one of various communication methods such as Universal Serial Bus (USB), Serial ATA Attachment (SATA), Serial Attached SCSI (SAS), High-Speed Inter-Chip (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), High-Speed PCI (PCIe), High-Speed Non-Volatile Memory (NVMe), Universal Flash Storage (UFS), Secure Digital (SD), Multimedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and Load-Reduced DIMM (LRDIMM) communication methods.

[0045] Figure 2 is a block diagram showing a memory device 100 according to an embodiment of the present disclosure.

[0046] Referring to Figure 2 , the memory device 100 may include a memory cell array 110, a peripheral circuit 120, and a control logic 130.

[0047] Figure 2 The illustrated memory cell array 110 includes a plurality of memory blocks BLK1 to BLKz. The plurality of memory blocks BLK1 to BLKz can be connected to a row decoder 121 via row lines RL. The row lines RL can include at least one source selection line, a plurality of word lines, and at least one drain selection line. The plurality of memory blocks BLK1 to BLKz can be connected to a page buffer group 123 via bit lines BL1 to BLn. Each of the plurality of memory blocks BLK1 to BLKz can include a plurality of memory cells. According to one embodiment, the plurality of memory cells can be non-volatile memory cells. Memory cells connected to the same word line can be defined as a page. Thus, a memory block can include a plurality of pages.

[0048] The memory cells included in the memory cell array 110 can include single-level cells (SLCs) that store a single data bit, multi-level cells (MLCs) that store two data bits, triple-level cells (TLCs) that store three data bits, or quad-level cells (QLCs) that store four data bits.

[0049] The peripheral circuit 120 can be configured to perform a programming operation, a read operation, or an erase operation on a selected area of the memory cell array 110 in response to the control of the control logic 130. In other words, the peripheral circuit 120 can drive the memory cell array 110 in response to the control logic 130. For example, the peripheral circuit 120 can apply various operating voltages to the row lines RL and the bit lines BL1 to BLn or discharge the applied voltages in response to the control of the control logic 130.

[0050] More specifically, the peripheral circuit 120 can include a row decoder 121, a voltage generator 122, a page buffer group 123, a column decoder 124, an input / output circuit 125, and a sense circuit 126.

[0051] The row decoder 121 can be connected to the memory cell array 110 via the row lines RL. The row lines RL can include at least one source selection line, a plurality of word lines, and at least one drain selection line. According to one embodiment, the word lines can include normal word lines and dummy word lines. Additionally, the row lines RL can further include tube selection lines.

[0052] The row decoder 121 can be configured to operate in response to the control of the control logic 130. The row decoder 121 can receive a row address RADD from the control logic 130. More specifically, the row decoder 121 can be configured to decode the row address RADD. The row decoder 121 can select at least one memory block among the memory blocks BLK1 to BLKz according to the decoded address. The row decoder 121 can select at least one word line WL of the selected memory block according to the decoded address to apply the voltage generated by the voltage generator 122 to the at least one word line WL.

[0053] In one embodiment, during a programming operation, the row decoder 121 may apply a programming voltage to a selected word line and apply a pass voltage having a voltage level lower than the programming voltage to unselected word lines. During a programming verification operation, the row decoder 121 may apply a verification voltage to a selected word line and apply a pass voltage greater than the verification voltage to unselected word lines. During a read operation, the row decoder 121 may apply a read voltage to a selected word line and apply a pass voltage greater than the read voltage to unselected word lines.

[0054] According to one embodiment, an erase operation of the memory cell array 110 may be performed in units of at least one memory block. During the erase operation, the row decoder 121 may select one of the memory blocks according to the decoded address, and the row decoder 121 may apply a ground voltage to the word lines coupled to the selected memory block.

[0055] The voltage generator 122 may operate in response to the control of the control logic 130. More specifically, the voltage generator 122 may be configured to generate a plurality of voltages in response to the control logic 130 using an external power supply voltage supplied to the memory device 100. For example, the voltage generator 122 may generate a programming voltage, a verification voltage, a pass voltage, a read voltage, and an erase voltage in response to the control of the control logic 130. In other words, the voltage generator 122 may generate various operation voltages Vop for programming operations, read operations, and erase operations in response to an operation signal OPSIG.

[0056] According to one embodiment, the voltage generator 122 may generate an internal power supply voltage by adjusting the external power supply voltage. The internal power supply voltage generated by the voltage generator 122 may be used as an operation voltage of the memory cell array 110.

[0057] According to one embodiment, the voltage generator 122 may generate a plurality of voltages using an external power supply voltage or an internal power supply voltage. For example, the voltage generator 122 may include a plurality of pumping capacitors that receive the internal power supply voltage, and generate a plurality of voltages by selectively enabling the plurality of pumping capacitors in response to the control of the control logic 130. The generated plurality of voltages may be supplied to the memory cell array 110 through the row decoder 121.

[0058] The page buffer group 123 may include a first page buffer PB1 to an nth page buffer PBn. The first page buffer PB1 to the nth page buffer PBn may be respectively connected to the memory cell array 110 through a first bit line BL1 to an nth bit line BLn. The first page buffer PB1 to the nth page buffer PBn may operate in response to the control of the control logic 130. More specifically, the first page buffer PB1 to the nth page buffer PBn may operate in response to a page buffer control signal PBSIGNALS. For example, the first page buffer PB1 to the nth page buffer PBn may temporarily store data received through the first bit line BL1 to the nth bit line BLn, or may sense a voltage or current in the first bit line BL1 to the nth bit line BLn during a read operation or a verify operation.

[0059] During a programming operation, when a programming pulse is applied to a selected word line during the programming operation, the first page buffer PB1 to the nth page buffer PBn may transfer data DATA received through the input / output circuit 125 to the selected memory cells through the first bit line BL1 to the nth bit line BLn. The memory cells of the selected page may be programmed according to the transferred data DATA. Memory cells connected to a bit line to which a programming enable voltage (e.g., a ground voltage) is applied may have an increased threshold voltage. The threshold voltage of memory cells connected to a bit line to which a programming inhibit voltage (e.g., a power supply voltage) is applied may be maintained.

[0060] During a programming verify operation, the first page buffer PB1 to the nth page buffer PBn may respectively read page data from the selected memory cells through the first bit line BL1 to the nth bit line BLn.

[0061] During a read operation, in response to the control of the column decoder 124, the first page buffer PB1 to the nth page buffer PBn may read data DATA from the memory cells of the selected page through the first bit line BL1 to the nth bit line BLn, and may output the read data DATA to the data input / output circuit 125.

[0062] During an erase operation, the first page buffer PB1 to the nth page buffer PBn may float the first bit line BL1 to the nth bit line BLn.

[0063] The column decoder 124 may transfer data between the input / output circuit 125 and the page buffer group 123 in response to a column address CADD. For example, the column decoder 124 may exchange data with the first page buffer PB1 to the nth page buffer PBn through a data line DL, or may exchange data with the input / output circuit 125 through a column line CL.

[0064] The input / output circuit 125 can transfer the command CMD and the address ADDR from the memory controller 200 to the control logic 130, or can exchange data DATA with the column decoder 124.

[0065] During a read operation or a verify operation, the sense circuit 126 can generate a reference current in response to the verify bit signal VRYBIT and compare the sense voltage VPB received from the page buffer bank 123 with the reference voltage generated by the reference current to output a pass signal PASS or a fail signal FAIL.

[0066] The control logic 130 can control the peripheral circuit 120 by outputting operation signals OPSIG, row address RADD, page buffer control signals PBSIGNALS, and verify bit signal VRYBIT in response to the command CMD and the address ADDR.

[0067] In addition, the control logic 130 can determine whether the verify operation passes or fails in response to the pass signal PASS or the fail signal FAIL. In addition, the control logic 130 can control the page buffer bank 123 to temporarily store the verify operation including the pass signal PASS or the fail signal FAIL in the page buffer bank 123. More specifically, the control logic 130 can determine the programming state of the memory cells in response to the pass signal PASS or the fail signal FAIL. For example, when the memory cells operate as triple-level cells (TLCs), the control logic 130 can determine whether the programming state of the memory cells is an erased state E or one of the first programming state P1 to the seventh programming state P7.

[0068] Figure 3 is a block diagram showing a memory block BLKi according to an embodiment of the present disclosure.

[0069] Referring to Figure 3 , the memory block BLKi can be coupled to a plurality of word lines arranged in parallel between a first selection line and a second selection line. The first selection line can be a source selection line SSL, and the second selection line can be a drain selection line DSL. Specifically, the memory block BLKi can include a plurality of strings ST coupled between bit lines BL1 to BLn and a source line SL. The bit lines BL1 to BLn can be respectively coupled to the strings ST, and the source line SL can be commonly coupled to the strings ST. Since the strings ST can have the same configuration, the string ST coupled to the first bit line BL1 will be described in detail as an example.

[0070] The string ST can include a source selection transistor SST, a plurality of memory cells F1 to F16, and a drain selection transistor DST connected in series between the source line SL and the first bit line BL1. Each string ST can include at least one source selection transistor SST, at least one drain selection transistor DST, and more Figure 3The number of memory cells F1 to F16 shown must be more memory cells.

[0071] The source of the source selection transistor SST may be connected to the source line SL, and the drain of the drain selection transistor DST may be connected to the first bit line BL1. The memory cells F1 to F16 may be connected in series between the source selection transistor SST and the drain selection transistor DST. The gates of the source selection transistors SST included in different strings ST may be connected to the source selection line SSL, the gates of the drain selection transistors DST may be connected to the drain selection line DSL, and the gates of the memory cells F1 to F16 may be connected to the plurality of word lines WL1 to WL16. A group of memory cells connected to the same word line among the memory cells included in different strings ST may be referred to as a physical page PPG. Therefore, the memory block BLKi may include as many physical pages PPG as the number of word lines WL1 to WL16.

[0072] The memory cell may be a single-level cell (SLC) that stores 1-bit data, a multi-level cell (MLC) that stores 2-bit data, a triple-level cell (TLC) that stores 3-bit data, and a quad-level cell (QLC) that stores 4-bit data.

[0073] The single-level cell (SCL) may include one-bit data. One physical page PPG of the single-level cell may store one logical page (LPG) data. One LPG data may include as many data bits as the number of cells included in one physical page PPG.

[0074] The multi-level cell (MLC), triple-level cell (TLC), and quad-level cell (QLC) may store two or more bits of data. One physical page PPG may store data corresponding to two or more logical pages LPG.

[0075] Figure 4 It is a diagram showing a pattern of an external clock signal according to an embodiment of the present disclosure.

[0076] Figure 4 The first external clock signal 41 and the second external clock signal 42 are shown. The memory device 100 may generate a data processing clock signal based on the external clock signal input from an external device. The external clock signal may be input in the form of a digital signal that repeatedly switches between 0 and 1 and includes a pause period during which the switching is temporarily stopped.

[0077] For example, the first external clock signal 41 may be input in the form of a digital signal that repeatedly switches between 0 and 1. In addition, the second external clock signal 42 may be input in the form of a digital signal that repeatedly switches and includes a pause period during which the switching is temporarily stopped.

[0078] Figure 5 FIG. is a diagram showing a warm-up cycle operation according to an embodiment of the present disclosure.

[0079] Referring to Figure 5 , the first signal set 51 may include a first data processing clock signal CLK_DP1, and the second signal set 52 may include a second data processing clock signal CLK_DP2. As Figure 5 shown, the first data processing clock signal CLK_DP1 included in the first signal set 51 may be generated based on an external clock signal EXT_CLK1. In the first signal set 51, after the external clock signal EXT_CLK1 is input, the first data processing clock signal CLK_DP1 may be generated without intentional delay. In other words, the first signal set 51 may correspond to a general clock operation that does not include a warm-up cycle operation.

[0080] On the other hand, the second data processing clock signal CLK_DP2 included in the second signal set 52 may be generated in response to a warm-up enable signal WARM_EN. More specifically, in the second signal set 52, the external clock signal EXT_CLK2 may be recognized as a dummy signal until the warm-up enable signal WARM_EN is applied, and the second data processing clock signal CLK_DP2 may be generated based on the external clock signal EXT_CLK2 after the warm-up enable signal WARM_EN is applied.

[0081] As the data exchange rate between the memory device 100 and the external device increases, signal integrity problems occur. When the clock switches at a high rate, due to channel effects, especially in the early stage, signal integrity problems may become problematic. The memory device 100 may recognize the clock switch during the initial period as a dummy to avoid signal integrity problems. In other words, the warm-up cycle operation may control the memory device 100 such that a part of the period of the external clock signal may be ignored. In addition, the memory device 100 may prevent signal integrity problems caused by channel effects in the early stage when the external clock switches through the warm-up cycle operation.

[0082] Figure 6 FIG. is a diagram showing a conventional warm-up cycle operation after a pause period.

[0083] Figure 6Shows the data processing clock signal CLK_DP generated according to a conventional method when the external clock signal EXT_CLK resumes after a pause period. More specifically, when the external clock signal EXT_CLK is input to a conventional memory device, the conventional memory device may recognize the external clock signal EXT_CLK input before the warm enable signal WARM_EN is input as a dummy signal. However, according to the conventional method, after a pause period during which the switching operation of the external clock signal EXT_CLK is temporarily stopped, there may be no signal and configuration for resetting the warm enable signal WARM_EN. Therefore, since the warm enable signal WARM_EN remains enabled after performing the warm-up cycle operation, signal integrity problems may occur.

[0084] Figure 7 Is a timing diagram showing a warm-up cycle operation including a pause period according to an embodiment of the present disclosure.

[0085] Refer to Figure 7 , shows a timing diagram of the external clock signal EXT_CLK, the internal clock signal INT_CLK, the warm enable signal WARM_EN, the data processing clock signal CLK_DP, the count enable signal CNT_EN, the count check signal CNT_CHK, and the warm reset signal RST_PAUSE.

[0086] First, when the memory device 100 receives the external clock signal EXT_CLK from an external clock, the memory device 100 may provide the internal clock signal INT_CLK into the memory device 100 based on the external clock signal EXT_CLK. Additionally, the memory device 100 may generate the warm enable signal WARM_EN after a predetermined period of time.

[0087] Additionally, the memory device 100 may generate the internal clock signal INT_CLK based on the external clock signal EXT_CLK. As Figure 7 shown, the internal clock signal INT_CLK may be a delayed version of the external clock signal EXT_CLK, so the pause period of the internal clock signal INT_CLK may lag behind the pause period of the external clock signal EXT_CLK. More specifically, the memory device 100 may generate the data processing clock signal CLK_DP according to the internal clock signal INT_CLK and the warm enable signal WARM_EN. As Figure 7As shown, the data processing clock signal CLK_DP may be a delayed version of the internal clock signal INT_CLK. Therefore, the pause period of the data processing clock signal CLK_DP may lag behind the pause period of the external clock signal EXT_CLK. When generating the data processing clock signal CLK_DP, the memory device 100 may generate a count enable signal CNT_EN. The memory device 100 may count the number of transitions of the data processing clock signal CLK_DP in response to the count enable signal CNT_EN. More specifically, the memory device 100 may detect the edges of the data processing clock signal CLK_DP to count the number of transitions of the data processing clock signal CLK_DP. The memory device 100 may check the status of the data processing clock signal CLK_DP by comparing the number of transitions of the data processing clock signal CLK_DP counted every predetermined period (e.g., the period of the count check signal CNT_CHK) with a predetermined number.

[0088] In addition, when the data processing clock signal CLK_DP is in a paused state, the memory device 100 may generate a warm reset signal RST_PAUSE and disable the count enable signal CNT_EN. More specifically, when the number of transitions of the data processing clock signal CLK_DP is greater than or equal to a predetermined number, the memory device 100 may keep the warm enable signal WARM_EN and the count enable signal CNT_EN enabled. On the other hand, when the number of transitions of the data processing clock signal CLK_DP is less than the predetermined number, the memory device 100 may generate a warm reset signal RST_PAUSE and disable the count enable signal CNT_EN. In other words, when the data processing clock signal CLK_DP is in a paused state that temporarily stops the transitions of the data processing clock signal CLK_DP, the memory device 100 may reset (i.e., disable) the warm enable signal WARM_EN and the count enable signal CNT_EN.

[0089] Thereafter, when the external clock signal EXT_CLK is detected, the memory device 100 may perform a warm-up cycle operation in the same manner.

[0090] Figure 8 is a block diagram showing a clock generator 300 according to an embodiment of the present disclosure.

[0091] Referring to Figure 8 , the clock generator 300 may include a warm-up operation controller 310 and a pause detector 320.

[0092] The clock generator 300 can generate a data processing clock signal CLK_DP based on an external clock signal EXT_CLK input from an external clock. More specifically, the clock generator 300 can include a receiver. The receiver can receive the external clock signal EXT_CLK from the external clock. The receiver can transmit an internal clock signal INT_CLK (based on the external clock signal EXT_CLK) to the warm-up operation controller 310 and the AND operator.

[0093] When detecting the internal clock signal INT_CLK, the warm-up operation controller 310 can generate a warm-up enable signal WARM_EN. More specifically, after a predetermined amount of time has passed since receiving the internal clock signal INT_CLK from the receiver, the warm-up operation controller 310 can generate the warm-up enable signal WARM_EN. The generated warm-up enable signal WARM_EN can be provided to the AND operator. Based on the internal clock signal INT_CLK and the warm-up enable signal WARM_EN, the AND operator can output the data processing clock signal CLK_DP. That is, when the warm-up enable signal WARM_EN is enabled, the AND operator can output the internal clock signal INT_CLK as the data processing clock signal CLK_DP.

[0094] The pause detector 320 can receive the data processing clock signal CLK_DP and determine whether there is a pause period that temporarily stops the switching of the data processing clock signal CLK_DP based on the received data processing clock signal CLK_DP. Additionally, when the pause detector 320 determines that there is a pause period, the pause detector 320 can transmit a warm-up reset signal RST_PAUSE to the warm-up operation controller 310.

[0095] The warm-up operation controller 310 may reset the warm-up cycle operation based on the warm-up reset signal RST_PAUSE received from the pause detector 320. More specifically, when the warm-up operation controller 310 receives the warm-up reset signal RST_PAUSE from the pause detector 320, the warm-up operation controller 310 may disable the warm-up enable signal WARM_EN. The warm-up reset signal RST_PAUSE may control the warm-up operation controller 310 to reset (i.e., disable) the warm-up enable signal WARM_EN. Additionally, when the warm-up operation controller 310 detects that the internal clock signal INT_CLK resumes toggling after its pause period while the warm-up enable signal WARM_EN remains disabled, the warm-up operation controller 310 may generate (i.e., enable) the warm-up enable signal WARM_EN and may execute the warm-up cycle operation again. In other words, when the external clock signal EXT_CLK resumes toggling after its pause period, the warm-up operation controller 310 may generate an enabled warm-up enable signal WARM_EN, and the clock generator 300 may resume toggling the data processing clock signal CLK_DP after its pause period. That is, the warm-up cycle operation may be performed on the resumed external clock signal EXT_CLK to resume the data processing clock signal CLK_DP after its pause period. In other words, the clock generator 300 may recognize an initial section of the resumed external clock signal EXT_CLK as a dummy signal. Here, the initial section may be at least the sum of the amount of time for which the receiver transmits the external clock signal EXT_CLK as the internal clock signal INT_CLK to the warm-up operation controller 310 and a predetermined amount of time for which the warm-up operation controller 310 generates the warm-up enable signal WARM_EN in response to the internal clock signal INT_CLK.

[0096] Figure 9 is a block diagram showing a pause detector 320 according to an embodiment of the present disclosure.

[0097] Referring to Figure 9 , the pause detector 320 may include a counter 321, a counter controller 323, and a comparator 325.

[0098] When the input count enable signal CNT_EN is received, the counter 321 may count the number of toggles of the data processing clock signal CLK_DP. Additionally, the counter 321 may output a result CNT representing the counted number of toggles of the data processing clock signal CLK_DP <n:0>Transferred to comparator 325.

[0099] When the data processing clock signal CLK_DP is detected, the counter controller 323 may generate a count enable signal CNT_EN so that the counter 321 can detect the transitions of the data processing clock signal CLK_DP. The counter controller 323 may transfer the generated count enable signal CNT_EN to the counter 321 and may control the counter 321 to count the transitions of the data processing clock signal CLK_DP. Additionally, the counter controller 323 may generate a count check signal CNT_CHK having a predetermined time period. The count check signal CNT_CHK may be used to check the result CNT representing the number of transitions of the counted data processing clock signal CLK_DP <n:0>The change. Additionally, the counter controller 323 can transmit a count check signal CNT_CHK to the comparator 325.

[0100] The comparator 325 can detect the pause period. More specifically, the comparator 325 can receive a result CNT representing the number of switching times of the counted data processing clock signal CLK_DP from the counter 321 <n:0>In addition, the comparator 325 can receive a count check signal CNT_CHK having a predetermined time period. The comparator 325 can compare the count result CNT every predetermined time period <n:0>Compare with a predetermined number of times. Additionally, the comparator 325 can use the count result CNT <n:0>Detect the pause period. More specifically, when the count result CNT <n:0>When the value is less than a predetermined number of times, the comparator 325 may generate a warm reset signal RST_PAUSE. For example, when the predetermined number of times is twenty (20), each time the comparator 325 receives a count check signal CNT_CHK at respective predetermined time intervals, the comparator 325 may count the result CNT representing the number of switching times of the data processing clock signal CLK_DP <n:0>is compared with a predetermined number (i.e., twenty). When the result CNT representing the number of switching times of the data processing clock signal CLK_DP being counted <n:0>When it is greater than or equal to 20, the comparator 325 can determine that the data processing clock signal CLK_DP is switching. On the other hand, when the result CNT representing the number of switching times of the counted data processing clock signal CLK_DP <n:0>When it is less than 20, the comparator 325 can determine that there is a pause period of the data processing clock signal CLK_DP. When there is a pause period of the data processing clock signal CLK_DP, the comparator 325 can generate a warm reset signal RST_PAUSE.

[0101] Figure 10 is a block diagram showing a counter controller 323 according to an embodiment of the present disclosure.

[0102] Referring to Figure 10 , the counter controller 323 can generate a count enable signal CNT_EN and a count check signal CNT_CHK. More specifically, when the data processing clock signal CLK_DP is detected, the counter controller 323 can use the enable controller ENABLE CNTL to generate the count enable signal CNT_EN. In addition, the counter controller 323 can use the ring oscillator 324 to determine the period of the count check signal CNT_CHK. The counter controller 323 can use the signal generator PLS GEN to generate the count check signal CNT_CHK. The count check signal CNT_CHK can be used to check the result of counting the data processing clock signal CLK_DP (CNT <n:0>) changes.

[0103] Figure 11 FIG. is a diagram showing a ring oscillator according to an embodiment of the present disclosure.

[0104] Referring to Figure 11 , the ring oscillator 324 may include a plurality of inverters. The plurality of inverters may form a chain. The number of inverters may be set according to a required period of the count check signal CNT_CHK. When the count enable signal CNT_EN is input to the ring oscillator 324, the ring oscillator 324 may generate an oscillator signal OSC_OUT having a predetermined period. In addition, the oscillator signal OSC_OUT may be transmitted to the signal generator PLS GEN, and the signal generator PLS GEN may generate a count check signal CNT_CHK based on the oscillator signal OSC_OUT.

[0105] Figure 12 FIG. is a timing diagram showing a counter controller 323 according to an embodiment of the present disclosure.

[0106] Figure 12 FIG. is a timing diagram of a data processing clock signal CLK_DP, a count enable signal CNT_EN, an oscillator signal OSC_OUT, and a count check signal CNT_CHK.

[0107] First, when the data processing clock signal CLK_DP switches, the count enable signal CNT_EN may be enabled. After the count enable signal CNT_EN is enabled, an oscillator signal OSC_OUT having a predetermined period may be generated by the operation of the ring oscillator 324. The oscillator signal OSC_OUT may be transmitted to the signal generator PLS GEN, and the signal generator PLS GEN may detect each edge (e.g., rising edge and falling edge) of the oscillator signal OSC_OUT and generate a count check signal CNT_CHK at each edge. In other words, whenever the digital value of the oscillator signal OSC_OUT changes from 0 to 1 or from 1 to 0 (i.e., at each check period), the signal generator PLS GEN may generate a count check signal CNT_CHK. The count check signal CNT_CHK generated by the signal generator PLS GEN at each check period may be transmitted to the comparator 325. The comparator 325 may check the number of switches of the data processing clock signal CLK_DP at each check period.

[0108] Figure 13 FIG. is a block diagram showing a storage controller 1300 according to another embodiment of the present disclosure.

[0109] Referring to Figure 13 , the storage controller 1300 may include a processor 1310, a RAM 1320, an ECC circuit 1330, a ROM 1360, a host interface 1370, and a flash memory interface 1380.

[0110] The processor 1310 may communicate with the host 2000 using the host interface 1370 and perform logical operations to control the operation of the storage controller 1300. For example, the processor 1310 may load program commands, data files, data structures, etc. based on requests from the host 2000 or another external device, and may perform various operations or generate commands or addresses. For example, the processor 1310 may generate various commands for programming operations, read operations, erase operations, pause operations, and parameter setting operations.

[0111] In addition, the processor 1310 may function as a flash translation layer FTL. The processor 1310 may convert a logical block address LBA provided by the host 2000 into a physical block address PBA through the flash translation layer FTL. The flash translation layer FTL may receive the logical block address LBA and use a mapping table to convert the logical block address LBA into a physical block address PBA. Based on the mapping unit, there may be various address mapping methods of the flash translation layer FTL. Typical address mapping methods may include a page mapping method, a block mapping method, and a hybrid mapping method.

[0112] According to one embodiment, the processor 1310 may generate commands without a request from the host 2000. For example, the processor 1310 may generate commands for background operations (e.g., wear leveling operations of the memory device 100 and garbage collection operations of the memory device 100).

[0113] The RAM 1320 may be used as a buffer memory, a working memory, or a cache memory of the processor 1310. In addition, the RAM 1320 may store the code and commands executed by the processor 1310. The RAM 1320 may store the data processed by the processor 1310. In addition, the RAM 1320 may be implemented using static RAM (SRAM) or dynamic RAM (DRAM).

[0114] The ECC circuit 1330 may detect errors and correct errors during programming operations or read operations. More specifically, the ECC circuit 1330 may perform error correction operations according to an error correction code (ECC). In addition, the ECC circuit 1330 may perform ECC encoding based on the data to be written to the memory device 100. The ECC-encoded data may be transmitted to the memory device 100 through the flash memory interface 1380. In addition, the ECC circuit 1330 may perform ECC decoding on the data transmitted from the memory device 100 through the flash memory interface 1380.

[0115] The ROM 1360 can be used as a storage unit for storing various types of information for the operation of the storage controller 1300. More specifically, the ROM 1360 may include a mapping table storing physical-logical address information and logical-physical address information. Additionally, the ROM 1360 can be controlled by the processor 1310.

[0116] The host interface 1370 may include a protocol for exchanging data between the host 2000 and the storage controller 1300. More specifically, the host interface 1370 can communicate with the host 2000 through one or more various protocols such as Universal Serial Bus (USB) protocol, Multimedia Card (MMC) protocol, Peripheral Component Interconnect (PCI) protocol, High-Speed PCI (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer System Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, proprietary protocol, etc.

[0117] The processor 1310 can control the flash interface 1380 to communicate with the memory device 100 using a communication protocol. More specifically, the flash interface 1380 can send / receive commands, addresses, and data to / from the memory device 100 through channels. For example, the flash interface 1380 may include a NAND interface.

[0118] Figure 14 is a block diagram showing a memory card system 3000 according to an embodiment of the present disclosure.

[0119] Refer to Figure 14 , the memory card system 3000 may include a storage controller 3100, a memory device 3200, and a connector 3300.

[0120] The storage controller 3100 may be coupled to the memory device 3200. The storage controller 3100 can access the memory device 3200. For example, the storage controller 3100 can control read operations, programming operations, erase operations, and background operations of the memory device 3200. The storage controller 3100 can be configured to provide an interface between the memory device 3200 and the host. The storage controller 3100 can be configured to drive firmware for controlling the memory device 3200.

[0121] In an embodiment, the storage controller 3100 may include components such as a Random Access Memory (RAM), a processing unit, a host interface, a flash interface, and an ECC circuit.

[0122] The storage controller 3100 can communicate with an external device through the connector 3300. The storage controller 3100 can communicate with an external device (e.g., a host) based on a specific communication protocol. In an embodiment, the storage controller 3100 can communicate with an external device through at least one of various communication protocols such as Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), High-Speed PCI (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Storage (UFS), Wi-Fi, Bluetooth, and High-Speed Non-Volatile Memory (NVMe) protocol. In one embodiment, the connector 3300 can be defined by at least one of the above various communication protocols.

[0123] In one embodiment, the memory device 3200 can be implemented as any one of various non-volatile memory devices such as Electrically Erasable Programmable ROM (EEPROM), NAND flash memory, NOR flash memory, Phase Change RAM (PRAM), Resistive RAM (ReRAM), Ferroelectric RAM (FRAM), Spin Transfer Torque Magnetic RAM (STT-MRAM).

[0124] In one embodiment, the memory device 3200 and the storage controller 3100 can be integrated into a single semiconductor device to form a memory card. For example, the storage controller 3100 and the memory device 3200 can be integrated into a single semiconductor device and form a memory card such as Personal Computer Memory Card International Association (PCMCIA), CompactFlash (CF) card, SmartMedia card (SM or SMC), Memory Stick, Multimedia Card (MMC, RS-MMC or MMCmicro), SD card (SD, miniSD, microSD or SDHC), Universal Flash Storage (UFS), etc.

[0125] Figure 15 is a block diagram showing a Solid State Drive (SSD) system 4000 according to an embodiment of the present disclosure.

[0126] Referring to Figure 15 , the SSD system 4000 can include a host 4100 and an SSD 4200. The SSD 4200 can exchange signals SIG with the host 4100 through the signal connector 4001, and can receive power PWR through the power connector 4002. The SSD 4200 can include an SSD controller 4210, a plurality of flash memories 4221 to 422n, an auxiliary power supply 4230, and a buffer memory 4240.

[0127] In one embodiment, the SSD controller 4210 may perform the functions of the storage controller 200 as described above with reference to Figure 13 . The SSD controller 4210 may control the plurality of flash memories 4221 to 422n in response to a signal SIG received from the host 4100. In one embodiment, the signal SIG may be based on the interface between the host 4100 and the SSD 4200. For example, the signal SIG may be defined by at least one of various interfaces such as Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), High-Speed PCI (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Storage (UFS), Wi-Fi, Bluetooth, and High-Speed Non-Volatile Memory (NVMe) interface.

[0128] In one embodiment, the auxiliary power supply 4230 may be connected to the host 4100 through a power connector 4002. The auxiliary power supply 4230 may be supplied with power PWR from the host 4100 and charged therewith. When the power PWR is not smoothly supplied from the host 4100, the auxiliary power supply 4230 may supply power to the SSD 4200. In one embodiment, the auxiliary power supply 4230 may be disposed inside or outside the SSD 4200. For example, the auxiliary power supply 4230 may be in the motherboard and may supply auxiliary power to the SSD 4200.

[0129] The buffer memory 4240 may be used as the buffer memory of the SSD 4200. For example, the buffer memory 4240 may temporarily store data received from the host 4100 or data received from the plurality of flash memories 4221 to 422n, or may temporarily store metadata (e.g., mapping table) of the flash memories 4221 to 422n. The buffer memory 4240 may include volatile memories such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM, or non-volatile memories such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0130] Figure 16 is a block diagram showing a user system 5000 according to an embodiment of the present disclosure.

[0131] Referring to Figure 16 , the user system 5000 may include an application processor 5100, a memory module 5200, a network module 5300, a storage module 5400, and a user interface 5500.

[0132] The application processor 5100 can run components, an operating system (OS), or user programs included in the user system 5000. In one embodiment, the application processor 5100 can include a controller, an interface, a graphics engine, etc. for controlling components included in the user system 5000. The application processor 5100 can be provided as a system-on-chip (SoC).

[0133] The memory module 5200 can be used as the main memory, working memory, buffer memory, or cache memory of the user system 5000. The memory module 5200 can include volatile RAM such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDRAM, LPDDR2 SDRAM, and LPDDR3 SDRAM, or non-volatile RAM such as PRAM, ReRAM, MRAM, and FRAM. In one embodiment, the application processor 5100 and the memory module 5200 can be packaged based on a package-on-package (PoP), and then provided as a single semiconductor package.

[0134] The network module 5300 can communicate with external devices. For example, the network module 5300 can support wireless communications such as code division multiple access (CDMA), global system for mobile communications (GSM), wideband CDMA (WCDMA), CDMA-2000, time division multiple access (TDMA), long term evolution (LTE), Wimax, WLAN, UWB, Bluetooth, or Wi-Fi communications. In one embodiment, the network module 5300 can be included in the application processor 5100.

[0135] The storage module 5400 can store data. For example, the storage module 5400 can store data received from the application processor 5100. Alternatively, the storage module 5400 can send the data stored in the storage module 5400 to the application processor 5100. In one embodiment, the storage module 5400 can be implemented as a non-volatile semiconductor memory device such as phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), NAND flash memory, NOR flash memory, or NAND flash memory having a three-dimensional (3D) structure. In one embodiment, the storage module 5400 can be provided as a removable storage medium (i.e., a removable drive) such as an external drive or a memory card of the user system 5000.

[0136] For example, the storage module 5400 can include a plurality of non-volatile memory devices, and the plurality of non-volatile memory devices can operate in the same manner as the memory device 100 described above with reference to Figure 1 The storage module 5400 can operate in the same manner as described above with reference to Figure 1 operates in the same manner as the described storage device 1000.

[0137] The user interface 5500 may include an interface for inputting data or commands to the application processor 5100 or outputting data to an external device. In one embodiment, the user interface 5500 may include one or more user input interfaces such as a keyboard, keypad, buttons, touch panel, touch screen, touchpad, touch ball, camera, microphone, gyro sensor, vibration sensor, and piezoelectric device. The user interface 5500 may also include one or more user output interfaces such as, for example, a liquid crystal display (LCD), organic light emitting diode (OLED) display device, active matrix OLED (AMOLED) display device, LED, speaker, and monitor.

[0138] According to one embodiment of the present disclosure, a warm-up cycle operation for improved data transmission / reception operations may be implemented.

[0139] In the above embodiments, all steps may be selectively performed or skipped. Additionally, the steps in each embodiment may not always be performed in a conventional order. Furthermore, although the embodiments disclosed in this specification and the drawings provide a clear understanding of the present disclosure to those of ordinary skill in the art, the present invention is not limited to the scope of the present disclosure. In other words, those of ordinary skill in the art to which the present disclosure pertains will understand that various modifications of the present invention are possible based on the technical scope of the present disclosure. It will be apparent to those skilled in the art that various modifications of the above embodiments of the present disclosure may be made without departing from the spirit or scope of the present invention. Accordingly, the present disclosure encompasses all such modifications.

[0140] Cross - reference to related applications

[0141] This application claims the priority of Korean Patent Application No. 10 - 2021 - 0017016, filed on February 5, 2021, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference.

Claims

1. A memory device, the memory device comprising: A clock generator that generates a data processing clock signal based on an external clock signal; And An input / output circuit that performs data transmission / reception operations of transmitting / receiving data to / from an external device based on the data processing clock signal, Wherein, the clock generator includes a warm-up operation controller that generates a warm-up enable signal for identifying a part of a period of the external clock signal as a dummy signal, and when detecting a pause period in which the switching of the external clock signal is temporarily stopped, the warm-up operation controller resets the warm-up enable signal.

2. The memory device according to claim 1, wherein The clock generator further includes a pause detector that detects the pause period based on the data processing clock signal.

3. The memory device according to claim 2, wherein, The pause detector includes: A counter that counts the number of times of switching of the data processing clock signal according to a counter enable signal; and A counter controller that generates the counter enable signal when detecting the data processing clock signal.

4. The memory device according to claim 3, Among them, The counter controller further generates a count check signal having a predetermined period, and Wherein, the pause detector detects whether there is the pause period according to the predetermined period.

5. The memory device according to claim 3, wherein, When detecting the pause period, the counter controller further disables the counter enable signal.

6. The memory device according to claim 3, wherein, The pause detector further includes a comparator that compares the number of times of switching of the data processing clock signal with a predetermined number to detect the pause period.

7. The memory device according to claim 6, wherein, When detecting the pause period, the comparator further generates a warm-up reset signal for the warm-up operation controller to reset the warm-up enable signal in response to the warm-up reset signal.

8. The memory device according to claim 1, wherein, When the input of the external clock signal is restored, the clock generator identifies a part of the restored external clock signal as the dummy signal.

9. The memory device according to claim 8, wherein, The warm-up operation controller generates the warm-up enable signal to identify a part of the restored external clock signal as the dummy signal.

10. The memory device according to claim 1, wherein, The part of the period corresponds to a predetermined time interval after the external clock signal is input to the clock generator.

11. A method of operating a memory device to transmit / receive data to / from an external device, the method comprising the following steps: Receiving an external clock signal; Generating a warm-up enable signal to identify a part of a period of the external clock signal as a dummy signal; Generating a data processing clock signal based on the warm-up enable signal and the external clock signal; Detecting a pause period in which the switching of the external clock signal is temporarily stopped; And When detecting the pause period, resetting the warm-up enable signal.

12. The method according to claim 11, wherein, The step of detecting the pause period includes: detecting the pause period based on the data processing clock signal.

13. The method according to claim 12, wherein, The step of detecting the pause period includes: When detecting the data processing clock signal, generating a count enable signal; and Counting the number of times of switching of the data processing clock signal according to the count enable signal.

14. The method according to claim 13, wherein, The step of detecting the pause period further includes: detecting whether there is the pause period according to a predetermined period.

15. The method according to claim 13, wherein, The step of detecting the pause period further includes: disabling the count enable signal when the pause period is detected.

16. The method according to claim 11, wherein, The pause period is detected by comparing the number of switching times of the data processing clock signal with a predetermined number.

17. The method according to claim 11, wherein, The step of resetting the warm-up enable signal includes: generating a warm-up reset signal to reset the warm-up enable signal when the pause period is detected.

18. The method according to claim 11, the method further comprising: When the input of the external clock signal is resumed after the pause period, a warm-up enable signal is generated to identify a part of the resumed external clock signal period as the dummy signal.

19. The method according to claim 11, wherein, The part of the period corresponds to a predetermined time interval after the external clock signal is input to the memory device.

20. A semiconductor device, the semiconductor device comprising: an operation control circuit that performs operations according to a first clock signal; and a clock generation circuit that: in response to the enabling of a second clock signal, enables a warm-up enable signal at a predetermined amount of time after the enabling to enable the first clock signal, the second clock signal having a leading disable time period and the first clock signal having a lagging disable time period; and disables the warm-up enable signal when the lagging disable time period is detected.

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