Integrated circuits, memory circuits, methods for forming integrated circuits and memory circuits

Abstract

This application relates to integrated circuits, memory circuits, methods for forming integrated circuits, and methods for forming memory circuits. A method for forming an integrated circuit includes forming horizontally spaced conductive vias above a substrate. A conductive material is formed directly above and abutting the conductive vias. The conductive material is patterned to form individual conductive lines, each individual conductive line being directly above a plurality of conductive vias spaced longitudinally along the respective individual conductive line. The patterning forms the individual conductive lines to have longitudinally alternating wider and narrower regions. The wider regions are directly above and abutting the top surface of each individual conductive via, and are wider in a horizontal cross-section at the top surface than the narrower regions in that horizontal cross-section. The narrower regions are longitudinally located between the wider regions. Other embodiments including method-independent structures are disclosed.

Description

Technical Field

[0001] The embodiments disclosed herein relate to integrated circuits, memory circuits, methods for forming integrated circuits, and methods for forming memory circuits. Background Technology

[0002] Memory is a type of integrated circuit used in computer systems to store data. Memory can be manufactured in one or more arrays of individual memory cells. Memory cells can be written to or read from using digital lines (also called bit lines, data lines, or sense lines) and access lines (also called word lines). Digital lines electrically interconnect memory cells along the columns of the array, and access lines electrically interconnect memory cells along the rows of the array. Each memory cell can be uniquely addressed using a combination of digital lines and access lines.

[0003] Memory cells can be volatile, semi-volatile, or non-volatile. Non-volatile memory cells can store data for extended periods without power. Non-volatile memory is typically specified as memory with a retention period of at least approximately 10 years. Volatile memory dissipates data and is therefore refreshed / rewritten to maintain data storage. Volatile memory can have a retention period of milliseconds or less. In any case, memory cells are configured to maintain or store memory in at least two different selectable states. In binary systems, these states are considered as "0" or "1". In other systems, at least some individual memory cells can be configured to store information in more than two levels or states.

[0004] A capacitor is a type of electronic component that can be used in memory cells. A capacitor has two electrical conductors separated by an electrically insulating material. Energy, as an electric field, can be stored electrostatically within this material. Depending on the composition of the insulating material, the stored field will be volatile or non-volatile. For example, a capacitor insulating material containing only SiO2 will be volatile. One type of non-volatile capacitor is a ferroelectric capacitor having at least a portion of a ferroelectric material as the insulating material. Ferroelectric materials are characterized by having two stable polarization states and thus can be programmable materials that include capacitors and / or memory cells. The polarization states of the ferroelectric material can be changed by applying a suitable programming voltage and remain (at least for a certain period of time) after the programming voltage is removed. Each polarization state has a different charge storage capacitance than the others, which is ideally used to write (i.e., store) and read the memory state without reversing the polarization state until such reversal is desired. Less desirablely, in a memory with ferroelectric capacitors, the act of reading the memory state may reverse the polarization. Therefore, after determining the polarization state, the memory cell is rewritten to place it in a prefetch state immediately after the polarization state is determined. In any case, due to the bistable nature of the ferroelectric material that forms part of the capacitor, the memory cell incorporating the ferroelectric capacitor is ideally non-volatile. Other programmable materials can be used as capacitor insulators to make the capacitor non-volatile.

[0005] Field-effect transistors (FETs) are another type of electronic component that can be used in memory cells. These transistors include a pair of conductive source / drain regions with a semi-conductive channel region between them. A conductive gate is adjacent to the channel region and separated from it by a thin gate insulator. Applying a suitable voltage to the gate allows current to flow through the channel region from one source / drain region to the other. When the voltage is removed from the gate, current flow through the channel region is largely prevented. FETs may also include additional structures, such as a reversible programmable charge storage region as part of the gate construction between the gate insulator and the conductive gate. In any case, the gate insulator can be programmable, for example, ferroelectric.

[0006] Of course, capacitors and transistors can be used in integrated circuits other than memory circuits. In any case, a via is a vertically extending (e.g., vertical) conductor used to electrically connect capacitors, transistors, and other integrated circuit components together. Such vias can be patterned in an array. As vias get closer to adjacent circuit components, unwanted parasitic capacitance increases and can adversely affect circuit operation. Furthermore, in the fabrication of such vias, pattern misalignment and / or manufacturing artifacts can cause unwanted short circuits from the vias to adjacent circuit components, which can destroy some or all of the manufactured integrated circuit. Summary of the Invention

[0007] In one aspect, this application provides a method for forming an integrated circuit, comprising: forming horizontally spaced conductive vias above a substrate; forming a conductive material directly above and abutting the conductive vias; patterning the conductive material to form individual conductive lines, each individual conductive line being directly above a plurality of conductive vias spaced longitudinally along the respective individual conductive lines; and patterning the individual conductive lines to have longitudinally alternating wider and narrower regions, the wider regions being directly above and abutting the top surface of an individual conductive via, and being wider in a horizontal cross-section at the top surface than the narrower regions in the horizontal cross-section, the narrower regions being longitudinally spaced between the wider regions.

[0008] In another aspect, this application provides a method for forming a memory circuit, comprising: forming a transistor, the transistor individually including a pair of source / drain regions, a channel region between the pair of source / drain regions, and a conductive gate operatively adjacent to the channel region; forming horizontally spaced conductive vias, the conductive vias individually being directly electrically coupled to one of the pair of source / drain regions of a plurality of transistors; vertically recessing the conductive vias to individually have a top surface lower than a top surface of a laterally surrounding material; forming a conductive material directly above and directly abutting the vertically recessed conductive vias, the conductive material having a top surface lower directly above the vertically recessed conductive vias relative to a higher top surface of a laterally adjacent vertically recessed conductive via; forming a masking material directly above the conductive material, the masking material being vertically thicker directly above the lower top surface relative to a higher top surface directly adjacent to it; and patterning the masking material. Materials and conductive materials are used to form individual conductive line structures, each of which is directly above a plurality of vertically recessed conductive vias spaced longitudinally along the respective individual conductive line structures. A vertically thicker masking material forms the individual conductive line structures to have longitudinally alternating wide and narrow regions of conductive material. The wider regions of conductive material are directly above and abut against the lower top surface of the individual vertically recessed conductive vias, and are wider in a horizontal cross-section at the lower top surface of the vertically recessed conductive vias than the narrower regions of conductive material in the horizontal cross-section. The narrower regions of conductive material are longitudinally located between the wider regions of conductive material. Conductive vias are formed laterally between digital line structures and spaced longitudinally along the digital line structures. Each of the conductive vias is directly electrically coupled to another source / drain region of the pair of source / drain regions of a plurality of transistors. A plurality of memory elements are formed, each of which is directly electrically coupled to the individual conductive vias.

[0009] In another aspect, this application provides an integrated circuit comprising: horizontally spaced conductive vias above a substrate; a plurality of conductive lines, each individually directly above the plurality of conductive vias spaced longitudinally along the respective individual conductive lines; and individual conductive lines having longitudinally alternating wider and narrower regions, the wider regions being directly above and abutting the top surface of the individual conductive vias, and being wider in a horizontal cross-section at the top surface than the narrower regions in the horizontal cross-section, the narrower regions being longitudinally spaced between the wider regions.

[0010] In another aspect, this application provides a memory circuit comprising: a substrate including transistors, each transistor individually including a pair of source / drain regions, a channel region between the pair of source / drain regions, and a conductive gate operatively adjacent to the channel region; horizontally spaced conductive vias, each individually directly electrically coupled to one of the pair of source / drain regions of a plurality of transistors; a digital line structure, each individually directly electrically coupled to a plurality of conductive vias along lines of the plurality of transistors; and, in some cases, the digital line structure having a relatively wide longitudinal alternation of conductive material. The wider region is directly above and abuts the top surface of each of the conductive vias, and is wider in a horizontal cross-section at the top surface than the narrower region in the horizontal cross-section, the narrower region being longitudinally located between the wider regions; conductive vias are laterally spaced between digital line structures and longitudinally spaced along the digital line structures, each of the conductive vias being directly electrically coupled to another source / drain region of the multiple transistors; and multiple memory elements are each directly electrically coupled to each of the conductive vias. Attached Figure Description

[0011] Figures 1 to 7 This is a schematic cross-sectional view of a portion of the DRAM construction process according to some embodiments of the present invention.

[0012] Figures 8 to 24 In the process according to some embodiments of the present invention Figures 1 to 7 The diagram of the structure is shown in sequence of cross-sectional views. Detailed Implementation

[0013] Embodiments of the present invention cover integrated circuit fabrication, such as DRAM fabrication, and methods for forming integrated circuit fabrication, such as DRAM circuit fabrication. Reference Figures 1 to 7 The description includes a first example embodiment of DRAM construction. Figures 1 to 7This illustration shows an example fragment of a substrate structure 8 comprising an array or array region 10 fabricated relative to a substrate 11. The substrate structure 11 may include any one or more of conductive / conductive / transducing, semiconductive / semiconductor / semiconductive, and insulating / insulator / isolation (i.e., electrically) materials. Various materials are located above the substrate 11. The materials may be... Figures 1 to 7 The material depicted is adjacent to, vertically inward, or vertically outward. For example, components that are fabricated or fully fabricated in other parts of the integrated circuit may be disposed above, around, or inside the substrate 11. Control circuitry and / or other peripheral circuitry for operating components within the memory array may also be fabricated, and said circuitry may or may not be fully or partially within the memory array or subarray. Furthermore, multiple subarrays may be fabricated and operated relatively independently of each other, sequentially, or otherwise. As used in this document, "subarray" may also be considered as an array.

[0014] The substrate 11 includes a semiconducting material 12 (e.g., suitably and differently doped single-crystal and / or polycrystalline silicon, Ge, SiGe, GaAs, and / or other existing or future-developed semiconducting materials), a trench isolation region 14 (e.g., silicon nitride and / or silicon dioxide), and an active region 16 including the suitably and differently doped semiconducting material 12. In one embodiment, configuration 8 includes a memory cell 75 ( Figure 5 and 7 And for clarity in these figures, it has Figure 5 Only four outlines are shown in the image: 75 and... Figure 7 Only two outlines 75), such as DRAM memory cells, individually include field-effect transistor devices 25. Figure 3 ) and storage elements (e.g., capacitors 85; Figure 1 and 7 However, embodiments of the present invention cover other memory cells and other configurations of integrated circuits, independent of whether or not they contain memory cells.

[0015] Example transistor device 25 individually includes a pair of source / drain regions, a channel region between the source / drain regions of the pair, a conductive gate operatively adjacent to the channel region, and a gate insulator between the conductive gate and the channel region. Device 25 is shown as a recessed access device, wherein example configuration 8 shows these recessed access devices grouped in individual pairs of such devices. Individual recessed access device 25 includes a buried access line configuration 18, for example, within a trench 19 in a semiconductive material 12. Configuration 18 includes a conductive gate material 22 (e.g., a conductive doped semiconductor material and / or a metallic material containing, for example, elements W, Ru, and / or Mo) that serves as the conductive gate of the individual device 25. Gate insulator 20 (e.g., silicon dioxide and / or silicon nitride) is located between the conductive gate material 22 and the semiconductive material 12 along the sidewalls 21 and substrate 23 of the individual trench 19. An insulating material 37 (e.g., silicon dioxide and / or silicon nitride) is located within trenches 19 above materials 20 and 22. Individual devices 25 include a pair of source / drain regions 24, 26 (e.g., regions 24, 26 extending laterally outward from and above access line configuration 18) in the upper portion of the semiconductive material 12 on opposite sides of the individual trenches 19. Each of the source / drain regions 24, 26 has at least one portion containing a conductivity-enhancing dopant, said dopant being the highest concentration of such conductivity-enhancing dopant within the corresponding source / drain region 24, 26, for example, to make this portion conductive (e.g., having at least 10). 19 atoms / cm 3 (Maximum dopant concentration). Therefore, all or only a portion of each source / drain region 24, 26 may have such a maximum concentration of conductivity-enhancing dopant. Source / drain regions 24 and / or 26 may contain other doped regions (not shown), such as halogen regions, LDD regions, etc.

[0016] In the individual of the pair of recessed access devices 25, one of the source / drain regions of the pair of source / drain regions (e.g., region 26) lies laterally between the conductive gate materials 22 and is shared by the pair of devices 25. The other source / drain regions of the pair of source / drain regions (e.g., region 24) are not shared by the pair of devices 25. Thus, in an exemplary embodiment, each active region 16 includes two devices 25 (e.g., a pair of devices 25), wherein each device shares the central source / drain region 26.

[0017] Example trench area 27 ( Figure 1 , 3 (6 and 7) along the trench sidewall 21 in the semiconductive material 12 Figure 6 and 7The channel region 27 is located below and around the trench substrate 23, beneath a pair of source / drain regions 24, 26. The channel region 27 may be undoped or suitably doped with a dopant that increases conductivity, the dopant likely being a dopant of the opposite conductivity type to that in the source / drain regions 24, 26, and having, for example, a conductivity not exceeding 1 x 10⁻⁶ in the channel. 17 atoms / cm 3 The maximum concentration. When a suitable voltage is applied to the gate material 22 of the access line configuration 18, a conductive channel is formed within the channel region 27 near the gate insulator 20 (e.g., along the channel current flow line / path 29). Figure 7 This allows current to flow between a pair of source / drain regions 24 and 26 within the access line configuration 18 in individual active region 16. The dotting patterns are illustrated to indicate the dopant concentration (regardless of type) for major conductivity modifications, with denser dotting indicating a larger dopant concentration and lighter dotting indicating a lower dopant concentration. Conductivity-modifying dopants can and will most likely be present in other portions of material 12 as shown. For simplicity, only two different dotting densities are shown in material 12, and additional dopant concentrations can be used; a constant dopant concentration is not required in any region.

[0018] Horizontally spaced conductive vias 33 are individually and directly electrically coupled to one of the source / drain regions (e.g., 26) of a plurality of transistors. Example conductive vias 33 are spaced apart from each other (e.g., longitudinally relative to the digital line 39 thereon, as described below) by intermediate materials (e.g., when present, one or more of materials 38, 32, and / or 46, wherein materials 38, 32, and 46 are described below) and include conductive materials (e.g., 34 and 35). In one embodiment, the conductive materials 34 / 35 of the conductive vias 33 comprise a lower conductive doped semiconducting material 34 (e.g., conductive doped polysilicon) below an upper conductive material 35 (e.g., a metallic material), the lower conductive material 35 having a composition different from that of the conductive doped semiconducting material 34. Additional examples of conductive materials in materials 34 and 35, and by way of example only, include metal nitrides (e.g., TiN, TaN, WN, MoN), metal carbonitrides (e.g., TiCN, TaCN, WCN, MoCN), and elemental metals (e.g., Ti, Ta, W, Mo, Co, Cu, Ru, Be), including combinations thereof, compounds, and alloys thereof.

[0019] Digital lines 39 are directly electrically coupled to multiple conductive vias 33 along the lines of multiple transistors 25. Digital lines 39 include conductive material 42 of conductive material 34 / 35 directly abutting the conductive vias 33. Example digital lines 39 include portions of digital line structures 30, which include opposing longitudinal insulating sides 38 (e.g., silicon dioxide and / or silicon nitride) and insulating caps 50 (e.g., silicon nitride and / or silicon dioxide). Example material 46 is located below digital lines 39, closely longitudinally adjacent to the conductive vias 33. Figure 6 Between the lower insulating material 48 (e.g., one or more of silicon dioxide, silicon nitride, aluminum dioxide, hafnium oxide, etc.; for example, a thickness of 50 to 200 angstroms) lies below the material 46 between closely longitudinally adjacent conductive vias 33. The material 46 may be insulating, semi-conductive (e.g., a material not sufficiently doped to be conductive), or conductive or eliminated, wherein the conductive material 42 extends inwardly to the lower insulating material 48 (not shown).

[0020] Individual digital line structures 30 have longitudinally alternating wide and narrow regions (e.g., 55 and 57, respectively) of a conductive material (e.g., 42). The wide region 55 lies directly above and abuts the top surface (e.g., 58) of the individual conductive via 33, and its horizontal cross-section at the top surface 58 (e.g., ...) Figure 5 The cross section is wider than the narrower region 57 in the horizontal cross section, wherein the narrower region 57 is longitudinally located between the wider regions 55.

[0021] In one embodiment, individual digital lines 39 have a lower bottom surface 60 directly above the conductive via 33 relative to the longitudinal surface therebetween along the respective individual digital line 39. In one embodiment, individual digital lines 39 have a wavy top surface 62. Figure 1 , 6 (and 7). In one embodiment, the highest portion 63 of the wavy top surface 62 is directly above the narrower region 57, and in another embodiment, the highest portion 63 is not directly above the wider region 55.

[0022] Conductive vias 36 are laterally spaced between and longitudinally spaced along the digital line structures 30. Individual vias 36 are directly electrically coupled to another source / drain region (e.g., 24) of the multiple transistors. Multiple storage elements (e.g., capacitors 85) are directly electrically coupled to individual conductive vias 36. For convenience and clarity, components 33, 30, 36, etc., are shown with vertical sidewalls, but this could be gradually narrowed inwards or outwards to allow movement within the depicted stack (not shown).

[0023] Any other attributes or aspects shown and / or described herein with reference to other embodiments may be used in the embodiments shown and described above.

[0024] Embodiments of the present invention cover integrated circuits that may or may not include memory circuitry. An integrated circuit according to the invention includes horizontally spaced conductive vias (e.g., 33) above a substrate (e.g., those portions of materials 12 and 14 below conductive via 33). A plurality of conductive lines (e.g., 39) are individually directly above the plurality of conductive vias that are longitudinally spaced along the respective individual conductive lines. Individual conductive lines have longitudinally alternating wider regions (e.g., 55) and narrower regions (e.g., 57). The wider regions are directly above and abut against the top surface (e.g., 58) of the individual conductive vias, and in a horizontal cross-section at the top surface (e.g., ... Figure 5 The cross-section is wider than the narrower region in the horizontal cross-section, wherein the narrower region is longitudinally located between the wider regions. Any other properties or aspects as shown and / or described herein with respect to other embodiments may be used.

[0025] Embodiments of the present invention cover methods for forming integrated circuit structures, such as DRAM, other memory, and / or non-memory circuitry. In any case, the method aspects of the present invention may use or have any of the properties described herein in the structural and / or device embodiments. Similarly, the structural embodiments described above may incorporate any of the properties described relative to the method embodiment aspects.

[0026] refer to Figures 8 to 24 Description of instance method implementations and methods for generating Figures 1 to 7 This embodiment provides an example of construction 8. (See reference...) Figure 8 , 9 And 10, which are respectively relative to Figure 1 , 4 The configuration of 6 illustrates a forward configuration, where configuration 8 has been fabricated to include points 32, 34, and 35 within array 10. Opening 56 has been formed to the source / drain region 26. Furthermore, Figures 8 to 10 A prior formation of transistor 25 is shown (in one embodiment), which individually includes a pair of source / drain regions 24, 26, a channel region 27 between the pair of source / drain regions 24, 26, and a conductive gate (e.g., conductive material 22) operatively adjacent to the channel region 27. Furthermore, and in one embodiment, horizontally spaced conductive vias 33 have been formed, each individually directly electrically coupled to one of the pair of source / drain regions of the plurality of transistors 25 (e.g., source / drain region 26).

[0027] refer to Figure 11 and 12The conductive via 33 has been vertically recessed (e.g., its conductive material 35 and by chemical etching) to individually have a top surface 58 that is lower than the top surface of the laterally surrounding material (e.g., 32 or 46).

[0028] refer to Figures 13 to 15 Conductive material 42 has been formed directly above and abutting the vertically recessed conductive via 33. Conductive material 42 has a top surface 51 that is lower than the higher top surface 52 of a laterally adjacent vertically recessed conductive via 33, directly above the vertically recessed conductive via 33. Masking material 50 (e.g., insulating silicon nitride or other material) has been formed directly above conductive material 42. Masking material 50 is vertically thicker (e.g., T1) directly above the lower top surface 51 compared to the higher top surface 52 (e.g., T2) directly adjacent to it. Masking material 50, which may or may not be at least partially retained as part of the completed circuit structure, may be initially deposited as not so vertically thick and thin, and may subsequently produce the depicted structure by subjecting masking material 50 to a planarization step (e.g., mechanical polishing or chemical mechanical polishing).

[0029] refer to Figures 16 to 19 Patterned masking material 50 and conductive material 42 (e.g., patterning using photolithography and etching using masking block 59 [e.g., photoresist]) are used to form individual conductive line structures 30, each of which is individually directly above a plurality of vertically recessed conductive vias 33 spaced longitudinally along the respective individual conductive line structure 30. In one embodiment, and due to artifacts caused by or because of the presence of a vertically thicker masking material (e.g., T1), this results in individual conductive line structures 30 having longitudinally alternating wider regions 55 and narrower regions 57 of the conductive material 42. The wider regions 55 of the conductive material 42 are directly above and abut against the lower top surface 58 of the individual vertically recessed conductive vias 33, and at the lower top surface 58 of the vertically recessed conductive vias (e.g., ... Figure 18 The narrower region 57 of the conductive material 42 in the horizontal cross-section is wider than the narrower region 57 in the horizontal cross-section. The narrower region 57 of the conductive material 42 is longitudinally located between the wider regions 55 of the conductive material 42. This action of patterning the masking material 50 and the conductive material 42 can form a circumferential gap 61 around the individual conductive via 33.

[0030] refer to Figures 20 to 23 Insulating spacers 38 have been formed (thus increasing the size of the digital line structure 30), and dielectric material 40 has been deposited therein. As shown, insulating spacers 38 can fill circumferential gaps 61. Figure 24 This demonstrates the subsequent formation of the opening 41 that extends to the source / drain region 24. Further processing will be performed to produce... Figures 1 to 7The configuration is shown in the diagram. For example, a conductive via 36 will be formed in the opening 41 to be individually and directly electrically coupled to other source / drain regions 24 of the source / drain region pair. Storage elements, such as capacitors 85, will be formed to be individually and directly electrically coupled to the conductive vias 36.

[0031] Any other properties or aspects as shown and / or described herein with respect to other embodiments may be used.

[0032] Embodiments of the present invention cover a method for forming an integrated circuit that may or may not be a memory circuit. This method includes forming horizontally spaced conductive vias (e.g., 33) over a substrate (e.g., those portions of materials 12 and 14 below conductive via 33). A conductive material (e.g., 42) is formed directly over and abutting the conductive vias. The conductive material (regardless of the presence of material 50) is patterned to form individual conductive lines (e.g., 39), said conductive lines individually directly over a plurality of conductive vias spaced longitudinally along the respective individual conductive lines. The patterning forms the individual conductive lines to have longitudinally alternating wider and narrower regions (e.g., 55, 57, respectively). The wider regions are directly over and abutting the individual top surfaces (e.g., 58) of the conductive vias, and on the top surfaces (e.g.,...)... Figure 18 The narrower region is wider than the narrower region in the horizontal cross-section at the top surface of the surface. The narrower region lies longitudinally between the wider regions. Any other properties or aspects as shown and / or described herein with respect to other embodiments may be used.

[0033] The above-described processing or construction can be viewed as an array of components formed as a single stack or group of such components, or within a single stack or group, above or as part of an underlying substrate (but a single stack / group may have multiple layers). Control and / or other peripheral circuitry for operating or accessing such components within the array can also be formed as part of the completed construction, and in some embodiments may be below the array (e.g., CMOS below the array). In any case, one or more additional such stacks / groups may be provided or fabricated above and / or below the stacks / groups shown in the figures or described above. Furthermore, arrays of components may be identical or different relative to each other in different stacks / groups, and different stacks / groups may have the same or different thicknesses relative to each other. Intermediate structures (e.g., additional circuitry and / or dielectric layers) may be disposed between closely vertically adjacent stacks / groups. Additionally, different stacks / groups may be electrically coupled relative to each other. Multiple stacks / groups can be manufactured individually and sequentially (e.g., one on top of another), or two or more stacks / groups can be manufactured substantially simultaneously.

[0034] The assemblies and structures discussed above can be used in integrated circuit / circuit systems and incorporated into electronic systems. Such electronic systems can be used in, for example, memory modules, device drivers, power modules, communication modems, processor modules, and special-purpose modules, and can contain multi-layered, multi-chip modules. Electronic systems can be any of the following wide range of systems: for example, cameras, wireless devices, displays, chipsets, set-top boxes, games, lighting, vehicles, clocks, televisions, cellular phones, personal computers, automobiles, industrial control systems, aircraft, etc.

[0035] In this document, unless otherwise indicated, “vertical,” “higher,” “upper,” “lower,” “top,” “above,” “bottom,” “above,” “below,” “under,” “upward,” and “downward” generally refer to the vertical direction. “Horizontal” means a general direction (i.e., within 10 degrees) along the surface of the main substrate and relative to its processing substrate during manufacturing, and vertical is a direction generally orthogonal to it. The reference to “exactly horizontal” means a direction along the surface of the main substrate (i.e., not forming degrees with said surface) and relative to its processing substrate during manufacturing. Furthermore, as used herein, “vertical” and “horizontal” are generally perpendicular to each other and independent of the orientation of the substrate in three-dimensional space. Additionally, “vertically extending” and “vertically extending” refer to a direction inclined at least 45° from exactly horizontal. Furthermore, with respect to field-effect transistors, “vertically extending,” “vertically extending,” “horizontally extending,” “horizontally extending,” etc., refer to the orientation of the transistor’s channel length along which current flows between the source / drain regions during operation. For bipolar junction transistors, terms such as "vertically extending," "vertically extending," "horizontally extending," and "horizontally extending" refer to the orientation of the substrate length along which current flows between the emitter and collector during operation. In some embodiments, any vertically extending component, feature, and / or region extends vertically or within a vertical 10°.

[0036] Furthermore, "directly above," "directly below," and "directly under" require at least some lateral overlap (i.e., horizontally) between the two stated areas / materials / components. Additionally, using "above" without the preceding "directly" only requires that a portion of the stated area / material / component above another stated area / material / component is vertically outside the other stated area / material / component (i.e., regardless of whether there is any lateral overlap between the two stated areas / materials / components). Similarly, using "below" and "under" without the preceding "directly" only requires that a portion of the stated area / material / component below another stated area / material / component is vertically inside the other stated area / material / component (i.e., regardless of whether there is any lateral overlap between the two stated areas / materials / components).

[0037] Any of the materials, regions, and structures described herein may be homogeneous or non-homogeneous, and in any event may be continuous or discontinuous over any material they cover. When one or more example compositions are provided for any material, the material may comprise, consist primarily of, or consist of such one or more compositions. Furthermore, unless otherwise stated, any suitable existing or future-developed techniques may be used to form each material, with atomic layer deposition, chemical vapor deposition, physical vapor deposition, epitaxial growth, diffusion doping, and ion implantation being examples.

[0038] Additionally, the term “thickness” (without a directional adjective) used alone is defined as the average straight-line distance perpendicular to the nearest surface of adjacent materials or regions with different compositions, passing through a given material or region. Furthermore, the various materials or regions described herein may have substantially constant thickness or variable thickness. If variable thickness is present, then unless otherwise indicated, the thickness refers to the average thickness, and such materials or regions will have a minimum thickness and a maximum thickness due to the variable thickness. As used herein, “different compositions” only requires that the portions of two stated materials or regions that are in direct contact with each other are chemically and / or physically different, for example, in the case where the materials or regions are non-uniform. If two stated materials or regions are not in direct contact with each other, then in the case where such materials or regions are non-uniform, “different compositions” only requires that the portions of the two stated materials or regions that are closest to each other are chemically and / or physically different. In this document, a material, region, or structure is “in direct contact” with another material, region, or structure when there is at least some physical contact between the stated materials, regions, or structures. In contrast, the preceding words “above,” “on,” “near,” “along,” and “against” do not encompass “directly against” and constructions in which the intervening material, area, or structure makes no physical contact between the stated material, area, or structure relative to each other.

[0039] In this text, if, during normal operation, current can flow continuously from one zone-material-component to another, and this flow is primarily accomplished by the movement of said subatomic positive and / or negative charges when sufficient subatomic positive and / or negative charges are generated, then the zone-material-components are “electrically coupled” relative to each other. Another electronic component may be electrically coupled between and to the zone-material-components. In contrast, when zone-material-components are referred to as “directly electrically coupled,” there are no intervening electronic components (e.g., no diodes, transistors, resistors, transducers, switches, fuses, etc.) between directly electrically coupled zone-material-components.

[0040] Any use of the terms "row" and "column" in this document is for the convenience of distinguishing one series or orientation of features from another series or orientation of features, and for components that have been or may be formed along said "row" and "column". "Row" and "column" are used synonymously with respect to any series of areas, components, and / or features, regardless of function. In any case, rows may be straight and / or curved and / or parallel and / or non-parallel relative to each other, and columns may be the same. Furthermore, rows and columns may intersect each other at 90° or at one or more other angles (i.e., other than straight angles).

[0041] The composition of any of the conductive / conductor / conductive materials mentioned herein may be a metallic material and / or a conductive-doped semiconducting / semiconductor / semiconductive material. "Metallic material" is any one or a combination of elemental metals, any mixture or alloy of two or more elemental metals, and any one or more conductive metallic compounds.

[0042] In this document, any use of "selective" in relation to etch, etching, removing, removal, deposition, forming, and / or formation is an action of a stated material relative to another stated material at a rate of at least 2:1 by volume. Furthermore, any use of selective deposition, selective growth, or selective formation is the deposition, growth, or formation of one material relative to one or more stated materials at a ratio of at least 2:1 by volume for a deposition, growth, or formation of at least a first 75 angstroms.

[0043] Unless otherwise indicated, the use of "or" in this document covers either one or both.

[0044] in conclusion

[0045] In some embodiments, a method for forming an integrated circuit includes forming horizontally spaced conductive vias above a substrate. A conductive material is formed directly above and abutting the conductive vias. The conductive material is patterned to form individual conductive lines, each of which is individually directly above a plurality of conductive vias spaced longitudinally along the respective individual conductive lines. The patterning forms individual conductive lines having longitudinally alternating wider and narrower regions. The wider regions are directly above and abutting the top surface of each individual conductive via, and are wider in a horizontal cross-section at the top surface than the narrower regions in that horizontal cross-section. Narrower regions are longitudinally spaced between the wider regions.

[0046] In some embodiments, a method of forming a memory circuit includes forming transistors, each transistor individually including a pair of source / drain regions, a channel region between the pair of source / drain regions, and a conductive gate operatively adjacent to the channel region. Horizontally spaced conductive vias are formed, each individually directly electrically coupled to one of the pair of source / drain regions of a plurality of transistors. The conductive vias are vertically recessed to each have a top surface lower than the top surface of a laterally adjacent vertically recessed conductive via. A conductive material is formed directly above and directly abutting the vertically recessed conductive via. The conductive material has a top surface lower directly above the vertically recessed conductive via than the higher top surface of a laterally adjacent vertically recessed conductive via. A masking material is formed directly above the conductive material. The masking material is vertically thicker directly above the lower top surface than directly above the higher top surface laterally adjacent to it. Patterned masking and conductive materials are used to form individual conductive line structures, each of which is directly above a plurality of vertically recessed conductive vias spaced longitudinally along the respective individual conductive line structures. A thicker vertical masking material forms the individual conductive line structures with alternating wide and narrow regions of the conductive material along its longitudinal direction. The wider regions of the conductive material are directly above and abut against the lower top surface of each individual vertically recessed conductive via, and are wider in a horizontal cross-section at the lower top surface of the vertically recessed conductive via than the narrower regions of the conductive material in that horizontal cross-section. The narrower regions of the conductive material lie longitudinally between the wider regions of the conductive material. Conductive vias are formed laterally between the digital line structures and longitudinally spaced along the digital line structures. Each conductive via is directly electrically coupled to another source / drain region in a plurality of transistor source / drain pairs. A plurality of memory elements are formed, each directly electrically coupled to an individual conductive via.

[0047] In some embodiments, the integrated circuit includes horizontally spaced conductive vias above a substrate. A plurality of conductive lines are individually positioned directly above the plurality of conductive vias that are longitudinally spaced along the respective individual conductive lines. Each conductive line has longitudinally alternating wider and narrower regions. The wider regions are directly above and abut against the top surface of each individual conductive via, and are wider in a horizontal cross-section at the top surface than the narrower regions in that horizontal cross-section. Narrower regions are longitudinally positioned between the wider regions.

[0048] In some embodiments, the memory circuitry includes a substrate comprising transistors, each transistor individually including a pair of source / drain regions, a channel region between the pair of source / drain regions, and a conductive gate operatively adjacent to the channel region. Horizontally spaced conductive vias are individually directly electrically coupled to one of the pair of source / drain regions of a plurality of transistors. Digital line structures are individually directly electrically coupled to a plurality of conductive vias along lines of a plurality of transistors. Individual digital line structures have longitudinally alternating wide and narrow regions of conductive material. A wider region lies directly above and abuts the top surface of an individual conductive via, and is wider in a horizontal cross-section at the top surface than a narrower region in that horizontal cross-section. Narrower regions are longitudinally spaced between the wider regions. Conductive vias are laterally spaced between digital line structures and longitudinally spaced along the digital line structures. Individual conductive vias are directly electrically coupled to another source / drain region of the pair of source / drain regions of a plurality of transistors. A plurality of memory elements are individually directly electrically coupled to an individual conductive via.

[0049] As per the description, the subject matter disclosed herein has been described in more or less specific language regarding structural and methodological features. However, it should be understood that the claims are not limited to the specific features shown and described, as the components disclosed herein include exemplary embodiments. Therefore, the claims have the full scope as stated in the writing and should be properly interpreted in accordance with the principle of equivalence.

Claims

1. A method for forming an integrated circuit, comprising: Horizontally spaced conductive vias are formed above the substrate; A conductive material is formed directly above and against the conductive through hole; The conductive material is patterned to form individual conductive lines, each of which is directly above a plurality of conductive vias spaced longitudinally along the respective individual conductive lines; as well as The patterning forms the individual conductive lines to have alternating wider and narrower longitudinal regions, the wider regions being directly above and abutting the top surface of the individual conductive vias, and being wider in a horizontal cross-section at the top surface than the narrower regions in the horizontal cross-section, the narrower regions being longitudinally spaced between the wider regions.

2. The method of claim 1, further comprising, prior to forming the conductive material, vertically recessing the individual conductive vias to have a top surface lower than the laterally surrounding material.

3. The method of claim 1, further comprising forming a masking material directly over the conductive material, the masking material being vertically thicker directly over the individual conductive vias relative to the material directly surrounding the individual conductive vias laterally.

4. The method of claim 3, wherein at least some of the masking material is retained in the completed construction of the integrated circuit.

5. The method of claim 4, wherein at least some of the materials are insulating.

6. The method according to claim 1, wherein the conductive line is a digital line of a memory circuit.

7. The method of claim 6, comprising a plurality of memory elements forming at least a portion of a memory cell, individually constituting the memory circuit.

8. The method of claim 6, wherein the memory circuitry comprises DRAM.

9. The method of claim 1, further comprising forming the individual conductive lines to have a wavy top surface.

10. The method of claim 9, wherein the highest portion of the wavy top surface is directly above the narrower region.

11. The method of claim 10, wherein the highest portion of the wavy top surface is not directly above the wider region.

12. A method for forming a memory circuit, comprising: Forming a transistor, which individually includes: A pair of source / drain regions; The channel region, which lies between the source and drain regions; and A conductive gate that is operatively close to the channel region; Horizontally spaced conductive vias are formed, each of which is individually and directly electrically coupled to one of the source / drain regions of the plurality of transistors; The conductive via is vertically recessed to individually have a top surface that is lower than the top surface of the laterally surrounding material; A conductive material is formed directly above and against the vertically recessed conductive via, the conductive material having a top surface that is lower than the higher top surface of the laterally adjacent vertically recessed conductive via. A masking material is formed directly above the conductive material, the masking material being thicker vertically above the lower top surface than above the higher top surface which is laterally adjacent to it; The masking material and the conductive material are patterned to form individual conductive line structures, each individual conductive line structure being directly above a plurality of vertically recessed conductive vias spaced longitudinally along the respective individual conductive line structure. A vertically thicker masking material forms the individual conductive line structure to have alternating wider and narrower regions longitudinally of the conductive material. The wider region of the conductive material is directly above and abuts the lower top surface of each of the individual vertically recessed conductive vias, and is wider in a horizontal cross-section at the lower top surface of the vertically recessed conductive vias than the narrower region of the conductive material in the horizontal cross-section. The narrower regions of the conductive material are longitudinally located between the wider regions of the conductive material. Conductive vias are formed laterally between the digital line structures and longitudinally spaced along the digital line structures, each of which is directly electrically coupled to another source / drain region in the plurality of transistors; and Multiple storage elements are formed, each individually directly electrically coupled to the conductor via.

13. The method of claim 12, wherein at least some of the masking material is retained in the completed construction of the memory circuit.

14. The method of claim 13, wherein at least some of the materials are insulating.

15. The method of claim 12, wherein the memory circuitry comprises DRAM.

16. Integrated circuits, including: Horizontally spaced conductive vias are located above the substrate; Multiple conductive lines, each individually directly above a plurality of conductive vias spaced longitudinally along the respective individual conductive lines; as well as Each of the conductive wires has alternating wide and narrow sections in the longitudinal direction. The wide section is directly above and abuts the top surface of the individual conductive via and is wider in the horizontal cross-section at the top surface than the narrow section in the horizontal cross-section. The narrow section is longitudinally located between the wide sections.

17. The integrated circuit of claim 16, wherein the individual conductive line has a lower bottom surface directly above the conductive via relative to the longitudinal direction therebetween along the respective individual conductive line.

18. The integrated circuit of claim 16, wherein the individual conductive lines have a wavy top surface.

19. The integrated circuit of claim 18, wherein the highest portion of the wavy top surface is directly above the narrower region.

20. The integrated circuit of claim 19, wherein the highest portion of the wavy top surface does not directly over the wider region.

21. The integrated circuit of claim 16, wherein the conductive line is a digital line of a memory circuit.

22. The integrated circuit of claim 21, comprising a plurality of memory elements, each being at least a portion of a memory cell of the memory circuit.

23. The integrated circuit of claim 21, wherein the memory circuitry comprises DRAM.

24. A memory circuit, comprising: A substrate comprising transistors, wherein the transistors individually include: A pair of source / drain regions; The channel region, which lies between the source and drain regions; and A conductive gate that is operatively close to the channel region; Horizontally spaced conductive vias, each individually and directly electrically coupled to one of the source / drain regions of the plurality of transistors; A digital line structure, which is individually and directly electrically coupled to the plurality of conductive vias along the lines of the plurality of transistors; Individuals of the digital line structure have longitudinally alternating wide and narrow regions of conductive material, the wider regions being directly above and abutting the top surface of the individual conductive via, and being wider in a horizontal cross-section at the top surface than the narrower regions in the horizontal cross-section, the narrower regions being longitudinally between the wider regions. Conductive vias, laterally spaced between the digital line structures and longitudinally spaced along the digital line structures, each of the conductive vias being directly electrically coupled to another source / drain region in one of the paired source / drain regions of the plurality of transistors; and Multiple storage elements, each individually electrically coupled directly to one of the conductor vias.

25. The memory circuit of claim 24, wherein the memory element is a capacitor.

26. The memory circuit of claim 24, comprising DRAM.

27. The memory circuit of claim 24, wherein the individual digital lines have a wavy top surface.

28. The memory circuit of claim 27, wherein the highest portion of the wavy top surface is directly above the narrower region.

29. The memory circuit of claim 28, wherein the highest portion of the wavy top surface does not directly over the wider region.

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