Method of programming non-volatile memory device including reversible resistance device

Abstract

A method of programming a non-volatile memory device including a plurality of memory cells is provided. Each memory cell of the plurality of memory cells includes a reversible resistance device. A target memory cell is selected from among the plurality of memory cells. A target resistance state of the reversible resistance device of the target memory cell is determined. A resistance state of the reversible resistance element of the target memory cell is read. The read resistance state is compared to the target resistance state. When the read resistance state is different from the target resistance state, one of a positive programming operation and a negative programming operation is performed on the reversible resistance device of the target memory cell.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0017100, filed on February 5, 2021, with the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure generally relates to a programming method for non-volatile storage devices. Background Technology

[0004] Various processes and operations can be applied to methods for writing signal information into non-volatile memory devices, depending on the configuration of the non-volatile memory device. In the case of flash memory devices, which are examples of non-volatile memory devices, the methods associated with writing signal information can include programming operations that store electrons in the charge storage layer of the memory cell and erasing operations that erase electrons from the charge storage layer. The programming and erasing operations can be performed by applying programming voltage and erasing voltage, respectively, to the gate electrode of the memory cell to change the electron density in the charge storage layer.

[0005] Non-volatile memory devices can be resistive random access memory (RRAM) devices that include reversible resistive devices. In RRAM devices with reversible resistance, signal information writing operations can be performed by changing the resistance of the reversible resistive device inside the memory cell. The signal information writing operation of RRAM devices can be distinguished from the programming operation of flash memory devices, which fills electrons into the charge storage layer, or the erasure operation, which erases electrons from the charge storage layer. Recently, with the increasing industrial attention to the use of RRAM devices, various methods for efficiently writing signal information into multiple memory cells of RRAM devices have been studied. Summary of the Invention

[0006] A method for programming a non-volatile memory device according to embodiments of the present disclosure is provided. In the programming method, a memory device comprising a plurality of memory cells may be provided. Each of the plurality of memory cells may include a reversible resistor device. A target memory cell may be selected from the plurality of memory cells. A target resistance state for the reversible resistor device of the target memory cell may be determined. The resistance state of the reversible resistor device of the target memory cell may be read. The read resistance state may be compared with the target resistance state. When the read resistance state may differ from the target resistance state, one of a positive programming operation and a negative programming operation may be performed on the reversible resistor device of the target memory cell. Positive programming may include applying a programming voltage of positive polarity to the reversible resistor device of the target memory cell, while negative programming may include applying a programming voltage of negative polarity to the reversible resistor device of the target memory cell.

[0007] A method for programming a non-volatile memory device according to another embodiment of this disclosure is provided. In this programming method, a memory element comprising a plurality of memory cells is provided, the plurality of memory cells being connected in series along a channel layer extending in a direction perpendicular to the upper surface of a substrate. Each of the plurality of memory cells may include a reversible resistive storage layer and a gate electrode layer disposed adjacent to a side surface of the channel layer. A target memory cell can be selected from the plurality of memory cells, and a target resistance state of the reversible resistive storage layer for the target memory cell can be determined. The resistance state can be read by measuring the operating current flowing through the reversible resistive storage layer of the target memory cell. The read resistance state can be compared with the target resistance state. When the read resistance state differs from the target resistance state, one of a positive programming operation and a negative programming operation can be performed on the reversible resistive storage layer of the target memory cell to change the resistance state of the reversible storage layer. Attached Figure Description

[0008] Figure 1 This is a circuit diagram of a non-volatile storage device according to an embodiment of the present disclosure.

[0009] Figure 2 This is a perspective view schematically illustrating a non-volatile storage device according to an embodiment of the present disclosure.

[0010] Figure 3 It is along Figure 2 A cross-sectional view of line II′ of a non-volatile storage device.

[0011] Figure 4 This is a flowchart schematically illustrating programming operations of a non-volatile storage device according to an embodiment of the present disclosure.

[0012] Figure 5 This is a view illustrating an example of storing signal information in a non-volatile storage device by programming operations according to an embodiment of the present disclosure.

[0013] Figure 6A and Figure 6B This is a view schematically illustrating a read operation of a non-volatile storage device according to an embodiment of the present disclosure.

[0014] Figure 7A and Figure 7B This is a view schematically illustrating the programming operation of a non-volatile storage device according to an embodiment of the present disclosure.

[0015] Figure 8A and Figure 8B This is a schematic view illustrating the programming voltage according to an embodiment of the present disclosure. Detailed Implementation

[0016] In the following, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the drawings, the dimensions of the components (such as the width and thickness of the components) are enlarged to clearly illustrate the parts of each device. The terms used herein may correspond to words chosen in consideration of their function in the embodiments, and the meaning of these terms may be interpreted differently by those skilled in the art to which the embodiments pertain. If defined in detail, these terms may be interpreted according to the definitions. Unless otherwise defined, the terms used herein (including technical and scientific terms) have the same meaning as commonly understood by those skilled in the art to which the embodiments pertain.

[0017] Furthermore, unless explicitly used otherwise in the context, the singular form of a word should be understood to include the plural form of that word. It should be understood that the terms "comprising" or "having" are intended to specify the presence of a feature, quantity, step, operation, component, device, part, or combination thereof, but are not intended to exclude the presence or possibility of adding one or more other features, quantities, steps, operations, components, devices, parts, or combinations thereof.

[0018] In this specification, the term "predetermined direction" can refer to a direction that includes a direction defined in a coordinate system and a direction opposite to that direction. For example, in an xyz coordinate system, the x-direction can include a direction parallel to the x-axis. That is, the x-direction can represent all the following directions: the direction in which the absolute value of the x-axis increases from the origin 0 along the positive x-axis direction, and the direction in which the absolute value of the x-axis increases from the origin 0 along the negative x-axis direction. In the xyz coordinate system, the y-direction and z-direction can both be interpreted in substantially the same way.

[0019] Embodiments of this disclosure provide a method for reliably performing programming operations on a reversible resistive device of a memory cell in a non-volatile memory device, the non-volatile memory device including the memory cell and its reversible resistive device. By applying a programming voltage, the memory cell can non-volatilely store different resistance states in the reversible resistive device. The non-volatile memory device of this disclosure can be a memory device that utilizes the resistive-changing characteristics of the reversible resistive device to store signal information.

[0020] Figure 1 This is a circuit diagram of a non-volatile storage device according to an embodiment of the present disclosure. Reference Figure 1The non-volatile memory device 1 may include first to fourth memory cells MC1, MC2, MC3, and MC4 connected in series. The first to fourth memory cells MC1, MC2, MC3, and MC4 may form a memory string S between the source line SL and the bit line BL. The first to fourth memory cells MC1, MC2, MC3, and MC4 may each include corresponding first to fourth transistor devices TR1, TR2, TR3, and TR4, and first to fourth reversible resistor devices VRa, VRb, VRc, and VRd. The first to fourth reversible resistor devices VRa, VRb, VRc, and VRd may be connected in parallel to the corresponding first to fourth transistor devices TR1, TR2, TR3, and TR4.

[0021] The first to fourth transistor devices TR1, TR2, TR3, and TR4 may each include corresponding first to fourth gate electrodes G1, G2, G3, and G4. Each of the first to fourth gate electrodes G1, G2, G3, and G4 may be connected to a different word line (not shown). When a gate voltage greater than or equal to a threshold voltage is applied to the first to fourth gate electrodes G1, G2, G3, and G4, the first to fourth transistor devices TR1, TR2, TR3, and TR4 may be turned on to form conductive channels located below the first to fourth gate electrodes G1, G2, G3, and G4, respectively. That is, each of the first to fourth transistor devices TR1, TR2, TR3, and TR4 may perform a threshold switching operation controlled by the gate voltage applied to the first to fourth gate electrodes G1, G2, G3, and G4, respectively.

[0022] Each of the first to fourth reversible resistive devices VRa, VRb, VRc, and VRd can have a resistance that can be reversibly changed by applying a programming voltage to the opposite ends of each of the first to fourth reversible resistive devices VRa, VRb, VRc, and VRd. After the programming voltage is removed, the changed resistance can be non-volatilely stored in each of the first to fourth reversible resistive devices VRa, VRb, VRc, and VRd. That is, the first to fourth reversible resistive devices VRa, VRb, VRc, and VRd can each perform a storage function of storing different resistances in a non-volatile manner. In one embodiment, each of the first to fourth reversible resistive devices VRa, VRb, VRc, and VRd can be a phase-change random access memory (PCRAM) device, a resistive random access memory (ReRAM) device, or a magnetic random access memory (MRAM) device.

[0023] In one embodiment, each of the first to fourth reversible resistors VRa, VRb, VRc, and VRd can perform the function of storing single-level information. That is, each of the first to fourth reversible resistors VRa, VRb, VRc, and VRd can store two different resistors corresponding to one (1) bit of signal information. In another embodiment, each of the first to fourth reversible resistors VRa, VRb, VRc, and VRd can perform the function of storing multi-level information. That is, each of the first to fourth reversible resistors VRa, VRb, VRc, and VRd can store multiple different resistors corresponding to two (2) or more bits of signal information. As an example, each of the first to fourth reversible resistors VRa, VRb, VRc, and VRd can store four different resistors corresponding to 2 bits of signal information. As another example, each of the first to fourth reversible resistors VRa, VRb, VRc, and VRd can store eight different resistors corresponding to 3 bits of signal information.

[0024] Figure 2 This is a perspective view schematically illustrating a non-volatile storage device according to an embodiment of the present disclosure. Figure 3 It is along Figure 2 A cross-sectional view of line II′ of a non-volatile storage device. (See diagram below.) Figure 2 and Figure 3 The non-volatile storage device 2 shown can be Figure 1 The implementation of the circuit diagram. The non-volatile memory device 2 may include components corresponding to... Figure 1 The reversible resistive devices VRa, VRb, VRc, and VRd shown are resistive switching devices.

[0025] refer to Figure 2 and Figure 3 The non-volatile memory device 2 may include a substrate 201 and a gate structure 220 disposed above the substrate 201. Furthermore, the non-volatile memory device 2 may include a hole pattern 21 penetrating the gate structure 220 above the substrate 201. The non-volatile memory device 2 may include a gate insulating layer 230, a channel layer 240, and a reversible resistive storage layer 250, these components sequentially covering the sidewall surface of the gate structure 220 located within the hole pattern 21.

[0026] Furthermore, the non-volatile memory device 2 may include a substrate insulating layer 202 and a lower channel contact layer 210 disposed between the substrate 201 and the gate structure 220. The lower channel contact layer 210 may contact the end of the channel layer 240. Although Figure 2 and Figure 3Not shown, but the non-volatile memory device 2 may include a channel-on-contact layer above the gate structure 220 and in contact with the other end of the channel layer 240. The non-volatile memory device 2 may include a filling insulating layer 260 that fills the remainder of the hole pattern 21 in which the gate insulating layer 230, the channel layer 240 and the reversible resistive storage layer 250 are disposed.

[0027] refer to Figure 2 and Figure 3 The provided substrate 201 may include a semiconductor material. A substrate insulating layer 202 may be disposed on the substrate 201. The substrate insulating layer 202 may electrically insulate the under-channel contact layer 210 from the substrate 201. The substrate insulating layer 202 may include an insulating material.

[0028] Although not shown, an integrated circuit may be disposed between the substrate 201 and the substrate insulating layer 202. The integrated circuit may include circuitry for driving and controlling a plurality of memory cells of the non-volatile memory device 2.

[0029] The lower channel contact layer 210 may be disposed on the substrate insulating layer 202. The lower channel contact layer 210 may be electrically connected to the channel layer 240. Although not shown, the lower channel contact layer 210 may be electrically connected to the source line. The lower channel contact layer 210 may include a conductive material.

[0030] Gate structure 220 may be disposed on the lower contact layer 210. Gate structure 220 may include a first gate electrode layer to a fourth gate electrode layer 222a, 222b, 222c, and 222d, and a first interlayer insulating layer to a fifth interlayer insulating layer 223a, 223b, 223c, 223d, and 223e. The gate electrode layer and the interlayer insulating layer may be alternately stacked along a first direction perpendicular to the upper surface of the substrate 201 (i.e., the z-direction). Figure 2 and Figure 3 As shown, the first to fourth gate electrode layers 222a, 222b, 222c, and 222d can be disposed adjacent to the channel layer 240 or the gate insulating layer 230. The first interlayer insulating layer 223a can be configured as the lower contact layer 210 of the contact channel. The fifth interlayer insulating layer 223e can be configured as the uppermost layer of the gate structure 220. Each of the first to fourth gate electrode layers 222a, 222b, 222c, and 222d may include a conductive material. Each of the first to fifth interlayer insulating layers 223a, 223b, 223c, 223d, and 223e may include an insulating material.

[0031] The number of gate electrode layers in gate structure 220 is not limited to four. In embodiments, the number of gate electrode layers can be set to different numbers, and the interlayer insulating layer can insulate different numbers of gate electrode layers from each other along a first direction (i.e., the z-direction).

[0032] refer to Figure 2 and Figure 3 The hole pattern 21 can be formed to penetrate the gate structure 220 in a first direction to expose the contact layer 210 below the channel. As an example, the hole pattern 21 can be formed by photolithography and etching processes.

[0033] A gate insulating layer 230 covering the sidewall surface of the gate structure 220 can be disposed inside the hole pattern 21. The gate insulating layer 230 may include an insulating material. A channel layer 240 may be disposed on the gate insulating layer 230 in a lateral direction. The channel layer 240 may extend inside the hole pattern 21 along a first direction (i.e., the z-direction). That is, the channel layer 240 may be disposed along the sidewall surface of the gate structure 220. The channel layer 240 may include a semiconductor material. The channel layer 240 may be doped with a dopant to have conductivity.

[0034] A reversible resistive storage layer 250 may be disposed on the sidewall surface of the channel layer 240. The reversible resistive storage layer 250 may extend in a first direction (i.e., the z-direction) within the hole pattern 21. That is, the reversible resistive storage layer 250 may be configured to contact the channel layer 240 along the sidewall surface of the gate structure 220.

[0035] The resistance state of the reversible resistance storage layer 250 can be variably changed according to the polarity or magnitude of the voltage applied to it. Furthermore, after the applied voltage is removed, the changed resistance state can be non-volatilely stored in the reversible resistance storage layer 250. As an example, the reversible resistance storage layer 250 can have two or more different resistance states, and it can non-volatilely store one of these two or more different resistance states. In other words, the reversible resistance storage layer 250 can have two or more resistance values ​​depending on the polarity or magnitude of the voltage applied to it.

[0036] The reversible resistive storage layer 250 may include a resistive switching material. The resistive switching material may have mobile oxygen vacancies or mobile metal ions. Oxygen vacancies may be positively charged. Metal ions may be positively charged cations or negatively charged anions. The resistive switching material may include, for example, titanium oxide, aluminum oxide, nickel oxide, copper oxide, zirconium oxide, manganese oxide, hafnium oxide, tungsten oxide, tantalum oxide, niobium oxide, iron oxide, or combinations of two or more of these. In other embodiments, the resistive switching material may include PCMO (Pr 1-x Ca x MnO3,0 <x<1)、LCMO(La 1-x Ca x MnO3,0 <x<1)、BSCFO(Ba 0.5Sr 0.5 Co 0.8 Fe 0.2 O 3-δ )、YBCO(YBa2Cu3O 7-x , 0 < x < 1), (Ba, Sr)TiO3 doped with chromium or niobium, SrZrO3 doped with chromium or vanadium, (La, Sr)MnO3, Sr 1-x La x TiO3(0 < x < 1), La 1-x Sr x FeO3(0 < x < 1), La 1-x Sr x CoO3(0 < x < 1), SrFeO 2.7 、LaCoO3、RuSr2GdCu2O3、YBa2Cu3O7, or a combination of two or more of them. The resistive switching material may include, for example, germanium-antimony-tellurium (GST), arsenic-antimony-tellurium (As-Sb-Te), tin-antimony-tellurium (Sn-Sb-Te), tin-indium-antimony-tellurium (Sn-In-Sb-Te), arsenic-germanium-antimony-tellurium (As-Ge-Sb-Te), Ge x Se 1-x (0 < x < 1), silver sulfide (Ag2S), copper sulfide (Cu2S), cadmium sulfide (CdS), zinc sulfide (ZnS) and cerium oxide (CeO2), or a combination of two or more of them.

[0037] On the other hand, a filling insulating layer 260 may be provided in the hole pattern 21 in which the gate insulating layer 230, the channel layer 240 and the reversible resistive memory layer 250 are formed. The filling insulating layer 260 may include an insulating material.

[0038] Although not shown in Figure 2 and Figure 3 , a contact layer on the channel in contact with the channel layer 240 may be provided on the gate structure 220. The contact layer on the channel may be electrically connected to a bit line (not shown). The contact layer on the channel may include a conductive material. The contact layer on the channel may be made of the same material as the contact layer 210 under the channel.

[0039] Referring to Figure 2 and Figure 3 , the non-volatile memory device 2 may include an arithmetic unit U21 in which the first storage unit to the fourth storage unit MC1, MC2, MC3 and MC4 are connected in series with each other. The arithmetic unit U21 may correspond to Figure 1 the storage string S in Figure 3 . That is, Figure 1The first to fourth storage units MC1, MC2, MC3 and MC4 in the circuit diagram.

[0040] As an example, the second memory cell MC2 may include a transistor device comprising a second gate electrode layer 222b, a portion 230MC2 of the gate insulating layer 230 that can be electrically controlled by or via the second gate electrode layer 222b, and a portion 240MC2 of the channel layer 240 that can be electrically controlled by or via the second gate electrode layer 222b. The transistor device may correspond to... Figure 1 The circuit diagram shows the second transistor device TR2. Furthermore, the second memory cell MC2 may include a portion 250MC2 of the reversible resistive storage layer 250 adjacent to a portion 240MC2 of the channel layer 240. This portion 250MC2 of the reversible resistive storage layer 250 can be used as a reversible resistive device for the second memory cell MC2. This portion 250MC2 of the reversible resistive storage layer 250 can correspond to... Figure 1 The second reversible resistor VRb in the circuit diagram.

[0041] Similarly, Figure 3 The first memory cell MC1, the third memory cell MC3, and the fourth memory cell MC4 shown can also be provided with corresponding transistor devices and reversible resistor devices in a manner substantially the same as that of the second memory cell MC2. That is, the first memory cell MC1, the third memory cell MC3, and the fourth memory cell MC4 can each include a first gate electrode layer 222a, a third gate electrode layer 222c, and a fourth gate electrode layer 222d. Furthermore, the first memory cell MC1, the third memory cell MC3, and the fourth memory cell MC4 can include portions of the gate insulating layer 230 and the channel layer 240 that are electrically controlled or via the first gate electrode layer 222a, the third gate electrode layer 222c, and the fourth gate electrode layer 222d, respectively. In addition, each of the first memory cell MC1, the third memory cell MC3 and the fourth memory cell MC4 may include a portion of the reversible resistive storage layer 250, which is adjacent to a portion of the corresponding channel layer 240 controlled by or via a corresponding portion of the gate electrode layer.

[0042] Figure 4 This is a flowchart schematically illustrating programming operations of a non-volatile storage device according to an embodiment of the present disclosure. Figure 5 This is a view illustrating an example of storing signal information in a non-volatile storage device by programming operations according to embodiments of the present disclosure. Figure 6A and Figure 6BThis is a view schematically illustrating a read operation of a non-volatile storage device according to an embodiment of the present disclosure. Figure 7A and Figure 7B This is a view schematically illustrating the programming operation of a non-volatile storage device according to an embodiment of the present disclosure. Figure 8A and Figure 8B This is a schematic view illustrating the programming voltage according to an embodiment of the present disclosure.

[0043] like Figure 4 The method shown for programming non-volatile memory devices can be used to... Figure 1 The storage cells MC1, MC2, MC3 and MC4 of the non-volatile storage device 1 and Figure 2 and Figure 3 The storage cells MC1, MC2, MC3 and MC4 of the non-volatile storage device 2 are programmed.

[0044] refer to Figure 4 Step S10 may provide a storage element comprising multiple storage cells. Each of the multiple storage cells may include a transistor device and a reversible resistor device.

[0045] In one embodiment, reference Figure 1 The storage element may include first to fourth storage cells MC1, MC2, MC3, and MC4 connected in series between the bit line BL and the source line SL. The first to fourth storage cells MC1, MC2, MC3, and MC4 may each include first to fourth transistors TR1, TR2, TR3, and TR4, and first to fourth reversible resistors VRa, VRb, VRc, and VRd. In one embodiment, reference... Figure 2 and Figure 3 The first to fourth memory cells MC1, MC2, MC3, and MC4 may share a channel layer 240 and a reversible resistive storage layer 250, each extending in a direction perpendicular to the upper surface of the substrate 201 (e.g., vertically). Each of the first to fourth memory cells MC1, MC2, MC3, and MC4 may include a portion of the reversible resistive storage layer 250, which is configured to be adjacent to the channel layer 240 and to overlap with the first to fourth gate electrode layers 222a, 222b, 222c, and 222d respectively in the vertical direction. These portions of the reversible resistive storage layer 250 may correspond to... Figure 1The first to fourth reversible resistive devices VRa, VRb, VRc, and VRd are included. Furthermore, the first to fourth memory cells MC1, MC2, MC3, and MC4 may include portions of the gate insulating layer 230, which are configured to be adjacent to the channel layer 240 and to overlap with the first to fourth gate electrode layers 222a, 222b, 222c, and 222d respectively in the vertical direction. These portions of the first to fourth gate electrode layers 222a, 222b, 222c, and 222d, and the gate insulating layer 230, can respectively constitute... Figure 1 The first to fourth transistors are TR1, TR2, TR3 and TR4.

[0046] refer to Figure 4 Step S11 involves selecting a target memory cell to be programmed from a plurality of memory cells. In the following description, an embodiment will be described in which... Figure 1 and Figure 2 The second storage unit MC2 among the first to fourth storage units MC1, MC2, MC3, and MC4 shown is selected as the target storage unit. In other embodiments, if the first storage unit MC1, the third storage unit MC3, or the fourth storage unit MC4 is selected as the target storage unit, essentially the same programming method can be applied.

[0047] refer to Figure 4 Step S12 determines the target resistance state of the target memory cell. That is, the target resistance state can be selected as the signal information to be written into the reversible resistor device of the target memory cell. In one embodiment, one of two different resistance states corresponding to 1 bit of signal information can be held as signal information in the reversible resistor device. In other embodiments, one of a plurality of different resistance states corresponding to 2 bits or more of signal information can be held as signal information in the reversible resistor device.

[0048] Figure 5 The illustration shows an example of signal information that can be selected in step S12 to be written into the reversible resistive device to indicate the target resistance state. (Reference) Figure 5In one embodiment, when the second storage cell MC2, serving as the target storage cell, stores 3 bits of signal information, the second storage cell MC2 can have one of eight different resistance states R1, R2, R3, R4, R5, R6, R7, and R8. The first to eighth resistance states R1, R2, R3, R4, R5, R6, R7, and R8 can be distinguished from each other using first to seventh reference resistors Rv1, Rv2, Rv3, Rv4, Rv5, Rv6, and Rv7, respectively. Each of the first to eighth resistance states R1, R2, R3, R4, R5, R6, R7, and R8 can have a resistance distribution. As an example, the resistance value of the fifth resistance state R5 can be distributed between the fourth reference resistor Rv4 and the fifth reference resistor Rv5. In this case, the probability distribution can be highest at the midpoint between the fourth reference resistor Rv4 and the fifth reference resistor Rv5, and lowest at the boundary values ​​adjacent to either the fourth or fifth reference resistor Rv4. Other resistance states besides the fifth resistance state can have the same or substantially similar resistance distribution shapes. Figure 4 In step S12, one of the first to eighth resistor states R1, R2, R3, R4, R5, R6, R7 and R8 can be determined as the target resistor state to be written into the reversible resistor device of the second memory cell MC2.

[0049] refer to Figure 4 Step S13 allows reading the resistance state of the target memory cell. That is, it allows reading the resistance state of the reversible resistive device stored or held in the target memory cell. In one embodiment, this can be achieved using... Figure 6A Circuit diagram and Figure 6B The structural diagram is used to describe step S13.

[0050] refer to Figure 6A The first transistor TR1 of the first memory cell MC1, the third transistor TR3 of the third memory cell MC3, and the fourth transistor TR4 of the fourth memory cell MC4 can be turned on to form the first conductive channel ch1, the third conductive channel ch3, and the fourth conductive channel ch4, respectively. At this time, the second transistor TR2 of the second memory cell MC2, which is the target memory cell, can be turned off. As an example, to turn on the first transistor TR1, the third transistor TR3, and the fourth transistor TR4, a pass voltage with an amplitude greater than or equal to a threshold voltage can be applied to the first gate electrode G1, the third gate electrode G3, and the fourth gate electrode G4. A voltage of 0V or lower than the threshold voltage can be applied to the second gate electrode G2 of the second transistor TR2.

[0051] Subsequently, a read voltage can be applied between the bit line BL and the source line SL to measure the operating current Ir1 through the first to fourth memory cells MC1, MC2, MC3, and MC4. The read voltage can have an amplitude that does not change the resistance state stored or maintained in the first to fourth reversible resistors VR1, VR2, VR3, and VR4 of the first to fourth memory cells MC1, MC2, MC3, and MC4.

[0052] Refer again Figure 6A When the operating current Ir1 passes through the first storage cell MC1, the third storage cell MC3, and the fourth storage cell MC4, it can flow along the first conductive channel ch1, the third conductive channel ch3, and the fourth conductive channel ch4. Because no conductive channel is formed in the second transistor device TR2 of the second storage cell MC2, the operating current Ir1 can flow along the second reversible resistor VRb when passing through the second storage cell MC2. By calculating the resistance of the second reversible resistor VRb based on the measured operating current Ir1, the current reflecting the resistance state of the second storage cell MC2 can be read or determined.

[0053] refer to Figure 6B A pass voltage with an amplitude greater than or equal to a threshold voltage can be applied to the first gate electrode layer 222a, the third gate electrode layer 222c, and the fourth gate electrode layer 222d. Therefore, conductive channels 2000 can be formed in those portions of the channel layer 240 electrically controlled by the first gate electrode layer 222a, the third gate electrode layer 222c, and the fourth gate electrode layer 222d. By applying a voltage of 0V or less than the threshold voltage to the second gate electrode layer 222b, conductive channels are not formed in the portions of the channel layer 240 electrically controlled by the second gate electrode layer 222b. Therefore, conductive channels 2000 can be disconnected within the portion of the channel layer 240 belonging to the second memory cell MC2.

[0054] Subsequently, a read voltage can be applied between the upper and lower ends of the channel layer 240, and the operating current Ir2 can be measured. As an example, a read voltage can be applied between the lower channel contact layer 210 and the upper channel contact layer (not shown). The upper channel contact layer can be configured to contact the channel layer 240 above the fifth interlayer insulating layer 223e. The operating current Ir2 can flow along the conductive channel 2000 of the channel layer 240. However, the conductive channel 2000 is disconnected at the portion of the channel layer 240 belonging to the second memory cell MC2, so the operating current Ir2 can flow through the reversible resistive storage layer 250 located between the two ends 2000E1 and 2000E2 of the conductive channel 2000. By calculating the resistance between the disconnected ends 2000E1 and 2000E2 of the conductive channel 2000 using the measured operating current Ir2, the resistance state of the second memory cell MC2 can be read or determined.

[0055] refer to Figure 4 Step S14 can compare the read resistance state of the target memory cell with the target resistance state. Step S14 may include steps S141 and S142, which are executed sequentially. First, refer to Figure 4 In step S141, it can be determined whether the read resistance state of the target memory cell is the same as the target resistance state. When the read resistance state of the target memory cell is the same as the target resistance state, the target memory cell can maintain its read resistance state and the programming operation on the target memory cell can be terminated. If the read resistance state of the target memory cell is different from the target resistance state, the process can proceed to step S142.

[0056] refer to Figure 4 In step S142, when the read resistance state of the target memory cell is higher than the target resistance state, the process can proceed to step S15 to perform a positive programming operation on the target memory cell. The positive programming operation can be an operation that converts or changes the existing resistance state of the reversible resistor of the target memory cell to the target resistance state by decreasing the resistance of the reversible resistor. Conversely, when the read resistance state of the target memory cell is lower than the target resistance state, the process can proceed to step S16 to perform a negative programming operation on the target memory cell. The negative programming operation can be an operation that converts or changes the existing resistance state of the reversible resistor of the target memory cell to the target resistance state by increasing the resistance of the reversible resistor.

[0057] In one embodiment, reference Figure 4 , Figure 5 and Figure 6AWhen the read resistance state Ri of the second memory cell MC2, which is the target memory cell, is the fifth resistance state R5 and the target resistance state Rf1 is the third resistance state R3, a positive programming operation can be performed in step S15. In another embodiment, when the read resistance state Ri of the second memory cell MC2, which is the target memory cell, is the fifth resistance state R5 and the target resistance state Rf2 is the seventh resistance state R7, a negative programming operation can be performed in step S16.

[0058] In the following text, reference will be made to Figure 7A and Figure 7B Describe in detail the positive and negative programming operations used for the second memory unit MC2.

[0059] refer to Figure 7A The first transistor TR1 of the first memory cell MC1, the third transistor TR3 of the third memory cell MC3, and the fourth transistor TR4 of the fourth memory cell MC4 can be turned on to form the first conductive channel ch1, the third conductive channel ch3, and the fourth conductive channel ch4, respectively. At this time, the second transistor TR2 of the second memory cell MC2, which is the target memory cell, can be turned off. As an example, to turn on the first transistor TR1, the third transistor TR3, and the fourth transistor TR4, a pass voltage with an amplitude greater than or equal to a threshold voltage can be applied to the first gate electrode G1, the third gate electrode G3, and the fourth gate electrode G4. A voltage of 0V or lower than the threshold voltage can be applied to the second gate electrode G2 of the second transistor TR2.

[0060] Subsequently, a write voltage can be applied between the bit line BL and the source line SL. In one embodiment, when performing a positive programming operation, a voltage of 0V can be applied to the source line SL and a write voltage with positive polarity can be applied to the bit line BL. In another embodiment, when performing a negative programming operation, a voltage of 0V can be applied to the source line SL and a write voltage with negative polarity can be applied to the bit line BL.

[0061] In the example of positive programming operation, the operating current Iw1 generated by the positive write voltage can flow through the first memory cell to the fourth memory cells MC1, MC2, MC3, and MC4. When the operating current Iw1 passes through the first memory cell MC1, the third memory cell MC3, and the fourth memory cell MC4, it can flow along the first conductive channel ch1, the third conductive channel ch3, and the fourth conductive channel ch4. Because no conductive channel is formed in the second transistor device TR2 of the second memory cell MC2, the operating current Iw1 can flow along the second reversible resistor device VRb when passing through the second memory cell MC2. Therefore, when the write voltage is applied, the positive programming voltage Vpg1 can be applied across the second reversible resistor device VRb of the second memory cell MC2. In this case, the polarity of the programming voltage Vpg1 can follow the polarity of the write voltage. The programming voltage Vpg1 can change the resistance of the second reversible resistor device VRb. For example, when the programming voltage Vpg1 has a positive polarity, the resistance of the second reversible resistor VRb can be reduced, thereby the resistance state of the second reversible resistor VRb can be switched or changed to a lower resistance state.

[0062] In another embodiment, a negative programming operation can be performed, wherein the operating current flows from the source line SL to the bit line BL. When a negative programming voltage Vpg1 is applied across the second reversible resistor VRb of the second memory cell MC2, the resistance of the second reversible resistor VRb can be increased, such that the resistance state of the second reversible resistor VRb can be switched to a higher resistance state.

[0063] After the write voltage is removed, the second reversible resistor VRb can retain its changed resistance state in a non-volatile manner. Through the above process, programming operations can be performed on the second reversible resistor VRb of the second memory cell MC2.

[0064] refer to Figure 7B A pass voltage with an amplitude greater than or equal to a threshold voltage can be applied to the first gate electrode layer 222a, the third gate electrode layer 222c, and the fourth gate electrode layer 222d. Therefore, a conductive channel 2000 can be formed in the portion of the channel layer 240 electrically controlled by the first gate electrode layer 222a, the third gate electrode layer 222c, and the fourth gate electrode layer 222d. By applying a voltage of 0V or less than the threshold voltage to the second gate electrode layer 222b, no conductive channel is formed in the portion of the channel layer 240 electrically controlled by the second gate electrode layer 222b. Therefore, the conductive channel 2000 can be disconnected in the portion of the channel layer 240 belonging to the second memory cell MC2.

[0065] Subsequently, a write voltage can be applied between the upper and lower ends of the channel layer 240. As an example, the write voltage can be applied between the lower channel contact layer 210 and the upper channel contact layer (not shown). The upper channel contact layer can be configured to contact the channel layer 240 above the fifth interlayer insulating layer 223e.

[0066] The operating current Iw2 generated by the positive write voltage can flow along the conductive channel 2000 of the channel layer 240. However, because the conductive channel 2000 is disconnected at the portion of the channel layer 240 belonging to the second memory cell MC2, the operating current Iw2 can flow through the reversible resistive storage layer 250 located between the disconnected ends 2000E1 and 2000E2 of the conductive channel 2000. Therefore, when the write voltage is applied, a positive programming voltage Vpg2 can be applied to the reversible resistive storage layer 250 located between the disconnected ends 2000E1 and 2000E2 of the conductive channel 2000. In this case, the polarity of the programming voltage Vpg2 can follow the polarity of the write voltage. The programming voltage Vpg2 can change the resistance of the portion of the reversible resistive storage layer 250 belonging to memory cell MC2. As an example, when a programming voltage Vpg2 with positive polarity is applied, the resistance of the reversible resistance storage layer 250 between the disconnected ends 2000E1 and 2000E2 of the conductive channel 2000 can be reduced, thereby the resistance state of the reversible resistance storage layer 250 between the disconnected ends 2000E1 and 2000E2 of the conductive channel 2000 can be converted to a lower resistance state.

[0067] In another embodiment, negative programming can be performed, wherein the operating current flows from the lower contact layer 210 of the channel to the upper contact layer of the channel. When a programming voltage Vpg2 with negative polarity is applied between the disconnected ends 2000E1 and 2000E2 of the conductive channel 2000, the resistance of the reversible resistance storage layer 250 located in this region increases, such that the resistance state of the reversible resistance storage layer 250 between the disconnected ends 2000E1 and 2000E2 of the conductive channel 2000 can be changed to a higher resistance state.

[0068] After the write voltage is removed, the portion of the second reversible resistive storage layer 250 corresponding to the second gate electrode layer 222b can non-volatilely retain the transformed resistive state. Through the above process, programming operations can be performed on the portion of the reversible resistive storage layer 250 of the second memory cell MC2.

[0069] In one embodiment, refer again Figure 4 When the operation moves from step S142 to step S15, a positive programming operation on the target memory cell can be performed in step S15. (Refer to...) Figure 5In the example, when the read resistance state Ri of the second memory cell MC2, which is the target memory cell, is the fifth resistance state R5 and the target resistance state Rf1 is the third resistance state R3, a positive programming operation can be performed on the second memory cell MC2. In one embodiment, the positive programming operation in step S15 can be performed by the following programming loop: Figure 8A The diagram includes the first writing steps to the Nth writing steps P1p, P2p, P3p, ... and PNp, and the first verification steps to the Nth verification steps P1f, P2f, P3f, ... and PNf.

[0070] Refer again Figure 4 Step S15 may include steps S151 and S152, which are executed sequentially. In step S151, a positive programming voltage may be applied to the reversible resistive device of the second memory cell MC2, which is the target memory cell. Specifically, refer to... Figure 8A The first write step P1p, which converts the resistance state of the reversible resistor to a third resistance state R3 corresponding to the target resistance state Rf1, can be performed by applying a first positive programming pulse voltage Vsp1 as the positive polarity programming voltage of the reversible resistor. In step S152, the first write step P1p, which converts the resistance state of the reversible resistor to a third resistance state R3 corresponding to the target resistance state Rf1, can be performed by applying a first positive programming pulse voltage Vsp1 as the positive polarity programming voltage of the reversible resistor of the second memory cell MC2. Figure 8A The positively polarized verification pulse voltage Vf is used to perform the first verification step P1f of the first write step P1p. The first verification step P1f may be a step to verify whether the resistance state in the reversible resistor device written to the second memory cell MC2 after the first write step P1p is the same as the target resistance state Rf1.

[0071] In step S152, when it is verified that the resistance state of the reversible resistor device of the second memory cell MC2 is the same as the third resistance state R3, which is the target resistance state Rf1, the second memory cell MC2 can maintain the third resistance state R3, and the programming operation on the second memory cell MC2 can be terminated. Specifically, if the resistance written into the reversible resistor device of the second memory cell MC2 is located at... Figure 5 The value between the second reference resistor Rv2 and the third reference resistor Rv3 can be used to verify that the resistor is in the third resistor state R3, and the programming operation can be terminated.

[0072] On the other hand, when it is verified in step S152 that the resistance state in the reversible resistor device written to the second memory cell MC2 is different from the target resistance state Rf1, the process returns to step S142. However, instead of comparing the read resistance state with the target resistance state, step S142 now compares the resistance state written to the reversible resistor device in step S151 with the target resistance state Rf1. Based on the comparison result of the resistance state in step S142, a positive programming operation can be performed again in step S15, or a negative programming operation can be performed in step S16. For example, when the resistance state of the reversible resistor device written to the second memory cell MC2 is higher than the target resistance state Rf1... Figure 5 When the third reference resistor Rv3 is used, the positive programming operation can be performed again in step S15. When the resistance state of the reversible resistor element written to the second memory cell MC2 is lower than the value of the third reference resistor Rv3, the positive programming operation can be performed again in step S15. Figure 5 When the second reference resistor Rv2 is used, a negative programming operation can be performed in step S16.

[0073] In one embodiment, when the positive programming operation is performed again in step S15, a further write step can be performed on the reversible resistive device of the second memory cell MC2 in step S151. (See reference) Figure 8A The second writing step P2p can be a step of applying a second positive programming pulse voltage Vsp2 with positive polarity to the reversible resistive device. The amplitude of the second positive programming pulse voltage Vsp2 can be larger than the amplitude of the first positive programming pulse voltage Vsp1 in the first writing step P1p by a step voltage ΔVs1.

[0074] Subsequently, in step S152, the second verification step P2f is performed, wherein, as shown in... Figure 8A The verification pulse voltage Vf shown is applied to the reversible resistor device to verify the result of the second write step P2p. In the second verification step P2f, when it is verified that the obtained resistance state in the reversible resistor device is the same as the target resistance state Rf1, the programming operation on the second memory cell MC2 can be terminated. However, if it is verified in the second verification step P2f that the resistance state of the written reversible resistor element is different from the target resistance state Rf1, the process can return to step S142 again.

[0075] The loop between S15 and S142 can be repeated. (See reference) Figure 8AWhen the resistance state written to the second memory cell MC2 continues to be greater than the target resistance state Rf1, additional positive write steps P3p, ..., PNp, and VspN can be performed by applying positive programming pulse voltages Vsp3, ..., PNp. Each subsequent positive programming pulse voltage can be incremented by a step voltage ΔVs1, and each change in the write resistance state can be verified separately by verification steps P3f, ..., PNf. The positive write steps P3p, ..., PNp and verification steps P3f, ..., PNf can be repeated until the resistance state written to the second memory cell MC2 is the same as the target resistance state Rf1, or until the resistance state written to the second memory cell MC2 is lower than the target resistance state Rf1. For example, during the sequential execution of the positive write steps P3p, ..., PNp, when the resistance state written to the second memory cell MC2 corresponds to the third resistance state R3 (which is... Figure 5 The programming operation can be terminated when the target resistance state (Rf1) is reached. In another example, during sequential execution... Figure 8A During the positive write steps P3p, ..., and PNp, when the resistance state of the second memory cell MC2 is lower than the resistance state R3 ( Figure 5 When the target resistance state is Rf1, the process can move to step S16 and negative programming can be performed.

[0076] In one embodiment, it can be performed in step S151. Figure 8A The magnitude of the step voltage ΔVs1 is determined before the first writing step P1p. In another embodiment, the magnitude of the step voltage ΔVs1 can be determined based on the result of the first verification step P1f in step S152.

[0077] In another embodiment, refer again Figure 4 When proceeding from step S142 to step S16, a negative programming operation on the target memory cell can be performed in step S16. (Refer to...) Figure 5 In the example, when the read resistance state Ri of the second memory cell MC2, which is the target memory cell, is the fifth resistance state R5 and the target resistance state Rf2 is the seventh resistance state R7, a negative programming operation can be performed on the second memory cell MC2. In one embodiment, the negative programming operation in step S16 can be performed by the following programming loop, which includes as follows: Figure 8B The first write steps to the Nth write steps P1n, P2n, P3n, ... and PNn, and the first verification steps to the Nth verification steps P1f, P2f, P3f, ... and PNf are shown.

[0078] Step S16 may include steps S161 and S162, which are executed sequentially. In step S161, a negative programming voltage may be applied to the reversible resistive device of the second memory cell MC2, which is the target memory cell. Specifically, refer to... Figure 8B The first write step P1n, which converts the resistance state of the reversible resistor to the seventh resistance state R7 corresponding to the target resistance state Rf2, can be performed by applying a first negative programming pulse voltage Vsn1, which is a negative programming voltage, to the reversible resistor. In step S162, the first write step P1n, which converts the resistance state of the reversible resistor to the seventh resistance state R7 corresponding to the target resistance state Rf2, can be performed by applying a first negative programming pulse voltage Vsn1, which is a negative programming voltage, to the reversible resistor of the second memory cell MC2. Figure 8B The positively polarized verification pulse voltage Vf shown is used to perform the first verification step P1f of the first write step P1n. The first verification step P1f can be a step that verifies, after the first write step P1n, whether the resistance state in the reversible resistor device written to the second memory cell MC2 is the same as the target resistance state Rf2.

[0079] In step S162, when it is verified that the resistance state of the reversible resistor in the second memory cell MC2 is the same as the seventh resistance state R7, which is the target resistance state Rf2, the second memory cell MC2 can maintain the seventh resistance state R7, and the programming operation on the second memory cell MC2 can be terminated. Specifically, if the value of the resistance state written into the reversible resistor in the second memory cell MC2 is between... Figure 5 By connecting the sixth reference resistor Rv6 and the seventh reference resistor Rv7, the resistor state can be verified as the seventh resistor state R7, and the programming operation can be terminated.

[0080] On the other hand, when it is verified in step S162 that the resistance state in the reversible resistor device written to the second memory cell MC2 is different from the target resistance state Rf2, the process returns to step S142. However, instead of comparing the read resistance state with the target resistance state, in step S142, the resistance state in the reversible resistor device written in step S161 is compared with the target resistance state Rf2. Based on the comparison result of the resistance state in step S142, a negative programming operation can be performed again in step S16, or a positive programming operation can be performed in step S15. For example, when the resistance state in the reversible resistor device written to the second memory cell MC2 is lower than the sixth reference resistor Rv6, a negative programming operation can be performed again in step S16. When the resistance state in the reversible resistor device written to the second memory cell MC2 is higher than the target resistance state Rf2, a negative programming operation can be performed again in step S16. Figure 5 When the seventh reference resistor Rv7 is used, a positive programming operation can be performed in step S15.

[0081] In one embodiment, when the negative programming operation is performed again in step S16, a further write step can be performed on the reversible resistive device of the second memory cell MC2 in step S161. (See reference) Figure 8B The second writing step can be a step P2n in which a second negative programming pulse voltage Vsn2 with negative polarity is applied to the reversible resistive device. The amplitude of the second negative programming pulse voltage Vsn2 can be larger than the amplitude of the first negative programming pulse voltage Vsn1 in the first writing step P1n by a step voltage ΔVs2.

[0082] Subsequently, in step S162, an application such as... can be performed on the reversible resistive device. Figure 8B The second verification step P2f, shown, verifies the result of the second write step P2n by verifying the pulse voltage Vf. In the second verification step P2f, if the obtained resistance state in the reversible resistor device is verified to be the same as the target resistance state Rf2, the programming operation on the second memory cell MC2 can be terminated. However, if in the second verification step P2f, it is verified that the resistance state written to the reversible resistor element is different from the target resistance state Rf2, the process can return to step S142.

[0083] The loop between S16 and S142 can be repeated. (See reference) Figure 8B When the resistance state of the second memory cell MC2 continues to be lower than the target resistance state Rf2, additional negative write steps P3n, ..., PNn can be performed by applying negative programming voltages Vsn3, ..., VsnN. Each subsequent negative programming pulse voltage can be incremented by a step voltage ΔVs2, and each change in the write resistance state can be verified separately by verification steps P3f, ..., PNf. The negative write steps P3n, ..., PNn and the verification steps P3f, ..., PNf can be repeated separately, while increasing the pulse voltage amplitude by a step voltage ΔVs2 in each cycle. The negative write steps P3n, P4n, ..., PNn can be repeated until the resistance state of the second memory cell MC2 is the same as the target resistance state Rf2, or until the resistance state of the second memory cell MC2 is higher than the target resistance state Rf2. For example, when the resistance state of the second memory cell MC2 is higher than the seventh resistance state R7, which is the target resistance state Rf2, the process can move to step S15 to perform a positive programming operation.

[0084] In one embodiment, it can be performed in step S161. Figure 8B The magnitude of the step voltage ΔVs2 is determined before the first writing step P1n. In another embodiment, the magnitude of the step voltage ΔVs2 can be determined based on the result of the first verification step P1f in step S162.

[0085] As described above, by executing according to Figure 4 The steps in the flowchart can be used to perform the operation method of the non-volatile storage device according to the embodiments of this disclosure.

[0086] As mentioned above, Figure 8A The programming loop provides for Figure 4 The positive programming operation in step S15, and Figure 8B The programming loop provides for Figure 4 The negative programming operation in step S16, but this disclosure is not necessarily limited to this. Specifically, in Figure 8A In the programming cycle, the first positive programming voltage to the Nth positive programming voltage Vsp1, Vsp2, Vsp3, ..., VspN are increased by a constant step voltage ΔVs1. However, in some embodiments, the first positive programming voltage to the Nth positive programming voltage Vsp1, Vsp2, Vsp3, ..., VspN may not necessarily increase by a constant voltage level sequentially. Similarly, in Figure 8B In the programming cycle, the first negative programming voltage to the Nth negative programming voltage Vsn1, Vsn2, Vsn3, ... and VsnN are increased by a constant step voltage ΔVs2. However, in some embodiments, the first negative programming voltage to the Nth negative programming voltage Vsn1, Vsn2, Vsn3, ... and VsnN may not necessarily increase by a constant voltage level.

[0087] When repeatedly performing a programming operation on one of a plurality of memory cells having a reversible resistive device according to embodiments of the present disclosure, an erase operation similar to that of conventional flash memory devices may not be necessary. That is, in conventional flash memory devices, when a second programming operation is performed on a memory cell that has already undergone a first programming operation, an erase operation is performed between operations—this erase operation erases electrons stored in the charge storage layer of the memory cell by the first programming operation. The second programming operation can be performed on a memory cell that has already undergone an erase operation. Conversely, in a non-volatile memory device including a reversible resistive device according to embodiments of the present disclosure, the resistance state of the reversible resistive device in the memory cell can be directly converted from the current resistance state to a target resistance state—which can be one of multiple resistance states. Therefore, the programming speed of the signal information of the memory cell can be improved by avoiding separate erase operations.

[0088] Furthermore, in the programming method for non-volatile storage devices according to embodiments of this disclosure, a programming loop including multiple write steps and multiple verification steps can be applied when performing a positive programming operation or a negative programming operation. Therefore, when signal information is stored, the signal level can be controlled more precisely, thereby enabling reliable execution of the programming operation.

[0089] Non-volatile memory devices according to various embodiments of this disclosure may have a cell structure similar to that of conventional NAND flash memory devices. As an example, a non-volatile memory device may include a plurality of memory strings S, the memory strings comprising, for example... Figure 1 The first to fourth memory cells MC1, MC2, MC3, and MC4 are shown. One end of each of the plurality of memory strings S can be connected to a common bit line BL, and the other end of each of the plurality of memory strings S can be connected to a common source line SL. In this way, a non-volatile storage device can include a memory block containing a plurality of memory strings S.

[0090] Furthermore, the first gate electrodes G1 of the first storage cells MC1 of the multiple storage strings S are connected to each other, so that the multiple first storage cells MC1 can form a first page. In the same way, the multiple second storage cells MC2, the multiple third storage cells MC3, and the multiple fourth storage cells MC4 can form a second page, a third page, and a fourth page, respectively.

[0091] In the case of the non-volatile memory device according to embodiments of the present disclosure, in the above-described cell structure, positive programming operations, negative programming operations, and read operations can be performed on a cell-by-cell basis in the random access method. In contrast, in the case of conventional NAND flash memory devices, erase operations can be performed on a block-by-block basis, and programming and read operations can be performed on a page-by-page basis. Therefore, the non-volatile memory device according to embodiments of the present disclosure can have an increased storage capacity for cell signal information due to the disclosed operating method.

[0092] For illustrative purposes, embodiments of this disclosure have been disclosed. Those skilled in the art will understand that various modifications, additions, and substitutions are possible without departing from the scope and spirit of this disclosure and the appended claims.

Claims

1. A method for programming a non-volatile storage device, comprising: A memory element comprising a plurality of memory cells is provided, the plurality of memory cells being connected in series along a channel layer extending in a direction perpendicular to the upper surface of a substrate, each of the plurality of memory cells comprising a reversible resistive memory layer and a gate electrode layer disposed adjacent to the channel layer; Select a target memory cell from the plurality of memory cells, and determine the target resistance state of the reversible resistive storage layer for the target memory cell; The resistance state is read by measuring the operating current flowing through the reversible resistive storage layer of the target memory cell; Compare the read resistance state with the target resistance state; as well as When the read resistance state differs from the target resistance state, one of a positive programming operation and a negative programming operation is performed on the reversible resistance storage layer of the target memory cell to change the resistance state of the reversible resistance storage layer. The step of reading the resistance state of the reversible resistive storage layer includes: Applying a pass voltage to the gate electrode layer of a non-target memory cell among the plurality of memory cells to form a conductive channel in the channel layer portion of the non-target memory cell; and A read voltage is applied to the upper and lower ends of the channel layer to measure the operating current flowing through the conductive channel of the non-target memory cell and the reversible resistive storage layer of the target memory cell.

2. The method of claim 1, further comprising: When the read resistance state is the same as the target resistance state, the programming operation of the reversible resistance storage layer of the target storage cell is terminated.

3. The method of claim 1, wherein, When the read resistance state is higher than the target resistance state, the positive programming operation is performed to reduce the resistance of the reversible resistive storage layer of the target memory cell, and The positive programming operation includes a first write step of applying a positive positive programming pulse voltage to the reversible resistive storage layer, and a first verification step of applying a positive verification pulse voltage to the reversible resistive storage layer to verify the first write step.

4. The method of claim 3, wherein, The positive programming operation further includes: a second write step, wherein when the first verification step determines that the resistance state of the reversible resistive storage layer is higher than the target resistance state, a second positive programming pulse voltage of positive polarity, which is one step larger than the first positive programming pulse voltage, is applied to the reversible resistive storage layer; and a second verification step, wherein the verification pulse voltage is applied to the reversible resistive storage layer to verify the second write step. Specifically, when the first verification step determines that the resistance state of the reversible resistance storage layer is lower than the target resistance state, the negative programming operation that increases the resistance of the reversible resistance storage layer is executed.

5. The method of claim 1, wherein, When the read resistance state is lower than the target resistance state, the negative programming operation is performed to increase the resistance of the reversible resistive storage layer of the target memory cell, and The negative programming operation includes a first write step of applying a negative polarity first negative programming pulse voltage to the reversible resistive storage layer, and a first verification step of applying a positive polarity verification pulse voltage to the reversible resistive storage layer to verify the first write step.

6. The method of claim 5, wherein, The negative programming operation further includes: a second write step, wherein when the first verification step determines that the resistance state of the reversible resistive storage layer is lower than the target resistance state, a second negative programming pulse voltage of negative polarity, which is one step larger than the first negative programming pulse voltage, is applied to the reversible resistive storage layer; and a second verification step, wherein the verification pulse voltage is applied to the reversible resistive storage layer to verify the second write step; and Specifically, when the first verification step determines that the resistance of the reversible resistance storage layer is higher than the target resistance state, the positive programming operation that reduces the resistance of the reversible resistance storage layer is executed.

7. The method of claim 1, wherein, The steps of performing the positive programming operation on the reversible resistive storage layer of the target memory cell include: Applying a pass voltage to the gate electrode layer of a non-target memory cell among the plurality of memory cells to form a conductive channel in the channel layer portion of the non-target memory cell; and A positive write voltage is applied to the upper and lower ends of the channel layer to change the resistance state of the reversible resistive storage layer of the target memory cell.

8. The method of claim 1, wherein, The steps of performing the negative programming operation on the reversible resistive storage layer of the target memory cell include: Applying a pass voltage to the gate electrode layer of a non-target memory cell among the plurality of memory cells to form a conductive channel in the channel layer portion of the non-target memory cell; and A negative write voltage is applied to the upper and lower ends of the channel layer to change the resistance state of the reversible resistive storage layer of the target memory cell.

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