Cell preparation method and structure of planar SiC MOSFET device

Abstract

The application relates to a cell preparation method and structure of a planar SiC MOSFET device. The method comprises the following steps: step 1, providing a SiC wafer and preparing a second conductive type layer; step 2, preparing a first implantation mask; step 3, forming a plurality of required first type implantation regions in the second conductive type layer; step 4, preparing a required implantation second mask; step 5, preparing a first conductive type connection region, so that the second conductive type layer on both sides of the first conductive type connection region is isolated through the first conductive type connection region and the first conductive type implantation region directly above the first conductive type connection region; and step 6, removing the implantation second mask and performing a required front cell process to prepare a required planar cell. The application can avoid damage caused by implantation at a channel, improve channel mobility and enhance reliability.

Description

Technical Field

[0001] This invention relates to a fabrication method, and more particularly to a cell fabrication method and structure for a planar SiC MOSFET device. Background Technology

[0002] The total on-resistance of a SiC MOSFET is composed of ohmic contact resistance, channel resistance, JFET resistance, drift region resistance, and wafer body resistance. Among these, the magnitude of the channel resistance is one of the key factors affecting the total on-resistance.

[0003] In the specific fabrication process of SiC MOSFETs, the main factors affecting the channel length are the layout linewidth and overlay accuracy. To avoid errors caused by photolithography, self-aligned processes are often used when using the dual-injection method to achieve uniformity in device performance. Specifically, the self-aligned process relies on the processing accuracy of the hard mask to control the size of the injection region. Due to the high difficulty of the precise etching process of the hard mask, controlling the processing uniformity is very challenging.

[0004] Furthermore, in planar SiC MOSFETs, cells are typically formed using ion implantation. Due to the inherent properties of silicon carbide, the damage caused by implantation results in roughness at the channel-gate oxide interface, significantly impacting key characteristics of SiC MOSFETs such as channel mobility and reliability. Simultaneously, it poses significant challenges to process control, making it difficult to meet current requirements for high-precision fabrication of planar SiC MOSFETs. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of the prior art and provide a cell fabrication method and structure for a planar SiC MOSFET device, which can avoid damage caused by implantation at the channel and improve channel mobility while enhancing reliability.

[0006] According to the technical solution provided by the present invention, a method and structure for fabricating a planar SiC MOSFET device are disclosed, wherein the method for fabricating the conductive channel includes the following steps:

[0007] Step 1: Provide a SiC wafer with a first conductivity type, and fabricate a layer with a second conductivity type on the SiC wafer;

[0008] Step 2: Fabricate the required first injection shield on the second conductivity type layer;

[0009] Step 3: Implant first conductivity type impurity ions above the second conductivity type layer, and use the first shielding body to shield the second conductivity type layer to form several required first type implantation regions in the second conductivity type layer. The implantation depth of the first conductivity type implantation region in the second conductivity type layer is less than the thickness of the second conductivity type layer.

[0010] Step 4: Remove the first injection shielding body and prepare the required second injection shielding body on the second conductivity type layer. The second injection shielding body includes a plurality of injection windows. The injection windows correspond to the first type injection areas between the conductive channel areas in the second conductivity type layer, and expose the first conductivity type injection areas between the conductive channel areas to be formed through the injection windows.

[0011] Step 5: Using the implantation of the second shield, perform first conductivity type impurity ion implantation on the second conductivity type layer to obtain a first conductivity type connection region directly below the first conductivity type implantation region between the conductive channel regions. The upper end of the first conductivity type connection region is in contact with the corresponding first conductivity type implantation region, and the lower end of the first conductivity type connection region is in contact with the SiC wafer. The second conductivity type layers on both sides of the first conductivity type connection region are isolated through the first conductivity type connection region and the first conductivity type implantation region directly above the first conductivity type connection region.

[0012] Step 6: Remove the injected second occluder and perform the required front cell process to prepare the desired planar cell.

[0013] The SiC wafer includes a first conductivity type substrate and a first conductivity type epitaxial layer disposed on the first conductivity type substrate.

[0014] The second conductivity type layer is adapted and connected to the first conductivity type epitaxial layer; the second conductivity type layer is prepared by epitaxial process or ion implantation process.

[0015] Step 2, when preparing the first shielding body, includes the following steps:

[0016] Step 2.1: Prepare an implanted first mask layer on the second conductivity type layer;

[0017] Step 2.2: Selectively mask and etch the first injection mask layer to obtain a plurality of first mask layer injection windows that penetrate the first injection mask layer, so as to form the desired first injection shield with the first injection mask layer using the injection windows of the first injection mask layer.

[0018] The material injected into the first mask layer includes photoresist, silicon oxide, polysilicon, or silicon nitride.

[0019] It also includes the front cell process for forming the front cell structure and the back electrode process for forming the back electrode structure.

[0020] The material injected into the second shield includes photoresist, silicon oxide, polysilicon, or silicon nitride.

[0021] The second conductive type layer on either side of the first conductive type connection region includes a second conductive type layer body and a second conductive type spacer for separating the first conductive type injection region, wherein the second conductive type spacer is integrally connected to the second conductive type layer body.

[0022] The second conductive type layer body includes a main support portion and an end support portion, wherein the main support portion and the end support portion are respectively located on both sides of the second conductive type spacer column;

[0023] For the first conductive type injection area corresponding to the second conductive type layer, one first conductive type injection area is directly connected to the main support portion, and the end of the other first conductive type injection area is connected to the end support portion of the corresponding second conductive type layer.

[0024] A cell structure for a planar SiC MOSFET device is prepared using the cell fabrication method described above.

[0025] For any planar cell, there are two second conductivity type layers disposed on the front side of the SiC wafer, and the two second conductivity type layers are located on the same plane within the SiC wafer; a first conductivity type injection region is disposed in each second conductivity type layer, and the upper parts of the two second conductivity type layers are connected through a first conductivity type injection region, and the lower parts of the two second conductivity type layers are separated by a first conductivity type connection region, and the first conductivity type connection region is located directly below the first conductivity type injection region connecting the upper part of the second conductivity type layer;

[0026] The first conductive type injection region on the upper part of the two second conductive type layers is separated from the first conductive type injection region in the connected second conductive type layer by the connected second conductive type layer.

[0027] For the first conductivity type injection region connecting two second conductivity type layers, the end of the first conductivity type injection region enters into the second conductivity type layer, or the end of the first conductivity type injection region contacts the end of the second conductivity type layer.

[0028] For N-type MOSFET devices, the first conductivity type refers to N-type and the second conductivity type refers to P-type. For P-type MOSFET devices, the first conductivity type and the second conductivity type refer to the opposite types as those for N-type MOSFET devices.

[0029] The advantages of this invention are as follows: After implanting impurity ions of the first conductivity type using the first shielding body, multiple first conductivity type implanted regions are obtained within the second conductivity type layer. Based on the characteristics of MOSFET devices, this achieves the formation of a conductive channel in a single implantation without involving alignment processes. During the second first conductivity type impurity ion implantation, since the channel length is already determined, the alignment accuracy required for preparing the second shielding body can be reduced, further simplifying the process. When preparing the conductive channel, the surface of the conductive channel is unaffected by the first conductivity type impurity ion implantation, resulting in no implantation damage. This avoids implantation-induced damage at the channel level, improves channel mobility, and enhances reliability. When preparing the first conductivity type implanted regions within the second conductivity type layer, it is easier to form a box-like distribution than with traditional processes, allowing for precise control of junction depth and improving process stability and reliability. Attached Figure Description

[0030] Figures 1 to 7 This is a cross-sectional view of the specific process steps of the present invention, wherein...

[0031] Figure 1 This is a cross-sectional view of the P-type layer prepared for the present invention.

[0032] Figure 2 A cross-sectional view of the first mask layer after it has been injected, prepared for the present invention.

[0033] Figure 3 A cross-sectional view of the first shielding body after it has been injected, prepared for the present invention.

[0034] Figure 4 This is a cross-sectional view of the N+ injection region prepared according to the present invention.

[0035] Figure 5 A cross-sectional view of the second mask layer after it has been injected, prepared for the present invention.

[0036] Figure 6 A cross-sectional view of the second shielding body after it has been injected, prepared for the present invention.

[0037] Figure 7 This is a cross-sectional view of the N-type connection region prepared according to the present invention.

[0038] Figure 8 This is a cross-sectional view of the present invention after removing the second blocking body.

[0039] Figure 9 This is a schematic diagram of the P-type layer after the conductive channel is prepared according to the present invention.

[0040] Explanation of reference numerals in the attached drawings: 1-N-type substrate, 2-N-type epitaxial layer, 3-P-type layer, 4-Impact first mask layer, 5-Impact window of first mask layer, 6-N-type implantation region, 7-Impact second mask layer, 8-Impact window of second shield, 9-N-type implantation region of the channel region, 10-N-type connection region, 11-Conductive channel region, 12-P-type spacer, 13-End support portion, and 14-Main support portion. Detailed Implementation

[0041] The present invention will be further described below with reference to specific accompanying drawings and embodiments.

[0042] To avoid damage caused by injection at the channel and to improve channel mobility while enhancing reliability, the conductive communication fabrication method of this invention, taking an N-type MOSFET device as an example, specifically includes the following steps for the fabrication of the conductive channel suitable for planar SiC MOSFET devices:

[0043] Step 1: Provide an N-type SiC wafer and fabricate a P-type layer 3 on the SiC wafer;

[0044] In a specific implementation, the SiC wafer includes an N-type substrate 1 and an N-type epitaxial layer 2 disposed on the N-type substrate 1, and a P-type layer 3 adapted and connected to the N-type epitaxial layer 2; the P-type layer 3 is prepared by epitaxial process or ion implantation process.

[0045] Specifically, the doping concentration of the N-type epitaxial layer 2 is generally lower than that of the N-type substrate 1. The N-type epitaxial layer 2 is located on the N-type substrate 1. The specific correspondence between the N-type epitaxial layer 2 and the N-type substrate 1 can be consistent with the existing ones, which are well known to those skilled in the art and will not be described in detail here.

[0046] The P-type layer 3 is adapted and connected to the N-type epitaxial layer 2, and the specific adaptation and connection depends on the formation method of the P-type layer 3. In specific implementation, the P-type layer 3 can be formed by epitaxial process or ion implantation process. When the P-type layer 3 is formed by epitaxial process, the P-type layer 3 is directly supported on the N-type epitaxial layer 2; when the P-type layer 3 is formed by ion implantation, P-type impurity ions need to be implanted into the N-type epitaxial layer 2. The specific process conditions and procedures for forming the P-type layer 3 by epitaxial process or ion implantation process can be selected and determined according to actual application, etc., and are well known to those skilled in the art, based on meeting actual design requirements, etc., and will not be elaborated here.

[0047] Regardless of whether epitaxial or ion implantation processes are used, the resulting P-type layer 3 appears in cross-section to be supported on the N-type epitaxial layer 2, such as... Figure 1 As shown.

[0048] Step 2: Prepare the required first injection shield on the P-type layer 3;

[0049] Specifically, the preparation of the first injection shield includes the following steps:

[0050] Step 2.1: Prepare and implant the first mask layer 4 on the second conductivity type layer;

[0051] In specific implementations, the material for implanting the first mask layer 4 includes photoresist, silicon oxide, polysilicon, or silicon nitride; of course, other materials that can serve as masks can also be used for implanting the first mask layer 4, and the specific choice can be made according to needs. Based on the material of the implanted first mask layer 4, the implanted first mask layer 4 can be prepared on the P-type layer 3 using techniques commonly used in this technical field, such as... Figure 2 As shown.

[0052] Step 2.2: Selectively mask and etch the first injection mask layer 4 to obtain a plurality of first mask layer injection windows 5 penetrating the first injection mask layer 4, so as to form the desired first injection shield with the first injection mask layer 4 using the injection windows 5.

[0053] Specifically, after the first injection mask layer 4 is prepared, the first injection mask layer 4 is selectively masked and etched to obtain a plurality of first mask layer injection windows 5 that penetrate the first injection mask layer 4 after etching, thereby using the first injection mask layer injection windows 5 and the first injection mask layer 4 to form the required first injection shield.

[0054] like Figure 3 As shown, the P-type layer 3 corresponding to the first mask layer injection window 5 can be exposed through the injection window 5, while the remaining area on the P-type layer 3 is blocked by the injection first mask layer 4.

[0055] Step 3: Perform N-type impurity ion implantation above the above-mentioned P-type layer 3. Utilize the first implantation shield to shield the P-type layer 3, thereby forming several required N+ implantation regions 6 within the P-type layer 3. The implantation depth of the N+ implantation regions 6 within the P-type layer 3 is less than the thickness of the P-type layer 3.

[0056] Specifically, the implantation of N-type impurity ions is carried out using techniques commonly used in this technical field. The type of N-type impurity ions and the implantation process conditions can be selected as needed, so as to prepare the required N+ implantation region 6 in the P-type layer 3. These are well known to those skilled in the art and will not be elaborated here.

[0057] like Figure 4As shown, the N+ implantation region 6 corresponds directly to the implantation window 5 of the first mask layer. That is, the area blocked by the first masking body is the N+ implantation region 6 in the non-n-type layer. Adjacent N+ implantation regions 6 within the P-type layer 3 are separated by the P-type layer 3, meaning each N+ implantation region 6 is independent. In specific implementation, the implantation depth of the N+ implantation region 6 within the P-type layer 3 is less than the thickness of the P-type layer 3, meaning the bottom of the N+ implantation region 6 is located within the P-type layer 3. At this time, the region between adjacent N+ implantation regions 6 forms the conductive channel region 11 of the MOSFET cell, meaning the formed conductive channel region 11 is not affected by N-type impurity ion implantation.

[0058] Step 4: Remove the first injection shielding body and prepare the required second injection shielding body on the P-type layer 3. The second injection shielding body includes a plurality of second injection shielding body injection windows 8. The second injection shielding body injection windows 8 correspond to the N+ injection regions 6 between the conductive channel regions 11 in the P-type layer 3, and expose the N+ injection regions 6 between the conductive channel regions 11 through the second injection shielding body injection windows 8.

[0059] Specifically, the first occluder can be removed using techniques commonly used in this field. The method and process of removing the first occluder are related to the type of the first occluder used, and are well known to those skilled in the art, so they will not be described in detail here.

[0060] After removing the first implanted mask, a second implanted mask can be prepared using commonly used techniques. The material of the second implanted mask includes photoresist, silicon oxide, polysilicon, or silicon nitride. The specific method and process for preparing the second implanted mask can be referred to the above description of the first implanted mask; that is, the second implanted mask can be formed by implanting a second mask layer 7, such as... Figure 5 As shown; the injection window 8 of the second injection mask layer 7 is obtained by etching, as shown. Figure 6 As shown; the second mask layer 7 and the second shielding injection window 8 are used to inject the required second shielding layer.

[0061] In this embodiment of the invention, the prepared second injection shield includes an injection window 8, which extends through the second injection shield. Of course, other areas outside the injection window 8 can be used to shield the P-type layer 3. Specifically, the injection window 8 corresponds to the N+ injection region 6 between the conductive channel region 11, and the N+ injection region 6 outside the conductive channel region 11 is shielded by the second shield. The N+ injection region 6 between the conductive channel regions 11 is the channel region N-type injection region 9, which corresponds to the injection window 8. Generally, a cell unit includes three adjacent N+ injection regions 6, with the middle N+ injection region 6 forming the channel region N-type injection region 9.

[0062] Step 5: Using the second implantation shield, N-type impurity ion implantation is performed on the P-type layer 3 to obtain an N-type connection region 10 directly below the N+ implantation region 6 between the conductive channel regions 11. The upper end of the N-type connection region 10 is in contact with the corresponding N+ implantation region 6, and the lower end of the N-type connection region 10 is in contact with the SiC wafer. The P-type layer 3 on both sides of the N-type connection region 10 is isolated by the N-type connection region 10 and the N+ implantation region 6 directly above the N-type connection region 10.

[0063] Specifically, after the second implantation shield is prepared, a second N-type impurity ion implantation is required. During N-type ion implantation, the second implantation shield ensures that N-type impurity ions are implanted only in the region directly corresponding to the implantation window 8 of the second implantation shield. By configuring the N-type impurity ion implantation process conditions, an N-type connection region 10 can be obtained directly below the N-type implantation region 9 in the channel region. The upper end of the N-type connection region 10 is in contact with the corresponding N+ implantation region 6, and the lower end of the N-type connection region 10 is in contact with the SiC wafer. This isolates the P-type layers 3 on both sides of the N-type connection region 10 through the N-type connection region 10 and the N+ implantation region 6 directly above it. Figure 7 As shown.

[0064] In specific implementation, by implanting a second N-type impurity ion, the P-type layer 3 directly below the N-type implantation region 9 in the channel region is transformed into an N-type N-type connection region 10 through ion implantation. This achieves the formation of a P-type layer 3 and an N+ implantation region 6 located in the P-type layer 3 on both sides of the conductive channel region, so as to meet the conductive channel form of forming a planar SiC MOSFET device.

[0065] Step 6: Remove the injected second occluder and perform the required front cell process to prepare the desired planar cell.

[0066] Specifically, the second occluder is removed using techniques commonly used in this field, such as... Figure 8 As shown, the conditions and process for removing the second occluder can be referred to the above description, and will not be repeated here.

[0067] Furthermore, it also includes a front cell process for forming the front cell structure and a back electrode process for forming the back electrode structure.

[0068] After removing the implanted second shield, in order to form a complete MOSFET device, front cell processing and back electrode processing are required. Generally, the front cell processing is performed first, followed by the back electrode processing. The specific details of the front cell processing and back electrode processing can be selected according to needs, based on the formation of the desired MOSFET device, and will not be elaborated here. Of course, the front cell processing implemented is the corresponding process step for fabricating planar SiC MOSFETs.

[0069] Furthermore, the size of the N-type connection area 10 is consistent with the lower part of the second shielding injection window 8. In specific implementations, the size of the second shielding injection window 8 can be adjusted to adjust the size of the N-type connection area 10. Figure 7 and Figure 8 As shown, the length of the N-type connection region 10 is less than the length of the N-type injection region 9 in the channel region, so that in the two P-type layers 3 separated by the N-type connection region 10, the N-type injection region 9 in the channel region extends into the P-type layer 3 in cross section.

[0070] like Figure 9 As shown, Figure 8 The schematic diagram of the P-type layer 3 after the implementation of the process is shown below. Specifically, for the P-type layer 3 on any side of the N-type connection region 10, the P-type layer 3 includes a P-type layer body and a P-type spacer 12 for separating the N+ injection region 6. The P-type spacer 12 is connected to the P-type layer body as a whole.

[0071] In this embodiment of the invention, a P-type spacer 12 protrudes from one end of the P-type layer body, and the P-type spacer 12 forms the conductive channel region 11 of the layer. Generally, one P-type layer 3 can correspond to two adjacent N+ injection regions 6, that is, to the N+ injection region 6 between the conductive channel regions 11 and the N+ injection region adjacent to one end of the N+ injection region 6, such as... Figure 8 In the middle, there is an N+ injection region 6 between the conductive channel region 11 and the corresponding N+ injection region 6 at the left or right end of the N+ injection region 6.

[0072] Furthermore, the P-type layer body includes a main support portion 14 and an end support portion 13, wherein the main support portion 14 and the end support portion 13 are respectively located on both sides of the P-type spacer 12;

[0073] For the N+ injection region 6 corresponding to the P-type layer 3, one N+ injection region 6 is directly connected to the main support portion 14, and the end of the other N+ injection region 6 is connected to the end support portion 13 of the corresponding P-type layer.

[0074] by Figure 8 Taking the N+ injection region 6 at the left end and the N+ injection region 6 in the middle position as examples, when correspondingly mating the P-type layer body, the N+ injection region 6 at the left end is supported and connected to the main support part 14, and the left end of the N+ injection region 6 in the middle position is correspondingly connected to the end support part 13. The specific connection and mating of the other P-type layer body with the two N+ injection regions 6 can be referred to the corresponding description, which is consistent with the description, and will not be repeated here.

[0075] The N+ injection region 6 is directly connected to the main support portion 14. Specifically, the main support portion 14 is aligned with the N+ injection region 6 in the length direction, and the two are adjacent to each other, or the N+ injection region 6 is supported on the main support portion 14 in cross-section. The N+ injection region 6 is also connected to the end support portion 13. Specifically, the end of the N+ injection region 6 corresponds to and contacts the end support portion 13.

[0076] In specific implementation, based on the P-type layers 3 on both sides of the two N-type connection regions 10, a structural shape corresponding to the N-type epitaxial layer 2, the N-type connection region 10, and the N+ injection region 6 directly above the N-type connection region 10 can be obtained.

[0077] Therefore, using the above process steps, the cell structure of a planar SiC MOSFET device can be fabricated, specifically, including a SiC wafer with N-type conductivity.

[0078] For any planar cell, there are two P-type layers 3 disposed on the front side of the SiC wafer, and the two P-type layers 3 are located on the same plane in the SiC wafer; an N+ implantation region 6 is disposed in each P-type layer 3, and the upper parts of the two P-type layers 3 are connected by an N+ implantation region 6, and the lower parts of the two P-type layers 3 are separated by an N-type connection region 10, which is located directly below the N+ implantation region 6 connecting the upper part of the P-type layer 3;

[0079] The N+ injection region 3 on the upper part of the two P-type layers 3 and the N+ injection region 6 in the connected P-type layer 3 are separated by the connected P-type layer 3.

[0080] In specific implementation, the N+ injection region 6 connecting the two P-type layers 3 is the aforementioned channel region N-type injection region 9. The end of the channel region N-type injection region 9 enters the P-type layer 3, or the end of the channel region N-type injection region 9 contacts the end of the P-type layer 6. For example... Figure 8The diagram shows the implementation where the end of the N-type injection region 9 in the channel region extends into the connected P-type layer 3. The case where the end of the N-type injection region 9 in the channel region contacts the end of the connected P-type layer 3 is not shown and will not be described further here.

[0081] In summary, this invention utilizes a first shielding body for N-type impurity ion implantation, resulting in multiple N+ implantation regions 6 within the P-type layer 3. Based on the characteristics of MOSFET devices, this achieves the formation of a conductive channel in a single implantation without involving alignment processes. During the second N-type impurity ion implantation, since the channel length is already determined, the alignment accuracy required for fabricating the second shielding body can be reduced, further simplifying the process. Figures 1 to 7 As can be seen from the above process, the surface of the conductive channel is not affected by the implantation of N-type impurity ions during the preparation of the conductive channel, and there is no implantation damage on the surface of the conductive channel. Thus, it can avoid the damage caused by implantation at the channel, and improve the channel mobility while enhancing reliability. By preparing the N+ implantation region 6 in the P-type layer 3, it is easier to form a box-shaped distribution than the traditional process, and the junction depth can be precisely controlled, thereby improving the stability and reliability of the process.

Claims

1. A method for fabricating a cell of a planar SiC MOSFET device, characterized in that, The cell preparation method includes the following steps: Step 1: Provide a SiC wafer with a first conductivity type, and fabricate a layer with a second conductivity type on the SiC wafer; Step 2: Fabricate the required first injection shield on the second conductivity type layer; Step 3: Implant first conductivity type impurity ions above the second conductivity type layer, and use the first shielding body to shield the second conductivity type layer to form several required first type implantation regions in the second conductivity type layer. The implantation depth of the first conductivity type implantation region in the second conductivity type layer is less than the thickness of the second conductivity type layer. Within the second conductivity type layer, adjacent first type implantation regions are separated by the second conductivity type layer so that each first type implantation region is independent of each other; the region between adjacent first type implantation regions forms the conductive channel region of the MOSFET cell, and the conductive channel region formed here is not affected by the implantation of first conductivity type impurity ions. Step 4: Remove the first injection shielding body and prepare the required second injection shielding body on the second conductivity type layer. The second injection shielding body includes a plurality of injection windows. The injection windows correspond to the first type injection areas between the conductive channel areas in the second conductivity type layer, and expose the first conductivity type injection areas between the conductive channel areas to be formed through the injection windows. Step 5: Using the implantation of the second shield, perform first conductivity type impurity ion implantation on the second conductivity type layer to obtain a first conductivity type connection region directly below the first conductivity type implantation region between the conductive channel regions. The upper end of the first conductivity type connection region is in contact with the corresponding first conductivity type implantation region, and the lower end of the first conductivity type connection region is in contact with the SiC wafer. The second conductivity type layers on both sides of the first conductivity type connection region are isolated through the first conductivity type connection region and the first conductivity type implantation region directly above the first conductivity type connection region. For the first conductivity type injection region connecting two second conductivity type layers, the end of the first conductivity type injection region enters into the second conductivity type layer, or the end of the first conductivity type injection region contacts the end of the second conductivity type layer; Step 6: Remove the injected second occluder and perform the required front cell process to prepare the desired planar cell.

2. The cell fabrication method for the planar SiC MOSFET device according to claim 1, characterized in that: The SiC wafer includes a first conductivity type substrate and a first conductivity type epitaxial layer disposed on the first conductivity type substrate. The second conductivity type layer is adapted and connected to the first conductivity type epitaxial layer; the second conductivity type layer is prepared by epitaxial process or ion implantation process.

3. The cell fabrication method for the planar SiC MOSFET device according to claim 1, characterized in that, Step 2, when preparing the first shielding body, includes the following steps: Step 2.1: Prepare an implanted first mask layer on the second conductivity type layer; Step 2.2: Selectively mask and etch the first injection mask layer to obtain a plurality of first mask layer injection windows that penetrate the first injection mask layer, so as to form the desired first injection shield with the first injection mask layer using the injection windows of the first injection mask layer.

4. The cell fabrication method for the planar SiC MOSFET device according to claim 3, characterized in that, The material injected into the first mask layer includes photoresist, silicon oxide, polysilicon, or silicon nitride.

5. The cell fabrication method for the planar SiC MOSFET device according to any one of claims 1 to 4, characterized in that, It also includes the back electrode process for forming the back electrode structure.

6. The cell fabrication method of the planar SiC MOSFET device according to any one of claims 1 to 4, characterized in that: The material injected into the second shield includes photoresist, silicon oxide, polysilicon, or silicon nitride.

7. The cell fabrication method of the planar SiC MOSFET device according to any one of claims 1 to 4, characterized in that: The second conductive type layer on either side of the first conductive type connection region includes a second conductive type layer body and a second conductive type spacer for separating the first conductive type injection region, wherein the second conductive type spacer is integrally connected to the second conductive type layer body.

8. The cell fabrication method for the planar SiC MOSFET device according to claim 7, characterized in that: The second conductive type layer body includes a main support portion and an end support portion, wherein the main support portion and the end support portion are respectively located on both sides of the second conductive type spacer column; For the first conductive type injection area corresponding to the second conductive type layer, one first conductive type injection area is directly connected to the main support portion, and the end of the other first conductive type injection area is connected to the end support portion of the corresponding second conductive type layer.

9. A cell structure for a planar SiC MOSFET device, characterized by: It is prepared using the cell preparation method described in any one of claims 1 to 4.

10. The cell structure of the planar SiC MOSFET device according to claim 9, characterized in that: For any planar cell, there are two second conductivity type layers disposed on the front side of the SiC wafer, and the two second conductivity type layers are located on the same plane within the SiC wafer; a first conductivity type injection region is disposed in each second conductivity type layer, and the upper parts of the two second conductivity type layers are connected through a first conductivity type injection region, and the lower parts of the two second conductivity type layers are separated by a first conductivity type connection region, and the first conductivity type connection region is located directly below the first conductivity type injection region connecting the upper part of the second conductivity type layer; The first conductive type injection region on the upper part of the two second conductive type layers is separated from the first conductive type injection region in the connected second conductive type layer by the connected second conductive type layer.

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