Carbon nanotube memory and manufacturing method

Abstract

An embodiment of the present application provides a carbon nanotube memory and a manufacturing method. The carbon nanotube memory includes: a substrate, an electrode structure, carbon nanotubes, and a gate electrode. The electrode structure includes a conductive electrode structure and a detection electrode structure. The conductive electrode structure is disposed on the substrate to provide a conductive circuit. The detection electrode structure is disposed on the substrate to detect non-local signals. The carbon nanotubes are disposed on the substrate to connect the conductive electrode structure and the detection electrode structure. The gate electrode is configured to provide a gate voltage to regulate the state of the non-local signal. The carbon nanotube memory and manufacturing method provided in the embodiment of the present application achieve information storage by regulating the state of the non-local signal through the gate voltage, and have the characteristics of low power consumption.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor memory, and in particular to a carbon nanotube memory and a manufacturing method thereof. Background Art

[0002] With the development of information technology, the rapid spread of the internet, and the availability of diverse content, the demand for high-capacity memories has increased. Nonvolatile memories have been developed that offer superior integration and electrical properties to ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), parallel random access machine (PRAM), or resistive random access memory (RRAM). Most nonvolatile memories developed to date use carbon nanotubes as storage nodes to improve integration.

[0003] Existing carbon nanotube memories typically use a layer of small transistors made of carbon nanotubes and storage cells that store electrons. The lower surface of the storage cell contacts the upper surface of the carbon nanotubes, and the lower surface of the gate electrode contacts the upper surface of the storage cell. The gate electrode controls the amount of charge flowing from the carbon nanotubes into the storage cell, achieving data storage by capturing a predetermined number of electrons.

[0004] However, the carbon nanotube memory in the prior art has the technical problem of high power consumption. Summary of the Invention

[0005] The embodiments of the present application provide a carbon nanotube memory and a manufacturing method thereof, which are used to solve the technical problem of high power consumption of carbon nanotube memories in the prior art.

[0006] The embodiment of the present application provides a carbon nanotube memory, comprising: a substrate, an electrode structure, carbon nanotubes, and a gate electrode;

[0007] Wherein, the electrode structure includes a conductive electrode structure and a detection electrode structure; the conductive electrode structure is arranged on the substrate to provide a conductive circuit;

[0008] The detection electrode structure is provided on the substrate and is used for detecting non-local signals;

[0009] The carbon nanotubes are arranged on the substrate and are used to connect the conductive electrode structure and the detection electrode structure;

[0010] The gate electrode is used to provide a gate voltage to regulate the state of the non-local signal.

[0011] According to a carbon nanotube memory provided by an embodiment of the present application, the conductive electrode structure includes a source electrode and a drain electrode;

[0012] A voltage or current is applied between the source electrode and the drain electrode to provide a conductive circuit.

[0013] According to a carbon nanotube memory provided by an embodiment of the present application, the conductive electrode structure and the detection electrode structure are respectively arranged at two ends of the carbon nanotube;

[0014] The carbon nanotubes in the channel are used for signal transmission;

[0015] The carbon nanotubes under the conductive electrode structure and the detection electrode structure are used to generate magnetic moments.

[0016] According to a carbon nanotube memory provided by an embodiment of the present application, the material of the electrode structure is molybdenum, iron, cobalt, nickel, titanium, gold, silver, copper, aluminum or polysilicon.

[0017] According to a carbon nanotube memory provided by an embodiment of the present application, the carbon nanotubes are single-walled carbon nanotubes, multi-walled carbon nanotubes, disordered carbon nanotube films, or ordered carbon nanotube films arranged in an array.

[0018] According to a carbon nanotube memory provided by an embodiment of the present application, the electrode structure and the carbon nanotube are arranged to cross each other, and the crossing angle is 0-180 degrees.

[0019] According to a carbon nanotube memory provided by an embodiment of the present application, the electrode structure and the carbon nanotubes are arranged to cross each other, and the crossing angle is 90 degrees.

[0020] According to a carbon nanotube memory provided by an embodiment of the present application, the gate electrode is a top gate, a back gate or an independent bottom gate.

[0021] The present application also provides a method for manufacturing any of the carbon nanotube memories described above, comprising:

[0022] depositing carbon nanotubes on a substrate;

[0023] preparing a pattern of the electrode structure based on the positions of the carbon nanotubes;

[0024] depositing an electrode material based on a pattern of the electrode structure;

[0025] The memory is constructed using a lift-off process.

[0026] According to an embodiment of the present application, a method for manufacturing any of the above-mentioned carbon nanotube memory devices is provided, wherein the step of depositing carbon nanotubes on a substrate comprises:

[0027] Directly depositing carbon nanotubes on a conductive substrate containing an insulating layer;

[0028] or,

[0029] depositing carbon nanotubes on a substrate comprising an insulating layer;

[0030] or,

[0031] forming a pattern of an independent bottom gate electrode on a substrate including an insulating layer;

[0032] depositing electrode materials based on the pattern of the independent bottom gate electrode;

[0033] forming an insulating layer above the independent bottom gate;

[0034] Carbon nanotubes are deposited on the insulating layer.

[0035] The embodiments of the present application provide a carbon nanotube memory and a manufacturing method, which completes the write and erase operations of the memory by regulating the state of the non-local signal through the gate voltage, completes the read operation of the memory by measuring the non-local signal of the memory through the detection electrode structure, and utilizes the electric field to complete the information storage of the memory, and has the characteristics of low power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0037] Figure 1 One of the cross-sectional views of the carbon nanotube memory provided in an embodiment of the present application;

[0038] Figure 2 The second cross-sectional view of the carbon nanotube memory provided in an embodiment of the present application;

[0039] Figure 3 One of the top views of the carbon nanotube memory provided in an embodiment of the present application;

[0040] Figure 4 A second top view of the carbon nanotube memory provided in an embodiment of the present application;

[0041] Figure 5 A third top view of the carbon nanotube memory provided in an embodiment of the present application;

[0042] Figure 6 The third cross-sectional view of the carbon nanotube memory provided in an embodiment of the present application;

[0043] Figure 7 A fourth cross-sectional view of the carbon nanotube memory provided in an embodiment of the present application;

[0044] Figure 8 A fifth cross-sectional view of the carbon nanotube memory provided in an embodiment of the present application;

[0045] Figure 9 A sixth cross-sectional view of the carbon nanotube memory provided in an embodiment of the present application;

[0046] Figure 10 A schematic diagram of a non-local signal measurement curve of a carbon nanotube memory provided in an embodiment of the present application;

[0047] Figure 11 A schematic diagram of electrical measurement results of a write operation of a carbon nanotube memory provided in an embodiment of the present application;

[0048] Figure 12 A schematic diagram showing the change in electrical measurement value of a read signal over time after a write operation of a carbon nanotube memory provided by an embodiment of the present application;

[0049] Figure 13 A schematic diagram of electrical measurement results of an erase operation of a carbon nanotube memory provided in an embodiment of the present application;

[0050] Figure 14 This is a schematic diagram showing the change in electrical measurement value of a read signal over time after an erase operation of a carbon nanotube memory provided in an embodiment of the present application. DETAILED DESCRIPTION

[0051] To make the purpose, technical solutions, and advantages of the embodiments of the present application more clear, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of them. Based on the embodiments in the embodiments of the present application, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the embodiments of the present application.

[0052] To solve the problems of the prior art, the present invention provides a carbon nanotube memory and a manufacturing method thereof. The following first introduces a carbon nanotube memory provided by the present invention.

[0053] Figure 1 This is one of the cross-sectional views of the carbon nanotube memory provided in the embodiment of the present application, as shown in FIG. Figure 1 As shown, an embodiment of the present application provides a carbon nanotube memory, comprising:

[0054] Substrate, electrode structure, carbon nanotubes and gate electrode;

[0055] Wherein, the electrode structure includes a conductive electrode structure and a detection electrode structure;

[0056] The conductive electrode structure is provided on the substrate to provide a conductive circuit;

[0057] The detection electrode structure is provided on the substrate and is used for detecting non-local signals;

[0058] The carbon nanotubes are arranged on the substrate and are used to connect the conductive electrode structure and the detection electrode structure;

[0059] The gate electrode is used to provide a gate voltage to regulate the state of the non-local signal.

[0060] like Figure 1 As shown, the substrate 1 includes a conductive substrate and a non-conductive substrate. Figure 1 The substrate used in the memory shown is a conductive substrate. The conductive layer in the conductive substrate serves as a back gate. Figure 1 The memory shown provides a gate voltage to regulate the storage state of the memory. An insulating layer 2 is covered on the substrate 1. The material of the insulating layer 2 is SiO2, SiN x Or insulating materials with good dielectric properties such as HfO2.

[0061] The electrode structure includes a conductive electrode structure 41 and a detection electrode structure 42 .

[0062] The conductive electrode structure 41 is disposed on the insulating layer 2 to provide a conductive circuit so that the memory can operate normally.

[0063] The detection electrode structure 42 is disposed on the insulating layer 2 and is used to detect non-local signals and complete the memory read operation.

[0064] The non-local signal is a non-local voltage or a non-local resistance, and the non-local signal is regulated with the gate voltage.

[0065] The carbon nanotubes 3 are disposed on the insulating layer 2 , and the carbon nanotubes 3 connect the conductive electrode structure 41 and the detection electrode structure 42 , for signal transmission and generation of magnetic moments.

[0066] For example, a carbon nanotube 3 is an allotrope of carbon that has a honeycomb shape formed by bonding carbon atoms together. In other words, a carbon nanotube has a shape in which a graphite sheet formed by bonding a plurality of carbon atoms is wound into a circle with a nanometer-scale diameter. Depending on the winding angle and structure of the graphite sheet, the carbon nanotube has either metallic properties or semiconductor properties. In the current industrial field, especially in the field of nanotechnology, people are actively studying this property of carbon nanotubes. Carbon nanotubes are divided into two different types according to their electrical properties. One type is metallic carbon nanotubes, whose electronic behavior is ohmic and is not affected by the gate voltage. The other type is semiconducting carbon nanotubes, whose electronic behavior is non-ohmic and is affected by the gate voltage.

[0067] For example, the gate electrode is made of metal or non-metal material with good conductivity, and the material of the gate electrode is molybdenum, iron, cobalt, nickel, titanium, gold, silver, copper, aluminum or polysilicon to reduce the loss of the memory.

[0068] For example, the number of detection electrode structures in the carbon nanotube memory is 1. Figure 1 As shown, Figure 1 The number of detection electrode structures in the memory shown is one.

[0069] For another example, the number of detection electrode structures in the carbon nanotube memory is two. Figure 2 This is the second cross-sectional view of the carbon nanotube memory provided in the embodiment of the present application, as shown in FIG. Figure 2 As shown, Figure 2 The substrate 1 used in the memory shown is a conductive substrate. The conductive layer in the conductive substrate serves as a back gate. Figure 2 The memory device shown provides a gate voltage. An insulating layer 2 is provided on a substrate 1, and carbon nanotubes 3 are disposed on the insulating layer 2 to connect the conductive electrode structure 41, the detection electrode structure 421, and the detection electrode structure 422. The detection electrode structures 421 and 422 are disposed at opposite ends of the carbon nanotubes 3, respectively. The conductive electrode structure 41 is positioned midway between the detection electrode structures 421 and 422. The carbon nanotubes 3 in the channel are used for signal transmission; the carbon nanotubes 3 beneath the conductive electrode structures 41, 421, and 422 are used to generate magnetic moments.

[0070] Specifically, the embodiment of the present application detects the non-local signals of the memory through two detection electrode structures, calculates the voltage difference or resistance difference between the non-local signals of the memory detected by the two detection electrode structures, and uses the voltage difference or resistance difference as reading information to improve the accuracy of memory information reading.

[0071] Specifically, the working principle of the carbon nanotube memory provided in the embodiments of the present application is as follows:

[0072] By changing the voltage scanning direction of the gate electrode, the non-local signal is regulated and the memory write or erase operation is completed according to the state of the non-local signal; the non-local signal is detected according to the detection electrode structure, and the detected non-local voltage or non-local resistance value is used as the read information to complete the memory read operation.

[0073] A carbon nanotube memory provided in an embodiment of the present application regulates the state of a non-local signal by means of a gate voltage, detects the non-local signal by means of a detection electrode structure, completes the read, write and erase operations of the memory, and stores information using only an electric field, thus having the characteristic of low power consumption.

[0074] Optionally, the conductive electrode structure includes a source electrode and a drain electrode;

[0075] A voltage or current is applied between the source electrode and the drain electrode to provide a conductive circuit.

[0076] For example, the source electrode and the drain electrode are made of metal or non-metal materials with good electrical conductivity, such as molybdenum, iron, cobalt, nickel, titanium, gold, silver, copper, aluminum or polysilicon.

[0077] A carbon nanotube memory provided in an embodiment of the present application provides a conductive circuit by applying a voltage or current between a source electrode and a drain electrode, thereby enabling the memory to operate normally.

[0078] Optionally, the conductive electrode structure and the detection electrode structure are respectively arranged at two ends of the carbon nanotube;

[0079] The carbon nanotubes in the channel are used for signal transmission;

[0080] The carbon nanotubes under the conductive electrode structure and the detection electrode structure are used to generate magnetic moments.

[0081] For example, the conductive electrode structure is disposed at a first end of the carbon nanotube, and the detection electrode structure is disposed at a second end of the carbon nanotube.

[0082] For another example, the conductive electrode structure is disposed at the second end of the carbon nanotube, and the detection electrode structure is disposed at the first end of the carbon nanotube.

[0083] Specifically, the channel is divided into the channel between the source and drain electrodes, and the channel between the conductive electrode structure and the detection electrode structure. The carbon nanotubes in the channel are used to transmit non-local signals.

[0084] Specifically, the carbon nanotubes under the conductive electrode structure and the detection electrode structure are used to generate magnetic moments, so that the carbon nanotubes produce semiconductor properties.

[0085] A carbon nanotube memory provided in an embodiment of the present application generates magnetic moments through carbon nanotubes under a conductive electrode structure and a detection electrode structure, causing the carbon nanotubes to produce semiconductor properties and generate non-local signals, which are then transmitted through the carbon nanotubes in the channel.

[0086] Optionally, the material of the electrode structure is molybdenum, iron, cobalt, nickel, titanium, gold, silver, copper, aluminum or polysilicon.

[0087] The electrode structure is made of metal or non-metal materials with good electrical conductivity to avoid the problem of high power consumption of the memory due to poor electrical conductivity of the material.

[0088] A carbon nanotube memory provided in an embodiment of the present application uses an electrode structure with good electrical conductivity to reduce the power consumption of the memory.

[0089] Optionally, the carbon nanotubes are single-walled carbon nanotubes, multi-walled carbon nanotubes, disordered carbon nanotube films, or ordered carbon nanotube films arranged in an array.

[0090] For example, carbon nanotubes are single-walled carbon nanotubes, which are formed by curling up a single layer of graphene and have semiconductor or metallic properties.

[0091] For another example, carbon nanotubes are multi-walled carbon nanotubes, which are formed by curling up multiple layers of graphene and have semiconductor properties or metallic properties.

[0092] For another example, carbon nanotubes are disordered carbon nanotube films, which are network films formed by disorderly arrangement of single-walled carbon nanotubes or multi-walled carbon nanotubes, and have semiconductor properties or metallic properties.

[0093] For another example, the carbon nanotubes are an ordered carbon nanotube film arranged in an array, a network film formed by arraying single-walled carbon nanotubes or multi-walled carbon nanotubes, and have semiconductor properties or metallic properties.

[0094] Specifically, carbon nanotubes use a universal type of carbon nanotubes, which improves the universality of the memory.

[0095] The carbon nanotube memory provided in the embodiment of the present application adopts universal carbon nanotubes, thereby enhancing the universality of the carbon nanotube memory and having the conditions and basis for promotion.

[0096] Optionally, the electrode structure and the carbon nanotubes are arranged to cross each other, and the crossing angle is 0-180 degrees.

[0097] For example, the crossing angle between the electrode structure and the carbon nanotubes is 60 degrees. Figure 3 This is one of the top views of the carbon nanotube memory provided in the embodiment of the present application, as shown in FIG. Figure 3As shown, the conductive electrode structure 41 and the detection electrode structure 42 in the memory of the embodiment of the present application are respectively arranged to cross the carbon nanotubes 3, and the crossing angle is 60 degrees.

[0098] For another example, the crossing angle between the electrode structure and the carbon nanotubes is 120 degrees. Figure 4 The second top view of the carbon nanotube memory provided in the embodiment of the present application is as follows Figure 4 As shown, the conductive electrode structure 41 and the detection electrode structure 42 in the memory of the embodiment of the present application are respectively arranged to cross the carbon nanotubes 3, and the crossing angle is 120 degrees.

[0099] Specifically, in the above specific embodiments, the electrode structure and the carbon nanotubes are cross-arranged, and the crossing angles are 60 degrees and 120 degrees, but the embodiments of the present application are not limited thereto. The electrode structure and the carbon nanotubes are cross-arranged, and the crossing angles are 0-180 degrees.

[0100] In the embodiment of the present application, the electrode structure and the carbon nanotubes are arranged in a cross-arrangement with a cross-angle of 0-180 degrees, thereby improving the integration of the memory.

[0101] Optionally, the electrode structure and the carbon nanotubes are arranged to cross each other, and the crossing angle is 90 degrees.

[0102] For example, the intersection angle between the electrode structure and the carbon nanotubes is 90 degrees. Figure 5 The third top view of the carbon nanotube memory provided in the embodiment of the present application is shown in FIG. Figure 5 As shown, the conductive electrode structure 41 and the detection electrode structure 42 in the memory of the embodiment of the present application are respectively arranged to cross the carbon nanotubes 3, and the crossing angle is 90 degrees.

[0103] In the embodiment of the present application, the electrode structure and the carbon nanotubes are cross-arranged at a crossing angle of 90 degrees, thereby reducing the loss of the carbon nanotubes in signal transmission.

[0104] Optionally, the gate electrode is a top gate, a back gate or an independent bottom gate.

[0105] For example, Figure 1 and Figure 2 The gate electrode of the carbon nanotube memory shown is a back gate. Figure 1 and Figure 2 The carbon nanotube memory shown provides a gate voltage.

[0106] For another example, when the gate electrode in the memory is a top gate, Figure 6 The third cross-sectional view of the carbon nanotube memory provided in the embodiment of the present application is shown as follows: Figure 6 As shown, the substrate 1 is a non-conductive substrate, and the first insulating layer 2 covers the substrate 1 . Figure 6The number of detection electrode structures in the memory shown is one. The conductive electrode structure 41, the detection electrode structure 42, and the carbon nanotube 3 are all disposed on the first insulating layer 2. The conductive electrode structure 41 and the detection electrode structure 42 are respectively disposed at both ends of the carbon nanotube 3. The carbon nanotube 3 in the channel is used for signal transmission; the carbon nanotube 3 below the conductive electrode structure 41 and the detection electrode structure 42 is used to generate a magnetic moment.

[0107] The second insulating layer 5 is located above the electrode structure and the carbon nanotubes 3. The second insulating layer 5 extends along the outer surface of the electrode structure and the carbon nanotubes 3 to the outer edge of the first insulating layer 2. The top gate 6 extends along the upper surface of the second insulating layer 5 to the outer edge of the second insulating layer 5.

[0108] Figure 6 The top gate 6 in the memory shown provides a gate voltage for the memory.

[0109] For another example, when the gate electrode in the memory is a top gate, Figure 7 This is a fourth cross-sectional view of the carbon nanotube memory provided in an embodiment of the present application, as shown in FIG. Figure 7 As shown, the substrate 1 is a non-conductive substrate, and the first insulating layer 2 covers the substrate 1 . Figure 7 The number of detection electrode structures in the memory shown is two. Conductive electrode structure 41, detection electrode structure 421, detection electrode structure 422, and carbon nanotubes 3 are all disposed on first insulating layer 2. Detection electrode structure 421 and detection electrode structure 422 are disposed at either end of the carbon nanotube 3, respectively. Conductive electrode structure 41 is disposed midway between detection electrode structure 421 and detection electrode structure 422. The carbon nanotubes 3 in the channel are used for signal transmission. The carbon nanotubes 3 beneath conductive electrode structure 41, detection electrode structure 421, and detection electrode structure 422 are used to generate magnetic moments.

[0110] The second insulating layer 5 is located above the electrode structure and the carbon nanotubes 3. The second insulating layer 5 extends along the outer surface of the electrode structure and the carbon nanotubes 3 to the outer edge of the first insulating layer 2. The top gate 6 extends along the upper surface of the second insulating layer 5 to the outer edge of the second insulating layer 5.

[0111] Figure 7 The top gate 6 in the memory shown provides a gate voltage for the memory.

[0112] For another example, when the gate electrode in the memory is an independent bottom gate, Figure 8 The fifth cross-sectional view of the carbon nanotube memory provided in the embodiment of the present application is as follows: Figure 8 As shown, the substrate 1 is a non-conductive substrate, and the first insulating layer 2 covers the substrate 1 . Figure 8The number of detection electrode structures in the memory shown is one. An independent bottom gate is located above the first insulating layer 2. A third insulating layer 8 is located above the independent bottom gate and is parallel to the first insulating layer 2, extending parallel to the outer edge of the first insulating layer 2. The conductive electrode structure 41, the detection electrode structure 42, and the carbon nanotubes 3 are all disposed on the third insulating layer 8. The conductive electrode structure 41 and the detection electrode structure 42 are respectively disposed at both ends of the carbon nanotubes 3. The carbon nanotubes 3 in the channel are used for signal transmission; the carbon nanotubes 3 below the conductive electrode structure and the detection electrode structure are used to generate magnetic moments.

[0113] Among them, the independent bottom gate includes a first independent bottom gate 71, a second independent bottom gate 72 and a third independent bottom gate 73. The first independent bottom gate 71 is located below the conductive electrode structure 41, the second independent bottom gate 72 is located below the carbon nanotubes between the conductive electrode structure 41 and the detection electrode structure 42, and the third independent bottom gate 73 is located below the detection electrode structure 42.

[0114] Figure 8 The independent bottom gate in the memory shown provides the gate voltage for the memory.

[0115] For another example, when the gate electrode in the memory is an independent bottom gate, Figure 9 The sixth cross-sectional view of the carbon nanotube memory provided in the embodiment of the present application is shown in FIG. Figure 9 As shown, the substrate 1 is a non-conductive substrate, and the first insulating layer 2 covers the substrate 1 . Figure 9 The number of detection electrode structures in the memory shown is two. An independent bottom gate is located above the first insulating layer 2. A third insulating layer 8 is located above the independent bottom gate and is parallel to the first insulating layer 2, extending parallel to the outer edge of the first insulating layer 2. The conductive electrode structure 41, the detection electrode structure 421, the detection electrode structure 422, and the carbon nanotubes 3 are all disposed on the third insulating layer 8. The detection electrode structure 421 and the detection electrode structure 422 are respectively disposed at both ends of the carbon nanotubes 3, and the conductive electrode structure 41 is located midway between the detection electrode structures 421 and 422. The carbon nanotubes 3 in the channel are used for signal transmission; the carbon nanotubes 3 below the conductive electrode structure 41, the detection electrode structure 421, and the detection electrode structure 422 are used to generate magnetic moments.

[0116] Among them, the independent bottom gate includes a first independent bottom gate 71, a second independent bottom gate 72, a third independent bottom gate 73, a fourth independent bottom gate 74 and a fifth independent bottom gate 75. The first independent bottom gate 71 is located below the detection electrode structure 421, the second independent bottom gate 72 is located below the carbon nanotubes between the conductive electrode structure 41 and the detection electrode structure 421, the third independent bottom gate 73 is located below the conductive electrode structure 41, the fourth independent bottom gate 74 is located below the carbon nanotubes between the conductive electrode structure 41 and the detection electrode structure 422, and the fifth independent bottom gate 75 is located below the detection electrode structure 422.

[0117] Figure 9 The independent bottom gate in the memory shown provides the gate voltage for the memory.

[0118] The gate electrode in the embodiment of the present application is a back gate, a top gate or an independent bottom gate, which enhances the universality of the memory and has the conditions and basis for promotion.

[0119] The above embodiments are described in detail below with a specific example.

[0120] For example, when the number of detection electrode structures in the memory is one, the gate electrode is a back gate, a top gate, or an independent bottom gate. The full electric field controlled read-write-erase storage method adopted in the embodiment of the present application includes the following steps:

[0121] S1, apply a voltage of 100 mV between the source and drain electrodes, sweep the gate voltage from -30 V to 30 V, and then from 30 V to -30 V, and obtain the electrical curve of the non-local signal of the memory. non-local = 400 ohms is defined as binary 1, R non-local = 230 ohms is defined as binary 0, where R non-local is a non-local resistance. The non-local signal measurement curve diagram of the carbon nanotube memory provided in the embodiment of the present application is shown as follows: Figure 10 As shown, Figure 10 The solid line curve in FIG represents the electrical curve of the non-local signal of the memory obtained by sweeping the gate voltage from -30V to 30V. Figure 10 The dotted curve in FIG represents the electrical curve of the non-local signal of the memory obtained by sweeping the gate voltage from 30 V to -30 V;

[0122] S2, apply a voltage of 100 mV between the source and drain electrodes, sweep the gate voltage from -30 V to -18 V, and complete the memory write operation by sweeping the gate voltage from negative to positive or using a pulsed gate voltage of a certain value. non-local When the resistance is adjusted to 400 ohms, the storage information of the memory is in state 1. The electrical measurement result of the write operation of the carbon nanotube memory provided in the embodiment of the present application is shown in FIG. Figure 11 As shown;

[0123] S3, apply a voltage of 100 mV between the source and drain electrodes, do not apply a gate voltage to the memory, and measure the voltage V of the detection electrode structure non-local , through the formula R non-local =V non-local / I ds , where I ds is the current between the source and drain, and the non-local resistance value R non-local , that is, the reading operation of the storage signal of the memory is completed, R non-local = 400 ohms, that is, the 1 state of the stored information does not change over time. The electrical measurement value of the read signal after the write operation of the carbon nanotube memory provided by the embodiment of the present application changes over time as shown in the following figure. Figure 12 As shown;

[0124] S4, apply a voltage of 100 mV between the source and drain electrodes, sweep the gate voltage from 30 V to -18 V, and complete the memory erasing operation by sweeping the gate voltage from positive to negative or using a pulsed gate voltage of a certain value. non-local When the resistance is adjusted to 230 ohms, the storage information of the memory is in the 0 state. The electrical measurement result of the erase operation of the carbon nanotube memory provided in the embodiment of the present application is shown in FIG. Figure 13 As shown;

[0125] S5, apply a voltage of 100 mV between the source and drain electrodes, do not apply a gate voltage to the memory, and measure the voltage V of the detection electrode structure non-local , through the formula R non-local =V non-local / I ds , where I ds is the current between the source and drain, and the non-local resistance value R non-local , complete the reading operation of the storage signal of the memory, R non-local = 230 ohms, that is, the 0 state of the stored information, which does not change with time. The electrical measurement value of the read signal after the erase operation of the carbon nanotube memory provided in the embodiment of the present application changes with time as shown in the following figure. Figure 14 shown.

[0126] For another example, when the number of detection electrode structures in the memory is 2, the gate voltage includes a back gate, a top gate, or an independent bottom gate. The full electric field controlled read-write-erase storage method adopted in the embodiment of the present application includes the following steps:

[0127] S1, electrical measurement of the memory, i.e., the non-local signal adjusts the gate voltage to set the 0 and 1 states of the stored information;

[0128] S2, according to the non-local signal of the memory with the gate voltage regulation characteristics, a constant voltage or current is applied between the drain electrode, and the gate voltage is scanned from negative to positive or a pulsed gate voltage of a certain value is used to perform the writing operation;

[0129] S3, the gate voltage is 0 volts, a constant voltage or current is applied between the source and drain electrodes, and the non-local resistance (V1-V2) / I between the detection electrode structures 1 and 2 is measured. ds 、V1 / I ds 、V2 / I ds , where I ds The current between the source and drain electrodes, or directly reading the voltage values ​​V1 and V2 of the detection electrode structure 1 or the detection electrode structure 2, is read after the writing operation is completed;

[0130] S4, according to the non-local signal of the memory and the gate voltage regulation characteristics, a constant voltage or current is applied between the source and drain electrodes, and the gate voltage is scanned from a positive value to a negative value or a pulsed gate voltage of a certain value is used to perform an erase operation;

[0131] S5: The gate voltage is 0 volts, a constant voltage or current is applied between the source and drain electrodes, and the non-local resistance (V1-V2) / I is measured between the detection electrodes 1 and 2. ds 、V1 / I ds 、V2 / I ds , where I ds The current between the source and drain electrodes, or the voltage values ​​V1 and V2 of the detection electrode structure 1 or the detection electrode structure 2 are directly read to complete the reading operation after the memory erase operation.

[0132] Specifically, the carbon nanotube memory provided in the embodiments of the present application modulates the nonlocal signal by changing the gate voltage scanning direction to complete the memory write or erase operation. Different nonlocal voltage values ​​or nonlocal resistance values ​​define the stored information 0 and 1. The nonlocal electrical signal of the memory is measured by the detection electrode structure to complete the memory read operation. This memory utilizes electric fields to store information in the memory, and has the characteristics of low power consumption.

[0133] On the other hand, an embodiment of the present application further provides a method for manufacturing any of the above-mentioned carbon nanotube memories, the manufacturing method comprising:

[0134] S1, depositing carbon nanotubes on a substrate;

[0135] S2, preparing the pattern of the electrode structure based on the position of the carbon nanotubes;

[0136] S3, depositing electrode material based on the pattern of the electrode structure;

[0137] S4, using the stripping process to construct the memory.

[0138] For example, in S2, the pattern of the electrode structure is prepared by electron beam exposure, ultraviolet lithography, or ion beam exposure.

[0139] For example, in S3, the electrode material is deposited by magnetron sputtering, thermal evaporation, electron beam evaporation, or atomic layer deposition.

[0140] The embodiments of the present application provide a method for manufacturing any of the above-mentioned carbon nanotube memories. The manufacturing process is compatible with the existing microelectronic silicon process and has the conditions and basis for achieving integration and promotion.

[0141] Optionally, depositing carbon nanotubes on a substrate includes:

[0142] Directly depositing carbon nanotubes on a conductive substrate containing an insulating layer;

[0143] or,

[0144] depositing carbon nanotubes on a substrate comprising an insulating layer;

[0145] or,

[0146] forming a pattern of an independent bottom gate electrode on a substrate including an insulating layer;

[0147] depositing electrode materials based on the pattern of the independent bottom gate electrode;

[0148] forming an insulating layer above the independent bottom gate;

[0149] Carbon nanotubes are deposited on the insulating layer.

[0150] For example, in S1 , depositing carbon nanotubes on a substrate includes: directly depositing carbon nanotubes on a conductive substrate including a first insulating layer, with the conductive layer of the conductive substrate serving as a back gate electrode.

[0151] For another example, in S1 , depositing carbon nanotubes on a substrate includes: depositing carbon nanotubes on a non-conductive substrate including a first insulating layer.

[0152] After S4, a second insulating layer is prepared on the upper layer of the memory by a thin film deposition method; an electrode pattern of a top gate is prepared on the second insulating layer; and a metal film with good conductivity is deposited to serve as a top gate electrode.

[0153] The materials of the first insulating layer and the second insulating layer are SiO2, SiN x Or insulating materials with good dielectric properties such as HfO2.

[0154] The thin film deposition method is PECVD, electron beam evaporation, thermal evaporation, magnetron sputtering or atomic layer deposition.

[0155] For another example, in S1, carbon nanotubes are deposited on a substrate, including: preparing a pattern of an independent bottom gate electrode on a substrate containing a first insulating layer; depositing an electrode material based on the pattern of the independent bottom gate electrode; preparing a third insulating layer above the independent bottom gate; and depositing carbon nanotubes on the third insulating layer.

[0156] The pattern of the independent bottom gate electrode is prepared by electron beam exposure, ultraviolet lithography or ion beam exposure.

[0157] The electrode material is deposited by magnetron sputtering, thermal evaporation, electron beam evaporation or atomic layer deposition.

[0158] The material of the third insulating layer is SiO2, SiN x Or insulating materials with good dielectric properties such as HfO2.

[0159] The third insulating layer is prepared by PECVD, electron beam evaporation, thermal evaporation, magnetron sputtering or atomic layer deposition.

[0160] The embodiment of the present application provides a method for manufacturing any of the above-mentioned carbon nanotube memories. The manufacturing method is compatible with the existing microelectronic silicon process and can be used to manufacture the back gate, top gate or independent bottom gate of the memory, thus having the conditions and basis for promotion.

[0161] It should also be noted that the exemplary embodiments mentioned in the embodiments of this application describe some methods or devices. However, the embodiments of this application are not limited to the order of the above steps. In other words, the steps can be performed in the order mentioned in the embodiments, or in a different order, or several steps can be performed simultaneously.

[0162] The above is only a specific implementation of the embodiment of the present application, which can be clearly understood by those skilled in the art. It should be understood that the scope of protection of the embodiment of the present application is not limited to this. Any person skilled in the art can easily think of various equivalent modifications or replacements within the technical scope disclosed in the embodiment of the present application, and these modifications or replacements should be included in the scope of protection of the embodiment of the present application.

Claims

1. A carbon nanotube memory, characterized in that: include: Substrate, electrode structure, carbon nanotubes and gate electrode; Wherein, the electrode structure includes a conductive electrode structure and a detection electrode structure; the conductive electrode structure is arranged on the substrate to provide a conductive circuit; The detection electrode structure is provided on the substrate and is used for detecting non-local signals; The carbon nanotubes are arranged on the substrate and are used to connect the conductive electrode structure and the detection electrode structure; The gate electrode is used to provide a gate voltage to regulate the state of the non-local signal; The state of the non-local signal is regulated by the gate voltage to complete the write and erase operations of the memory, and the non-local signal of the memory is measured by the detection electrode structure to complete the read operation of the memory.

2. The carbon nanotube memory according to claim 1, characterized in that The conductive electrode structure includes a source electrode and a drain electrode; A voltage or current is applied between the source electrode and the drain electrode to provide a conductive circuit.

3. The carbon nanotube memory according to claim 1, characterized in that The conductive electrode structure and the detection electrode structure are respectively arranged at two ends of the carbon nanotube; The carbon nanotubes in the channel are used for signal transmission; The carbon nanotubes under the conductive electrode structure and the detection electrode structure are used to generate magnetic moments.

4. The carbon nanotube memory according to claim 1, wherein: The material of the electrode structure is molybdenum, iron, cobalt, nickel, titanium, gold, silver, copper, aluminum or polysilicon.

5. The carbon nanotube memory according to claim 1, characterized in that The carbon nanotubes are single-walled carbon nanotubes, multi-walled carbon nanotubes, disordered carbon nanotube films or ordered carbon nanotube films arranged in an array.

6. The carbon nanotube memory according to claim 1, characterized in that The electrode structure and the carbon nanotubes are arranged to cross each other, and the crossing angle is greater than 0 degree and less than 180 degrees.

7. The carbon nanotube memory according to claim 1, characterized in that The electrode structure and the carbon nanotubes are arranged to cross each other, and the crossing angle is 90 degrees.

8. The carbon nanotube memory according to claim 1, characterized in that The gate electrode is a top gate, a back gate or an independent bottom gate.

9. A method for manufacturing the carbon nanotube memory according to any one of claims 1 to 8, characterized in that: include: depositing carbon nanotubes on a substrate; preparing a pattern of the electrode structure based on the positions of the carbon nanotubes; depositing an electrode material based on a pattern of the electrode structure; The memory is constructed using a lift-off process.

10. The method according to claim 9, characterized in that The step of depositing carbon nanotubes on a substrate comprises: depositing carbon nanotubes on a substrate comprising an insulating layer; or, forming a pattern of an independent bottom gate electrode on a substrate including an insulating layer; depositing electrode materials based on the pattern of the independent bottom gate electrode; forming an insulating layer above the independent bottom gate; Carbon nanotubes are deposited on the insulating layer.

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