VHF band limiter and limiter method thereof

Abstract

The application provides a VHF band limiter and a limiter method thereof, a first-stage limiter circuit, a second-stage limiter circuit and a third-stage limiter circuit are sequentially and electrically connected through a delay line, the time delay phase of the delay line between the first-stage limiter circuit and the second-stage limiter circuit is 90°, the impedance matching between the power signal input end and the load end of the first-stage limiter circuit can be ensured, most of the power of the high-power input signal can flow into the load end, and thus the limiter function is realized; the length of the delay line is limited, the influence of the delay line on the high-power time standing wave and power leakage can be reduced; the thickness and the distance from the cavity of the delay line are limited to ensure the power capacity of the limiter and reduce the insertion loss; the length, the thickness and the distance from the cavity of the delay line after the limitation can make the power signal delayed through the delay line to realize the time delay and the frequency band matching of the very high frequency band.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of amplitude limiter, in particular to a VHF band amplitude limiter and an amplitude limiting method thereof. BACKGROUND

[0002] The amplitude limiter is used to protect the receiver, and can protect the receiver from being burned when a large signal exists, and the receiving path can quickly recover to normal when a strong signal disappears, while the small signal insertion loss is low, and the receiver sensitivity is ensured. However, the general amplitude limiter is difficult to withstand more than 2000 watts in the case of limited volume, and the time delay and frequency band of the very high frequency band are not matched, and the small signal difference loss and other indicators are also difficult to consider. Therefore, in order to solve the above problems, the present application provides a VHF band amplitude limiter and an amplitude limiting method thereof, which can withstand more than 2000 watts of pulse power, and has low insertion loss, and the time delay and frequency band of the very high frequency band are matched. SUMMARY

[0003] Therefore, the present application provides a VHF band amplitude limiter and an amplitude limiting method thereof, which can withstand more than 2000 watts of pulse power, and has low insertion loss, and the time delay and frequency band of the very high frequency band are matched.

[0004] The technical scheme of the present application is as follows: the present application provides a VHF band amplitude limiter, which comprises a first-stage amplitude limiting circuit, a second-stage amplitude limiting circuit and a third-stage amplitude limiting circuit, and the first-stage amplitude limiting circuit, the second-stage amplitude limiting circuit and the third-stage amplitude limiting circuit are sequentially and electrically connected through a delay line.

[0005] The delay line between the first-stage amplitude limiting circuit and the second-stage amplitude limiting circuit has a time delay phase of 90°.

[0006] On the basis of the above technical scheme, preferably, the total length of the delay line satisfies the following formula: λ is the wavelength of the VHF band.

[0007] On the basis of the above technical scheme, preferably, the cross-sectional side length of the delay line and the distance from the cavity satisfy the formula:

[0008]

[0009]

[0010] Wherein, Z o is 50 ohm impedance; ε r =1; b is the width and height of the delay line cavity; a is the cross-sectional side length of the delay line; P is the power capacity; E b is the breakdown electric field strength, which is 30kV / cm.

[0011] On the basis of the above technical scheme, preferably, the first-stage limiting circuit comprises a plurality of PIN switch tube pairs with the same structure, an inductor, a power signal input end, a load end and a power signal output end;

[0012] The PIN switch tube pair comprises two PIN switch tubes connected in anti-phase in parallel;

[0013] The plurality of PIN switch tube pairs are divided into two groups, and the PIN switch tube pairs in each group are connected in parallel with each other; the input end of the first group is connected in series between the power signal input end and the power signal output end, the output end of the first group is electrically connected with the input end of the second group, the output end of the second group is electrically connected with the load end, and the load end is electrically connected with an external power load;

[0014] The inductor is connected in parallel between the load end and the power signal output end.

[0015] On the basis of the above technical scheme, preferably, the total number of the PIN switch tube pairs in the first-stage limiting circuit satisfies the following formula:

[0016]

[0017] Wherein, P is the power capacity; R is the load impedance, which is a constant of 50Ω; i is the current effective value flowing through a single PIN switch tube, i≤1; N is the total number of the PIN switch tube pairs, and N is an integer multiple of 2.

[0018] On the basis of the above technical scheme, preferably, the second-stage limiting circuit comprises a plurality of first PIN limiting tube pairs with the same structure;

[0019] The first PIN limiting tube pair comprises two PIN limiting tubes connected in anti-phase in parallel;

[0020] The plurality of first PIN limiting tube pairs are connected in parallel with each other; the input end of the first PIN limiting tube pair is connected in series between the power signal output end of the first-stage limiting circuit and the power signal input end of the third-stage limiting circuit, and the output end of the first PIN limiting tube pair is grounded.

[0021] On the basis of the above technical scheme, preferably, the third-stage limiting circuit comprises a plurality of second PIN limiting tube pairs with the same structure;

[0022] The second PIN limiting tube pair comprises two PIN limiting tubes connected in anti-phase in parallel;

[0023] The plurality of second PIN limiting tube pairs are connected in parallel with each other; the input end of the second PIN limiting tube pair is electrically connected with the power signal output end of the second-stage limiting circuit, and the output end of the first PIN limiting tube pair is grounded.

[0024] On the basis of the above technical scheme, preferably, the matching circuit is further included.

[0025] The input end of the matching circuit is electrically connected with the power signal output end of the third-stage limiting circuit, and the output end of the matching circuit is electrically connected with an external subsequent circuit.

[0026] On the basis of the above technical scheme, preferably, the matching circuit includes inductors L2-L4 and capacitors C1-C2.

[0027] One end of the inductor L3 is electrically connected with the power signal output end of the third-stage limiting circuit, one end of the inductor L2 and one end of the capacitor C1 respectively, and the other end of the inductor L2 and the other end of the capacitor C1 are grounded; the other end of the inductor L3 is electrically connected with one end of the inductor L4, one end of the capacitor C2 and an external subsequent circuit, and the other end of the inductor L4 and the other end of the capacitor C2 are grounded.

[0028] On the other hand, the present application provides a limiting method of the VHF frequency band limiter, which comprises the following steps:

[0029] S1, a VHF frequency band limiter is built, and an external input signal is input from a power signal input end to a first-stage limiting circuit;

[0030] S2, if the power of the external input signal is lower than a preset value, the PIN switch tube in the first-stage limiting circuit cannot be turned on, the external input signal is delayed for a certain time through a delay line, the time delay of the very high frequency band is matched with the frequency band, and then the external input signal directly enters a matching circuit, is input to a receiver after the insertion loss is reduced through the matching circuit, and the like.

[0031] On the contrary, the PIN switch tube in the first-stage limiting circuit is automatically turned on, the power signal input end of the first-stage limiting circuit is connected with a load end, most of the power flows to an external power load through the PIN switch tube and is absorbed by the power load; at the same time, the PIN limiting tube in the second-stage limiting circuit is turned on, a ground short circuit is formed, a small amount of leakage power is clamped through the third-stage limiting circuit, and the leakage power is further limited until the power leaked to the receiver is reduced to within a safe range.

[0032] The VHF frequency band limiter and the limiting method thereof have the following beneficial effects compared with the prior art:

[0033] (1) The first-stage limiting circuit, the second-stage limiting circuit and the third-stage limiting circuit are sequentially and electrically connected through the delay line, and the time delay phase of the delay line between the first-stage limiting circuit and the second-stage limiting circuit is 90°, which can ensure that the impedance between the power signal input end and the load end of the first-stage limiting circuit is matched, so that most of the power of the high-power input signal flows into the load end, thereby realizing the limiting function.

[0034] (2) Limiting the length of the delay line can reduce the influence of the delay line on the high-power standing wave and power leakage; limiting the thickness of the delay line and the distance between the delay line and the cavity can ensure the power capacity of the limiter and reduce the insertion loss;

[0035] (3) The delay line limited in length, thickness and distance from the cavity can make the power signal delayed through the delay line to achieve time delay and frequency band matching in the very high frequency band;

[0036] (4) By limiting the number of PIN switch tube pairs in parallel in the first-stage limiting circuit, the limiter can withstand a power of more than 2000 watts while the capacitance from the input end to the load end is small, reducing the isolation and insertion loss of the small signal to the load end;

[0037] (5) The PIN switch tube pairs in the first-stage limiting circuit adopt a parallel-serial-parallel structure, which on the one hand improves the power capacity of the limiter without affecting the working frequency and bandwidth of the limiter circuit, and on the other hand, the introduction of the series structure reduces the capacitance to ground, improving the working frequency and bandwidth of the limiter circuit;

[0038] (6) By setting the matching circuit, the power capacity of more than 2000 watts can be met while reducing the insertion loss. BRIEF DESCRIPTION OF DRAWINGS

[0039] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description only constitute some embodiments of the present application, and for those skilled in the art, other drawings can be obtained without creative labor on the basis of these drawings.

[0040] Figure 1 The structure diagram of the VHF band limiter of the present application;

[0041] Figure 2 The circuit diagram of the VHF band limiter of the present application. DETAILED DESCRIPTION

[0042] The technical solutions in the embodiments of the present application will be described in detail below. Obviously, the described embodiments only constitute some embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0043] Embodiment 1

[0044] For VHF frequency band, the time delay of the current limiter in VHF frequency band does not match the frequency band. Therefore, in order to solve the above problems, the VHF frequency band limiter provided by the embodiment includes a first-stage limiting circuit, a second-stage limiting circuit and a third-stage limiting circuit connected in sequence, as shown in Figure 1 The first-stage limiting circuit, the second-stage limiting circuit and the third-stage limiting circuit are sequentially and electrically connected through a delay line. The delay line is an element or device for delaying an electrical signal for a period of time. By delaying the electrical signal through the delay line, the time delay of the VHF frequency band can be matched with the frequency band.

[0045] Preferably, in order to ensure impedance matching between the power signal input end and the load end of the first-stage limiting circuit, so that most of the power of the high-power input signal flows into the load end, the embodiment requires that the time delay phase of the delay line between the first-stage limiting circuit and the second-stage limiting circuit is 90°. In order to achieve a 90° phase delay, the total length of the delay line needs to satisfy the following formula: L is the total length of the delay line; and λ is the wavelength of the VHF frequency band. According to the wavelength of the VHF frequency band, L≈280mm. The serpentine layout of the delay line of the embodiment can ensure sufficient delay in a limited volume. The length of the delay line determined by the above formula can ensure that the time delay phase of the delay line between the first-stage limiting circuit and the second-stage limiting circuit is 90°. On the other hand, since the length of the delay line greatly affects the standing wave and power leakage of high power, the appropriate length is the key to the design of the delay line. The length of the delay line determined by the above formula can reduce the influence of the delay line on the standing wave and power leakage of high power.

[0046] Preferably, in order to ensure power capacity and reduce insertion loss, the embodiment limits the thickness and distance of the delay line from the cavity. The cross-sectional side length of the delay line and the distance from the cavity satisfy the formula:

[0047]

[0048]

[0049] wherein, Z o is 50 ohms impedance; ε r =1; b is the width and height of the delay line cavity; a is the cross-sectional side length of the delay line; P is the power capacity; E bFor the breakdown electric field strength, the value is 30 kV / cm; first, the value of a is calculated based on formula (2), and then the value of a is substituted into formula (1) to calculate the value of b. After preliminary estimation: a ≈ 0.5 mm, in actual design, enough margin should be left, combined with engineering practice, a is taken as 3 mm, which can completely withstand the power of 3500W (15% duty cycle). According to the impedance formula, b ≈ 7 mm, in the CST software simulation, the impedance is 50 ohms when b is corrected to 9 mm. The metal conductor with a length of 3 mm is used as the delay line in this embodiment, which ensures the power capacity and has little effect on the insertion loss.

[0050] The principle of solving the problem of mismatching between time delay and frequency band of the limiter in the very high frequency band in this embodiment is that the first-stage limiting circuit, the second-stage limiting circuit and the third-stage limiting circuit are sequentially and electrically connected through the delay line, and the time delay phase of the delay line between the first-stage limiting circuit and the second-stage limiting circuit is 90°; the total length of the delay line needs to meet the formula: L is the total length of the delay line; λ is the wavelength of the VHF frequency band; the thickness and the distance from the cavity of the delay line meet formula (1) and formula (2), by limiting the length, thickness and distance from the cavity of the delay line, the power signal can be delayed through the delay line to realize the matching between time delay and frequency band in the very high frequency band.

[0051] The beneficial effects of this embodiment are that the first-stage limiting circuit, the second-stage limiting circuit and the third-stage limiting circuit are sequentially and electrically connected through the delay line, and the time delay phase of the delay line between the first-stage limiting circuit and the second-stage limiting circuit is 90°, which can ensure the impedance matching between the power signal input end and the load end of the first-stage limiting circuit, so that most of the power of the high-power input signal flows into the load end, thereby realizing the limiting function;

[0052] Limiting the length of the delay line can reduce the influence of the delay line on the high-power standing wave and power leakage; limiting the thickness and distance from the cavity of the delay line can ensure the power capacity of the limiter and reduce the insertion loss;

[0053] The delay line limited in length, thickness and distance from the cavity can make the power signal delayed through the delay line to realize the matching between time delay and frequency band in the very high frequency band.

[0054] Embodiment 2

[0055] The limiter designed by PIN limiting diode usually adopts the parallel circuit scheme of multiple PIN limiting diodes, and the microwave high-power signal is attenuated step by step when passing through the limiter, so the input power of the limiter is mainly determined by the power bearing characteristics of the first-stage PIN limiting diode. Generally, the higher the power bearing of the PIN limiting diode, the greater the junction capacitance of the PIN diode, and the increase of the junction capacitance of the PIN diode directly limits the working frequency and working bandwidth of the limiter circuit. At present, the first-stage PIN limiting circuit adopts the method of connecting multiple PIN limiting diodes in parallel to improve the power bearing capacity of the limiter, and the more parallel branches, the greater the ground capacitance of the first-stage limiting circuit, thereby limiting the working frequency and working bandwidth of the microwave limiter circuit. At present, it is difficult for the VHF limiter to bear more than 2000 watts. Therefore, how to design the number of parallel branches of the first-stage PIN limiting circuit so that the limiter bears more than 2000 watts while the ground capacitance is small becomes a design difficulty. In order to solve the above difficulty, the embodiment provides a specific circuit structure of a VHF band limiter, which is as follows:

[0056] As shown in Figure 2 The first-stage limiting circuit includes a plurality of PIN switch tube pairs with the same structure, an inductor, a power signal input end, a load end and a power signal output end. The PIN switch tube pair includes two anti-phase PIN switch tubes connected in parallel. The plurality of PIN switch tube pairs are divided into two groups, and the PIN switch tube pairs in each group are connected in parallel with each other. The input end of the first group is connected in series between the power signal input end and the power signal output end, the output end of the first group is electrically connected to the input end of the second group, the output end of the second group is electrically connected to the load end, and the load end is electrically connected to an external power load. The inductor is connected in parallel between the load end and the power signal output end. Among them, the first-stage limiting circuit bears the maximum power, if the selected PIN switch tube type and quantity cannot bear the high-power signal, the high-power signal will flow to the subsequent circuit and burn the subsequent circuit, therefore, in order to make the high-power signal flow to the load through the first limiting circuit and bear the high-power signal, the PIN switch tube is preferably a high-power PIN switch tube. In the first-stage limiting circuit of the embodiment, the plurality of PIN switch tube pairs are divided into two groups, and the PIN switch tube pairs in each group are connected in parallel with each other, and the two groups are connected in series, that is, the plurality of PIN switch tube pairs adopt the structure of parallel-serial-parallel, on the one hand, without affecting the working frequency and working bandwidth of the limiter circuit, the power bearing capacity of the limiter is improved; on the other hand, the introduction of the series structure reduces the ground capacitance, and improves the working frequency and working bandwidth of the limiter circuit.

[0057] Preferably, since a large amount of heat is generated by the high-power through the PIN tube, especially in the first-stage limiting circuit, therefore, in the embodiment, the PIN switch tube does not directly contact the shell, and the heat needs to be conducted to the shell through the high-thermal-conductivity ceramic.

[0058] Preferably, the total number of PIN switch tube pairs in the first stage limiting circuit satisfies the following formula: Wherein, P is the power capacity, P=I 2 R, I is the total current effective value through the PIN switch tube pairs, R is the load impedance, which is a constant of 50Ω; i is the current effective value through a single PIN switch tube, i≤1; N is the total number of PIN switch tube pairs, and N is an integer multiple of 2. In this embodiment, the total number of PIN switch tube pairs in parallel is determined according to the total current effective value, and the current effective value i of a single PIN switch tube is required to be within 1A. In this embodiment, P=3500W, R is 50Ω, and the current effective value That is, the total current effective value of the switch tube is 8.4A, and the number of parallel switch tubes is And is a multiple of 2. Therefore, N=10 parallel is adopted in this embodiment. As shown in Figure 2 D1-D20 represent 20 PIN switch tubes respectively. It should be noted that: only the switch tube pair contains two switch tubes, and the number of switch tube pairs can satisfy the above formula.

[0059] As shown in Figure 2 The second stage limiting circuit includes a plurality of first PIN limiting tube pairs with the same structure; the first PIN limiting tube pair includes two anti-phase PIN limiting tubes in parallel; a plurality of first PIN limiting tube pairs are connected in parallel; the input end of the first PIN limiting tube pair is connected in series between the power signal output end of the first stage limiting circuit and the power signal input end of the third stage limiting circuit, and the output end of the first PIN limiting tube pair is grounded. Among them, since the first stage limiting circuit bears the maximum power, the second stage limiting circuit bears less power than the first stage limiting circuit, therefore, the PIN tube of the second stage limiting circuit requires to be lower, and a high-power PIN limiting tube can be used. Preferably, in this embodiment, the second stage limiting circuit includes three first PIN limiting tube pairs, and six first PIN limiting tubes are represented by D21-D26.

[0060] As shown in Figure 2The third stage limiting circuit includes a plurality of second PIN limiting tube pairs which are identical in structure; the second PIN limiting tube pair includes two PIN limiting tubes connected in anti-phase in parallel; the plurality of second PIN limiting tube pairs are connected in parallel with each other; the input end of the second PIN limiting tube pair is electrically connected with the power signal output end of the second stage limiting circuit, and the output end of the first PIN limiting tube pair is grounded. The third stage limiting circuit bears the minimum power, and the main function of the third stage limiting circuit is to clamp the leakage power and reduce the power leaked to the receiver to within a safe range, therefore, the second PIN limiting tube pair adopts a low-leakage PIN limiting tube. Preferably, in the embodiment, the third stage limiting circuit includes one second PIN limiting tube pair, and the two second PIN limiting tubes are represented by D27 and D28 respectively.

[0061] The working principle of the embodiment is as follows: the external input signal is input from the power signal input end to the first stage limiting circuit; when the power of the external input signal is lower than the preset value, the PIN switch tube in the first stage limiting circuit cannot be turned on, and the external input signal directly enters the receiver through the delay line;

[0062] On the contrary, the PIN switch tube in the first stage limiting circuit is automatically turned on, the power signal input end of the first stage limiting circuit is connected with the load end, most of the power flows to the external power load through the PIN switch tube and is absorbed by the power load; at the same time, the PIN limiting tube in the second stage limiting circuit is turned on, a short circuit to the ground is formed, a small amount of leakage power is clamped through the third stage limiting circuit, and is further limited until the power leaked to the receiver is reduced to within a safe range.

[0063] The embodiment has the beneficial effect that by limiting the number of the PIN switch tube pairs connected in parallel in the first stage limiting circuit, the limiter bears a power of 2000 watts or above while the input end to load end capacitance is small, and the isolation degree and insertion loss to the load end when a small signal is input are reduced.

[0064] The plurality of PIN switch tube pairs of the first stage limiting circuit adopt a parallel-serial-parallel structure, which on the one hand, improves the power bearing capacity of the limiter without affecting the working frequency and working bandwidth of the limiter circuit, and on the other hand, the introduction of the serial structure reduces the capacitance to the ground and improves the working frequency and working bandwidth of the limiter circuit.

[0065] Embodiment 3

[0066] The embodiment 1 limits the thickness of the delay line and the distance from the cavity to ensure the power capacity of the limiter and reduce the insertion loss, but the reduced insertion loss of the embodiment 1 meets the index that the small-signal insertion loss is less than 0.5 dB, and cannot meet the industrial demand. Therefore, in order to solve the above problems, on the basis of the embodiment 2, the embodiment provides a scheme for reducing the small-signal insertion loss, specifically, a matching circuit is added at the output end of the third-stage limiting circuit, the input end of the matching circuit is electrically connected with the power signal output end of the third-stage limiting circuit, and the output end of the matching circuit is electrically connected with an external subsequent circuit.

[0067] Preferably, because PIN tubes are used in the second-stage limiting circuit and the third-stage limiting circuit, the junction capacitance of the PIN tubes causes impedance mismatching, therefore, in order to solve the above problems, the matching circuit is arranged in the embodiment. As shown in the figure, Figure 2 The matching circuit includes inductors L2-L4 and capacitors C1-C2; one end of the inductor L3 is electrically connected with the power signal output end of the third-stage limiting circuit, one end of the inductor L2 and one end of the capacitor C1 respectively, and the other end of the inductor L2 and the other end of the capacitor C1 are both grounded; the other end of the inductor L3 is electrically connected with one end of the inductor L4, one end of the capacitor C2 and an external subsequent circuit, and the other end of the inductor L4 and the other end of the capacitor C2 are both grounded. Wherein, the inductors L2-L4 and the capacitors C1-C2 constitute a band-pass filter, which on the one hand matches to 50 ohms in the working frequency band, ensures the minimum insertion loss under the working frequency, and on the other hand has a suppression effect on spurs.

[0068] The working principle of the embodiment is as follows: when a small-signal power is input to the first-stage limiting circuit, the PIN tubes in the first-stage limiting circuit, the second-stage limiting circuit and the third-stage limiting circuit are not conductive, and the small-signal power is directly input to the receiver after passing through the matching circuit to reduce the insertion loss.

[0069] The embodiment has the beneficial effect that the matching circuit can reduce the insertion loss while meeting the power capacity of more than 2000 watts.

[0070] Embodiment 4

[0071] On the basis of any one of the embodiments 1-3, the embodiment provides a limiting method of a VHF frequency band limiter, which includes the following steps:

[0072] S1, the VHF frequency band limiter described in the embodiments 1-3 is built, and an external input signal is input from a power signal input end to a first-stage limiting circuit;

[0073] S2, if the power of the external input signal is lower than a preset value, the PIN switch tube in the first-stage limiting circuit cannot be conductive, the external input signal is delayed for a certain time through a delay line, the time delay of the very high frequency band is matched with the frequency band, and then the external input signal directly enters a matching circuit, is input to a receiver after the insertion loss is reduced through the matching circuit.

[0074] Conversely, the PIN switch tube in the first stage limiting circuit is automatically turned on, the power signal input end of the first stage limiting circuit is in communication with the load end, most of the power flows to the external power load through the PIN switch tube and is absorbed by the power load; at the same time, the PIN limiting tube in the second stage limiting circuit is turned on, a small part of the leakage power is reflected by the short circuit to the ground, is clamped by the third stage limiting circuit, is further limited, and the power leaked to the receiver is reduced to within a safe range.

[0075] The above merely describes the preferred embodiments of the present application, but should not be used to limit the present application, and any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims

1. A VHF band limiter comprising a first stage of limiting circuitry, a second stage of limiting circuitry and a third stage of limiting circuitry, characterised in that: The first-stage limiting circuit, the second-stage limiting circuit and the third-stage limiting circuit are sequentially and electrically connected through a delay line; The time delay phase of the delay line between the first-stage limiting circuit and the second-stage limiting circuit is 90°; The first-stage limiting circuit comprises a plurality of PIN switch tube pairs with the same structure, an inductor, a power signal input end, a load end and a power signal output end; The PIN switch tube pair comprises two PIN switch tubes connected in anti-phase and in parallel; The plurality of PIN switch tube pairs are divided into two groups, and the PIN switch tube pairs in each group are connected in parallel with each other; the input end of the first group is connected in series between the power signal input end and the power signal output end, the output end of the first group is electrically connected with the input end of the second group, the output end of the second group is electrically connected with the load end, and the load end is electrically connected with an external power load; The inductor is connected in parallel between the load end and the power signal output end; The second-stage limiting circuit comprises a plurality of first PIN limiting tube pairs with the same structure; The first PIN limiting tube pair comprises two PIN limiting tubes connected in anti-phase and in parallel; The plurality of first PIN limiting tube pairs are connected in parallel with each other; the input end of the first PIN limiting tube pair is connected in series between the power signal output end of the first-stage limiting circuit and the power signal input end of the third-stage limiting circuit, and the output end of the first PIN limiting tube pair is grounded; The third-stage limiting circuit comprises a plurality of second PIN limiting tube pairs with the same structure; The second PIN limiting tube pair comprises two PIN limiting tubes connected in anti-phase and in parallel; The plurality of second PIN limiting tube pairs are connected in parallel with each other; the input end of the second PIN limiting tube pair is electrically connected with the power signal output end of the second-stage limiting circuit, and the output end of the first PIN limiting tube pair is grounded.

2. The VHF band limiter of claim 1, wherein: The total length of the delay line satisfies the following formula: ; is the wavelength of the VHF band.

3. The VHF band limiter of claim 1, wherein: The cross-sectional side length and the distance from the cavity of the delay line satisfy the formula: （1）； （2）； wherein, is 50 ohm impedance; ; is the delay line cavity width and height; is the delay line cross section side length; is the power capacity; is the breakdown electric field strength, taking 30 kV / cm.

4. The VHF band limiter of claim 1, wherein: The total number of PIN switch tube pairs in the first-stage limiting circuit satisfies the formula: ； wherein, is the power capacity; is the load impedance, is a constant 50Ω; is the effective value of the current flowing through the single PIN switch tube, ; is the total number of PIN switch tube pairs, and is an integer multiple of 2.

5. The VHF band limiter of claim 1 or 4, wherein: The matching circuit is further included; The input end of the matching circuit is electrically connected with the power signal output end of the third-stage limiting circuit, and the output end of the matching circuit is electrically connected with an external subsequent circuit.

6. The VHF band limiter of claim 5, wherein: The matching circuit comprises inductors L2-L4 and capacitors C1-C2; One end of the inductor L3 is electrically connected with the power signal output end of the third-stage limiting circuit, one end of the inductor L2 and one end of the capacitor C1, respectively; the other end of the inductor L2 and the other end of the capacitor C1 are both grounded; the other end of the inductor L3 is electrically connected with one end of the inductor L4, one end of the capacitor C2 and an external subsequent circuit; the other end of the inductor L4 and the other end of the capacitor C2 are both grounded.

7. A method of limiting a VHF band limiter, characterized by: The method comprises the following steps: S1, a VHF frequency band limiter as claimed in claim 1 is built, and an external input signal is input from the power signal input end to the first-stage limiting circuit; S2, when the power of the external input signal is lower than a preset value, the PIN switch tube in the first-stage limiting circuit cannot be turned on; the external input signal is delayed for a certain time through the delay line, and after the time delay of the very high frequency band is matched with the frequency band, the external input signal directly enters the matching circuit, is input to a receiver after the insertion loss is reduced through the matching circuit, and the like. Conversely, the PIN switch tube in the first stage of the limiting circuit is automatically turned on, the power signal input end of the first stage of the limiting circuit is in communication with the load end, most of the power flows to the external power load through the PIN switch tube and is absorbed by the power load; at the same time, the PIN limiting tube in the second stage of the limiting circuit is turned on, forms a reflection to the ground, a small part of the leakage power is clamped through the third stage of the limiting circuit, is further limited, until the power leaked to the receiver is reduced to within a safe range.

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