Semiconductor device

Abstract

A semiconductor device that protects a power switching element from damage in an overcurrent state and suppresses reverse current generated when a negative drive voltage is applied. The semiconductor device (S1) includes a main IGBT (5), a sensing IGBT (4), a resistor (2), a MOSFET (3), and a diode (1) as main structural elements. The sensing IGBT (4) and the main IGBT (5) are connected in parallel with each other. The drain of the MOSFET (3) is connected to the gate of the sensing IGBT (4), the source is connected to the gate of the main IGBT (5), and the gate is connected to the emitter of the sensing IGBT (4) and the cathode of the diode (1). One end of the resistor (2) is connected to the gate of the main IGBT (5) and the source of the MOSFET (3), and the other end of the resistor (2) is connected to the emitter of the main IGBT (5) and the anode of the diode (1).

Description

Technical Field

[0001] The present invention relates to a semiconductor device having a function of protecting a power switching element from being damaged by an overcurrent state. Background Art

[0002] In a semiconductor device having a power switching element such as a power transistor, in order to achieve both a long non-destructive short-circuit time and low loss, a method is adopted in which the current amount is reduced only during a short circuit and a high conduction ability is maintained during non-short circuit, wherein the power transistor has an on / off function.

[0003] As a semiconductor device adopting the above method, for example, there is a protection circuit of the semiconductor device disclosed in Patent Document 1. In this protection circuit, the following method is adopted, that is, an element having a current sensing function disposed between the chip unit portion and the unit portion is provided to detect a state in which an excessive current flows due to a short circuit.

[0004] Specifically, a configuration is provided in which, when an excessive current is applied, based on a signal obtained by current sensing using a parallel configuration, feedback control is performed to suppress the gate voltage of the power transistor to be controlled and limit the current flowing through the power transistor. In Patent Document 1, the above protection circuit is constructed in a monolithic manner to control the gate voltage of the power switching element.

[0005] Patent Document 1: Japanese Patent Laid-Open No. 10-145206

[0006] However, in the protection circuit disclosed in Patent Document 1, there is a problem that when a negative drive voltage is applied to the gate of the power transistor, there is a possibility that the gate resistor may be burned out and the gate driver may be damaged due to a reverse current flowing through a parasitic diode in the MOSFET constituting the protection circuit.

[0007] In addition, the gate driver is a drive voltage imparting unit that imparts a gate voltage as a drive voltage, and the gate resistor is a resistor for transmitting the gate voltage. In addition, the parasitic diode in the MOSFET is sometimes referred to as a body diode. Summary of the Invention

[0008] The present invention has been made to solve the above problems, and an object thereof is to obtain a semiconductor device that protects a power switching element from being damaged by an overcurrent state and suppresses a reverse current generated when a negative drive voltage is applied.

[0009] The semiconductor device according to the present invention includes: an n-channel first power switching element having one electrode, another electrode, and a control electrode; an n-channel second power switching element having one electrode, another electrode, and a control electrode, with one electrode of the second power switching element connected to one electrode of the first power switching element; a first diode having an anode connected to the other electrode of the first power switching element and a cathode disposed in the direction of the other electrode of the second power switching element; an n-channel first MOSFET having one electrode, another electrode, and a control electrode, with one electrode of the first MOSFET receiving the driving voltage for the first and second power switching elements, one electrode of the first MOSFET connected to the control electrode of the second power switching element, another electrode connected to the control electrode of the second power switching element, and the control electrode connected to the other electrode of the second power switching element; and a charge release circuit having a charge release path provided from the control electrode to the other electrode of the first power switching element.

[0010] Effects of the Invention

[0011] In the semiconductor device of the present invention, when an overcurrent flows through the first power switching element, the first control voltage applied to the control electrode of the first power switching element becomes higher.

[0012] Therefore, when an overcurrent flows through the first power switching element, it acts in a direction to reduce the potential difference between the control electrode and the other electrode of the first MOSFET, and the on-state of the first MOSFET becomes weaker. Along with the weakening of the on-state of the first MOSFET, the excess charge accumulated on the control electrode of the first power switching element is released to the outside on the other electrode side of the first power switching element via the charge release path of the charge release circuit.

[0013] As a result, the semiconductor device of the present invention can reduce the amount of current flowing through the first power switching element by rapidly reducing the first control voltage in an overcurrent state.

[0014] When a negative driving voltage is applied, the following phenomenon is assumed: a reverse current flows through the parasitic diode in the first MOSFET from the other electrode of the first power switching element to the driving voltage applying unit that applies the driving voltage.

[0015] The charge release circuit of the semiconductor device of the present invention has a charge release path from the control electrode to the other electrode of the first power switching element. Therefore, the charge release path exists between the other electrode of the first MOSFET and the other electrode of the first power switching element.

[0016] Therefore, when a negative driving voltage is applied to the semiconductor device of the present invention, due to the presence of the charge release circuit, it is also possible to suppress the phenomenon of reverse current flowing through the parasitic diode in the first MOSFET. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 FIG. is a cross-sectional view showing the cross-sectional structure of the semiconductor device of Embodiment 1.

[0018] Figure 2 FIG. is a top view showing the planar structure of the semiconductor device of Embodiment 1.

[0019] Figure 3 FIG. is a circuit diagram showing the circuit structure of the semiconductor device of Embodiment 1.

[0020] Figure 4 FIG. is a cross-sectional view showing the cross-sectional structure of the semiconductor device of Embodiment 2.

[0021] Figure 5 FIG. is a top view showing the planar structure of the semiconductor device of Embodiment 2.

[0022] Figure 6 FIG. is a circuit diagram showing the circuit structure of the semiconductor device of Embodiment 2.

[0023] Figure 7 FIG. is a cross-sectional view showing the cross-sectional structure of the semiconductor device of Embodiment 3.

[0024] Figure 8 FIG. is a top view showing the planar structure of the semiconductor device of Embodiment 3.

[0025] Figure 9 FIG. is a circuit diagram showing the circuit structure of the semiconductor device of Embodiment 3.

[0026] Figure 10 FIG. is a circuit diagram showing a circuit structure equivalent to the protection circuit of the semiconductor device as the basic technology. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0027] <FOREWORD>

[0028] The present invention is directed to a semiconductor device that controls the current flowing through a power switching element by changing the voltage of the control electrode of the power switching element. In the embodiments described below, a trench-type insulated gate bipolar transistor (IGBT; Insulated Gate Bipolar Transistor) is used as the power switching element for explanation.

[0029] In addition, a term such as "MOS" was previously used for a stacked structure of metal / oxide / semiconductor and is an abbreviation of the initial letters of Metal-Oxide-Semiconductor. However, particularly in a field-effect transistor having a MOS structure (hereinafter simply referred to as "MOSFET"), from the viewpoints of recent integration and improvement of manufacturing processes, etc., the materials of the gate insulating film and the gate electrode are being improved.

[0030] Therefore, a term such as "MOS" is not necessarily limited to a stacked structure of metal / oxide / semiconductor, and this specification is not premised on such a limitation. That is, in view of common technical knowledge, here, "MOS" not only has the meaning as an abbreviation derived from its etymology, but also has a meaning that widely includes a stacked structure of conductor / insulator / semiconductor.

[0031] <Basic Technology>

[0032] Figure 10 It is a circuit diagram showing a circuit structure equivalent to the protection circuit of the semiconductor device as the basic technology disclosed in Patent Document 1. In Figure 10 As the semiconductor device of the basic technology, for example, a main IGBT 110 constituting a bridge arm of an inverter is provided. The emitter of the main IGBT 110 is connected to the emitter electrode terminal 112, and the collector is connected to the collector electrode terminal 114.

[0033] In order to protect the main IGBT 110 from overcurrent damage, an overcurrent protection circuit is provided. The overcurrent protection circuit is configured to include a detection IGBT 118, a gate resistor 120, transistors 122 and 124 composed of n-type MOSFETs, a detection resistor 126, and an auxiliary detection resistor 128.

[0034] The detection IGBT 118 is connected in parallel with the main IGBT 110. The collector is connected to the collector electrode terminal 114, the gate is connected to the gate of the main IGBT 110 and is connected to the gate electrode terminal 130 via the gate resistor 120, and the emitter is connected to one end of the detection resistor 126 and the gate of the transistor 122.

[0035] In addition, a gate voltage that becomes a drive voltage is applied to the gate electrode terminal 130 from a drive voltage application unit such as a gate driver (not shown). Hereinafter, this voltage will be referred to as a drive gate voltage.

[0036] The drain of transistor 122 is connected to the gate of detection IGBT 118, and the source is connected to emitter electrode terminal 112. This transistor 122 is configured as an overcurrent protection unit and a voltage control unit. The overcurrent protection unit becomes conductive only when the gate voltage Vs exceeds the threshold voltage, reducing the driving gate voltage at point A118 and decreasing the conduction current of main IGBT 110 and the conduction current of detection IGBT 118. The voltage control unit reduces the level of the driving gate voltage at point A118 corresponding to the gate voltage Vs.

[0037] Detection resistor 126 and auxiliary detection resistor 128 are connected in series between the emitter of detection IGBT 118 and emitter electrode terminal 112, forming a current-voltage conversion unit. This current-voltage conversion unit detects the current flowing through detection IGBT 118 and converts the detected current into a voltage corresponding to the resistance value.

[0038] The overcurrent protection operation of the semiconductor device with such a structure is performed in the following manner. If an excessive main current flows through main IGBT 110, the current flowing through detection IGBT 118 also increases, and the detection voltage obtained by the detection of detection resistor 126 also increases. Moreover, if the gate voltage Vs, which is the detection voltage, exceeds the threshold voltage of transistor 122, transistor 122 becomes in an on state, and the driving gate voltage at point A118 decreases. In this way, the driving gate voltage decreases corresponding to the magnitude of the gate voltage Vs applied to the gate of transistor 122. If the driving gate voltage at point A118 decreases, the main current of main IGBT 110 and the current of detection IGBT 118 also decrease corresponding to the decrease in the driving gate voltage.

[0039] In this way, the semiconductor device of the basic technology can reduce the current flowing through main IGBT 110 in an overcurrent state through the above overcurrent protection circuit.

[0040] Next, consider the case where a negative driving gate voltage is applied as the driving voltage applied to gate electrode terminal 130. In this case, there is a problem that a reverse current flows from emitter electrode terminal 112, which is set to a reference potential such as GND potential, through the parasitic diode and gate resistor 120 in transistor 122 to gate electrode terminal 130.

[0041] If a non-negligible level of reverse current flows, it may have an adverse effect on the driving voltage application unit that applies the driving voltage to gate electrode terminal 130 and the gate resistor 120, which is an external resistor.

[0042] The semiconductor devices S1 to S3 of Embodiments 1 to 3 described below have an overcurrent protection function and a function of suppressing a reverse current flowing when a negative driving voltage is applied.

[0043] <Embodiment 1>

[0044] Figure 1 It is a cross-sectional view showing the cross-sectional structure of the semiconductor device of Embodiment 1. Figure 2 It is a top view showing the planar structure of the semiconductor device of Embodiment 1. Figure 2 The A-A cross-section of Figure 1 is Figure 2 . In addition, in

[0045] As Figure 1 shown, from the top to the bottom, the semiconductor substrate 100 includes a range from the drift layer 50 to the collector layer 25, and the drift layer 50 includes the base layer 40 and the base layer 14. Moreover, the semiconductor substrate 100 of the semiconductor device S1 is classified into a main region 91 and an auxiliary region 92, and the auxiliary region 92 is classified into a sensing region 93, a diode region 94, a resistor region 95, and a transistor region 96.

[0046] In Figure 1 the upper end of the paper surface of the drift layer 50 including the base layer 40 and the base layer 14 is referred to as the first main surface of the semiconductor substrate 100, and the lower end of the paper surface of the collector layer 25 is referred to as the second main surface of the semiconductor substrate 100. The first main surface of the semiconductor substrate 100 is the main surface on the surface side of the semiconductor device S1, and the second main surface of the semiconductor substrate 100 is the main surface on the back side of the semiconductor device S1.

[0047] In the entire region of the semiconductor substrate 100, a drift layer 50, a buffer layer 24, a collector layer 25, and a collector electrode 26 are provided.

[0048] On the second main surface side of the n - -type drift layer 50 of the first conductivity type, a buffer layer 24 is provided adjacent to the drift layer 50. The buffer layer 24 is of an n + -type with an n-type impurity concentration higher than that of the drift layer 50.

[0049] On the second main surface side of the buffer layer 24, a collector layer 25 is provided adjacent to the buffer layer 24. The collector layer 25 is of a p + -type with a relatively high p-type impurity concentration of the second conductivity type. A collector electrode 26 is provided on the second main surface of the collector layer 25.

[0050] The base layer 40 and the base layer 14 are selectively provided on the first main surface side within the drift layer 50. Both the base layer 40 and the base layer 14 are of p-type. The base layer 40 is provided in the transistor region 96, and the base layer 14 is provided in such a manner as to extend from a part of the resistor region 95 to the diode region 94, the sense region 93, and the main region 91. The base layer 14 is provided such that the formation depth of the region from a part of the resistor region 95 to the diode region 94 is deeper than the formation depths of the sense region 93 and the main region 91.

[0051] On the first main surface side within the base layer 40, a drain region 41 and a source region 42 are selectively provided. The drain region 41 and the source region 42 are of n-type with a relatively high impurity concentration. + type. Above the first main surface of the base layer 40 between the drain region 41 and the source region 42, a gate electrode 47 is provided with a gate insulating film 46 interposed therebetween.

[0052] An n-channel type MOSFET 3 is constituted with the base layer 40, the drain region 41, the source region 42, the gate insulating film 46, and the gate electrode 47 as main structural elements.

[0053] In the diode region 94, on the first main surface side within the base layer 14, a p-type anode region 29 and an n-type cathode region 30 are provided adjacent to each other. A diode 1 is constituted with the anode region 29 and the cathode region 30 as main structural elements.

[0054] In the sense regions 93 of the main region 91 and the auxiliary region 92, a carrier storage layer 39 is provided adjacent to the base layer 14 on the second main surface side of the base layer 14. The carrier storage layer 39 is of n-type, and the impurity concentration of the n-type is set higher than that of the drift layer 50. The carrier storage layer 39 is provided in such a manner that the formation depth is shallower than that of the base layer 14 in the diode region 94.

[0055] In the main region 91 and the sense region 93, a plurality of trenches are formed that penetrate the base layer 14 and the carrier storage layer 39 from the first main surface of the semiconductor substrate 100 to reach the drift layer 50. In each of the plurality of trenches, a gate electrode 19 serving as a buried gate electrode is provided with an insulating film 18 serving as a gate trench insulating film interposed therebetween.

[0056] In the main region 91 and the sense region 93, a plurality of n + source regions 15 are provided on the first main surface side within the base layer 14. The plurality of n + source regions 15 are each provided adjacent to the corresponding one of the plurality of insulating films 18.

[0057] Between adjacent gate electrodes 19, 19, a p + diffusion region 16 is provided on the first main surface side within the base layer 14. p+ The diffusion region 16 is arranged in such a way as to be in contact with each of a pair of n + source regions 15 existing on both sides.

[0058] With the above-mentioned drift layer 50, buffer layer 24, collector layer 25, carrier storage layer 39, base layer 14, n + source region 15, p + diffusion region 16, insulating film 18, and gate electrode 19 as main structural elements, a sensing IGBT 4 and a main IGBT 5 are respectively formed. The sensing IGBT 4 and the main IGBT 5 are each an n-channel type IGBT. The main IGBT 5 provided in the main region 91 is an n-channel type first power switching element, and the sensing IGBT 4 provided in the sensing region 93 is an n-channel type second power switching element.

[0059] Moreover, in the transistor region 96, an interlayer insulating film 21 is arranged so as to cover the gate electrode 47. In the resistor region 95, the interlayer insulating film 21 is arranged on the first main surface of the drift layer 50 between the base layer 40 and the base layer 14. In the diode region 94, the interlayer insulating film 21 is arranged on the first main surface of the anode region 29 and the cathode region 30. In the sensing region 93 and the main region 91, the interlayer insulating film 21 is arranged on the first main surface of the plurality of insulating films 18 and the plurality of gate electrodes 19.

[0060] In the resistor region 95, a conductive polysilicon layer 64 is arranged on the interlayer insulating film 21. This polysilicon layer 64 functions as a resistor 2. A charge release circuit is constituted by the single resistor 2, and the resistor 2 itself is a charge release path arranged in a manner from the gate to the collector of the main IGBT 5.

[0061] Moreover, a drain electrode 48, a source electrode 49, an anode electrode 58, an emitter electrode 60, and an emitter electrode 20 are arranged on the first main surface of the semiconductor substrate 100.

[0062] The drain electrode 48 is arranged in a manner from a part of the base layer 40 to a part of the drain region 41, and the source electrode 49 is arranged in a manner from a part of the source region 42 to a part of the base layer 40 and above one end of the polysilicon layer 64. Therefore, the drain electrode 48 is electrically connected to the drain region 41, and the source electrode 49 is electrically connected to the source region 42 and the polysilicon layer 64.

[0063] The anode electrode 58 is arranged in a manner from the other end of the polysilicon layer 64 to a part of the base layer 14 and a part of the anode region 29. Therefore, the anode electrode 58 is electrically connected to the polysilicon layer 64 and the anode region 29.

[0064] The emitter electrode 60 is disposed in such a manner as to cover the entire area from a part of the cathode region 30 to the sensing region 93. Accordingly, the emitter electrode 60 is electrically connected to the cathode region 30 and is also connected to the n + source region 15 and the p + diffusion region 16.

[0065] The emitter electrode 20 is disposed over the entire area of the main region 91. Accordingly, the emitter electrode 20 is electrically connected to the n + source region 15 and the p + diffusion region 16.

[0066] As Figure 1 shown, the semiconductor device S1 has an electrical connection relationship represented by electrical connection lines EL among the drain electrode 48, the gate electrode 47, the source electrode 49, the anode electrode 58, the emitter electrode 60, the emitter electrode 20, the gate electrode 19 of the sensing region 93, and the gate electrode 19 of the main region 91. In addition, each of the above electrodes is made of, for example, aluminum.

[0067] In addition, the electrical connection lines EL are virtual lines schematically showing the electrical connection relationships between the electrodes and are illustrated in such a manner as to connect the electrodes having the electrical connection relationships. In addition, among the multiple gate electrodes 19 provided in the sensing region 93 and the main region 91 respectively, each represents one gate electrode 19. That is, the multiple gate electrodes 19 of the main region 91 are electrically connected to each other, and the gate electrode 19 of the sensing region 93 is electrically connected to each other.

[0068] As Figure 1 shown, the drain electrode 48 is electrically connected to the gate electrode 19 of the sensing region 93. The gate electrode 47 is electrically connected to the emitter electrode 60. The source electrode 49 is electrically connected to the gate electrode 19 of the main region 91. The anode electrode 58 is electrically connected to the emitter electrode 20.

[0069] As Figure 2 shown, a part of the emitter electrode 20 extends over the diode region 94 and thus also serves as Figure 1 the anode electrode 58 shown. That is, the emitter electrode 20 and the anode electrode 58 are integrally provided.

[0070] In addition, most of the gate lead portion 71 is disposed along the outer periphery of the emitter electrode 20, and a part of the gate lead portion 71 is disposed to extend over the resistor region 95 and the transistor region 96, and thus also functions as Figure 1 the source electrode 49 shown. In addition, the gate lead portion 71 is electrically connected to the multiple gate electrodes 19 of the main region 91.

[0071] Moreover, the main part of the gate pad 72 is formed in the lower right region in the figure, and a part is formed to extend over the transistor region 96, and thus it also functions as the Figure 1 drain electrode 48 shown.

[0072] In addition, as Figure 2 shown, by providing a wiring layer 81 between the sensing region 93 and the gate pad 72, the gate pad 72 is electrically connected to the gate electrode 19 of the sensing region 93 via the wiring layer 81.

[0073] Moreover, a wiring layer 82 is provided between the emitter electrode 60 and the transistor region 96. Therefore, the emitter electrode 60 of the sensing region 93 is electrically connected to the gate electrode 47 of the transistor region 96 via the wiring layer 82.

[0074] In addition, as Figure 2 shown, a protection ring 79 is provided along the outer periphery of the gate lead-out portion 71. The protection ring 79 is provided to cut off the electrical connection relationship between the semiconductor device S1 and the outside.

[0075] Figure 3 It is a circuit diagram showing the Figure 1 and Figure 2 circuit structure of the semiconductor device S1 shown. Hereinafter, with reference to this figure, the circuit structure of the semiconductor device S1 will be described.

[0076] The semiconductor device S1 includes, as main structural elements, a first power switching element, i.e., a main IGBT 5, a second power switching element, i.e., a sensing IGBT 4, a first resistor, i.e., a resistor 2, a first MOSFET, i.e., an n-type MOSFET 3, and a first diode, i.e., a diode 1. A charge release circuit is constituted by the single resistor 2.

[0077] Each of the sensing IGBT 4 and the main IGBT 5 has a collector as one electrode, an emitter as the other electrode, and a gate as the control electrode.

[0078] Hereinafter, regarding the semiconductor device S1 of Embodiment 1, the Figure 1 and Figure 2 corresponding relationship between the device configuration shown and the Figure 3 circuit structure shown with respect to the electrodes will be described.

[0079] Regarding the main IGBT 5, the emitter corresponds to the emitter electrode 20, the gate corresponds to the gate electrode 19 of the main region 91, and the collector corresponds to the collector electrode 26. Regarding the sensing IGBT 4, the emitter corresponds to the emitter electrode 60, the gate corresponds to the gate electrode 19 of the sensing region 93, and the collector corresponds to the collector electrode 26.

[0080] MOSFET 3 has a drain as one electrode, a source as another electrode, and a gate as a control electrode. Regarding MOSFET 3, the drain corresponds to the drain electrode 48, the gate corresponds to the gate electrode 47, and the source corresponds to the source electrode 49.

[0081] Regarding diode 1, the anode corresponds to the anode electrode 58, and the cathode corresponds to the emitter electrode 60.

[0082] The sensing IGBT 4 and the main IGBT 5 are connected in parallel to each other. That is, the collectors of the sensing IGBT 4 and the main IGBT 5 are commonly connected, and the emitter of the sensing IGBT 4 is connected to the emitter of the main IGBT 5 via diode 1.

[0083] In addition, in the semiconductor device S1 at the practical level, as Figure 3 shown, a gate voltage VG that becomes a driving voltage is applied to the drain of MOSFET 3 and the gate of the sensing IGBT 4 from the gate driver 12 via the gate resistor 11. That is, the gate driver 12 functions as a driving voltage applying unit, and the gate voltage VG is a driving voltage for the sensing IGBT 4 and the main IGBT 5.

[0084] In addition, a variable power supply voltage VCC is applied to the collectors of the sensing IGBT 4 and the main IGBT 5 from the power supply 13, and the emitter of the main IGBT 5 is set to a common potential. For example, the GND potential is considered as the common potential.

[0085] The anode of diode 1 is connected to the emitter of the main IGBT 5, and the cathode of diode 1 is connected to the emitter of the sensing IGBT 4. That is, the cathode of diode 1 is arranged in the direction of the emitter of the sensing IGBT 4.

[0086] Diode 1 is provided to prevent the current flowing in the sensing IGBT 4 from flowing out to the common potential side. By providing diode 1, it is possible to accumulate charge at the gate of MOSFET 3, and thus it is possible to adjust the potential between the gate and the source of MOSFET 3.

[0087] The drain of MOSFET 3 is connected to the gate of the sensing IGBT 4, the source is connected to the gate of the main IGBT 5, and the gate is connected to the emitter of the sensing IGBT 4 and the cathode of diode 1.

[0088] Moreover, MOSFET 3 receives the gate voltage VG at the drain. The gate voltage VG is a driving voltage output from the driving voltage applying unit, that is, the gate driver 12, via the gate resistor 11. The gate voltage VG is a driving voltage for the sensing IGBT 4 and the main IGBT 5.

[0089] Moreover, one end of the resistor 2 constituting the charge release circuit is connected to the gate of the main IGBT 5 and the source of the MOSFET 3, and the other end of the resistor 2 is connected to the emitter of the main IGBT 5 and the anode of the diode 1.

[0090] The sensing IGBT 4 and the main IGBT 5 constituting the semiconductor device S1 are manufactured by the same manufacturing method as that of the existing IGBT. As a document disclosing the manufacturing method of the existing IGBT, for example, the manufacturing method disclosed in Japanese Patent Publication No. 4575713 is considered.

[0091] The diode 1, the resistor 2, and the MOSFET 3, which are other structural elements of the semiconductor device S1, are selectively manufactured as shown in the following (1) to (4), for example.

[0092] (1) In the diode region 94, after boron and phosphorus are implanted into adjacent regions on the first main surface side of the base layer 14, they are diffused by high-temperature heat treatment, and an anode region 29 and a cathode region 30 are formed on the first main surface side in the base layer 40. As a result, the diode 1 can be obtained in the diode region 94.

[0093] (2) In the resistor region 95, a conductive polysilicon layer 64 can be formed by depositing doped polysilicon on the interlayer insulating film 21. As a result, the resistor 2 can be obtained through the polysilicon layer 64. In addition, after depositing polysilicon on the interlayer insulating film 21, boron and phosphorus can be implanted to obtain a conductive polysilicon layer 64.

[0094] (3) In the transistor region 96, after boron is implanted into the first main surface side of the drift layer 50 and diffused by high-temperature heat treatment to form a p-type base layer 40, phosphorus is implanted into the first main surface side of the base layer 40 and diffused by high-temperature heat treatment to selectively form a drain region 41 and a source region 42.

[0095] (4) In the transistor region 96, after a gate insulating film 46 is formed on the first main surface of the semiconductor substrate 100, a gate electrode 47 is formed on the gate insulating film 46. At this time, the gate insulating film 46 is formed in a manner extending from the drain region 41 to the source region 42. Therefore, the upper surface of the gate insulating film 46 is the formation surface of the gate electrode 47, and the lower surface of the gate insulating film 46 is the formation surface of the drain region 41 and the source region 42.

[0096] In addition, the drain electrode 48, the source electrode 49, and the anode electrode 58 are formed, for example, when manufacturing the emitter electrode 20 and the emitter electrode 60.

[0097] Thus, in the semiconductor device S1 of Embodiment 1, the main IGBT 5, the sensing IGBT 4, the MOSFET 3, the diode 1, and the resistor 2, which are structural elements, are integrally provided on one semiconductor substrate 100. Therefore, the semiconductor device S1 can achieve miniaturization of the device.

[0098] (Overcurrent state)

[0099] Due to a bridge arm short circuit state or the like, an overcurrent state occurs in which an overcurrent flows through the semiconductor device S1. In this case, it is assumed that a certain voltage is applied to the collector electrode 26 from the outside, and a relatively high main gate voltage VM is applied to each of the plurality of gate electrodes 19. This main gate voltage VM is the first control voltage.

[0100] In addition, the turn-on operation during normal operation is performed as follows. First, as a drive voltage, a gate voltage VG of "H" level is applied to the gate of the sensing IGBT 4 to set the sensing IGBT 4 to the on state. Then, the gate voltage VE of the MOSFET 3 is set by the emitter voltage of the on-state sensing IGBT 4. As a result, the MOSFET 3 becomes the on state. Next, a gate current IG flows through the drain and source of the on-state MOSFET 3, and the main gate voltage VM is applied to the gate of the main IGBT 5. As a result, the main IGBT 5 becomes the on state.

[0101] In addition, the reason why the MOSFET 3 becomes the on state is that charge is stored in the gate of the MOSFET 3 through the diode 1, and the voltage between the gate and source of the MOSFET 3 exceeds the threshold voltage.

[0102] In the semiconductor device S1 of Embodiment 1, when an overcurrent flows through the main IGBT 5, which is the first power switching element, the main gate voltage VM, which is the first control voltage applied to the gate of the main IGBT 5, is higher than normal.

[0103] Therefore, when an overcurrent flows through the main IGBT 5, it acts in a direction to reduce the potential difference between the gate and source of the first MOSFET, i.e., the MOSFET 3, and the on state of the MOSFET 3 becomes weaker. The reason is that the main gate voltage VM, which is the source voltage of the MOSFET 3, rises. In addition, the MOSFET 3 may become the off state.

[0104] Along with the weakening of the on state of the MOSFET 3, the excess charge stored in the gate of the main IGBT 5 is released to the outside on the emitter side of the main IGBT 5 through the resistor 2, which itself becomes a charge release path.

[0105] As a result, the semiconductor device S1 of Embodiment 1 can reduce the amount of current flowing through the main IGBT 5 by rapidly reducing the first control voltage, i.e., the main gate voltage VM, in an overcurrent state.

[0106] (When applying the negative gate voltage VG)

[0107] Next, consider the case where the negative gate voltage VG is applied from the gate driver 12 as the driving voltage.

[0108] Imagine the following phenomenon: when the negative gate voltage VG is applied, even if the MOSFET 3 is in the off state, a reverse current flows from the emitter of the main IGBT 5 to the gate driver 12 through the parasitic diode in the MOSFET 3.

[0109] In the semiconductor device S1 of Embodiment 1, the resistor 2 that constitutes the charge release circuit and itself becomes the charge release path is provided between the source of the MOSFET 3 and the emitter of the main IGBT 5. Therefore, even if the gate voltage VG becomes negative, due to the voltage drop caused by the resistor 2, the source potential of the MOSFET 3 can change in the direction close to the negative gate voltage VG. That is, the current flowing through the resistor 2 becomes the limiting factor for the reverse current.

[0110] As described above, in the semiconductor device S1 of Embodiment 1, there is a resistor 2 that becomes the charge release path from the gate to the emitter of the main IGBT 5. This resistor 2 is the charge release circuit, and the above charge release path exists between the source of the MOSFET 3 and the emitter of the main IGBT 5.

[0111] Therefore, for the semiconductor device S1 of Embodiment 1, even if the gate voltage VG becomes negative, due to the presence of the resistor 2, the potential difference between the drain and source of the MOSFET 3 is reduced, thereby suppressing the phenomenon that the reverse current flows through the parasitic diode in the MOSFET 3.

[0112] Therefore, in the semiconductor device S1, when the negative gate voltage VG is applied, a reverse current with an ignorable amount of current does not flow, and no adverse effects are caused to the gate driver 12 as the driving voltage supply unit and the gate resistor 11 as the external resistor.

[0113] <Embodiment 2>

[0114] Figure 4 It is a cross-sectional view showing the cross-sectional structure of the semiconductor device S2 of Embodiment 2. Figure 5 It is a top view showing the planar structure of the semiconductor device of Embodiment 2. Figure 5 The B-B cross-section of is Figure 4 . In addition,Figure 5 The cross-section B-B2 is the same as the cross-sectional structure of Embodiment 1 shown in Figure 1 . In addition, in Figure 5 , for convenience of explanation, the illustration of the interlayer insulating film 21, the gate electrode 47, and the polysilicon layer 64 is omitted.

[0115] As shown in Figure 1 and Figure 4 , the semiconductor substrate 100 of the semiconductor device S2 is classified into a main region 91 and an auxiliary region 92. Moreover, the auxiliary region 92 is classified into a sensing region 93, a diode region 94, a resistor region 95, a transistor region 96, and a diode region 94B.

[0116] Hereinafter, the same components as those of the semiconductor device S1 are denoted by the same reference numerals and the description thereof is appropriately omitted, and the diode region 94B, which is a characteristic part of the semiconductor device S2 of Embodiment 2, will be described.

[0117] In the diode region 94B, a base layer 43 is provided on the first main surface side within the drift layer 50. The impurity concentration of the base layer 43 is p-type.

[0118] Moreover, on the first main surface side within the base layer 43, a p-type anode region 44 and an n-type cathode region 45 are provided adjacent to each other.

[0119] The second diode, i.e., diode 6, is formed with the above anode region 44 and cathode region 45 as main structural elements.

[0120] Moreover, in addition to the drain electrode 48, the source electrode 49, the anode electrode 58, the emitter electrode 60, and the emitter electrode 20, an anode electrode 68 and a cathode electrode 69 are provided on the first main surface of the semiconductor substrate 100.

[0121] The anode electrode 68 is provided so as to extend from one end of the polysilicon layer 64 to a part of the base layer 43 and a part of the anode region 44. Therefore, the anode electrode 68 is electrically connected to the anode region 44 and the polysilicon layer 64.

[0122] The cathode electrode 69 is provided so as to extend from a part of the base layer 43 to a part of the cathode region 45. Therefore, the cathode electrode 69 is electrically connected to the cathode region 45.

[0123] As shown in Figure 4 , the semiconductor device S2 has an electrical connection relationship represented by an electrical connection line EL among the cathode electrode 69, the anode electrode 68, the anode electrode 58, the emitter electrode 60, the emitter electrode 20, the gate electrode 19 of the sensing region 93, and the gate electrode 19 of the main region 91. In addition, each of the above electrodes is made of, for example, aluminum as a constituent material.

[0124] As Figure 4 shown, the cathode electrode 69 is electrically connected to the gate electrode 19 of the sensing region 93. The anode electrode 68 is electrically connected to the gate electrode 19 of the main region 91. The anode electrode 58 is electrically connected to the emitter electrode 20.

[0125] In addition, although not shown in Figure 4 , the semiconductor device S2 of Embodiment 2 is the same as that of Embodiment 1. As Figure 1 shown, between the drain electrode 48 and the gate electrode 19 of the sensing region 93, between the gate electrode 47 and the emitter electrode 60, and between the source electrode 49 and the gate electrode 19 of the main region 91 are electrically connected respectively.

[0126] In addition, as Figure 5 shown, an isolation region 88 is provided between the transistor region 96 and the diode region 94B. The isolation region 88 extends from the first main surface of the semiconductor substrate 100 toward the second main surface and is formed deeper than the formation depths of the base layers 40 and 43. Through this isolation region 88, the base layer 40 of the transistor region 96 and the base layer 43 of the diode region 94B are separated. The isolation region 88 only needs to electrically isolate between the base layers 40 and 43, and its material is not particularly limited. For example, the isolation region 88 may also be constituted by a trench in which no elements are provided inside.

[0127] In this way, by providing the isolation region 88, the MOSFET 3 formed in the transistor region 96 and the diode 6 formed in the diode region 94B do not affect each other. In addition, a protective film such as an oxide film may be provided on the isolation region 88.

[0128] As Figure 5 shown, most of the gate lead portion 71 is provided along the outer periphery of the emitter electrode 20, and a part is provided to extend above the resistor region 95, the transistor region 96, and the diode region 94B, and thus it also functions as the Figure 4 shown source electrode 49 and anode electrode 68.

[0129] Moreover, by forming the gate pad 72 so that a part extends above the transistor region 96 and the diode region 94B, it also functions as the Figure 1 shown drain electrode 48 and the Figure 4 shown cathode electrode 69.

[0130] Since Figure 5 the other planar structures in Figure 2 are the same as the planar structure shown in , the same reference numerals are used and the description is appropriately omitted.

[0131] The diode 6, which is a structural element of the semiconductor device S2, can be manufactured by the same manufacturing method as the diode 1.

[0132] Thus, in the semiconductor device S2 of the second embodiment, the main IGBT 5, the sensing IGBT 4, the MOSFET 3, the diode 1, the diode 6, and the resistor 2, which are structural elements, are integrally provided on a single semiconductor substrate 100. Therefore, the semiconductor device S2 can achieve miniaturization of the device.

[0133] Figure 6 It represents Figure 4 and Figure 5 The circuit diagram showing the circuit structure of the semiconductor device S2 shown. Hereinafter, the same reference numerals are given to the same structures as those of the semiconductor device S1, and the description will be appropriately omitted. Referring to Figure 6 The circuit structure of the semiconductor device S2 will be described.

[0134] The semiconductor device S2 includes, as main structural elements, a first power switching element, i.e., the main IGBT 5, a second power switching element, i.e., the sensing IGBT 4, a first resistor, i.e., the resistor 2, a first MOSFET, i.e., the MOSFET 3, a first diode, i.e., the diode 1, and a second diode, i.e., the diode 6.

[0135] Regarding Figure 6 the diode 6 shown, the anode corresponds to Figure 4 and Figure 5 the anode electrode 68 shown, and the cathode corresponds to Figure 4 and Figure 5 the cathode electrode 69 shown.

[0136] The anode of the diode 6 is connected to the source of the MOSFET 3, the gate of the main IGBT 5, and one end of the resistor 2, and the cathode of the diode 6 is connected to the drain of the MOSFET 3 and the gate of the sensing IGBT 4.

[0137] (Overcurrent state)

[0138] Similar to the semiconductor device S1 of the first embodiment, the semiconductor device S2 of the second embodiment can reduce the amount of current flowing through the main IGBT 5 by rapidly reducing the first control voltage, i.e., the main gate voltage VM, in an overcurrent state.

[0139] (At cutoff operation)

[0140] The semiconductor device S2 of Embodiment 2 further includes a second diode, i.e., diode 6. Therefore, when the gate voltage VG is less than or equal to 0V in the on-state of the main IGBT 5 to turn off the main IGBT 5, the charge applied to the gate of the main IGBT 5 can be quickly released to the outside of the gate driver 12 via the diode 6.

[0141] That is, in addition to the resistor 2 that itself forms a charge release path, the diode 6 can ensure a charge release path for releasing the charge applied to the gate of the main IGBT 5 when it is turned off.

[0142] Therefore, even if the resistance value of the resistor 2 is set to be sufficiently large in the semiconductor device S2 of Embodiment 2, it will not pose an obstacle to the turn-off operation.

[0143] In this way, by providing the diode 6 in the semiconductor device S2 of Embodiment 2, the high-speed turn-off operation can be achieved.

[0144] (When applying a negative gate voltage VG)

[0145] Next, consider the case where a negative gate voltage VG is applied from the gate driver 12.

[0146] As described above, in the semiconductor device S2, the resistance value of the resistor 2 can be set to be sufficiently large.

[0147] Therefore, the resistor 2 is provided between the source of the MOSFET 3 and the emitter of the main IGBT 5, and the resistance value of the resistor 2 can be set to be sufficiently large. Thus, even when the gate voltage VG becomes a negative level, the source potential of the MOSFET 3 can be set to the same level as the gate voltage VG due to the voltage drop caused by the resistor 2. Therefore, almost no reverse current flows through the parasitic diode of the MOSFET 3 or the diode 6.

[0148] As a result, in the semiconductor device S2 of Embodiment 2, even when the gate voltage VG becomes a negative level, the reverse current flowing through the parasitic diode of the MOSFET 3 or the diode 6 can be suppressed to a minimum.

[0149] <Embodiment 3>

[0150] Figure 7 It is a cross-sectional view showing the cross-sectional structure of the semiconductor device S3 of Embodiment 3. Figure 8 It is a top view showing the planar structure of the semiconductor device of Embodiment 3. Figure 8 The C-C cross-section of is Figure 7 . In addition, in Figure 8In the figure, for ease of explanation, illustrations of the interlayer insulating film 21, the source-anode electrode 53, the gate electrode 67, the gate electrode 77, and the polysilicon layer 65 are omitted.

[0151] As Figure 7 shown, the semiconductor substrate 100 of the semiconductor device S3 is classified into a main region 91 and an auxiliary region 92. Further, the auxiliary region 92 is classified into a sensing region 93, a resistance region 95B, a diode region 94, a diode region 94C, a transistor region 96B, and a transistor region 96.

[0152] Hereinafter, since the main region 91 and the sensing region 93 of the auxiliary region 92 have the same structure as those of the semiconductor device S1, the same reference numerals are given and the description is appropriately omitted, and the description will be centered on the characteristic parts of the semiconductor device S3 of the third embodiment.

[0153] A base layer 14B is provided on the first main surface side within the drift layer 50. The base layer 14B is of p-type. The base layer 14B is provided in a manner extending from the auxiliary region 92 to the main region 91. The base layer 14B is provided such that the formation depth of the region from the transistor region 96 to a part of the resistance region 95B is deeper than the formation depths of the sensing region 93 and the main region 91.

[0154] In the transistor region 96, a drain region 61 and a source-drain region 62 are selectively provided on the first main surface side within the base layer 14B. The drain region 61 and the source-drain region 62 are of n-type with a relatively high n-type impurity concentration. + type. A gate electrode 67 is provided over the first main surface of the base layer 14B between the drain region 61 and the source-drain region 62 with a gate insulating film 66 interposed therebetween.

[0155] In the transistor region 96B, a source-drain region 62 and a source region 63 are selectively provided on the first main surface side within the base layer 14B. The source region 63 is of n-type with a relatively high n-type impurity concentration. + type. A gate electrode 77 is provided over the first main surface of the base layer 14B between the source-drain region 62 and the source region 63 with a gate insulating film 76 interposed therebetween.

[0156] The first MOSFET, i.e., an n-type MOSFET 3, is constituted mainly by the base layer 14B, the drain region 61, the source-drain region 62, the gate insulating film 66, and the gate electrode 67. The source-drain region 62 functions as the source region of the MOSFET 3.

[0157] The second MOSFET, i.e., the n-channel MOSFET 7, is formed with the base layer 14B, source-drain region 62, source region 63, gate insulating film 76, and gate electrode 77 as main structural elements. The source-drain region 62 functions as the drain region of the MOSFET 7.

[0158] In the diode region 94C, on the first main surface side within the base layer 14B, a p-type anode region 33 and an n-type cathode region 34 are provided adjacent to each other.

[0159] The third diode, i.e., the diode 8, is formed with the anode region 33 and the cathode region 34 as main structural elements.

[0160] In the diode region 94, on the first main surface side within the base layer 14B, a p-type anode region 35 and an n-type cathode region 36 are provided adjacent to each other.

[0161] The first diode, i.e., the diode 1, is formed with the anode region 35 and the cathode region 36 as main structural elements.

[0162] In the sensing regions 93 of the main region 91 and the auxiliary region 92 of the semiconductor device S3, sensing IGBTs 4 and main IGBTs 5 are provided in the same manner as in the semiconductor devices S1 and S2. However, the semiconductor device S3 of the third embodiment is different from the semiconductor devices S1 and S2 in that the base layer 14 is replaced with the base layer 14B.

[0163] In the transistor region 96, an interlayer insulating film 21 is provided so as to cover the gate electrode 67. In the transistor region 96B, an interlayer insulating film 21 is provided so as to cover the gate electrode 77.

[0164] In the diode region 94C, an interlayer insulating film 21 is provided on the first main surface of the anode region 33 and the cathode region 34. In the diode region 94, an interlayer insulating film 21 is provided on the first main surface of the anode region 35 and the cathode region 36.

[0165] In the resistor region 95B, an interlayer insulating film 21 is provided on the first main surface of the base layer 14B.

[0166] In the resistor region 95B, a conductive polysilicon layer 65 is provided on the interlayer insulating film 21. The polysilicon layer 65 functions as the resistor 9.

[0167] Moreover, a drain electrode 51, a source-drain electrode 52, a source-anode electrode 53, a cathode-anode electrode 54, a cathode electrode 55, an emitter electrode 60, and an emitter electrode 20 are provided on the first main surface of the semiconductor substrate 100.

[0168] The drain electrode 51 is disposed over a part of the drain region 61, and the source-drain electrode 52 is disposed over a part of the source-drain region 62. Accordingly, the drain electrode 51 is electrically connected to the drain region 61, and the source-drain electrode 52 is electrically connected to the source-drain region 62.

[0169] The source-anode electrode 53 is disposed in such a manner as to extend from a part of the source region 63 to a part of the base layer 14B and a part of the anode region 33. Accordingly, the source-anode electrode 53 is electrically connected to the source region 63 and the anode region 33.

[0170] The cathode-anode electrode 54 is disposed in such a manner as to extend from a part of the cathode region 34 to a part of the base layer 14B and a part of the anode region 35. Accordingly, the cathode-anode electrode 54 is electrically connected to the cathode region 34 and the anode region 35.

[0171] The cathode electrode 55 is disposed in such a manner as to extend from a part of the cathode region 36 to a part of the base layer 14B and over one end portion of the polysilicon layer 65. Accordingly, the cathode electrode 55 is electrically connected to the cathode region 36 and the polysilicon layer 65.

[0172] The emitter electrode 60 is disposed in such a manner as to extend from the other end portion of the polysilicon layer 65 to the entire region of the sensing region 93. Accordingly, the emitter electrode 60 is electrically connected to the polysilicon layer 65, the n + source region 15 and the p + diffusion region 16 at the sensing region 93.

[0173] The emitter electrode 20 is disposed over the entire region of the main region 91. Accordingly, the emitter electrode 20 is electrically connected to the n + source region 15 and the p + diffusion region 16 at the main region 91.

[0174] As Figure 7 shown, the semiconductor device S3 has an electrical connection relationship represented by the electrical connection line EL among the drain electrode 51, the gate electrode 67, the source-drain electrode 52, the gate electrode 77, the cathode-anode electrode 54, the cathode electrode 55, the emitter electrode 60, the emitter electrode 20, the gate electrode 19 of the sensing region 93, and the gate electrode 19 of the main region 91. Further, each of the above electrodes is made of, for example, aluminum as a constituent material.

[0175] As Figure 7 shown, the drain electrode 51 and the gate electrode 19 of the sensing region 93 are electrically connected, the gate electrode 67 and the emitter electrode 60 are electrically connected, and the source-drain electrode 52 and the gate electrode 19 of the main region 91 are electrically connected.

[0176] In addition, the gate electrode 77 and the cathode electrode 55 are electrically connected, and the cathode-anode electrode 54 and the emitter electrode 20 are electrically connected.

[0177] As Figure 8 shown, a part of the emitter electrode 20 extends over the diode region 94 and the diode region 94C, thereby also serving as Figure 7 the function of the cathode-anode electrode 54 shown. That is, the emitter electrode 20 and the cathode-anode electrode 54 are integrally provided.

[0178] In addition, most of the gate lead-out portion 71 is provided along the outer periphery of the emitter electrode 20, and a part is provided to extend over between the transistor region 96 and the transistor region 96B, thereby also acting as Figure 7 the source-drain electrode 52 shown. In addition, the gate lead-out portion 71 is also electrically connected to the plurality of gate electrodes 19 in the main region 91.

[0179] Moreover, the gate pad 72 is formed such that a part extends over the transistor region 96, thereby also acting as Figure 7 the drain electrode 51 shown.

[0180] In addition, as Figure 8 shown, by providing a wiring layer 81 between the sensing region 93 and the gate pad 72, the gate pad 72 is electrically connected to the gate electrode 19 in the sensing region 93 via the wiring layer 81.

[0181] Moreover, a wiring layer 82 is provided between the emitter electrode 60 and the transistor region 96. Therefore, the emitter electrode 60 in the sensing region 93 is electrically connected to the gate electrode 67 in the transistor region 96 via the wiring layer 82.

[0182] In addition, a wiring layer 83 is provided between the cathode electrode 55 and the transistor region 96B. Therefore, the cathode electrode 55 is electrically connected to the gate electrode 77 in the transistor region 96B via the wiring layer 83.

[0183] The diode 1 and the diode 6 of the semiconductor device S3 can be manufactured by the same manufacturing method as the diode 1 of the semiconductor device S1. The MOSFET 3 and the MOSFET 7 of the semiconductor device S3 can be manufactured by the same manufacturing method as the MOSFET 3 of the semiconductor device S1. The resistor 9 of the semiconductor device S3 can be manufactured by the same manufacturing method as the resistor 2 of the semiconductor device S1.

[0184] Thus, in the semiconductor device S3 of Embodiment 3, the main IGBT 5, the sensing IGBT 4, the MOSFET 3, the diode 1, the MOSFET 7, the diode 8, and the resistor 9, which are structural elements, are integrally provided on a single semiconductor substrate 100. Therefore, the semiconductor device S3 can achieve miniaturization of the device.

[0185] Figure 9 represents Figure 7 and Figure 8 The circuit diagram showing the circuit structure of the semiconductor device S3 shown in. Hereinafter, the same reference numerals are given to the same structures as those of the semiconductor device S1, and the description will be appropriately omitted. Refer to Figure 9 The circuit structure of the semiconductor device S3 will be described.

[0186] The semiconductor device S3 includes, as main structural elements, a first power switch element, i.e., the main IGBT 5, a second power switch element, i.e., the sensing IGBT 4, a first MOSFET, i.e., an n-type MOSFET 3, a first diode, i.e., the diode 1, a second MOSFET, i.e., an n-type MOSFET 7, and a third diode, i.e., the diode 8.

[0187] Hereinafter, regarding the semiconductor device S3 of Embodiment 3, Figure 7 and Figure 9 The correspondence between the electrodes of the device structure shown in and Figure 9 The circuit structure shown in will be described.

[0188] Regarding the MOSFET 3, the drain corresponds to the drain electrode 51, the gate corresponds to the gate electrode 67, and the source corresponds to the source-drain electrode 52.

[0189] The MOSFET 7 has a drain as one electrode, a source as the other electrode, and a gate as the control electrode. Regarding the MOSFET 7, the drain corresponds to the source-drain electrode 52, the gate corresponds to the gate electrode 77, and the source corresponds to the source-anode electrode 53.

[0190] Regarding the diode 1, the anode corresponds to the cathode-anode electrode 54, and the cathode corresponds to the cathode electrode 55. Regarding the diode 8, the anode corresponds to the source-anode electrode 53, and the cathode corresponds to the cathode-anode electrode 54.

[0191] As Figure 9 shown, the drain of the second MOSFET, i.e., the MOSFET 7, is connected to the gate of the main IGBT 5.

[0192] The anode of the third diode, i.e., the diode 8, is connected to the source of the MOSFET 7, and the cathode of the diode 8 is connected to the emitter of the main IGBT 5 and the anode of the diode 1.

[0193] One end of the second resistor, i.e., resistor 9, is connected to the emitter of the sensing IGBT 4 and the gate of the MOSFET 3, and the other end of resistor 9 is connected to the gate of the MOSFET 7 and the cathode of the diode 1. In this way, the cathode of the first diode, i.e., diode 1, is arranged in the direction of the emitter of the sensing IGBT 4.

[0194] The diode 8 is provided for the purpose of suppressing the reverse current flowing from the emitter to the gate of the main IGBT 5 through the parasitic diode of the MOSFET 7.

[0195] In the semiconductor device S3, the charge release circuit C3 is composed of the above-mentioned MOSFET 7, diode 8 and resistor 9. Moreover, the MOSFET 7 and the diode 8 are charge release paths arranged from the gate to the emitter of the main IGBT 5. The above-mentioned charge release path becomes conductive when the MOSFET 7 is in the on state, and can release the charge accumulated in the gate of the main IGBT 5 via the above-mentioned charge release path.

[0196] (Overcurrent state)

[0197] In the semiconductor device S3 of the third embodiment, when an overcurrent flows through the first power switching element, i.e., the main IGBT 5, the main gate voltage VM, which is the first control voltage applied to the gate of the main IGBT 5, becomes higher.

[0198] Therefore, when an overcurrent flows through the main IGBT 5, it acts in the direction of reducing the potential difference between the gate and the source of the first MOSFET, i.e., MOSFET 3, and the on state of the MOSFET 3 becomes weaker. In addition, the MOSFET 3 may become in the off state.

[0199] At the same time, since an overcurrent also flows through the sensing IGBT 4, the gate potential of the second MOSFET, i.e., MOSFET 7, exceeds the threshold voltage and becomes in the on state. Therefore, when an overcurrent flows through the main IGBT 5, a conductive charge release path is formed through the on-state MOSFET 7 and diode 8.

[0200] Therefore, along with the weakening of the on state of the MOSFET 3, the excess charge accumulated in the gate of the main IGBT 5 is released to the outside on the emitter side of the main IGBT 5 via the above-mentioned charge release path in the charge release circuit C3.

[0201] As a result, the semiconductor device S3 of the third embodiment can reduce the amount of current flowing through the main IGBT 5 by rapidly reducing the main gate voltage VM in the overcurrent state.

[0202] (At cut-off operation)

[0203] The semiconductor device S3 of Embodiment 3 includes a charge release circuit C3 including a MOSFET 7, a diode 8, and a resistor 9.

[0204] In the state just before cutoff, both the sensing IGBT 4 and the main IGBT 5 are in the on state. Therefore, the source potential of the MOSFET 3 becomes a relatively high potential of "H" level through the main gate voltage VM. On the other hand, the source potential of the MOSFET 7 is close to the common potential of "L" level and is a relatively low potential.

[0205] Therefore, by appropriately setting the resistance value of the resistor 9, during the cutoff period, even if the MOSFET 3 becomes off, the MOSFET 7 can be designed to be on. That is, by appropriately setting the resistance value of the resistor 9, a charge release path composed of the on-state MOSFET 7 and the diode 8 can be formed during the cutoff operation.

[0206] Therefore, when the gate voltage VG is made less than or equal to 0V to turn off the main IGBT 5 in the on state of the main IGBT 5, it can be quickly released to the outside of the emitter side of the main IGBT 5 via the above charge release path in the charge release circuit C3.

[0207] That is, a charge release path for releasing the charge applied to the gate of the main IGBT 5 during cutoff can be ensured by the MOSFET 7 and the diode 8 of the charge release circuit C3.

[0208] In this way, the semiconductor device S3 of Embodiment 3 can achieve high-speed cutoff operation through the charge release circuit C3.

[0209] (When applying a negative gate voltage VG)

[0210] Next, consider the case where a negative gate voltage VG is applied as the drive voltage given from the gate driver 12.

[0211] Imagine the following phenomenon: when a negative gate voltage VG is applied, even if the MOSFET 3 and the MOSFET 7 are in the off state, a reverse current flows from the emitter of the main IGBT 5 to the gate driver 12 via the parasitic diode in the MOSFET 3 and the parasitic diode in the MOSFET 7.

[0212] In the semiconductor device S3, a second MOSFET, i.e., the MOSFET 7, and a third diode, i.e., the diode 8, are provided between the source of the MOSFET 3 and the emitter of the main IGBT 5.

[0213] As described above, the charge release circuit C3 of the semiconductor device S3 has a charge release path formed by the MOSFET 7 and the diode 8 from the gate to the emitter of the main IGBT 5. That is, the above charge release path exists between the source of the MOSFET 3 and the emitter of the main IGBT 5.

[0214] Therefore, in the semiconductor device S3 of the third embodiment, when the gate voltage VG becomes negative, the current path of the reverse current flowing from the emitter of the main IGBT 5 to the gate driver 12 is the diode 8, the MOSFET 7, the MOSFET 3, and the gate resistor 11.

[0215] As a result, the semiconductor device S3 of the third embodiment can limit the reverse current by the leakage current of the diode 8, that is, can suppress the amount of the reverse current to a minute leakage current amount flowing through the diode 8, and thus can effectively suppress the reverse current.

[0216] <Others>

[0217] In the above embodiment, an n-channel IGBT is shown as the n-channel power switching element, but it can be applied to other power switching elements such as an n-channel power MOSFET.

[0218] In the above embodiment, the sensing IGBT 4 and the main IGBT 5 having the trench gate electrode 19 are shown, but it is not limited to this configuration. For example, the sensing IGBT 4 and the main IGBT 5 having a planar gate electrode can also be configured.

[0219] In the above embodiment, the planar MOSFETs 3 and 7 are shown, but it is not limited to this configuration. For example, the MOSFETs 3 and 7 having a trench gate electrode can also be configured.

[0220] In addition, the configurations of the resistors 2 and 9 and the diodes 1, 6, and 8 are of course not limited to the configurations shown in the first to third embodiments.

[0221] Furthermore, the present invention can freely combine the respective embodiments within the scope of its invention, and appropriately deform and omit the respective embodiments.

[0222] Description of reference numerals

[0223] 1, 6, 8 Diodes, 2, 9 Resistors, 3, 7 MOSFETs, 4 Sensing IGBT, 5 Main IGBT, 11 Gate resistor, 12 Gate driver, 91 Main region, 92 Auxiliary region, 93 Sensing region, 94, 94B, 94C Diode regions, 95, 95B Resistor regions, 96, 96B Transistor regions, C3 Charge release circuit.

Claims

1. A semiconductor device having: A first power switching element of n-channel type, having one electrode, another electrode, and a control electrode; A second power switching element of n-channel type, having one electrode, another electrode, and a control electrode, and one electrode of the second power switching element is connected to one electrode of the first power switching element; A first diode, having an anode connected to the other electrode of the first power switching element, and a cathode disposed in the direction of the other electrode of the second power switching element; A first n-channel MOSFET, having one electrode, another electrode, and a control electrode, one electrode of the first MOSFET receives the driving voltage for the first and second power switching elements, one electrode of the first MOSFET is connected to the control electrode of the second power switching element, another electrode is connected to the control electrode of the first power switching element, and the control electrode is connected to the other electrode of the second power switching element; And A charge release circuit having a charge release path provided from the control electrode to the other electrode of the first power switching element.

2. The semiconductor device according to claim 1, wherein The cathode of the first diode is connected to the other electrode of the second power switching element, The charge release circuit is a first resistor having one end connected to the control electrode of the first power switching element and the other end connected to the other electrode of the first power switching element.

3. The semiconductor device according to claim 2, wherein It further has a second diode, having an anode connected to the other electrode of the first MOSFET and a cathode connected to one electrode of the first MOSFET.

4. The semiconductor device according to claim 1, wherein The charge release circuit includes: A second n-channel MOSFET, having one electrode, another electrode, and a control electrode, one electrode of the second MOSFET is connected to the control electrode of the first power switching element, and the control electrode is connected to the cathode of the first diode; A third diode, having an anode connected to the other electrode of the second MOSFET and a cathode connected to the other electrode of the first power switching element; And A second resistor, having one end connected to the other electrode of the second power switching element and the control electrode of the first MOSFET, and the other end connected to the control electrode of the second MOSFET and the cathode of the first diode.

5. The semiconductor device according to any one of claims 1 to 4, wherein The first and second power switching elements, the first diode, the first MOSFET, and the charge release circuit are integrally provided on one semiconductor substrate.

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