Chip frequency modulation methods, devices, computing boards, computing devices, and storage media for computing devices.

Abstract

This invention provides a chip frequency adjustment method, apparatus, computing board, computing device, and storage medium for a computing device. The method includes: setting multiple operating frequencies for the computing chip of the computing device; operating multiple cores of the computing chip at each operating frequency; analyzing whether each calculation by a core at its current operating frequency is correct; increasing the correct calculation weight value by one for each correct calculation and decreasing the incorrect calculation weight value by one for each incorrect calculation; increasing the current operating frequency of the core if its current value reaches a correct calculation threshold; and decreasing the current operating frequency of the core if its current value reaches a calculation error threshold. Therefore, this invention can automatically adjust the frequency of each core according to its actual computing performance, thereby maximizing the computing performance of the cores and improving the computing performance of the computing chip and the overall computing device.

Description

[0001] This application is a divisional application. The original application was filed on June 6, 2018; the original application number was 201810576572.2; and the original invention was entitled: Chip Frequency Modulation Method, Apparatus, Computing Board, Computing Device, and Storage Medium for Computing Devices. Technical Field

[0002] This invention relates to the field of chip frequency modulation technology for computing devices, and more particularly to a chip frequency modulation method, apparatus, computing board, computing device, and storage medium for computing devices. Background Technology

[0003] Computing devices used for massive data processing typically integrate a large number of computing chips. Due to limitations in chip manufacturing processes, the performance, computing power, and frequency of different chips vary. Furthermore, a single computing chip usually consists of multiple independent cores, and variations in process variations and voltage drops at different locations within the chip also result in different actual performance characteristics for each core. Therefore, dynamically adjusting the actual required frequency of the computing chips and setting adaptive schemes for each core to address these performance differences is a pressing issue. Currently, computing devices provide a uniform frequency for each computing chip and its cores, which fails to leverage the computational advantages of higher-performing cores, while weaker cores negatively impact the overall computing performance of the device.

[0004] Furthermore, Chinese patent application CN201611169618.6 discloses a series power supply chip and system, including an adjustment circuit connected to each series power supply chip to adjust the voltage, temperature, or frequency of each chip. When adjusting the frequency of each series power supply chip, the adjustment unit checks the operating status of each power supply unit within the chip at a preset cycle. If any power supply unit is not operating normally, its operating frequency is increased or decreased within a preset frequency range by a preset frequency step. The system determines whether the operating status of the power supply unit is normal based on the status register indicating the voltage, temperature, or operating frequency; or it determines the operating status of the power supply unit based on feedback data from the power supply unit to the data sent to it.

[0005] In one embodiment disclosed in Chinese patent application CN201611169618.6, when the adjustment circuit adjusts the frequency of each series-connected power supply chip, the frequency adjustment circuit specifically uses a detector to detect whether the working state of each power supply unit in the series-connected power supply chip is normal according to a preset cycle. If the working state of any power supply unit is abnormal, a regulator can be used to increase or decrease the working frequency of the abnormal power supply unit within a preset frequency range according to a preset frequency step size. It can be seen that CN201611169618.6 discloses that the regulator can adjust the chip frequency, but it only adjusts the chip's working frequency based on the working state of the power supply unit, such as whether it is transmitting and receiving data normally, voltage status, temperature status, and frequency status. The frequency adjustment mechanism lacks accuracy and cannot fully utilize the chip's computing performance.

[0006] In conclusion, the existing technology obviously has inconveniences and defects in practical use, so it is necessary to improve it. Summary of the Invention

[0007] To address the aforementioned shortcomings, the present invention aims to provide a chip frequency tuning method, apparatus, computing board, computing device, and storage medium for a computing device. This method can automatically adjust the frequency of each core according to its actual computing performance, thereby maximizing the computing performance of the cores and improving the computing performance of the computing chip and the overall computing device.

[0008] This invention provides a chip frequency modulation method for a computing device, wherein the computing device is provided with at least one computing chip, and the computing chip is provided with multiple cores, characterized by comprising the following steps:

[0009] The frequency setting step involves setting multiple operating frequency points for the computing chip of the computing device.

[0010] The computational performance analysis steps analyze whether each calculation of the kernel at the current operating frequency is correct. For each correct calculation by the kernel, a predetermined correct calculation weight value is increased by one, and for each incorrect calculation by the kernel, a predetermined incorrect calculation weight value is decreased by one.

[0011] In the frequency adjustment step, if the current value of the kernel reaches a predetermined correct calculation threshold, the current operating frequency of the kernel is increased; or, if the current value of the kernel reaches a predetermined incorrect calculation threshold, the current operating frequency of the kernel is decreased.

[0012] The above-described chip frequency modulation method, wherein the frequency point setting step further includes:

[0013] Multiple operating frequencies are set for the computing chip through multiple phase-locked loop circuits, and the operating frequencies are in a one-to-one correspondence with the phase-locked loop circuits.

[0014] The frequency adjustment step further includes:

[0015] The current operating frequency of the core is adjusted up or down through the phase-locked loop circuit.

[0016] In the above-described chip frequency modulation method, the phase-locked loop circuit is located inside or outside the computing chip.

[0017] In the above-described chip frequency modulation method, the frequency difference between adjacent operating frequency points is 1~10%.

[0018] In the above-described chip frequency modulation method, if the core operating at at least one or more of the predetermined optimized operating frequencies exceeds a predetermined first ratio, frequency modulation of the core is stopped.

[0019] In the above-described chip frequency tuning method, if the number of cores operating at at least one or more predetermined optimized operating frequencies is the maximum, frequency tuning of the cores is stopped.

[0020] In the above-described chip frequency tuning method, the multiple cores in the computing chip operate at their respective operating frequencies, and the number of the multiple operating frequencies and the frequency differences between them are adjustable.

[0021] In the above-described chip frequency modulation method, multiple cores are distributed evenly, unevenly, or randomly at the operating frequency point according to predetermined rules.

[0022] The above-described chip frequency modulation method further includes the following step:

[0023] If the current value of the kernel reaches the calculated correct threshold, the current operating frequency of the kernel is increased to the previous operating frequency.

[0024] If the current value of the kernel reaches the calculation error threshold, the current operating frequency of the kernel will be lowered to the next operating frequency.

[0025] The aforementioned chip frequency modulation method, wherein the computational performance analysis step further includes:

[0026] Based on preset real-time adjustment instructions, it is determined in real time whether the current value of the kernel has reached the correct calculation threshold or the incorrect calculation threshold;

[0027] The frequency adjustment step further includes:

[0028] According to the preset real-time adjustment instructions, if the current value of the kernel reaches the calculated correct threshold, the current operating frequency of the kernel is increased in real time; if the current value of the kernel reaches the calculated incorrect threshold, the current operating frequency of the kernel is decreased in real time.

[0029] The aforementioned chip frequency modulation method, wherein the computational performance analysis step further includes:

[0030] According to the preset timed adjustment instruction, within the adjustment time period set by the timed adjustment instruction, it is determined whether the current value of the kernel has reached the calculation correct threshold or the calculation error threshold.

[0031] The frequency adjustment step further includes:

[0032] According to the preset timed adjustment instruction, if the current value of the kernel reaches the calculation correctness threshold within the adjustment period, the current operating frequency of the kernel is increased; if the current value of the kernel reaches the calculation error threshold within the adjustment period, the current operating frequency of the kernel is decreased.

[0033] The aforementioned chip frequency modulation method, wherein the computational performance analysis step further includes:

[0034] Based on the received real-time adjustment instructions, analyze whether the current value of the kernel has reached the correct calculation threshold or the incorrect calculation threshold;

[0035] The frequency adjustment step further includes:

[0036] According to the received real-time adjustment instruction, if the current value of the kernel reaches the calculation correct threshold, the current operating frequency of the kernel is increased; if the current value of the kernel reaches the calculation error threshold, the current operating frequency of the kernel is decreased; according to the received stop adjustment instruction, the adjustment of the current operating frequency of the kernel is stopped.

[0037] The aforementioned chip frequency modulation method further includes a reference node value, and the computational performance analysis step further includes:

[0038] Analyze whether the kernel's calculations at the current operating frequency are correct. For each correct calculation by the kernel, add the correct weight value to the reference node value.

[0039] The aforementioned chip frequency modulation method, wherein the computational performance analysis step further includes:

[0040] Analyze whether the kernel's calculations at the current operating frequency are correct. If the kernel makes a calculation error at least once, reduce the error weight value of the calculation by one point on the reference node value.

[0041] The aforementioned chip frequency modulation method further includes:

[0042] Determine whether the current reference node value of the kernel has reached the correct calculation threshold or the incorrect calculation threshold;

[0043] The frequency adjustment step further includes:

[0044] If the current reference node value of the kernel reaches the calculated correct threshold, the current operating frequency of the kernel will be increased.

[0045] If the current reference node value of the kernel reaches the calculation error threshold, the current operating frequency of the kernel will be lowered.

[0046] The aforementioned chip frequency modulation method further includes:

[0047] The kernel's expected tolerance for resident error rate is controlled by adjusting the ratio of the correctly calculated weight value to the incorrectly calculated weight value.

[0048] The aforementioned chip frequency modulation method further includes:

[0049] The adjustment period is controlled by adjusting the absolute values ​​of the correctly calculated weight value and the incorrectly calculated weight value.

[0050] The aforementioned chip frequency modulation method further includes:

[0051] The adjustment period is controlled by adjusting the absolute values ​​of the correct calculation threshold and the incorrect calculation threshold.

[0052] In the above-mentioned chip frequency modulation method, the formula for calculating the dwell error rate is: Dwell error rate = calculated correct weight value / (calculated correct weight value + calculated incorrect weight value).

[0053] The above-described chip frequency tuning method, wherein the step of analyzing whether the core's calculation at the current operating frequency is correct in each step further includes:

[0054] Analyze whether the random numbers submitted by the kernel each time are correct;

[0055] For each correct random number submitted by the kernel, the calculated correct weight value is increased by one to the current value; for each incorrect random number submitted by the kernel, the calculated incorrect weight value is decreased by one to the current value.

[0056] The above-described chip frequency tuning method, wherein the step of analyzing whether the random number submitted by the kernel each time is correct further includes:

[0057] After the kernel submits a random number, the kernel calculates a first result from the random number using a predetermined algorithm, and the first result contains a first feature;

[0058] The verification unit of the computing chip calculates a second result from the random number using the same algorithm, and the second result contains a second feature;

[0059] If the first feature is the same as the second feature, the verification unit determines that the random number is a correct random number; otherwise, it determines that the random number is an incorrect random number.

[0060] In the above-described chip frequency modulation method, the random number submitted by the kernel each time is a Nonce;

[0061] The kernel calculates a first hash result from the Nonce embedded block header, and the first hash result contains a first feature;

[0062] The verification unit calculates a second hash result from the Nonce embedded block header, and the second hash result contains a second feature.

[0063] The present invention also provides a chip frequency modulation device for a computing device, based on the chip frequency modulation method described in any one of the above claims, wherein the computing device is provided with at least one arithmetic chip, and the arithmetic chip is provided with multiple cores, characterized in that the chip frequency modulation device comprises:

[0064] A frequency setting module is used to set multiple operating frequency points for the computing chip of the computing device;

[0065] The computational performance analysis module is used to analyze whether each calculation of the kernel at the current operating frequency is correct. For each correct calculation by the kernel, a predetermined calculation correctness weight value is increased by one, and for each incorrect calculation by the kernel, a predetermined calculation error weight value is decreased by one.

[0066] The frequency adjustment module is used to increase the current operating frequency of the kernel if the current value of the kernel reaches a predetermined calculation correctness threshold; or to decrease the current operating frequency of the kernel if the current value of the kernel reaches a predetermined calculation error threshold.

[0067] In the aforementioned chip frequency tuning device, the frequency setting module is used to set multiple operating frequencies for the computing chip through multiple phase-locked loop circuits, wherein the operating frequencies and the phase-locked loop circuits have a one-to-one correspondence.

[0068] The frequency adjustment module is used to adjust the current operating frequency of the core upward or downward through the phase-locked loop circuit.

[0069] In the aforementioned chip frequency modulation device, the phase-locked loop circuit is located inside or outside the computing chip.

[0070] In the aforementioned chip frequency modulation device, the frequency difference between adjacent operating frequency points is 1~10%.

[0071] The aforementioned chip frequency modulation device, wherein the frequency adjustment module further includes:

[0072] The frequency adjustment submodule is used to adjust the current operating frequency of the kernel upwards or downwards.

[0073] In the aforementioned chip frequency modulation device, the computing performance analysis module executes one of the following instructions: real-time adjustment instruction, timed adjustment instruction, and instant adjustment instruction.

[0074] The aforementioned chip frequency modulation device, wherein the computing performance analysis module further includes:

[0075] The analysis submodule is used to analyze whether the kernel's calculations at the current operating frequency are correct.

[0076] A counting submodule is configured to increment the correct calculation weight value by one to the reference node value for each correct calculation by the kernel at least once, and decrement the incorrect calculation weight value by one to the reference node value for each incorrect calculation by the kernel at least once.

[0077] The judgment submodule is used to determine whether the current reference node value of the kernel has reached the correct calculation threshold or the incorrect calculation threshold;

[0078] The frequency adjustment module is used to increase the current operating frequency of the kernel if the current reference node value of the kernel reaches the calculation correct threshold; and to decrease the current operating frequency of the kernel if the current reference node value of the kernel reaches the calculation error threshold.

[0079] In the aforementioned chip frequency modulation device, the analysis submodule is used to analyze whether the random numbers submitted by the kernel each time are correct;

[0080] The counting submodule is used to increment the calculated correct weight value by one for each correct random number submitted by the kernel, and to decrement the calculated incorrect weight value by one for each incorrect random number submitted by the kernel.

[0081] The present invention also provides a computing board including any of the above-described chip frequency modulation devices.

[0082] The present invention also provides a computing device including any one of the chip frequency modulation devices described above.

[0083] The present invention also provides a storage medium for storing a computer program for a chip frequency modulation method for any of the above-described computing devices.

[0084] This invention automatically adjusts the frequency of the cores in a computing chip. First, multiple suitable operating frequencies are set, and the cores in the computing chip operate at different frequencies. Then, for each correct calculation by a core, a predetermined correct calculation weight value is increased; for each incorrect calculation by a core, a predetermined incorrect calculation weight value is decreased. If a predetermined correct calculation threshold is reached, the current operating frequency is increased, i.e., the frequency of the core with higher computing performance is increased; if a predetermined incorrect calculation threshold is reached, the current operating frequency is decreased, i.e., the frequency of the core with lower computing performance is decreased. In this way, this invention can automatically adjust the frequency of each core according to its actual computing performance in the computing chip, thereby maximizing the computing performance of the cores and improving the computing performance of the computing chip and the overall computing device. Attached Figure Description

[0085] Figure 1 This is a schematic diagram of the chip frequency modulation device of the computing device of the present invention;

[0086] Figure 2 This is a schematic diagram of the chip frequency modulation device of a computing device in one embodiment of the present invention;

[0087] Figure 3 This is a schematic diagram of the chip frequency modulation device of a computing device in another embodiment of the present invention;

[0088] Figure 4 This is a flowchart of the chip frequency modulation method for the computing device of the present invention;

[0089] Figure 5 This is a flowchart of a chip frequency modulation method for a computing device in another embodiment of the present invention;

[0090] Figure 6 This is a flowchart of a chip frequency modulation method for a computing device in another embodiment of the present invention;

[0091] Figure 7 This is a schematic diagram of the structure of the computing device of the present invention.

[0092] Figure label:

[0093] 100-Chip frequency modulation device for computing equipment

[0094] 10-Frequency Setting Module

[0095] 20-Computational Performance Analysis Module

[0096] 21-Analysis Submodule

[0097] 211-Calculation Unit 212-Verification Unit

[0098] 22-Settings Submodule 23-Counting Submodule

[0099] 24-Judgment Submodule

[0100] 30-Frequency Adjustment Module

[0101] 31-Frequency Adjustment Submodule 32-Stop Frequency Adjustment Submodule

[0102] 40-Phase-Locked Loop Circuit 50-Core Detailed Implementation

[0103] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0104] It should be noted that references to "an embodiment," "embodiment," "example embodiment," etc., in this specification refer to the described embodiment including specific features, structures, or characteristics, but not every embodiment must include these specific features, structures, or characteristics. Furthermore, such expressions do not refer to the same embodiment. Moreover, when describing specific features, structures, or characteristics in conjunction with embodiments, whether or not explicitly described, it is indicated that incorporating such features, structures, or characteristics into other embodiments is within the knowledge of those skilled in the art.

[0105] Furthermore, certain terms are used in the specification and subsequent claims to refer to specific components or parts. Those skilled in the art will understand that manufacturers may use different names or terms to refer to the same component or part. This specification and subsequent claims do not distinguish components or parts by differences in name, but rather by differences in function. The terms "comprising" and "including" used throughout the specification and subsequent claims are open-ended and should be interpreted as "including but not limited to." Additionally, the term "connection" here includes any direct and indirect electrical connection means. Indirect electrical connection means include connections made through other means.

[0106] Figure 1 This is a schematic diagram of the chip frequency modulation device of the computing device of the present invention. The computing device is preferably used for massive computing. The computing device is provided with at least one computing chip, and the computing chip is provided with multiple cores 50. The computing device preferably includes a control board and a computing board connected to the control board. The computing board is provided with at least one computing chip, and the computing chip is provided with multiple cores 50. Of course, the computing device may also include a heat sink, a connection board, a power module, etc.

[0107] It should be noted that the chip frequency adjustment technology of this invention actually involves two levels of frequency adjustment mechanisms: a frequency adjustment mechanism for the computing chip and a frequency adjustment mechanism at the core level. The frequency adjustment mechanism for the computing chip refers to setting several suitable operating frequencies for each computing chip and allowing each core 50 of the computing chip to operate at each of these operating frequencies, thereby fully utilizing the performance of each core 50. The frequency adjustment mechanism at the core level refers to adjusting the core 50 to a suitable operating frequency based on its actual computing performance, increasing the frequency of cores 50 with high computing performance and decreasing the frequency of cores 50 with low computing performance, thereby fully utilizing the computing performance of each core 50.

[0108] The chip frequency modulation device 100 includes at least a frequency setting module 10, a performance analysis module 20, and a frequency adjustment module 30, wherein:

[0109] The frequency setting module 10 is used to set multiple working frequency points for the computing chip of the computing device. Each working frequency point has a different frequency, and the multiple cores 50 in the computing chip work at each working frequency point respectively.

[0110] According to the frequency adjustment mechanism of the computing chip, several different frequency points are set for each computing chip, and each core 50 of the computing chip operates at each of these operating frequencies. For example, six operating frequencies are set: 500MHz, 550MHz, 600MHz, 650MHz, 700MHz, and 750MHz. The number of operating frequencies and the frequency differences between them can be set according to actual needs; the more operating frequencies, the more fully the computing performance of each core 50 can be utilized. When the frequency adjustment switch is activated (before the core 50 is frequency-adjusted), the cores 50 can be evenly, unevenly, or randomly distributed across the operating frequencies according to predetermined rules. Preferably, the frequency setting module 10 can, as shown in the example... Figure 2 The multiple phase-locked loop (PPL) circuits 40 shown provide multiple operating frequencies for the computing chip. Of course, the frequency setting module 10 can also set multiple operating frequencies for the computing chip through other hardware or software.

[0111] It is worth noting that the frequency difference between operating frequencies in this invention needs to be controlled within a reasonable range. When the core 50 increases its operating frequency by one frequency point, its operating frequency will increase by one frequency difference value, which can improve its computing performance due to the increased computational speed. At the same time, increasing the core's operating frequency may result in a decrease in computational accuracy, thus sacrificing some computing performance. Therefore, the frequency setting module 10 should reasonably control the frequency difference between adjacent operating frequencies so that when the core 50 adjusts from its current operating frequency to the previous operating frequency, the benefit to the core 50's computing performance should outweigh the loss. Preferably, the frequency difference between adjacent operating frequencies is 1% to 10%.

[0112] The computational performance analysis module 20 is used to analyze whether each calculation of the kernel 50 at the current operating frequency is correct. For each correct calculation by the kernel 50, a predetermined correct calculation weight value is increased; for each incorrect calculation by the kernel 50, a predetermined incorrect calculation weight value is decreased. If the current value of the kernel 50 reaches the predetermined correct calculation threshold, it indicates that the computational performance of the kernel 50 is high, and the computational performance of the kernel 50 may have room for improvement. If the current value of the kernel 50 reaches the predetermined incorrect calculation threshold, it indicates that the computational performance of the kernel 50 is low, and the computational performance of the kernel 50 may be insufficient to operate at the frequency corresponding to the current operating frequency.

[0113] The frequency adjustment module 30 is used to increase the current operating frequency of kernel 50 if the current value of kernel 50 reaches a predetermined calculation correctness threshold; or, to decrease the current operating frequency of kernel 50 if the current value of kernel 50 reaches a predetermined calculation error threshold. That is, according to the kernel-level frequency adjustment mechanism, kernel 50 is adjusted to a suitable operating frequency based on its actual computing performance, increasing the frequency of kernels with high computing performance and decreasing the frequency of kernels with low computing performance, thereby fully utilizing the computing performance of each kernel 50.

[0114] The chip frequency tuning device 100 of this invention can be located inside or outside the computing chip. This invention evaluates the performance of each core 50 in the computing chip based on its actual computing performance, adjusts the corresponding frequency of each core 50, fully utilizes the computing advantages of the higher-performing core 50, and avoids the impact of the lower-performing core 50 on the computing chip's performance, thereby maximizing the computing performance of each core 50 and improving the computing speed and accuracy of the computing chip and the overall computing device. Furthermore, the cores 50 of the computing chip of this invention do not jump between different frequencies, maintaining a relatively stable operating frequency.

[0115] Figure 2 This is a schematic diagram of a chip frequency modulation device for a computing device according to an embodiment of the present invention. The computing device is preferably used for massive computation. The computing device preferably includes a control board and a computing power board connected to the control board. At least one computing chip is disposed on the computing power board, and the computing chip has multiple cores 50. Of course, the computing device may also include a heat sink, a connection board, a power module, etc. The chip frequency modulation device 100 includes at least a frequency setting module 10, a computing performance analysis module 20, and a frequency adjustment module 30, wherein:

[0116] The frequency setting module 10 is used to set multiple operating frequencies for the computing chip through multiple phase-locked loop circuits 40, so that the multiple cores 50 in the computing chip operate at each operating frequency. The frequencies of each operating frequency are different, and there is a one-to-one correspondence between the operating frequencies and the phase-locked loop circuits 40. Preferably, the phase-locked loop circuits 40 are located inside or outside the computing chip.

[0117] The computational performance analysis module 20 is used to analyze whether each calculation of the kernel 50 at the current operating frequency is correct. For each correct calculation by the kernel 50, a predetermined correct calculation weight value is increased by one; and for each incorrect calculation by the kernel 50, a predetermined incorrect calculation weight value is decreased by one.

[0118] The frequency adjustment module 30 is used to adjust the current operating frequency of the core 50 upwards or downwards through the phase-locked loop circuit 40. Specifically, if the current value of the core 50 reaches a predetermined correct calculation threshold, the current operating frequency of the core 50 is adjusted upwards through the phase-locked loop circuit 40; or, if the current value of the core 50 reaches a predetermined incorrect calculation threshold, the current operating frequency of the core 50 is adjusted downwards through the phase-locked loop circuit 40.

[0119] Preferably, the frequency adjustment module 30 further includes a frequency adjustment submodule 31 and a stop frequency adjustment submodule 32, wherein:

[0120] The frequency adjustment submodule 31 is used to increase or decrease the current operating frequency of the core 50. Preferably, the frequency adjustment submodule 31 increases or decreases the current operating frequency of the core 50 through the phase-locked loop circuit 40. Of course, the frequency adjustment submodule 31 can also increase or decrease the current operating frequency of the core 50 through other hardware or software.

[0121] The stop frequency adjustment submodule 32 is used to stop frequency adjustment of the core 50 if the number of cores 50 operating at at least one predetermined optimized operating frequency exceeds a predetermined first ratio; or to stop frequency adjustment of the core 50 if the number of cores 50 operating at at least one optimized operating frequency is the largest.

[0122] For example, one or more optimized operating frequencies can be preset from several operating frequencies. If the operating frequency of most cores 50 has reached the optimized operating frequency, it indicates that the operating frequency of each core 50 in the computing chip is already in an optimized state, which can fully utilize the computing performance of each core 50, and no further frequency adjustment is needed. Therefore, the adjustment of the core 50's operating frequency is stopped. For example, if six operating frequencies are set: 500MHz, 550MHz, 600MHz, 650MHz, 700MHz, and 750MHz, and two optimized operating frequencies of 600MHz and 650MHz are selected as optimized operating frequencies, if more than 80% of the cores 50 are operating at operating frequencies of 600MHz and 650MHz, then frequency adjustment of the cores 50 is stopped.

[0123] Figure 3 This is a schematic diagram of the chip frequency modulation device of a computing device according to another embodiment of the present invention. The computing device is preferably used for massive computation. The computing device preferably includes a control board and a computing power board connected to the control board. At least one computing chip is disposed on the computing power board, and the computing chip has multiple cores 50. Of course, the computing device may also include a heat sink, a connection board, a power module, etc. The chip frequency modulation device 100 includes a frequency setting module 10, a computing performance analysis module 20, and a frequency adjustment module 30, wherein:

[0124] The frequency setting module 10 is used to set multiple operating frequencies for the computing chip of the computing device, each operating frequency having a different frequency, and to operate the multiple cores 50 in the computing chip at each operating frequency. That is, according to the frequency adjustment mechanism of the computing chip, several different frequency points are set for each computing chip, and each core 50 of the computing chip operates at each operating frequency point. For example, six operating frequencies can be set: 500MHz, 550MHz, 600MHz, 650MHz, 700MHz, and 750MHz. The number of operating frequencies and the frequency differences between them can be set according to actual needs; the more operating frequencies, the more fully the computing performance of each core 50 can be utilized. When the frequency adjustment switch is activated (before the core 50 is frequency-adjusted), the cores 50 can be evenly distributed, unevenly distributed, or randomly distributed across the operating frequencies according to a predetermined rule. Preferably, the frequency setting module 10 can, as shown in the example... Figure 2 The multiple phase-locked loop circuits 40 shown provide multiple operating frequencies for the computing chip.

[0125] The computational performance analysis module 20 further includes:

[0126] Submodule 22 is used to pre-set the reference node value, correctly calculated weight value, incorrectly calculated weight value, correctly calculated threshold, and incorrectly calculated threshold of kernel 50. The correctly calculated weight value and the incorrectly calculated weight value can be the same or different; the correctly calculated threshold and the incorrectly calculated threshold can also be the same or different. The reference node value, correctly calculated weight value, incorrectly calculated weight value, correctly calculated threshold, and incorrectly calculated threshold are all adjustable parameters and can be optimized according to actual needs such as frequency adjustment speed.

[0127] The analysis submodule 21 is used to analyze whether each calculation of kernel 50 at the current operating frequency is correct. Kernel 50 can perform various calculations, and the submodule can analyze whether each calculation of kernel 50 is correct. Preferably, it analyzes whether the Nonce calculated by kernel 50 is correct.

[0128] The counting submodule 23 is configured to increment the correct calculation weight value of the reference node value by one for each correct calculation by the kernel 50 at least once, and decrement the incorrect calculation weight value of the reference node value by one for each incorrect calculation by the kernel 50 at least once. Preferably, the kernel 50 increments the correct calculation weight value of the reference node value by one for each correct calculation. Of course, it can be set to increment the correct calculation weight value of the reference node value by one for each N correct calculations (where N is a natural number greater than 1), and decrement the incorrect calculation weight value of the reference node value by one for each incorrect calculation by the kernel 50. Of course, it can be set to decrement the incorrect calculation weight value of the reference node value by one for each N incorrect calculations (where N is a natural number greater than 1).

[0129] The judgment submodule 24 is used to determine whether the current reference node value of kernel 50 has reached the correct calculation threshold or the incorrect calculation threshold. If the current reference node value reaches the correct calculation threshold, it means that the computing performance of kernel 50 is high and may have room for improvement; if the current reference node value reaches the incorrect calculation threshold, it means that the computing performance of kernel 50 is weak and may not be sufficient to work at the frequency corresponding to the current operating frequency.

[0130] The frequency adjustment module 30 is configured to: increase the current operating frequency of the kernel 50 if the current reference node value of the kernel 50 reaches a correct calculation threshold, indicating that the kernel 50 has not yet reached its optimal computing performance; and decrease the current operating frequency of the kernel 50 if the current reference node value of the kernel 50 reaches a calculation error threshold, indicating that the computing performance of the kernel 50 is insufficient to operate at the current operating frequency. Preferably, the frequency adjustment module 30 can be configured to: Figure 2 The phase-locked loop circuit 40 or software shown adjusts the frequency of core 50. Those skilled in the art will understand that the adjustment method of the frequency adjustment module 30 to set the operating frequency is not limited to this. That is, according to the core-level frequency adjustment mechanism, the core 50 is adjusted to a suitable operating frequency based on its actual computing performance, increasing the frequency of cores with high computing performance and decreasing the frequency of cores with low computing performance, thereby fully utilizing the computing performance of each core 50.

[0131] Preferably, the frequency adjustment module 30 is used to adjust the current operating frequency of the core 50 to the previous operating frequency if the current value of the core 50 reaches the calculated correct threshold; or to adjust the current operating frequency of the core 50 to the next operating frequency if the current value of the core 50 reaches the calculated incorrect threshold. Those skilled in the art will understand that the previous operating frequency is not limited to the previous adjacent operating frequency, and more than one previous adjacent operating frequency can be set as the previous operating frequency; similarly, the next operating frequency is not limited to the next adjacent operating frequency, and more than one next adjacent operating frequency can be set as the next operating frequency. That is, the current operating frequency of the core 50, 600MHz, is adjusted to the previous operating frequency, 700MHz; the current operating frequency of the core 50, 600MHz, is adjusted to the next operating frequency, 500MHz. And so on, without limiting the interval between the previous and next operating frequencies. Preferably, the frequency difference between the current operating frequency and the previous operating frequency is 1~10%, and the frequency difference between the current operating frequency and the next operating frequency is 1~10%, so that when the core 50 is adjusted from the current operating frequency to the previous or next operating frequency, the benefit to the computing performance of the core 50 should outweigh the loss.

[0132] For example, set 400000 as the reference node value, set the correct calculation weight value to 180, set the incorrect calculation weight value to 9000, and set both the correct calculation threshold and the incorrect calculation threshold to 100000.

[0133] For each correct calculation by kernel 50, 180 is added to the reference node value (correct calculation weight value); for each incorrect calculation by kernel 50, 9000 is decremented from the reference node value (incorrect calculation weight value); based on the reference node value, for each increase or decrease of 100000 (correct calculation threshold and incorrect calculation threshold), the order is advanced to the next frequency point or downgraded to the next frequency point.

[0134] The current mechanism is similar to a tug-of-war between correct and incorrect results, where correct and incorrect results can have different weights. A reference node value is set. Each correct result increases the correct weight value, and each incorrect result decreases the incorrect weight value. If the reward or penalty exceeds a corresponding threshold, the frequency is adjusted upwards or downwards. The system can be understood as having a marker, with the reference node value being the marker's initial value. For each correct submission, the marker increases by 180, and for each incorrect submission, it decreases by 9000. After N correct submissions (N is a natural number greater than or equal to 1) and M incorrect submissions (M is a natural number greater than or equal to 1), the marker should be at the position 400000 + N * 180 – M * 9000. If the marker exceeds a certain threshold, the corresponding frequency is adjusted (increased or decreased). Then, each time the frequency is adjusted to a new frequency point, this value is initialized, that is, the current reference node value is reset to the initial reference node value.

[0135] Preferably, the setting submodule 22 is used to set and adjust the reference node value, calculate the correct weight value, calculate the incorrect weight value, calculate the correct threshold and / or calculate the incorrect threshold of the kernel 50 according to actual needs. The calculated correct weight value and the calculated incorrect weight value may be the same or different, and the calculated correct threshold and the calculated incorrect threshold may be the same or different.

[0136] Preferably, the setting submodule 22 is used to control the resident error rate that the kernel 50 expects to tolerate by controlling the ratio of correctly calculated weight values ​​to incorrectly calculated weight values. The formula for calculating the resident error rate is: Resident error rate = Correctly calculated weight value / (Correctly calculated weight value + Incorrectly calculated weight value).

[0137] Preferably, the setting submodule 22 is used to control the adjustment period by controlling the absolute values ​​of the correctly calculated weight value and the incorrectly calculated weight value.

[0138] Preferably, the setting submodule 22 is used to control the adjustment period by controlling the absolute values ​​of the calculated correct threshold and the calculated incorrect threshold.

[0139] Preferably, the correct calculation of kernel 50 refers to kernel 50 correctly calculating the Nonce.

[0140] The analysis submodule 21 is used to analyze whether the Nonce submitted by kernel 50 each time is correct.

[0141] The counting submodule 26 is configured to increment the reference node value by one calculated correct weight value for each correct nonce submitted by kernel 50; and decrement the reference node value by one calculated incorrect weight value for each incorrect nonce submitted by kernel 50. Preferably, the correct weight value is incremented for each correct nonce submitted by kernel 50. Alternatively, it can be configured to increment the correct weight value for each N (N is a natural number greater than 1) correct nonce submitted by kernel 50, and decrement the incorrect weight value for each incorrect nonce submitted by kernel 50. Alternatively, it can be configured to decrement the incorrect weight value for each N (N is a natural number greater than 1) incorrect nonce submitted by kernel 50.

[0142] Even better, the analysis submodule 21 further includes:

[0143] The calculation unit 211 is used to calculate a first result from the Nonce after the kernel 50 submits a Nonce, and the first result contains a first feature.

[0144] The verification unit 212 is used to calculate a second result from the Nonce using the same algorithm, and the second result contains a second feature. If the first feature is the same as the second feature, the Nonce is determined to be a correct Nonce; otherwise, the Nonce is determined to be an incorrect Nonce.

[0145] For example, after kernel 50 calculates a Nonce and submits it, it embeds the Nonce into the block header to calculate a first hash result. The first 20 bits of the first hash result are 0 (first characteristic). Verification unit 212 also embeds the Nonce into the block header to calculate a second hash result. If the first 20 bits of the second hash result are also 0 (second characteristic), then the Nonce is considered a correct submission.

[0146] It should be noted that, in order to increase the probability that a single kernel 80 can calculate a nonce value that satisfies the requirement for writing to the blockchain, a much easier method than the aforementioned "target value Target" (Target_Lite) can be used to determine the hash. Each kernel 80 can submit nonces more frequently. The first verification unit 212 verifies the nonces submitted by kernel 80. If the hash calculated using the nonce submitted by kernel 80 also passes the Target_Lite determination, then kernel 80's submission is considered correct; otherwise, it is considered an incorrect submission. This invention is not limited to using a nonce that can be written to the final blockchain. The nonces exchanged between the first verification unit 212 and kernel 80 satisfy a lower threshold, have a high submission density, and are conducive to frequency adjustment.

[0147] In a specific application embodiment of the present invention: six phase-locked loop circuits 40 are used, and six operating frequencies are set: 500MHz, 550MHz, 600MHz, 650MHz, 700MHz, and 750MHz. For example, 400000 is set as the reference node value, the correct calculation weight value is set to 180, the incorrect calculation weight value is set to 9000, and both the correct calculation threshold and the incorrect calculation threshold are set to 100000.

[0148] The number of cores distributed at each corresponding frequency based on the four computing boards is as follows:

[0149] Computing board 0: [294 26 96 224 1023 1665]

[0150] Computing board 1: [274 47 111 212 963 1721]

[0151] Computing board 2: [350 25 153 369 1381 1050]

[0152] Computing board 3: [488 33 184 367 1342 950]

[0153] First, let's further explain the mechanism using data. Based on the formula S = Correctly calculated weight value / (Correctly calculated weight value + Incorrectly calculated weight value), and using the given data, we can deduce that the resident error rate S of kernel 50 (which can be understood as the frequency at which it can reside for a long time) is 180 / (180 + 9000) = 1.96%. At this point, kernel 50 will operate at a certain frequency for an extended period (because the expected step size is 0), and its operating frequency will not be increased or decreased. Therefore, it can be inferred that if the calculation error rate of kernel 50 is less than 1.96% (resident error rate S), its operating frequency will be increased; if the calculation error rate of kernel 50 is greater than 1.96% (resident error rate S), its operating frequency will be decreased.

[0154] Based on the set difficulty (which is related to the benchmark and affects the accuracy of kernel 50 calculations; the higher the difficulty coefficient, the lower the accuracy; conversely, the higher the accuracy), the approximate adjustment period when errors increase can be calculated. Assuming the error rate is e, the expected step size for each Nonce is: (1-e)*180-e*9000=180-9180e. Taking e=0.5% as an example, the expected step size is 134.1; taking e=1% as an example, the expected step size is 88.2; taking e=2% as an example, the expected step size is -3.6.

[0155] Taking 650MHz as an example, the expected rate of a single nonce submission by kernel 50 is 1.3 per second (i.e., 1.3 nonces submitted per second). Explaining this with an error probability of 0.5%, it means that after 746 nonce submissions, an upward adjustment can be expected; with an error probability of 1.0%, 1134 submissions are needed, with an expected upward adjustment; if the error probability is 2.0%, 27778 submissions are needed, with an expected downward adjustment, and so on.

[0156] Preferably, the computational performance analysis module 20 is used to determine in real time whether the current reference node of the kernel 50 has reached the correct computation threshold or the incorrect computation threshold according to the preset real-time adjustment instructions, wherein the correct computation threshold and the incorrect computation threshold are the same or different.

[0157] The frequency adjustment module 30 is used to adjust the current operating frequency of the kernel 50 in real time according to a preset real-time adjustment command. If the current reference node of the kernel 50 reaches the correctly calculated threshold, the current operating frequency of the kernel 50 is adjusted upward in real time. If the current reference node of the kernel 50 reaches the incorrectly calculated threshold, the current operating frequency of the kernel 50 is adjusted downward in real time, so that the operating frequency of the kernel 50 is dynamically adjusted in real time.

[0158] Preferably, the computing performance analysis module 20 is used to determine whether the current reference node of the kernel 50 has reached the correct calculation threshold or the incorrect calculation threshold within the adjustment time period set by the preset time adjustment instruction, wherein the correct calculation threshold and the incorrect calculation threshold are the same or different.

[0159] The frequency adjustment module 30 is used to adjust the current operating frequency of kernel 50 according to a preset timed adjustment instruction. If the current reference node of kernel 50 reaches the correct calculation threshold within the adjustment period, the current operating frequency of kernel 50 is increased. If the current reference node of kernel 50 reaches the incorrect calculation threshold within the adjustment period, the current operating frequency of kernel 50 is decreased, thus allowing the operating frequency of kernel 50 to be adjusted periodically. For example, it can be set to count the number of correct nonces generated by kernel 50 only during the 24 hours of Saturday each week, and adjust the frequency based on the calculation accuracy.

[0160] Preferably, the computational performance analysis module 20 is used to analyze whether the current reference node of the kernel 50 has reached the correct computation threshold or the incorrect computation threshold according to the received real-time adjustment instructions, wherein the correct computation threshold and the incorrect computation threshold are the same or different.

[0161] The frequency adjustment module 30 is used to adjust the current operating frequency of the kernel 50 upwards if the current reference node of the kernel 50 reaches the correctly calculated threshold, and downwards if the current reference node of the kernel 50 reaches the incorrectly calculated threshold, based on the received real-time adjustment command. It also stops adjusting the current operating frequency of the kernel 50 based on the received stop adjustment command.

[0162] For example, users can send real-time adjustment commands to the computing device at any time as needed. Users can set the weight A to be increased on the reference node for each correct Nonce calculated by kernel 50, and the weight B to be decreased on the reference node for each incorrect Nonce calculated by kernel 50. When the current increase reaches the threshold C for the number of correct calculations, kernel 50 is upgraded to the next frequency. When the current decrease reaches the threshold D for the number of incorrect calculations, kernel 50 is downgraded to the next frequency. Furthermore, users can send a stop adjustment command to the computing device at any time as needed. Upon receiving this stop adjustment command, the computing device immediately stops frequency adjustment of kernel 50.

[0163] The present invention also provides a computing board including the chip frequency modulation device 100 as described above.

[0164] The present invention also provides a computing device including the chip frequency modulation device 100.

[0165] Figure 4 This is a flowchart of the chip frequency tuning method for the computing device of the present invention, which can be implemented by the chip frequency tuning device 100 of the computing device. The computing device includes at least one computing chip, and the computing chip is provided with multiple cores. The computing device is preferably used for massive computing. It should be noted that the chip frequency tuning technology of the present invention actually involves two levels of frequency adjustment mechanisms: a frequency adjustment mechanism at the computing chip level and a frequency adjustment mechanism at the core level. The frequency adjustment mechanism at the computing chip level refers to setting several suitable operating frequency points for each computing chip and allowing each core 50 of the computing chip to work at each operating frequency point, so as to give full play to the working performance of each core 50. The frequency adjustment mechanism at the core level refers to adjusting the core 50 to a suitable operating frequency point according to the actual computing performance of the core 50, increasing the frequency of the core 50 with high computing performance and decreasing the frequency of the core 50 with low computing performance, thereby giving full play to the computing performance of each core 50. The method includes the following steps:

[0166] Step S401: Set multiple operating frequencies for the computing chip of the computing device, and make the multiple cores 50 in the computing chip work at each operating frequency.

[0167] This step, based on the frequency adjustment mechanism of the computing chips, sets several different frequency points for each computing chip and allows each core 50 of the computing chip to operate at each of these operating frequencies. For example, six operating frequencies can be set: 500MHz, 550MHz, 600MHz, 650MHz, 700MHz, and 750MHz. The number of operating frequencies and the frequency differences between them can be set according to actual needs; more operating frequencies allow for better utilization of the computing performance of each core 50. When the frequency adjustment switch is activated (before the core 50 has been frequency-adjusted), the cores 50 can be evenly, unevenly, or randomly distributed across the operating frequencies according to predetermined rules. Preferably, this step can be achieved through methods such as... Figure 2 The multiple phase-locked loop circuits 40 shown provide multiple operating frequencies for the computing chip. Of course, multiple operating frequencies can also be set for the computing chip through other hardware or software.

[0168] Step S402: Analyze whether each calculation of kernel 50 at the current operating frequency is correct. For each correct calculation by kernel 50, increase the predetermined correct calculation weight value by one. For each incorrect calculation by kernel 50, decrease the predetermined incorrect calculation weight value by one.

[0169] If the current value of kernel 50 reaches the predetermined correct calculation threshold, it indicates that the computational performance of kernel 50 is high, and the computational performance of kernel 50 may have room for improvement. If the current value of kernel 50 reaches the predetermined incorrect calculation threshold, it indicates that the computational performance of kernel 50 is low, and the computational performance of kernel 50 may be insufficient to operate at the frequency corresponding to the current operating frequency.

[0170] In step S403, if the current value of kernel 50 reaches the predetermined correct calculation threshold, the current operating frequency of kernel 50 is increased; or, if the current value of kernel 50 reaches the predetermined incorrect calculation threshold, the current operating frequency of kernel 50 is decreased.

[0171] This step involves adjusting the core 50 to a suitable operating frequency based on its actual computing performance, according to the kernel-level frequency adjustment mechanism. This involves increasing the frequency of cores with high computing performance and decreasing the frequency of cores with low computing performance, thereby fully utilizing the computing performance of each core 50.

[0172] This invention evaluates the performance of each core 50 in the computing chip based on their actual computational performance, adjusts the corresponding frequency of each core 50, fully utilizes the computational advantages of the higher-performing core 50, and avoids the impact of the lower-performing core 50 on the computing chip's overall performance. This maximizes the computational performance of each core 50, thereby improving the computing speed and accuracy of the computing chip and the overall computing device. Furthermore, the core 50 of the computing chip in this invention does not fluctuate in frequency, maintaining a relatively stable operating frequency.

[0173] Preferably, step S401 can set multiple operating frequencies for the computing chip through multiple phase-locked loop circuits 40, with a one-to-one correspondence between the operating frequencies and the phase-locked loop circuits 40. For example... Figure 2 The phase-locked loop circuit 40 shown can be located inside or outside the computing chip. The number of operating frequencies and the frequency differences between them can be set according to actual needs; more operating frequencies allow for full utilization of the computing performance of each core 50. For example, six operating frequencies can be set: 500MHz, 550MHz, 600MHz, 650MHz, 700MHz, and 750MHz. Therefore, this invention allows for the setting of more phase-locked loop circuits 40 to achieve more operating frequencies, thus maximizing the computing performance of each core 50.

[0174] It is worth noting that the frequency difference between operating frequencies in this invention needs to be controlled within a reasonable range. When the core 50 increases its operating frequency by one frequency point, its operating frequency will increase by one frequency difference value, which can improve its computing performance due to the increased computational speed. At the same time, increasing the core's operating frequency may result in a decrease in computational accuracy, thus sacrificing some computing performance. Therefore, the frequency setting module 10 should reasonably control the frequency difference between adjacent operating frequencies so that when the core 50 adjusts from its current operating frequency to the previous operating frequency, the benefit to the core 50's computing performance should outweigh the loss. Preferably, the frequency difference between adjacent operating frequencies is 1% to 10%.

[0175] Preferably, step S403 can adjust the current operating frequency of the core 50 by increasing or decreasing the phase-locked loop circuit 40. Specifically, if the current value of the core 50 reaches a predetermined correct calculation threshold, the current operating frequency of the core 50 is increased by the phase-locked loop circuit 40; or, if the current value of the core 50 reaches a predetermined incorrect calculation threshold, the current operating frequency of the core 50 is decreased by the phase-locked loop circuit 40.

[0176] The chip frequency modulation method of the computing device of the present invention may further include:

[0177] If core 50 operating at at least one predetermined optimized operating frequency exceeds a predetermined first ratio, frequency adjustment of core 50 is stopped. Or

[0178] If the number of cores 50 operating at at least one optimized operating frequency is the largest, stop adjusting the frequency of cores 50.

[0179] For example, one or more optimized operating frequencies can be preset from several operating frequencies. If the operating frequency of most cores 50 has reached the optimized operating frequency, it indicates that the operating frequency of each core 50 in the computing chip is already in an optimized state, which can fully utilize the computing performance of each core 50, and no further frequency adjustment is needed. Therefore, the adjustment of the core 50's operating frequency is stopped. For example, if six operating frequencies are set: 500MHz, 550MHz, 600MHz, 650MHz, 700MHz, and 750MHz, and two optimized operating frequencies of 600MHz and 650MHz are selected as optimized operating frequencies, if more than 80% of the cores 50 are operating at operating frequencies of 600MHz and 650MHz, then frequency adjustment of the cores 50 is stopped.

[0180] Figure 5 This is a flowchart of a chip frequency modulation method for a computing device in another embodiment of the present invention. It can be implemented by the chip frequency modulation device 100. The computing device includes at least one computing chip, and the computing chip has multiple cores. The method includes the following steps:

[0181] Step S501: Set multiple operating frequencies for the computing chip of the computing device, and make the multiple cores 50 in the computing chip work at each operating frequency.

[0182] This step, based on the frequency adjustment mechanism at the computing chip level, sets several different frequency points for each computing chip and allows each core 50 of the computing chip to operate at each of these operating frequencies. For example, six operating frequencies can be set: 500MHz, 550MHz, 600MHz, 650MHz, 700MHz, and 750MHz. The number of operating frequencies and the frequency differences between them can be set according to actual needs; more operating frequencies allow for better utilization of the computing performance of each core 50. When the frequency adjustment switch is activated (before the core 50 has been frequency-adjusted), the cores 50 can be evenly, unevenly, or randomly distributed across the operating frequencies according to predetermined rules. Preferably, this can be achieved through mechanisms such as... Figure 2 The multiple phase-locked loop circuits 40 shown provide multiple operating frequencies for the computing chip. Of course, multiple operating frequencies can also be set for the computing chip through other hardware or software. Preferably, the frequency difference between adjacent operating frequencies is 1~10%.

[0183] Step S502: Pre-set the reference node value, correctly calculated weight value, incorrectly calculated weight value, correctly calculated threshold, and incorrectly calculated threshold of kernel 50. The correctly calculated weight value and the incorrectly calculated weight value can be the same or different; the correctly calculated threshold and the incorrectly calculated threshold can also be the same or different. The reference node value, correctly calculated weight value, incorrectly calculated weight value, correctly calculated threshold, and incorrectly calculated threshold are all adjustable parameters and can be optimized according to actual needs such as frequency adjustment speed.

[0184] Preferably, the reference node value, the correctly calculated weight value, the incorrectly calculated weight value, the correctly calculated threshold and / or the incorrectly calculated threshold of kernel 50 are set and adjusted according to actual needs. The correctly calculated weight value and the incorrectly calculated weight value may be the same or different, and the correctly calculated threshold and the incorrectly calculated threshold may be the same or different.

[0185] The kernel 50's expected tolerance for residency error rate is controlled by adjusting the ratio of correctly calculated weight values ​​to incorrectly calculated weight values. The residency error rate is calculated as follows: Residency Error Rate = Correctly Calculated Weight Value / (Correctly Calculated Weight Value + Incorrectly Calculated Weight Value).

[0186] The adjustment cycle is controlled by adjusting the absolute values ​​of correctly calculated weight values ​​and incorrectly calculated weight values.

[0187] The adjustment cycle is controlled by adjusting the absolute values ​​of the correct and incorrect thresholds.

[0188] Step S503: Analyze whether the kernel 50's calculations at the current operating frequency are correct.

[0189] Kernel 50 can perform various calculations, and its accuracy can be analyzed for each calculation. Preferably, the accuracy of the Nonce calculated by kernel 50 is analyzed.

[0190] In step S504, for each correct calculation by kernel 50 at least once, a correct calculation weight value is added to the reference node value, and for each incorrect calculation by kernel 50 at least once, an incorrect calculation weight value is deducted from the reference node value. Preferably, for each correct calculation by kernel 50, a correct calculation weight value is added to the reference node value. Alternatively, it can be set to add a correct calculation weight value to the reference node value for every N correct calculations (N being a natural number greater than 1), and deduct a incorrect calculation weight value from the reference node value for each incorrect calculation. Again, it can be set to deduct a incorrect calculation weight value from the reference node value for every N incorrect calculations (N being a natural number greater than 1).

[0191] Step S505: Determine whether the current reference node value of kernel 50 has reached the correct calculation threshold or the incorrect calculation threshold. If the current reference node value of kernel 50 has reached the correct calculation threshold, proceed to step S506; if the current reference node value of kernel 50 has reached the incorrect calculation threshold, proceed to step S507.

[0192] This step preferably includes:

[0193] (1) Based on the preset real-time adjustment instructions, determine in real time whether the current reference node of kernel 50 has reached the correct calculation threshold or the incorrect calculation threshold; or

[0194] (2) Based on the preset timed adjustment instruction, within the adjustment time period set by the timed adjustment instruction, determine whether the current reference node of kernel 50 has reached the correct calculation threshold or the incorrect calculation threshold; or

[0195] (3) Based on the received real-time adjustment instructions, analyze whether the current reference node of kernel 50 has reached the correct calculation threshold or the incorrect calculation threshold.

[0196] Step S506: If the current reference node value of kernel 50 reaches the correct calculation threshold, it indicates that kernel 50 has not yet reached its optimal computing performance, and the current operating frequency of kernel 50 is increased. Preferably, if the current value of kernel 50 reaches the correct calculation threshold, the current operating frequency of kernel 50 is increased to the previous operating frequency.

[0197] This step preferably includes:

[0198] (1) According to the preset real-time adjustment instructions, if the current reference node of kernel 50 reaches the calculated correct threshold, the current operating frequency of kernel 50 is increased in real time; or

[0199] (2) According to the preset timing adjustment instruction, if the current reference node of kernel 50 reaches the calculated correct threshold within the adjustment period, the current operating frequency of kernel 50 is increased; or

[0200] (3) If the current reference node of kernel 50 reaches the calculated correct threshold according to the received real-time adjustment instruction, the current operating frequency of kernel 50 is increased. And according to the received stop adjustment instruction, the adjustment of the current operating frequency of kernel 50 is stopped.

[0201] In step S507, if the current reference node value of kernel 50 reaches the calculation error threshold, it indicates that the computing performance of kernel 50 is insufficient to operate at the current operating frequency, and the current operating frequency of kernel 50 is lowered. Preferably, if the current value of kernel 50 reaches the calculation error threshold, the current operating frequency of kernel 50 is lowered to the next operating frequency.

[0202] This step preferably includes:

[0203] (1) According to the preset real-time adjustment instructions, if the current reference node of kernel 50 reaches the calculation error threshold, the current operating frequency of kernel 50 is adjusted down in real time; or

[0204] (2) According to the preset timed adjustment instruction, if the current reference node of kernel 50 reaches the calculation error threshold within the adjustment period, the current operating frequency of kernel 50 will be lowered; or

[0205] (3) If the current reference node of kernel 50 reaches the calculation error threshold according to the received real-time adjustment instruction, the current operating frequency of kernel 50 is reduced; according to the received stop adjustment instruction, the adjustment of the current operating frequency of kernel 50 is stopped.

[0206] For example, users can send real-time adjustment commands to the computing device at any time as needed. Users can set the weight A to be increased on the reference node for each correct Nonce calculated by kernel 50, and the weight B to be decreased on the reference node for each incorrect Nonce calculated by kernel 50. When the current increase reaches the threshold C for the number of correct calculations, kernel 50 is advanced to the next operating frequency. When the current decrease reaches the threshold D for the number of incorrect calculations, kernel 50 is downgraded to the next operating frequency. Furthermore, users can send a stop adjustment command to the computing device at any time as needed. Upon receiving this stop adjustment command, the computing device immediately stops adjusting the frequency of kernel 50.

[0207] Those skilled in the art will understand that the previous operating frequency is not limited to the previous adjacent operating frequency; more than one previous adjacent operating frequency can be set as the previous operating frequency. Similarly, the next operating frequency is not limited to the next adjacent operating frequency; more than one next adjacent operating frequency can be set as the next operating frequency. Preferably, the frequency difference between the current operating frequency and the previous operating frequency, and the frequency difference between the current operating frequency and the next operating frequency, are 1-10%, such that when the core 50 is adjusted from the current operating frequency to the previous or next operating frequency, the benefit to the computing performance of the core 50 should outweigh the loss. That is, the current operating frequency of the core 50 is adjusted from 600MHz to the previous operating frequency of 700MHz; the current operating frequency of the core 50 is adjusted from 600MHz to the next operating frequency of 500MHz. And so on. The interval between the previous and next operating frequencies is not limited here.

[0208] This step can preferably be achieved through, for example... Figure 2The phase-locked loop circuit 40 shown or the software adjusts the frequency of the core 50. That is, according to the core-level frequency adjustment mechanism, the core 50 is adjusted to a suitable operating frequency point based on its actual computing performance. The frequency of the core 50 with high computing performance is increased, and the frequency of the core 50 with low computing performance is decreased, thereby giving full play to the computing performance of each core 50.

[0209] For example, set 400000 as the reference node value, set the correct calculation weight value to 180, set the incorrect calculation weight value to 9000, and set both the correct calculation threshold and the incorrect calculation threshold to 100000.

[0210] For each correct calculation by kernel 50, add 180 to the reference node value (for correct calculation weight); for each incorrect calculation by kernel 50, reduce the reference node value by 9000 (for incorrect calculation weight); based on the reference node value, for each increase or decrease of 100000 (for correct calculation threshold and incorrect calculation threshold), advance to the next frequency point or decrease to the next frequency point.

[0211] The current mechanism is similar to a tug-of-war between correct and incorrect results, where correct and incorrect results can have different weights. A reference node value is set. Each correct result increases the correct weight value, and each incorrect result decreases the incorrect weight value. If the reward or penalty exceeds a corresponding threshold, the frequency is adjusted upwards or downwards. The system can be understood as having a marker, with the reference node value being the marker's initial value. For each correct submission, the marker increases by 180, and for each incorrect submission, it decreases by 9000. After N correct submissions (N is a natural number greater than or equal to 1) and M incorrect submissions (M is a natural number greater than or equal to 1), the marker should be at the position 400000 + N * 180 – M * 9000. If the marker exceeds a certain threshold, the corresponding frequency is adjusted (increased or decreased). Then, each time the frequency is adjusted to a new frequency point, this value is initialized, that is, the current reference node value is reset to the initial reference node value.

[0212] Figure 6 This is a flowchart of a preferred chip frequency modulation method for a computing device in another embodiment of the present invention. It can be implemented by the chip frequency modulation device 100. The computing device includes at least one computing chip, and the computing chip has multiple cores. The method includes the following steps:

[0213] Step S601: Set multiple operating frequencies for the computing chip of the computing device, and make the multiple cores 50 in the computing chip work at each operating frequency.

[0214] Step S602: Pre-set the reference node value of kernel 50, calculate the correct weight value, calculate the incorrect weight value, calculate the correct threshold, and calculate the incorrect threshold.

[0215] Step S603: Analyze whether the Nonce submitted by kernel 50 each time is correct.

[0216] Preferably, this step further includes:

[0217] (1) After kernel 50 submits a Nonce, kernel 50 calculates the first result of the Nonce using a predetermined algorithm. The first result contains the first feature.

[0218] (2) The verification unit of the computing chip calculates the second result of the Nonce using the same algorithm, and the second result contains the second feature.

[0219] (3) If the first feature is the same as the second feature, the verification unit determines that the Nonce is a correct Nonce; otherwise, it determines that the Nonce is an incorrect Nonce.

[0220] For example, after kernel 50 calculates a Nonce and submits it, it embeds the Nonce into the block header to calculate a first hash result. The first 20 bits of the first hash result are 0 (first characteristic). Verification unit 212 also embeds the Nonce into the block header to calculate a second hash result. If the first 20 bits of the second hash result are also 0 (second characteristic), then the Nonce is considered a correct submission.

[0221] In step S604, for each correct nonce submitted by kernel 50, a correct weight value is added to the reference node value; for each incorrect nonce submitted by kernel 50, an incorrect weight value is decremented from the reference node value. Preferably, for each correct nonce submitted by kernel 50, a correct weight value is added to the reference node value. Alternatively, it can be set to add a correct weight value to the reference node value for every N (N is a natural number greater than 1) correct nonces submitted by kernel 50, and decrement an incorrect weight value from the reference node value for every N (N is a natural number greater than 1) incorrect nonces submitted by kernel 50. Alternatively, it can be set to decrement an incorrect weight value from the reference node value for every N (N is a natural number greater than 1) incorrect nonces submitted by kernel 50.

[0222] Step S605: Determine whether the current reference node value of kernel 50 has reached the correct calculation threshold or the incorrect calculation threshold. If the current reference node value of kernel 50 has reached the correct calculation threshold, proceed to step S606; if the current reference node value of kernel 50 has reached the incorrect calculation threshold, proceed to step S607.

[0223] Step S606: If the current reference node value of kernel 50 reaches the calculated correct threshold, the current operating frequency of kernel 50 is adjusted up to the previous operating frequency.

[0224] Step S607: If the current reference node value of kernel 50 reaches the calculation error threshold, the current operating frequency of kernel 50 is lowered to the next operating frequency.

[0225] In a specific application embodiment of the present invention: six phase-locked loop circuits 40 are used, with six operating frequencies set: 500MHz, 550MHz, 600MHz, 650MHz, 700MHz, and 750MHz. A reference node value of 400000 is set, the correct calculation weight value is set to 180, the incorrect calculation weight value is set to 9000, and both the correct calculation threshold and the incorrect calculation threshold are set to 100000.

[0226] The number of cores distributed at each corresponding frequency based on the four computing boards is as follows:

[0227] Computing board 0: [294 26 96 224 1023 1665]

[0228] Computing board 1: [274 47 111 212 963 1721]

[0229] Computing board 2: [350 25 153 369 1381 1050]

[0230] Computing board 3: [488 33 184 367 1342 950]

[0231] First, let's further explain the mechanism using data. Based on the formula S = Correctly calculated weight value / (Correctly calculated weight value + Incorrectly calculated weight value), and using the given data, we can deduce that the resident error rate S of kernel 50 (which can be understood as the frequency at which it can reside for a long time) is 180 / (180 + 9000) = 1.96%. At this point, kernel 50 will operate at a certain frequency for an extended period (because the expected step size is 0), and its operating frequency will not be increased or decreased. Therefore, it can be inferred that if the calculation error rate of kernel 50 is less than 1.96% (resident error rate S), its operating frequency will be increased; if the calculation error rate of kernel 50 is greater than 1.96% (resident error rate S), its operating frequency will be decreased.

[0232] Based on the set difficulty (which is related to the benchmark and affects the accuracy of kernel 50 calculations; the higher the difficulty coefficient, the lower the accuracy; conversely, the higher the accuracy), the approximate adjustment period when errors increase can be calculated. Assuming the error rate is e, the expected step size for each Nonce is: (1-e)*180-e*9000=180-9180e. Taking e=0.5% as an example, the expected step size is 134.1; taking e=1% as an example, the expected step size is 88.2; taking e=2% as an example, the expected step size is -3.6.

[0233] Taking 650MHz as an example, the expected rate of a single nonce submission by kernel 50 is 1.3 per second (i.e., 1.3 nonces submitted per second). Explaining this with an error probability of 0.5%, it means that after 746 nonce submissions, an upward adjustment can be expected; with an error probability of 1.0%, 1134 submissions are needed, with an expected upward adjustment; if the error probability is 2.0%, 27778 submissions are needed, with an expected downward adjustment, and so on.

[0234] The present invention also provides a storage medium for storing, for example, Figures 4-6 A computer program for a chip frequency modulation method of any of the computing devices described herein. For example, computer program instructions, when executed by a computer, can invoke or provide the methods and / or technical solutions according to this application through the operation of the computer. The program instructions for invoking the methods of this application may be stored in a fixed or removable storage medium, and / or transmitted via data streams in broadcast or other signal carrying media, and / or stored in the memory of a computing device operating according to the program instructions. Here, one embodiment according to this application includes a... Figure 7 The computing device shown preferably includes a control board and at least one computing board connected to the control board. The control board is equipped with a processor, and the computing board is equipped with a plurality of computing chips for computation, each computing chip having a plurality of cores. The device includes a storage medium for storing computer program instructions and a processor for executing the program instructions. When the computer program instructions are executed by the processor, the computing device is triggered to execute the methods and / or technical solutions based on the foregoing embodiments.

[0235] It should be noted that this application can be implemented in software and / or a combination of software and hardware, for example, using an application-specific integrated circuit (ASIC), a general-purpose computer, or any other similar hardware device. In one embodiment, the software program of this application can be executed by a processor to implement the steps or functions described above. Similarly, the software program of this application (including related data structures) can be stored in a computer-readable recording medium, such as RAM memory, magnetic or optical drives, floppy disks, and similar devices. Furthermore, some steps or functions of this application can be implemented in hardware, for example, as circuitry that works with a processor to perform the various steps or functions.

[0236] The method according to the invention can be implemented on a computer as a computer-implemented method, or in dedicated hardware, or a combination of both. Executable code or portions thereof for the method according to the invention can be stored on a computer program product. Examples of computer program products include memory devices, optical storage devices, integrated circuits, servers, online software, etc. Preferably, the computer program product includes non-transitory program code components stored on a computer-readable medium so as to execute the method according to the invention when the program product is executed on a computer.

[0237] In a preferred embodiment, the computer program includes computer program code components adapted to perform all the steps of the method according to the invention when the computer program is run on a computer. Preferably, the computer program is embodied on a computer-readable medium.

[0238] In summary, this invention automatically adjusts the frequency of the cores in a computing chip. First, multiple suitable operating frequencies are set, and the cores in the computing chip operate at different frequencies. Then, for each correct calculation by a core, a predetermined correct calculation weight value is increased; for each incorrect calculation by a core, a predetermined incorrect calculation weight value is decreased. If a predetermined correct calculation threshold is reached, the current operating frequency is increased, i.e., the frequency of the core with higher computing performance is increased; if a predetermined incorrect calculation threshold is reached, the current operating frequency of the core is decreased, i.e., the frequency of the core with lower computing performance is decreased. Therefore, this invention can automatically adjust the frequency of each core according to its actual computing performance in the computing chip, thereby maximizing the computing performance of the cores and improving the computing performance of the computing chip and the overall computing device.

[0239] Of course, the present invention may have other various embodiments. Without departing from the spirit and essence of the present invention, those skilled in the art can make various corresponding changes and modifications according to the present invention, but these corresponding changes and modifications should all fall within the protection scope of the appended claims.

Claims

1. A chip frequency modulation method for a computing device, wherein the computing device is provided with at least one arithmetic chip, and the arithmetic chip is provided with multiple cores, characterized in that, The steps include: The frequency setting step involves setting multiple operating frequency points for the computing chip of the computing device. The computational performance analysis steps analyze whether each calculation of the kernel at the current operating frequency is correct. For each correct calculation by the kernel, a predetermined correct calculation weight value is increased by one, and for each incorrect calculation by the kernel, a predetermined incorrect calculation weight value is decreased by one. The frequency adjustment step, if the current value of the kernel reaches a predetermined calculation correctness threshold, increases the current operating frequency of the kernel; or, if the current value of the kernel reaches a predetermined calculation error threshold, decreases the current operating frequency of the kernel, includes: The kernel's expected tolerance for resident error rate is controlled by controlling the ratio of the correctly calculated weight value to the incorrectly calculated weight value; When the calculation error rate at the current operating frequency is less than the resident error rate, the kernel increases the current operating frequency; when the calculation error rate at the current operating frequency is greater than the resident error rate, the kernel decreases the current operating frequency.

2. The chip frequency modulation method according to claim 1, characterized in that, The frequency point setting step further includes: Multiple operating frequencies are set for the computing chip through multiple phase-locked loop circuits, and the operating frequencies are in a one-to-one correspondence with the phase-locked loop circuits. The frequency adjustment step further includes: The current operating frequency of the core is adjusted up or down through the phase-locked loop circuit.

3. The chip frequency modulation method according to claim 2, characterized in that, The phase-locked loop circuit is located inside or outside the computing chip.

4. The chip frequency modulation method according to claim 1, characterized in that, The frequency difference between adjacent operating frequency points is 1~10%.

5. The chip frequency modulation method according to claim 1, characterized in that, If the core operating at at least one or more predetermined optimized operating frequencies exceeds a predetermined first ratio, frequency tuning of the core is stopped.

6. The chip frequency modulation method according to claim 1, characterized in that, If the number of kernels operating at at least one or more predetermined optimized operating frequencies is the highest, then frequency tuning of the kernels is stopped.

7. The chip frequency modulation method according to claim 1, characterized in that, The multiple cores in the computing chip operate at their respective operating frequencies, and the number of operating frequencies and the frequency differences between the multiple operating frequencies are adjustable.

8. The chip frequency modulation method according to claim 1, characterized in that, Multiple kernels are distributed evenly, unevenly, or randomly at the operating frequency points according to predetermined rules.

9. The chip frequency modulation method according to claim 1, characterized in that, The frequency adjustment step further includes: If the current value of the kernel reaches the calculated correct threshold, the current operating frequency of the kernel is increased to the previous operating frequency. If the current value of the kernel reaches the calculation error threshold, the current operating frequency of the kernel will be lowered to the next operating frequency.

10. The chip frequency modulation method according to claim 1, characterized in that, The computational performance analysis step also includes: Based on preset real-time adjustment instructions, it is determined in real time whether the current value of the kernel has reached the correct calculation threshold or the incorrect calculation threshold; The frequency adjustment step further includes: According to the preset real-time adjustment instructions, if the current value of the kernel reaches the calculated correct threshold, the current operating frequency of the kernel is increased in real time; if the current value of the kernel reaches the calculated incorrect threshold, the current operating frequency of the kernel is decreased in real time.

11. The chip frequency modulation method according to claim 1, characterized in that, The computational performance analysis step also includes: According to the preset timed adjustment instruction, within the adjustment time period set by the timed adjustment instruction, it is determined whether the current value of the kernel has reached the calculation correct threshold or the calculation error threshold. The frequency adjustment step further includes: According to the preset timed adjustment instruction, if the current value of the kernel reaches the calculation correctness threshold within the adjustment period, the current operating frequency of the kernel is increased; if the current value of the kernel reaches the calculation error threshold within the adjustment period, the current operating frequency of the kernel is decreased.

12. The chip frequency modulation method according to claim 1, characterized in that, The computational performance analysis step also includes: Based on the received real-time adjustment instructions, analyze whether the current value of the kernel has reached the correct calculation threshold or the incorrect calculation threshold; The frequency adjustment step further includes: According to the received real-time adjustment instruction, if the current value of the kernel reaches the calculation correct threshold, the current operating frequency of the kernel is increased; if the current value of the kernel reaches the calculation error threshold, the current operating frequency of the kernel is decreased; according to the received stop adjustment instruction, the adjustment of the current operating frequency of the kernel is stopped.

13. The chip frequency modulation method according to claim 1, characterized in that, It also includes reference node values, and the computational performance analysis step further includes: Analyze whether the kernel's calculations at the current operating frequency are correct. For each correct calculation by the kernel, add the correct weight value to the reference node value.

14. The chip frequency modulation method according to claim 13, characterized in that, The computational performance analysis step further includes: Analyze whether the kernel's calculations at the current operating frequency are correct. If the kernel makes a calculation error at least once, reduce the error weight value of the calculation by one point on the reference node value.

15. The chip frequency modulation method according to claim 14, characterized in that, The method further includes: Determine whether the current reference node value of the kernel has reached the correct calculation threshold or the incorrect calculation threshold; The frequency adjustment step further includes: If the current reference node value of the kernel reaches the calculated correct threshold, the current operating frequency of the kernel will be increased. If the current reference node value of the kernel reaches the calculation error threshold, the current operating frequency of the kernel will be lowered.

16. The chip frequency modulation method according to claim 1, characterized in that, The method further includes: The adjustment period is controlled by adjusting the absolute values ​​of the correctly calculated weight value and the incorrectly calculated weight value.

17. The chip frequency modulation method according to claim 1, characterized in that, The method further includes: The adjustment period is controlled by adjusting the absolute values ​​of the correct calculation threshold and the incorrect calculation threshold.

18. The chip frequency modulation method according to claim 1, characterized in that, The formula for calculating the dwell error rate is: Dwell Error Rate = Correct Calculation Weight Value / (Correct Calculation Weight Value + Incorrect Calculation Weight Value).

19. The chip frequency modulation method according to claim 1, characterized in that, The step of analyzing whether the kernel's calculations at the current operating frequency are correct also includes: Analyze whether the random numbers submitted by the kernel each time are correct; For each correct random number submitted by the kernel, the calculated correct weight value is increased by one to the current value; for each incorrect random number submitted by the kernel, the calculated incorrect weight value is decreased by one to the current value.

20. The chip frequency modulation method according to claim 19, characterized in that, The step of analyzing whether the random number submitted by the kernel each time is correct also includes: After the kernel submits a random number, the kernel calculates a first result from the random number using a predetermined algorithm, and the first result contains a first feature; The verification unit of the computing chip calculates a second result from the random number using the same algorithm, and the second result contains a second feature; If the first feature is the same as the second feature, the verification unit determines that the random number is a correct random number; otherwise, it determines that the random number is an incorrect random number.

21. The chip frequency modulation method according to claim 20, characterized in that: The random number submitted by the kernel each time is a Nonce; The kernel calculates a first hash result from the Nonce embedded block header, and the first hash result contains a first feature; The verification unit calculates a second hash result from the Nonce embedded block header, and the second hash result contains a second feature.

22. A chip frequency modulation device for a computing device, based on the chip frequency modulation method according to any one of claims 1-21, wherein the computing device is provided with at least one arithmetic chip, and the arithmetic chip is provided with multiple cores, characterized in that, The chip frequency modulation device includes: A frequency setting module is used to set multiple operating frequency points for the computing chip of the computing device; The computational performance analysis module is used to analyze whether each calculation of the kernel at the current operating frequency is correct. For each correct calculation by the kernel, a predetermined calculation correctness weight value is increased by one, and for each incorrect calculation by the kernel, a predetermined calculation error weight value is decreased by one. A frequency adjustment module is used to increase the current operating frequency of the kernel if the current value of the kernel reaches a predetermined calculation correctness threshold; or to decrease the current operating frequency of the kernel if the current value of the kernel reaches a predetermined calculation error threshold, comprising: The kernel's expected tolerance for resident error rate is controlled by controlling the ratio of the correctly calculated weight value to the incorrectly calculated weight value; When the calculation error rate at the current operating frequency is less than the resident error rate, the kernel increases the current operating frequency; when the calculation error rate at the current operating frequency is greater than the resident error rate, the kernel decreases the current operating frequency.

23. The chip frequency modulation device according to claim 22, characterized in that, The frequency setting module is used to set multiple operating frequencies for the computing chip through multiple phase-locked loop circuits, and the operating frequencies are in a one-to-one correspondence with the phase-locked loop circuits. The frequency adjustment module is used to adjust the current operating frequency of the core by means of the phase-locked loop circuit.

24. The chip frequency modulation device according to claim 23, characterized in that, The phase-locked loop circuit is located inside or outside the computing chip.

25. The chip frequency modulation device according to claim 22, characterized in that, The frequency difference between adjacent operating frequency points is 1~10%.

26. The chip frequency modulation device according to claim 22, characterized in that, The computing performance analysis module executes one of the following instructions: real-time adjustment instruction, timed adjustment instruction, and instant adjustment instruction.

27. The chip frequency modulation device according to claim 22, characterized in that, The computational performance analysis module further includes: The analysis submodule is used to analyze whether the kernel's calculations at the current operating frequency are correct. The counting submodule is used to increment the correct calculation weight value on the reference node value once for each correct calculation by the kernel at least once, and to decrement the incorrect calculation weight value on the reference node value once for each incorrect calculation by the kernel at least once. The judgment submodule is used to determine whether the current reference node value of the kernel has reached the correct calculation threshold or the incorrect calculation threshold; The frequency adjustment module is used to increase the current operating frequency of the kernel if the current reference node value of the kernel reaches the calculated correct threshold. And to reduce the current operating frequency of the kernel if the current reference node value of the kernel reaches the calculation error threshold.

28. The chip frequency modulation device according to claim 27, characterized in that, The analysis submodule is used to analyze whether the random numbers submitted by the kernel each time are correct; The counting submodule is used to increment the calculated correct weight value by one for each correct random number submitted by the kernel, and to decrement the calculated incorrect weight value by one for each incorrect random number submitted by the kernel.

29. A computing board comprising the chip frequency modulation device according to any one of claims 22 to 28.

30. A computing device comprising the chip frequency modulation device according to any one of claims 22 to 28.

31. A storage medium for storing a computer program for executing a chip frequency modulation method of any one of the computing devices of claims 1 to 21.

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