A high-voltage level shift circuit suitable for GaN driver chips

Abstract

The present invention relates to the field of integrated circuit technology, and specifically to a high-voltage level shift circuit suitable for a GaN driver chip. The circuit converts a signal in a low-voltage domain into a signal in a high-voltage domain, and is characterized in that it includes a voltage-to-current signal module, a current mirror module, a push-pull output module, a current compensation branch, and a signal maintenance module; the voltage-to-current signal module is used to convert a PWM voltage signal into a current signal, the current mirror module is used to mirror the current signal converted by the PWM voltage as the input signal of the push-pull output module, the push-pull output module converts the current signal into a voltage signal in the high-voltage domain, the current compensation branch is used to compensate for the current of the node, and the signal maintenance module provides a small current to maintain the established signal state. This solution effectively solves the contradiction between power consumption, transmission delay, CMTI capability, and the ability to resist negative pressure of the switch node in the traditional level shift circuit.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a high-voltage level shift circuit suitable for a GaN driver chip. Background Art

[0002] As a core component of the driver chip, the high-voltage level shift circuit has a serious impact on the performance of the gate driver chip due to its transmission delay and reliability. In the driver chip, the level shift is implemented based on a high-voltage LDMOS device, which has a large drain-source parasitic capacitance CDS. When common-mode noise dV / dt occurs, due to the presence of parasitic capacitance CDS, the output node of the level shift circuit cannot keep up with the transient jump speed of the high-side floating power supply voltage rail and generates glitches. When dV / dt is large, it is easy to cause the subsequent circuit to be mistriggered and produce erroneous outputs, that is, the common-mode transient noise suppression capability (CMTI) of the level shift circuit is insufficient. In order to improve the CMTI capability of the level shift circuit, it is necessary to filter out the glitches caused by dV / dt noise. The traditional solution is to add an RC filter circuit to the post-stage of the high-voltage level shift circuit, but this solution is at the expense of the operating frequency of the driver chip, which is obviously not suitable for high-frequency GaN driver chips. In addition, the current high-voltage level shift circuit mostly adopts the method of identifying the voltage drop at the output end. This identification method has two disadvantages: first, the LDMOS drain-source parasitic capacitance will introduce a low-frequency pole in the signal transmission path, slowing down the signal response speed and increasing the transmission delay; second, due to the large reverse conduction voltage drop of the GaN power device, the switch node voltage drops to a heavier negative voltage during the dead time, changing the threshold voltage of the subsequent circuit of the level shift circuit, resulting in output error logic and insufficient resistance to negative voltage of the switch node. In addition to the above problems, the triggering method of the traditional level shift circuit will also affect the delay and power consumption of the circuit. If the level shift adopts the pulse control method, an RS trigger must be added in the subsequent stage to latch the level state. However, the use of the RS trigger will increase the transmission delay of the level. If the level control method is adopted, although the subsequent RS trigger is not required to store the level state, there will always be a path between the floating voltage and the ground, resulting in greater power consumption.

[0003] In summary, the traditional high-voltage level shift circuit has a contradictory and restrictive relationship among transmission delay, CMTI capability, ability to resist negative voltage of switching nodes, and power consumption. It cannot be applied to high-speed, high-reliability GaN driver chips. It is necessary to design a high-voltage level shift circuit with high speed, high reliability and low power consumption. Summary of the invention

[0004] In view of the shortcomings of the prior art, the present invention provides a high-voltage level shift circuit suitable for a GaN driver chip to solve the problem of mutual constraints among transmission delay, CMTI capability, ability to resist negative pressure of switching nodes, and power consumption in traditional high-voltage level shift circuits, thereby improving the operating frequency and reliability of the driver chip.

[0005] The present invention is achieved through the following technical solutions:

[0006] A high-voltage level shift circuit suitable for a GaN driver chip, which converts a signal in a low-voltage domain into a signal in a high-voltage domain, includes a voltage-to-current signal module, a current mirror module, a push-pull output module, a current compensation branch and a signal maintenance module;

[0007] The voltage-to-current signal module is used to convert the PWM voltage signal into a current signal, the current mirror module is used to mirror the current signal converted from the PWM voltage as the input signal of the push-pull output module, the push-pull output module converts the current signal into a voltage signal in the high-voltage domain, the current compensation branch is used to compensate for the current of the node, and the signal maintenance module provides a small current for maintaining the established signal state.

[0008] Optionally, the voltage-to-current signal module includes two left and right branches, the left voltage-to-current signal branch is composed of a PMOS tube P1, an NMOS tube N3, an NMOS tube N5, a capacitor C1, an LDMOS tube LD1, a PMOS tube P3, and a buffer buf, and the right voltage-to-current signal branch is composed of a PMOS tube P2, an NMOS tube N4, an NMOS tube N6, a capacitor C2, an LDMOS tube LD2, a PMOS tube P4, and an inverter inv;

[0009] The source terminal of P1 is connected to the power supply voltage VDD, the drain terminal is connected to the drain terminal of N5, the source terminal of LD1, the output terminal of the gate terminal buf, the input terminal of inv, the gate terminal of N5, and the gate terminal of N4; one end of C1 is connected to node C, and the other end is grounded; the source terminal of N5 is connected to node C; the gate terminal of LD1 is connected to the power supply voltage VDD, and the drain terminal is connected to node A; the source terminal of P3 is connected to the high-side floating power supply voltage VBST, and the gate terminal and the drain terminal are connected to node A; the drain terminal of N3 tube is connected to node C, the source terminal is grounded, and the gate terminal is connected to the input terminal of inv, the gate terminal of P2, and the gate terminal of N6; the input terminal of buf is connected to PWM;

[0010] The source terminal of P2 is connected to the power supply voltage VDD, and the drain terminal is connected to the drain terminal of N6 and the source terminal of LD2; one terminal of C2 is connected to node D, and the other terminal is grounded; the source terminal of N6 is connected to node D; the gate terminal of LD2 is connected to the power supply voltage VDD, and the drain terminal is connected to node B; the source terminal of P4 is connected to the high-side floating power supply voltage VBST, and the gate and drain terminals are connected to node B; the drain terminal of N4 tube is connected to node D, and the source terminal is grounded.

[0011] The LDMOS tubes LD1 and LD2 are both single-sided high-voltage resistant devices.

[0012] The device sizes of P1 and P2, N3 and N4, N5 and N6, LD1 and LD2, P3 and P4 are set to be consistent, and the capacitance values ​​of C1 and C2 are set to be consistent.

[0013] Optionally, the current mirror module includes PMOS tube P3, PMOS tube P5, PMOS tube P4, and PMOS tube P6, the source of P5 is connected to the high-side floating power supply voltage VBST, the drain is connected to the output node OUT+, and the gate is connected to node A; the source of P6 is connected to the high-side floating power supply voltage VBST, the drain is connected to the output node OUT-, and the gate is connected to node B.

[0014] The device sizes of P5 and P6 are set to be consistent.

[0015] Optionally, the push-pull output module includes a PMOS tube P5, an NMOS tube N7, a PMOS tube P6, and an NMOS tube N8, the source terminal of N7 is connected to the high-side floating power ground VSW, and the drain terminal and the gate terminal are connected to the output node OUT+ and the gate terminal of N8; the source terminal of N8 is connected to the high-side floating power ground VSW, and the drain terminal is connected to the output node OUT-.

[0016] The device sizes of N7 and N8 are set to be consistent.

[0017] Optionally, the current compensation branch includes two left and right branches. The left current compensation branch compensates the current of node A and is composed of PMOS tube P7 and PMOS tube P9; the right current compensation branch compensates the current of node B and is composed of PMOS tube P8 and PMOS tube P10.

[0018] The source terminal of P7 is connected to the high-side floating power supply voltage VBST, the gate terminal is connected to node B, and the drain terminal is connected to the source terminal of P9; the gate terminal and the drain terminal of P9 are connected to node A; the source terminal of P8 is connected to the high-side floating power supply voltage VBST, the gate terminal is connected to node A, and the drain terminal is connected to the source terminal of P10; the gate terminal and the drain terminal of P10 are connected to node B.

[0019] The device size settings of P7 are consistent with those of P8, P9 and P10.

[0020] Optionally, the signal maintaining module includes a bias current source Ibias, an NMOS tube N0, an NMOS tube N1, and an NMOS tube N2;

[0021] One end of the bias current source Ibias is connected to the power supply voltage VDD, and the other point is connected to the drain and gate of N0, the gate of N1, and the gate of N2; the source of N0 is grounded; the drain of N1 is connected to node C, and the source is grounded; the drain of N2 is connected to node D, and the source is grounded.

[0022] The device sizes of N1 and N2 are set to be consistent.

[0023] The beneficial effects of the present invention are:

[0024] 1. While improving the CMTI capability of the high-voltage level shift circuit, it also reduces the signal transmission delay. It is not only suitable for traditional high-voltage floating gate driver chips, but also for driver chips of third-generation semiconductor power devices;

[0025] 2. Low power consumption, greatly reducing the dynamic power consumption during the switching process;

[0026] 3. Improved the ability to resist negative pressure at switch nodes;

[0027] 4. The circuit structure is simple, avoiding additional costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0029] Figure 1 It is a schematic diagram of the topology of a conventional high voltage level shift circuit;

[0030] Figure 2 It is a topological schematic diagram of a high-voltage level shift circuit applicable to a GaN driver chip provided by the present invention. DETAILED DESCRIPTION

[0031] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0032] Embodiment 1:

[0033] See also Figure 2As shown: The embodiment of the present invention specifically discloses a technical solution of a high-voltage level shift circuit suitable for a GaN driver chip, which converts a signal in a low-voltage domain into a signal in a high-voltage domain, including a voltage-to-current signal module, a current mirror module, a push-pull output module, a current compensation branch and a signal maintenance module;

[0034] The voltage-to-current signal module is used to convert the PWM voltage signal into a current signal, the current mirror module is used to mirror the current signal converted from the PWM voltage as the input signal of the push-pull output module, the push-pull output module converts the current signal into a voltage signal in the high-voltage domain, the current compensation branch is used to compensate for the current of the node, and the signal maintenance module provides a small current for maintaining the established signal state.

[0035] Specifically, the voltage-to-current signal module includes two branches, the left voltage-to-current signal branch is composed of a PMOS tube P1, an NMOS tube N3, an NMOS tube N5, a capacitor C1, an LDMOS tube LD1, a PMOS tube P3, and a buffer buf, and the right voltage-to-current signal branch is composed of a PMOS tube P2, an NMOS tube N4, an NMOS tube N6, a capacitor C2, an LDMOS tube LD2, a PMOS tube P4, and an inverter inv;

[0036] The source terminal of P1 is connected to the power supply voltage VDD, the drain terminal is connected to the drain terminal of N5, the source terminal of LD1, the output terminal of the gate terminal buf, the input terminal of inv, the gate terminal of N5, and the gate terminal of N4; one end of C1 is connected to node C, and the other end is grounded; the source terminal of N5 is connected to node C; the gate terminal of LD1 is connected to the power supply voltage VDD, and the drain terminal is connected to node A; the source terminal of P3 is connected to the high-side floating power supply voltage VBST, and the gate terminal and the drain terminal are connected to node A; the drain terminal of N3 tube is connected to node C, the source terminal is grounded, and the gate terminal is connected to the input terminal of inv, the gate terminal of P2, and the gate terminal of N6; the input terminal of buf is connected to PWM;

[0037] The source terminal of P2 is connected to the power supply voltage VDD, and the drain terminal is connected to the drain terminal of N6 and the source terminal of LD2; one terminal of C2 is connected to node D, and the other terminal is grounded; the source terminal of N6 is connected to node D; the gate terminal of LD2 is connected to the power supply voltage VDD, and the drain terminal is connected to node B; the source terminal of P4 is connected to the high-side floating power supply voltage VBST, and the gate and drain terminals are connected to node B; the drain terminal of N4 tube is connected to node D, and the source terminal is grounded.

[0038] The LDMOS tubes LD1 and LD2 are both single-sided high-voltage resistant devices.

[0039] The device sizes of P1 and P2, N3 and N4, N5 and N6, LD1 and LD2, P3 and P4 are set to be consistent, and the capacitance values ​​of C1 and C2 are set to be consistent.

[0040] Specifically, the current mirror module includes PMOS tube P3, PMOS tube P5, PMOS tube P4, and PMOS tube P6, the source terminal of P5 is connected to the high-side floating power supply voltage VBST, the drain terminal is connected to the output node OUT+, and the gate terminal is connected to node A; the source terminal of P6 is connected to the high-side floating power supply voltage VBST, the drain terminal is connected to the output node OUT-, and the gate terminal is connected to node B.

[0041] The device sizes of P5 and P6 are set to be consistent.

[0042] Specifically, the push-pull output module includes a PMOS tube P5, an NMOS tube N7, a PMOS tube P6, and an NMOS tube N8. The source terminal of N7 is connected to the high-side floating power ground VSW, and the drain terminal and the gate terminal are connected to the output node OUT+ and the gate terminal of N8; the source terminal of N8 is connected to the high-side floating power ground VSW, and the drain terminal is connected to the output node OUT-.

[0043] The device sizes of N7 and N8 are set to be consistent.

[0044] Specifically, the current compensation branch includes two branches, the left current compensation branch compensates the current of node A and is composed of PMOS tube P7 and PMOS tube P9; the right current compensation branch compensates the current of node B and is composed of PMOS tube P8 and PMOS tube P10.

[0045] The source terminal of P7 is connected to the high-side floating power supply voltage VBST, the gate terminal is connected to node B, and the drain terminal is connected to the source terminal of P9; the gate terminal and the drain terminal of P9 are connected to node A; the source terminal of P8 is connected to the high-side floating power supply voltage VBST, the gate terminal is connected to node A, and the drain terminal is connected to the source terminal of P10; the gate terminal and the drain terminal of P10 are connected to node B.

[0046] The device size settings of P7 are consistent with those of P8, P9 and P10.

[0047] Specifically, the signal maintaining module includes a bias current source Ibias, an NMOS tube N0, an NMOS tube N1, and an NMOS tube N2;

[0048] One end of the bias current source Ibias is connected to the power supply voltage VDD, and the other point is connected to the drain and gate of N0, the gate of N1, and the gate of N2; the source of N0 is grounded; the drain of N1 is connected to node C, and the source is grounded; the drain of N2 is connected to node D, and the source is grounded.

[0049] The device sizes of N1 and N2 are set to be consistent.

[0050] Figure 2The invention proposes a high-voltage circuit shift circuit suitable for a GaN driver chip, which comprises two symmetrical branches. P1, N3, N5, C1, LD1, P3 and P5 constitute a left voltage-to-current signal path, and P2, N4, N6, C2, LD2, P4 and P6 constitute a right voltage-to-current signal path. P3 and P5 and P4 and P6 respectively constitute two groups of current mirror structures, which respectively mirror the current signals of PWM voltage conversion on both sides, thereby avoiding the low-frequency poles introduced by the parasitic capacitance of the LDMOS device at the key nodes A and B, and improving the response speed of the circuit to the PWM signal.

[0051] Specifically, P5, N7 and P6, N8 respectively constitute two pairs of push-pull output structures for current comparison, and the output voltage is approximately rail-to-rail, thereby ensuring that when the switch node voltage enters a heavier negative voltage during the dead time, the output state can still be correctly established and correctly identified by the subsequent circuit, thereby improving the circuit's ability to resist negative pressure at the switch node.

[0052] Specifically, P7, P9 and P8, P10 respectively constitute two groups of dynamic large current compensation branches, which compensate the key nodes A and B when dV / dt occurs. Under normal conditions, both compensation branches are not turned on, and there is no static power consumption. When dV / dt occurs, relative to VBST, due to the influence of the LD1 and LD2 drain-source parasitic capacitance, the A and B nodes will be pulled down at the same time, and the compensation branch will be turned on to compensate for the dynamic current Ic, increase the floating slew rate of nodes A and B, and improve the circuit's ability to resist CMTI. By optimizing the compensation current, the burrs of the output node can be controlled to the order of tens of mV, avoiding the use of the post-stage RC filter circuit and reducing the level transmission delay.

[0053] Specifically, in terms of the response mode of the level shift circuit, the inventors have proposed an innovative and ingenious solution to achieve both delay and power consumption. The following is an example of PWM jumping from a low level to a high level. First, although the level shift circuit adopts a level triggering mode, capacitors C1 and C2 are added between VBST and the ground. When the high level arrives, P1 is turned off, N5 is turned on, C1 is instantly charged, and A is instantly pulled down; at the same time, P2 is turned on, N6 is turned off, B is quickly pulled up close to VBST, and the voltage mutations at points A and B are responded to by the current mirror, changing the output state. N4 is turned on, C2 is discharged, and the PWM signal jumps. N0, N1, and N2 constitute a small bias current to maintain the established output state. The compromise response method avoids the use of the subsequent RS trigger, reduces the delay of the level shift circuit, and reduces power consumption due to the absence of a DC path.

[0054] Comparative Example 1:

[0055] Figure 1The figure shows a commonly used high-voltage level shift circuit structure, in which M1 and M2 are high-voltage resistant LDMOS devices. This structure uses a pulse triggering method to reduce the power consumption of the level shift circuit while ensuring a certain conversion speed. During the hard switch switching process, the large current pulse on the switch node forms dV / dt noise through the parasitic inductance, and the dV / dt will be coupled to the high-side floating power rail through the bootstrap path. Due to the large drain-source parasitic capacitance CDS of the LDMOS tubes M1 and M2, when dV / dt arrives, the voltage of the A and B nodes cannot keep up with the transient jump speed of the high-side floating power rail and produce glitches. In a low-frequency environment, due to the small dV / dt noise, the voltage glitches of the A and B nodes will not trigger the trigger threshold VT of the subsequent RS trigger. However, in a high-frequency environment, the dV / dt noise is large, and the voltage glitches of the A and B nodes will be larger, reaching below the trigger level VT, changing the output state of the subsequent RS trigger, affecting the transmission of the gate drive signal and the circuit reliability. To improve reliability, a common solution is to add an RC filter between the A and B nodes and the RS trigger, but this will result in a loss in conversion speed, thereby limiting the operating frequency of the half-bridge drive circuit.

[0056] In addition, the commonly used high-voltage level shift structure uses the method of identifying voltage drop at the output end, which will bring two disadvantages: 1. Due to the large drain-source parasitic capacitance CDS of LDMOS tubes M1 and M2, low-frequency nodes will be introduced in the signal transmission path, and the method of identifying voltage drop will increase the transmission delay of the signal; 2. Due to the large reverse conduction voltage drop of GaN power devices, the voltage at the switch node will drop to a heavier negative voltage during the dead time, changing the threshold voltage of the subsequent RS trigger, resulting in output error logic. In summary, the commonly used high-voltage level shift circuit structure is no longer suitable for GaN driver chips.

[0057] Compared with comparative example 1, embodiment 1 of the present invention has the following advantages: compared with the traditional high-voltage level shift circuit structure, the level shift circuit proposed in the high-voltage level shift circuit of the present invention adopts a high-bandwidth current mirror structure as the basis, avoids the low-frequency pole introduced by the LDMOS parasitic capacitor at the key node of signal transmission, and reduces the transmission delay; introduces a dynamic current compensation branch at the key node to improve the CMTI capability, and at the same time abandons the use of the post-stage RC filter circuit, further reducing the transmission delay; adopts a push-pull structure to achieve rail-to-rail output, and improves the circuit's ability to resist negative pressure at the switch node; uses the addition of capacitance on the response branch to change the response mode of the level shift circuit to the input signal, block the DC path, and reduce dynamic power consumption. The proposed high-voltage level shift circuit can effectively solve the contradiction between power consumption, transmission delay, CMTI capability, and ability to resist negative pressure at the switch node in the traditional high-voltage level shift circuit.

[0058] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A high-voltage level shift circuit suitable for a GaN driver chip, which converts a signal in a low-voltage domain into a signal in a high-voltage domain, characterized in that: It includes a voltage-to-current signal module, a current mirror module, a push-pull output module, a current compensation branch and a signal maintenance module; The voltage-to-current signal module is used to convert the PWM voltage signal into a current signal, the current mirror module is used to mirror the current signal converted by the PWM voltage as the input signal of the push-pull output module, the push-pull output module converts the current signal into a voltage signal in the high-voltage domain, the current compensation branch is used to compensate for the current of the node, and the signal maintenance module provides a small current for maintaining the established signal state; The voltage-to-current signal module includes two left and right branches. The left voltage-to-current signal branch is composed of a PMOS tube P1, an NMOS tube N3, an NMOS tube N5, a capacitor C1, an LDMOS tube LD1, a PMOS tube P3, and a buffer buf. The right voltage-to-current signal branch is composed of a PMOS tube P2, an NMOS tube N4, an NMOS tube N6, a capacitor C2, an LDMOS tube LD2, a PMOS tube P4, and an inverter inv. The source terminal of P1 is connected to the power supply voltage VDD, the drain terminal is connected to the drain terminal of N5, the source terminal of LD1, the output terminal of the gate terminal buf, the input terminal of inv, the gate terminal of N5, and the gate terminal of N4; one end of C1 is connected to node C, and the other end is grounded; the source terminal of N5 is connected to node C; the gate terminal of LD1 is connected to the power supply voltage VDD, and the drain terminal is connected to node A; the source terminal of P3 is connected to the high-side floating power supply voltage VBST, and the gate terminal and the drain terminal are connected to node A; the drain terminal of N3 tube is connected to node C, the source terminal is grounded, and the gate terminal is connected to the input terminal of inv, the gate terminal of P2, and the gate terminal of N6; the input terminal of buf is connected to PWM; The source terminal of P2 is connected to the power supply voltage VDD, and the drain terminal is connected to the drain terminal of N6 and the source terminal of LD2; one terminal of C2 is connected to node D, and the other terminal is grounded; the source terminal of N6 is connected to node D; the gate terminal of LD2 is connected to the power supply voltage VDD, and the drain terminal is connected to node B; the source terminal of P4 is connected to the high-side floating power supply voltage VBST, and the gate terminal and the drain terminal are connected to node B; the drain terminal of N4 tube is connected to node D, and the source terminal is grounded; The current mirror module includes PMOS tube P3, PMOS tube P5, PMOS tube P4, and PMOS tube P6, wherein the source of P5 is connected to the high-side floating power supply voltage VBST, the drain is connected to the output node OUT+, and the gate is connected to the node A; the source of P6 is connected to the high-side floating power supply voltage VBST, the drain is connected to the output node OUT-, and the gate is connected to the node B; The push-pull output module includes a PMOS tube P5, an NMOS tube N7, a PMOS tube P6, and an NMOS tube N8. The source terminal of N7 is connected to the high-side floating power ground VSW, and the drain terminal and the gate terminal are connected to the output node OUT+ and the gate terminal of N8; the source terminal of N8 is connected to the high-side floating power ground VSW, and the drain terminal is connected to the output node OUT-; The current compensation branch includes two branches, the left current compensation branch compensates the current of node A and is composed of PMOS tube P7 and PMOS tube P9; the right current compensation branch compensates the current of node B and is composed of PMOS tube P8 and PMOS tube P10; The source terminal of P7 is connected to the high-side floating power supply voltage VBST, the gate terminal is connected to node B, and the drain terminal is connected to the source terminal of P9; the gate terminal and the drain terminal of P9 are connected to node A; the source terminal of P8 is connected to the high-side floating power supply voltage VBST, the gate terminal is connected to node A, and the drain terminal is connected to the source terminal of P10; the gate terminal and the drain terminal of P10 are connected to node B; The signal maintaining module includes a bias current source Ibias, an NMOS tube N0, an NMOS tube N1, and an NMOS tube N2; One end of the bias current source Ibias is connected to the power supply voltage VDD, and the other point is connected to the drain and gate of N0, the gate of N1, and the gate of N2; the source of N0 is grounded; the drain of N1 is connected to node C, and the source is grounded; the drain of N2 is connected to node D, and the source is grounded.

2. A high voltage level shift circuit suitable for a GaN driver chip according to claim 1, characterized in that: When working, it includes two symmetrical branches, the P1, N3, N5, C1, LD1, P3, P5 constitute the left voltage-to-current signal path, the P2, N4, N6, C2, LD2, P4, P6 constitute the right voltage-to-current signal path, P3, P5 and P4, P6 respectively constitute two groups of current mirror structures, respectively mirroring the current signals converted by PWM voltage on both sides.

3. The high-voltage level shift circuit suitable for a GaN driver chip according to claim 2, characterized in that: When working, P5, N7 and P6, N8 respectively form two pairs of current comparison push-pull output structures, and the output voltage is approximately rail-to-rail.

4. The high-voltage level shift circuit suitable for a GaN driver chip according to claim 3, characterized in that: When working, P7, P9 and P8, P10 respectively constitute two groups of dynamic large current compensation branches, which compensate the key nodes A and B respectively when dV / dt occurs; in normal state, both compensation branches are not turned on and there is no static power consumption. When dV / dt occurs, relative to VBST, due to the influence of the drain-source parasitic capacitance of LD1 and LD2, the A and B nodes will be pulled down at the same time, and the compensation branch will be turned on to compensate the dynamic current Ic, increase the floating slew rate of nodes A and B, and improve the circuit's ability to resist CMTI; when optimizing the compensation current, the burrs of the output node can be controlled to the order of tens of mV, avoiding the use of the post-stage RC filter circuit and reducing the transmission delay of the level.

5. The high-voltage level shift circuit suitable for a GaN driver chip according to claim 4, characterized in that: When working, first, although the level shift circuit adopts the level triggering mode, it will add capacitors C1 and C2 between VBST and ground; when the high level comes, P1 is turned off, N5 is turned on, C1 is charged instantly, and A will be pulled down instantly; at the same time, P2 is turned on, N6 is turned off, B will be quickly pulled up close to VBST, and the voltage mutations at points A and B will be responded by the current mirror, changing the output state; N4 is turned on, discharging C2, waiting for the jump of the PWM signal; N0, N1, and N2 constitute a small bias current to maintain the established output state.

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