Analog-to-digital conversion circuit, analog-to-digital conversion device, and digital x-ray imaging system

Abstract

The application relates to an analog-digital conversion circuit, an analog-digital conversion device and a digital X-ray imaging system. The analog-digital conversion circuit comprises a first reference voltage source and a second reference voltage source; a first analog-digital converter connected with the first reference voltage source; a second analog-digital converter connected with the second reference voltage source; a connecting circuit connected with the first analog-digital converter and the second analog-digital converter respectively; and a negative temperature coefficient current source connected with the first reference voltage source and the second reference voltage source respectively.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of analog-digital circuit, in particular to an analog-digital conversion circuit, an analog-digital conversion device and a digital X-ray imaging system. BACKGROUND

[0002] Two-stage analog-digital converters are usually applied in high-definition image, video processing and wireless communication fields due to their good comprehensive performance among high speed, high precision and low power consumption. Two-stage analog-digital converters can also be applied in digital X-ray imaging systems.

[0003] In the prior art, there is a gain error problem caused by the mismatch between the reference voltage source of the first-stage analog-digital converter and the reference voltage source of the second-stage analog-digital converter in the two-stage analog-digital converter. SUMMARY

[0004] Therefore, it is necessary to provide an analog-digital conversion circuit, an analog-digital conversion device and a digital X-ray imaging system to solve the gain error problem caused by the mismatch between the reference voltage source of the first-stage analog-digital converter and the reference voltage source of the second-stage analog-digital converter in the two-stage analog-digital converter.

[0005] An analog-digital conversion circuit comprises:

[0006] a first reference voltage source and a second reference voltage source;

[0007] a first analog-digital converter connected with the first reference voltage source;

[0008] a second analog-digital converter connected with the second reference voltage source;

[0009] a connection circuit connected with the first analog-digital converter and the second analog-digital converter respectively, and

[0010] a negative temperature coefficient current source comprising a negative temperature coefficient voltage buffer circuit connected with the first reference voltage source and the second reference voltage source respectively;

[0011] The negative temperature coefficient voltage buffer circuit is configured to reduce the influence of temperature change on the output voltage of the first reference voltage source and the output voltage of the second reference voltage source.

[0012] In one embodiment, the analog-digital conversion circuit is a two-stage analog-digital converter.

[0013] In one embodiment, the negative temperature coefficient current source further comprises:

[0014] a negative temperature coefficient voltage generation circuit connected with the negative temperature coefficient voltage buffer circuit.

[0015] In one embodiment, the negative temperature coefficient current source further comprises:

[0016] A start-up circuit connected with the negative temperature coefficient voltage generating circuit.

[0017] In one embodiment, the negative temperature coefficient voltage generating circuit comprises:

[0018] A first operational amplifier, an output terminal of which is connected with the start-up circuit.

[0019] In one embodiment, the negative temperature coefficient voltage generating circuit further comprises:

[0020] A first branch connected with the inverting input terminal of the first operational amplifier and the start-up circuit;

[0021] A second branch connected with the non-inverting input terminal of the first operational amplifier and the start-up circuit, the output voltage of the negative temperature coefficient voltage generating circuit is adjusted to be negative temperature characteristic by adjusting the first branch and the second branch.

[0022] In one embodiment, the first branch comprises a transistor M5, a triode Q2 and a resistor R1.

[0023] The second branch comprises a transistor M6, a triode Q3 and a resistor R2.

[0024] The output voltage of the negative temperature coefficient voltage generating circuit is adjusted to be negative temperature coefficient characteristic by adjusting the ratio of the resistor R2 and the resistor R1.

[0025] In one embodiment, the negative temperature coefficient voltage generating circuit further comprises:

[0026] A second operational amplifier, an inverting input terminal of which is connected with the drain of the transistor M6, an output terminal of which is connected with the first reference voltage source and the second reference voltage source.

[0027] An analog-to-digital conversion device comprising the analog-to-digital conversion circuit.

[0028] A digital X-ray imaging system comprising the analog-to-digital conversion device.

[0029] The analog-to-digital conversion circuit, the analog-to-digital conversion device and the digital X-ray imaging system provided by the embodiment of the present application, the negative temperature coefficient voltage buffer circuit in the negative temperature coefficient current source is connected with the first reference voltage source and the second reference voltage source respectively. The negative temperature coefficient voltage buffer circuit is used for reducing the influence of temperature change on the output voltage of the first reference voltage source and the output voltage of the second reference voltage source. The negative temperature coefficient voltage buffer circuit can offset the lifting of the output voltage of the first reference voltage source and the output voltage of the second reference voltage source caused by the temperature rise in the high-temperature stage, and will not affect the output voltage of the first reference voltage source in the low-temperature stage. Therefore, the gain error caused by the mismatch between the first reference voltage source and the second reference voltage source is reduced or eliminated. BRIEF DESCRIPTION OF DRAWINGS

[0030] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0031] Figure 1 The structure diagram of the analog-to-digital conversion circuit provided by an embodiment of the present application is provided.

[0032] Figure 2 The structure diagram of the negative temperature coefficient current source, the first reference voltage source and the second reference voltage source provided by an embodiment of the present application is provided.

[0033] Figure 3 The structure diagram of the analog-to-digital conversion circuit provided by another embodiment of the present application is provided.

[0034] Figure 4 The schematic diagram of the negative temperature coefficient voltage generation circuit provided by an embodiment of the present application is provided.

[0035] Figure 5 The structure diagram of the analog-to-digital conversion circuit provided by another embodiment of the present application is provided.

[0036] Explanation of reference signs:

[0037] Analog-to-digital conversion circuit 10, first reference voltage source 110, second reference voltage source 120, first analog-to-digital converter 210, second analog-to-digital converter 220, connection circuit 230, intermediate amplification circuit 231, negative temperature coefficient current source 130, starting circuit 132, negative temperature coefficient voltage generation circuit 136, negative temperature coefficient voltage buffer circuit 134, gain calibration circuit 140, first operational amplifier 112, second operational amplifier 114, first branch 137, second branch 138. DETAILED DESCRIPTION

[0038] In order to make the purposes, technical solutions and advantages of the present application clearer, the present application will be further described in detail through embodiments and in conjunction with the drawings. It should be understood that the specific embodiments described herein are only used to explain the present application and not used to limit the present application.

[0039] The serial numbers of components in the present application, such as "first", "second", etc., are only used to distinguish the described objects, and do not have any sequence or technical meaning. In the present application, "connection" and "coupling" include direct and indirect connection (coupling) unless otherwise specified. In the description of the present application, it should be understood that the orientation or positional relationship indicated by the terms "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application.

[0040] In the present application, unless otherwise expressly specified and limited, the first feature is "on" or "under" the second feature, which can be direct contact between the first and second features, or indirect contact between the first and second features through an intermediate medium. Moreover, the first feature "above", "above" and "above" the second feature can be directly above or obliquely above the first feature, or only indicate that the horizontal height of the first feature is higher than that of the second feature. The first feature "below", "below" and "below" the second feature can be directly below or obliquely below the first feature, or only indicate that the horizontal height of the first feature is less than that of the second feature.

[0041] Please refer to Figure 1 The embodiment of the present application provides an analog-to-digital conversion circuit 10. The analog-to-digital conversion circuit 10 comprises a first reference voltage source 110, a second reference voltage source 120, a first analog-to-digital converter 210, a second analog-to-digital converter 220, a connection circuit 230 and a negative temperature coefficient current source 130. The first analog-to-digital converter 210 is connected with the first reference voltage source 110. The second analog-to-digital converter 220 is connected with the second reference voltage source 120. The connection circuit 230 is connected with the first analog-to-digital converter 210 and the second analog-to-digital converter 220 respectively. The negative temperature coefficient current source 130 is connected with the first reference voltage source 110 and the second reference voltage source 120 respectively. The negative temperature coefficient current source 130 is used to reduce the influence of temperature change on the output voltage of the first reference voltage source 110 and the output voltage of the second reference voltage source 120.

[0042] The first reference voltage source 110 and the second reference voltage source 120 can be integrated in a chip. An external power source is input into the chip, and after being output by the first reference voltage source 110 and the second reference voltage source 120, the external power source serves as the reference level of the first analog-to-digital converter 210 and the second analog-to-digital converter 220, respectively.

[0043] In a digital X-ray imaging system, when X-rays irradiate an imaging plate, electric charges are generated, and the electric charges are converted into voltages. The voltages are sampled and quantized by two-stage analog-to-digital converters. The first analog-to-digital converter 210 can perform coarse quantization on a sampling signal, and output a digital code and a residual signal. The residual signal can be sampled by the second analog-to-digital converter 220 after being scaled by the connection circuit 230. The residual signal is further finely quantized, and a digital code is output. After the output codes of the first analog-to-digital converter 210 and the second analog-to-digital converter 220 are processed by a digital circuit, a 16-bit digital code can be obtained. After the digital code is processed by an FPGA, the digital code is processed by image processing software to form real image information.

[0044] In this embodiment, the analog-to-digital conversion circuit 10 can include n reference voltage sources, n analog-to-digital converters, m connection circuits 230, and m negative temperature coefficient current sources 130, where n can be an integer greater than or equal to 2, and m can be an integer greater than or equal to 1.

[0045] Each reference voltage source in the analog-to-digital conversion circuit 10 is connected to a corresponding analog-to-digital converter. If m is less than or equal to (n-1) and greater than or equal to 1, at least one negative temperature coefficient current source 130 in the analog-to-digital conversion circuit 10 is connected to at least two reference voltage sources, and each connection circuit 230 is connected to at least two analog-to-digital converters. The negative temperature coefficient current source 130 is used to reduce the influence of temperature changes on the output voltage of each reference voltage source. The circuit structure and working principle of each reference voltage source in the analog-to-digital conversion circuit 10 can be the same as those of the first reference voltage source 110 and the second reference voltage source 120. The circuit structure and working principle of each analog-to-digital converter in the analog-to-digital conversion circuit 10 can be the same as those of the first analog-to-digital converter 210 and the second analog-to-digital converter 220.

[0046] In this embodiment, the analog-to-digital conversion circuit 10 is a two-stage analog-to-digital converter. The connection circuit 230 includes an intermediate amplification circuit 231 connected to the first analog-to-digital converter 210 and the second analog-to-digital converter 220, respectively.

[0047] Taking the two-stage analog-to-digital converter as an example, the two-stage analog-to-digital converter is composed of a first analog-to-digital converter and a second analog-to-digital converter, and the connection circuit 230 includes an intermediate amplification circuit 231.

[0048] The analog-to-digital conversion circuit 10 will generate temperature change during operation, and the temperature will rise during long-time continuous operation. The temperature change of the analog-to-digital conversion circuit 10 will cause the output voltage of the first reference voltage source 110 and the second reference voltage source 120 to deviate, thus causing an unpredictable mismatch between the first reference voltage source 110 and the second reference voltage source 120, which seriously affects the accuracy and linearity of the analog-to-digital converter. The negative temperature coefficient current source 130 is connected to the first reference voltage source 110 and the second reference voltage source 120, respectively. The negative temperature coefficient current source 130 is used to reduce the influence of temperature change on the output voltage of the first reference voltage source 110 and the output voltage of the second reference voltage source 120. The negative temperature coefficient current source 130 can offset the lifting of the output voltage of the first reference voltage source 110 and the output voltage of the second reference voltage source 120 caused by temperature rise in the high-temperature stage, and will not affect the output voltage of the first reference voltage source 110 and the output voltage of the second reference voltage 120 in the low-temperature stage. Thus, the gain error caused by the mismatch between the first reference voltage source 110 and the second reference voltage source 120 is reduced or eliminated.

[0049] Please refer to Figure 2 In an embodiment, the negative temperature coefficient current source 130 includes a negative temperature coefficient voltage buffer circuit 134 connected to the first reference voltage source 110 and the second reference voltage source 120, respectively. The negative temperature coefficient current source 130 further includes a negative temperature coefficient voltage generation circuit 136 connected to the negative temperature coefficient voltage buffer circuit 134. The negative temperature coefficient voltage generation circuit 136 can offset the lifting of the output voltage of the first reference voltage source 110 and the output voltage of the second reference voltage source 120 caused by temperature rise in the high-temperature stage, and will not affect the output voltage of the first reference voltage source 110 and the output voltage of the second reference voltage 120 in the low-temperature stage. The negative temperature coefficient voltage buffer circuit 134 can play an isolating role. The negative temperature coefficient voltage buffer circuit 134 can make the output voltage VBG of the negative temperature coefficient voltage generation circuit 136 not be disturbed by the rear stage, and improve the stability.

[0050] In an embodiment, the negative temperature coefficient current source 130 further includes a start-up circuit 132. The negative temperature coefficient voltage generation circuit 136 is connected to the start-up circuit 132. The start-up circuit 132 can be used to ensure that the analog-to-digital conversion circuit 10 can be normally started when powered on. The start-up circuit 132 can also be turned off after the analog-to-digital conversion circuit 10 is powered on to reduce power consumption.

[0051] Please refer to Figure 3 In one embodiment, the start-up circuit 132 comprises a transistor M1, a transistor M2, a transistor M3, a resistor R0 and a transistor M7. The source of the transistor M1 is connected to ground. The drain of the transistor M1 is connected to the drain of the transistor M2. The source of the transistor M2 is connected to an external power supply. The gate of the transistor M1 and the gate of the transistor M2 are connected together. The first end of the resistor R0 is connected to the gate of the transistor M1, the gate of the transistor M2 and the drain of the transistor M3 respectively. The second end of the resistor R0 is connected to ground. The source of the transistor M3 is connected to an external power supply. The gate of the transistor M7 is connected to the drain of the transistor M1 and the drain of the transistor M2 respectively. The drain of the transistor M7 is connected to the gate of the transistor M3 and the negative temperature coefficient voltage generating circuit 136 respectively. The source of the transistor M7 is connected to ground. The transistor M2 and the transistor M3 can be P-type MOS transistors. The transistor M1 and the transistor M7 can be N-type MOS transistors.

[0052] In one embodiment, the negative temperature coefficient voltage generating circuit 136 comprises a first operational amplifier 112. The negative temperature coefficient voltage generating circuit 136 further comprises a first branch 137 and a second branch 138. The first branch 137 is connected to the inverting input of the first operational amplifier 112 and the start-up circuit 132. The second branch 138 is connected to the non-inverting input of the first operational amplifier 112 and the start-up circuit 132. By adjusting the ratio of the resistors in the first branch 137 and the second branch 138, the output voltage of the negative temperature coefficient voltage generating circuit 136 is adjusted to have a negative temperature characteristic.

[0053] In one embodiment, the first branch 137 is used to generate a positive temperature coefficient current, which provides current to the second branch 138 by mirroring. The second branch 138 is used to generate a bandgap output voltage V BG .

[0054] In one embodiment, the first branch 137 comprises a transistor M5, a transistor Q2 and a resistor R1. The second branch 138 comprises a transistor M6, a transistor Q3 and a resistor R2.

[0055] In one embodiment, based on the bandgap output voltage V BG generated by the negative temperature coefficient voltage generating circuit 136, by adjusting the ratio of the resistor R2 and the resistor R1, the output voltage of the negative temperature coefficient voltage generating circuit 136 is adjusted to have a negative temperature coefficient characteristic.

[0056] In one embodiment, the negative temperature coefficient voltage generating circuit 136 comprises a transistor M4 and a triode Q1. The first branch 137 comprises a transistor M5 and a triode Q2. The second branch 138 comprises a transistor M6 and a triode Q3. The drain of the transistor M4 is connected to the emitter of the triode Q1. The source of the transistor M4 is connected to an external power source. The gate of the transistor M4 is connected to the output of the first operational amplifier 112. The collector of the triode Q1 and the base of the triode Q1 are connected to ground. The inverting input of the first operational amplifier 112 is connected to the drain of the transistor M4 and the emitter of the triode Q1 respectively. The gate of the transistor M5 is connected to the gate of the transistor M4. The source of the transistor M5 is connected to an external power source. The drain of the transistor M5 is connected to the first end of the resistor R1 and the non-inverting input of the first operational amplifier 112 respectively. The second end of the resistor R1 is connected to the emitter of the triode Q2. The collector and the base of the triode Q2 are connected to ground. The source of the transistor M6 is connected to an external power source. The drain of the transistor M6 is connected to the first end of the resistor R2 and the negative temperature coefficient voltage buffer circuit 134 respectively. The gate of the transistor M6 is connected to the output of the first operational amplifier 112. The second end of the resistor R2 is connected to the emitter of the triode Q3. The collector and the base of the triode Q3 are connected to ground.

[0057] The transistor M4, the transistor M5 and the transistor M6 can be P-type MOS transistors. The transistor M7 can be an N-type MOS transistor.

[0058] The transistor M1 and the transistor M2 constitute an inverter. The first end of the resistor R0 is connected to the gate of the transistor M1 and the gate of the transistor M2 to generate the input of the inverter. In the power-on stage, the gate voltage of the transistor M2 can be low level, and the output of the inverter is high level. At this time, the transistor M7 is turned on. The transistor M7 turns on and pulls down the gate potential of the transistor M3, the transistor M4 and the transistor M5. The transistor M3, the transistor M4 and the transistor M5 are turned on. The transistor M3, the transistor M4 and the transistor M5 generate start-up current. The voltage of the first end of the resistor R0 gradually rises. The output of the inverter jumps to low level. The transistor M7 is turned off. The start-up circuit 132 is started up.

[0059] The first operational amplifier 112 has the characteristics of virtual short and virtual open. Therefore, the first end of the resistor R1 is the emitter-base voltage V BE1 of the triode Q1. The potential of the second end of the resistor R1 is the emitter-base voltage V BE2, so that the resistance R1 voltage is ΔV BE = V BE1 - V BE2 The resistance R1 branch produces a current of ΔV BE / R1, and the current is shown as a positive correlation with temperature characteristics, after the transistor M6 mirror produces the triode Q3 branch current. The resistance R2 voltage plus the triode Q3 emitter-base voltage V BE3 The bandgap reference output voltage V BG , expressed as: V BG = R2 x ΔV BE / R1 + V BE3 Since the emitter-base voltage V BE3 shows a negative correlation with temperature characteristics, the temperature characteristics of the voltage VBG can be adjusted by the ratio of the resistance R2 and the resistance R1. Therefore, the temperature characteristics of the output voltage V BG can be adjusted to a negative temperature coefficient characteristic.

[0060] Please refer to Figure 4 In one embodiment, unlike the negative temperature coefficient voltage generating circuit 136 shown in Figure 3 , the negative temperature coefficient voltage generating circuit 136 in this embodiment does not include the second branch 138. The negative temperature coefficient voltage generating circuit 136 includes resistance R4, resistance R1 and resistance R5. The two ends of the resistance R4 are respectively connected with the collector of the triode Q1 and the emitter of the triode Q1. The two ends of the resistance R1 are respectively connected with the non-inverting input terminal of the first operational amplifier 112 and the emitter of the triode Q2. The two ends of the resistance R5 are respectively connected with the non-inverting input terminal of the first operational amplifier 112 and the collector of the triode Q2.

[0061] The resistance R4 can have the same resistance value as the resistance R5. The resistance R1 can be used to generate a positive temperature coefficient current, and the resistance R2 can be used to generate an output stage current. By adjusting the ratio of the resistance R1 and the resistance R2, a negative temperature coefficient current can be obtained.

[0062] In one embodiment, the negative temperature coefficient voltage generating circuit 136 comprises a second operational amplifier 114. The inverting input of the second operational amplifier 114 is connected to the drain of the transistor M6, and the output of the second operational amplifier 114 is connected to the first reference voltage source 110 and the second reference voltage source 120. The negative temperature coefficient voltage generating circuit 136 further comprises a transistor M8 and a resistor R3. The source of the transistor M8 is connected to an external power source. The drain of the transistor M8 is connected to the first end of the resistor R3. The first end of the resistor R3 is connected to the non-inverting input of the second operational amplifier 114. The second end of the resistor R3 is connected to ground. After the voltage VBG is generated, the voltage VBG is applied to the resistor R3 through the second operational amplifier 114, generating a reference bias current. The second operational amplifier 114 functions as an isolation, so that the fluctuation of the subsequent circuit will not affect the output voltage VBG of the previous negative temperature coefficient voltage generating circuit 136, improving the stability of the circuit.

[0063] In one embodiment, the first reference voltage source 110 comprises a transistor M9, a transistor M10, a transistor M11, a transistor M13, a transistor M14, a transistor M12, a transistor M15, a transistor M16, a transistor M17, a transistor M18, a transistor M23, a transistor M24, a transistor M19, a transistor M20, a transistor M25, a transistor M27, a transistor M21, a transistor M22, a transistor M26, a transistor M28, and a transistor M29. The source of the transistor M9 is connected to an external power source. The drain of the transistor M9 is connected to the drain of the transistor M10. The drain of the transistor M10 is connected to the gate of the transistor M10 and the second reference voltage source 120, respectively. The source of the transistor M11 is connected to ground. The gate of the transistor M11 is connected to the gate of the transistor M10. The source of the transistor M13 is connected to an external power source. The drain of the transistor M13 is connected to the source of the transistor M14. The gate of the transistor M13 is connected to the gate of the transistor M14. The drain of the transistor M14 is connected to the drain of the transistor M11. The gate of the transistor M14 is connected to the drain of the transistor M14. The source of the transistor M12 is connected to ground. The drain of the transistor M12 is connected to the drain of the transistor M16. The gate of the transistor M12 is connected to the drain of the transistor M10. The source of the transistor M15 is connected to an external power source. The drain of the transistor M15 is connected to the source of the transistor M16. The gate of the transistor M16 is connected to the drain of the transistor M14.

[0064] The source of the transistor M17 is connected to an external power source. The drain of the transistor M17 is connected to the source of the transistor M18. The gate of the transistor M17 is connected to the gate of the transistor M15. The drain of the transistor M18 is connected to the drain of the transistor M23. The gate of the transistor M18 is connected to the gate of the transistor M16. The gate of the transistor M23 is connected to the drain of the transistor M18 and the gate of the transistor M24. The source of the transistor M23 is connected to the drain of the transistor M24.

[0065] The source of the transistor M19 is connected to an external power source. The drain of the transistor M19 is connected to the source of the transistor M20. The gate of the transistor M19 is connected to the drain of the transistor M20. The drain of the transistor M20 is connected to the drain of the transistor M25. The source of the transistor M25 is connected to the drain of the transistor M27. The gate of the transistor M27 is connected to the non-inverting terminal vip of the first reference voltage source 110. The source of the transistor M27 is connected to the source of the transistor M24.

[0066] The source of the transistor M21 is connected to an external power source. The drain of the transistor M21 is connected to the source of the transistor M22. The gate of the transistor M21 is connected to the gate of the transistor M19 and the drain of the transistor M25, respectively. The gate of the transistor M22 is connected to the gate of the transistor M20. The drain of the transistor M22 is connected to the drain of the transistor M26. The gate of the transistor M26 is connected to the gate of the transistor M25. The source of the transistor M26 is connected to the drain of the transistor M28. The source of the transistor M28 is connected to the drain of the transistor M29 and the source of the transistor M27, respectively. The gate of the transistor M28 is connected to the drain of the transistor M26. The source of the transistor M29 is connected to ground. The gate of the transistor M29 is connected to the drain of the transistor M10. The transistors M9, M13, M14, M15, M16, M17, M18, M19, M20, M21, M22 can be P-type MOS transistors.

[0067] The transistors M10, M11, M12, M23, M24, M25, M26, M27, M28, M29 can be N-type MOS transistors.

[0068] In one embodiment, the second reference voltage source 120 comprises a transistor M32, a transistor M33, a transistor M30, a transistor M34, a transistor M35, a transistor M31, a transistor M36, a transistor M37, a transistor M38, a transistor M39, a transistor M40, a transistor M42, a transistor M44, a transistor M46, a transistor M41, a transistor M43, a transistor M45, a transistor M47, and a transistor M48.

[0069] The source of the transistor M32 is connected to an external power source. The drain of the transistor M32 is connected to the source of the transistor M33. The gate of the transistor M32 is connected to the gate of the transistor M33. The drain of the transistor M33 is connected to the gate of the transistor M33 and the drain of the transistor M30, respectively. The gate of the transistor M30 is connected to the gate of the transistor M10, and the source of the transistor M30 is connected to ground.

[0070] The source of the transistor M34 is connected to ground. The drain of the transistor M34 is connected to the source of the transistor M35. The gate of the transistor M34 is connected to the drain of the transistor M35. The gate of the transistor M35 is connected to the gate of the transistor M33. The drain of the transistor M35 is connected to the drain of the transistor M31. The source of the transistor M31 is connected to ground. The gate of the transistor M31 is connected to the gate of the transistor M10.

[0071] The source of the transistor M36 is connected to an external power source. The gate of the transistor M36 is connected to the gate of the transistor M34. The drain of the transistor M36 is connected to the source of the transistor M37. The gate of the transistor M37 is connected to the gate of the transistor M35 and the gate of the transistor M33, respectively. The drain of the transistor M37 is connected to the drain of the transistor M38, the gate of the transistor M38, and the gate of the transistor M39, respectively. The source of the transistor M38 is connected to the drain of the transistor M39.

[0072] The source of the transistor M40 is connected to an external power source. The drain of the transistor M40 is connected to the source of the transistor M42. The gate of the transistor M40 is connected to the drain of the transistor M42. The drain of the transistor M42 is connected to the drain of the transistor M44. The source of the transistor M44 is connected to the drain of the transistor M46. The gate of the transistor M46 is connected to the non-inverting terminal of the second reference voltage source 120. The source of the transistor M46 is connected to the source of the transistor M39.

[0073] The source of the transistor M41 is connected to an external power supply. The drain of the transistor M41 is connected to the source of the transistor M43. The gate of the transistor M41 is connected to the gate of the transistor M40. The gate of the transistor M43 is connected to the gate of the transistor M42. The drain of the transistor M43 is connected to the drain of the transistor M45 and the gate of the transistor M47, respectively. The gate of the transistor M45 is connected to the gate of the transistor M44. The source of the transistor M45 is connected to the drain of the transistor M47. The source of the transistor M47 is connected to the source of the transistor M46 and the drain of the transistor M48, respectively. The gate of the transistor M48 is connected to the gate of the transistor M10, and the source of the transistor M48 is connected to ground.

[0074] The transistor M32, the transistor M33, the transistor M34, the transistor M35, the transistor M36, the transistor M37, the transistor M40, the transistor M41, the transistor M42, and the transistor M43 can be P-type MOS transistors.

[0075] The transistor M30, the transistor M31, the transistor M38, the transistor M39, the transistor M44, the transistor M45, the transistor M46, the transistor M47, and the transistor M48 can be N-type MOS transistors.

[0076] The circuit structure and working principle of the first reference voltage source 110 and the second reference voltage source 120 can be the same. The first reference voltage source 110 and the second reference voltage source 120 can share the negative temperature coefficient current source 130. The circuit structure of the first reference voltage source 110 and the second reference voltage source 120 being the same can avoid mutual influence on the reference voltage when the first analog-to-digital converter 210 and the second analog-to-digital converter 220 work alternately.

[0077] For example, the first reference voltage source 110, the current generated by the negative temperature coefficient current source 130 is mirrored to the bias current of the main circuit of the first reference voltage source 110 through the transistor M10, the transistor M11 and the transistor M12. The transistors M19, the transistor M20, the transistor M21 and the transistor M22, the transistors M25, the transistor M26, the transistor M27, the transistor M28 and the transistor M29 constitute a single pole sleeve amplifier. The drain of the transistor M26 can be the output terminal vrefl_out of the first reference voltage source 110. The transistors M13 and M14 provide the bias voltage vref1_vp for the transistors M20 and M22. The transistors M23 and M24 provide the bias voltage vref1_vn for the transistors M25 and M26.

[0078] By adjusting the ratio of the resistance R2 / resistance Rl, the voltage VBG can exhibit a slight negative temperature characteristic. With the temperature rising, the voltage VBG has a tendency to decrease. After passing through the negative temperature coefficient voltage buffer circuit 134, the voltage at the first terminal of the resistance R3 also has the same characteristic. Therefore, the current passing through the resistance R3 also exhibits a negative temperature characteristic, which can be characterized as the current passing through the resistance R3 decreases exponentially with the temperature rising. After being mirrored by the transistors M10, M11 and M12, the current exhibiting the negative temperature characteristic flows into the main circuit of the first reference voltage source 110. At the output terminal of the first reference voltage source 110, the output voltage also has a slight tendency to decrease due to the decrease of the current. By finely adjusting the ratio of the resistance R2 / resistance Rl, the output voltage of the first reference voltage source 110 can be decreased to a range acceptable by the system with the temperature changing.

[0079] In one embodiment, continuing to refer to Figure 1 As shown, the analog-to-digital conversion circuit 10 further comprises a gain calibration circuit 140. The gain calibration circuit 140 is connected to the intermediate amplification circuit 231. The gain calibration circuit 140 cooperates with the negative temperature coefficient current source 130 to eliminate the gain error problem caused by the mismatch between the first reference voltage source 110 and the second reference voltage source 120. The gain calibration circuit 140 can eliminate the offset of the output voltage between the first reference voltage source 110 and the second reference voltage source 120 due to the temperature change.

[0080] Please refer to Figure 5In one embodiment, the first reference voltage source 110 includes transistors M49-M58 and transistor M67. The source of transistor M49 is connected to an external power source. The gate of transistor M49 is connected to the output of the second operational amplifier 114. The drain of transistor M49 is connected to the drain and gate of transistor M67. The source of transistor M67 is connected to ground.

[0081] The source of transistor M50 is connected to an external power source. The drain of transistor M50 is connected to the source of transistor M52. The drain of transistor M52 is connected to the drain of transistor M54. The source of transistor M54 is connected to the drain of transistor M56. The source of transistor M56 is connected to the drain of transistor M58. The source of transistor M58 is connected to ground. The drain of transistor M52 is connected to the gate of transistor M50.

[0082] The source of transistor M51 is connected to an external power source. The gate of transistor M51 is connected to the gate of transistor M50. The drain of transistor M50 is connected to the source of transistor M53. The gate of transistor M53 is connected to the gate of transistor M52. The drain of transistor M53 is connected to the drain of transistor M55. The gate of transistor M55 is connected to the gate of transistor M54. The source of transistor M55 is connected to the drain of transistor M57. The source of transistor M57 is connected to the source of transistor M56.

[0083] In one embodiment, the second reference voltage source 120 includes transistors M59-M66 and transistor M68. The source of transistor M59 is connected to an external power source. The drain of transistor M59 is connected to the source of transistor M61. The drain of transistor M61 is connected to the drain of transistor M63. The drain of transistor M61 is also connected to the gate of transistor M59. The source of transistor M63 is also connected to the drain of transistor M65. The source of transistor M65 is connected to the drain of transistor M68. The source of transistor M68 is connected to ground. The gate of transistor M68 is connected to the gate of transistor M67.

[0084] The source of the transistor M60 is grounded. The gate of the transistor M60 is connected with the gate of the transistor M59. The drain of the transistor M60 is connected with the source of the transistor M62. The drain of the transistor M62 is connected with the drain of the transistor M64. The gate of the transistor M64 is connected with the gate of the transistor M63. The source of the transistor M64 is connected with the drain of the transistor M66. The source of the transistor M66 is connected with the drain of the transistor M68. The gate of the transistor M66 is connected with the drain of the transistor M64.

[0085] The first reference voltage source 110 and the second reference voltage source 120 can have the same structure and working principle. Here, the first reference voltage source 110 is taken as an example for description. The current generated by the negative temperature coefficient current source 130 is mirrored by the transistor M58 and the transistor M67 to obtain the tail current of the main circuit of the first reference voltage source 110. The transistors M50 to M58 constitute a single pole sleeve amplifier. The drain of the transistor M15 is the output terminal of the first reference voltage source 110.

[0086] The embodiment of the present application further provides an analog-to-digital conversion device. The analog-to-digital conversion device comprises the analog-to-digital conversion circuit 10 in any of the above embodiments.

[0087] The embodiment of the present application further provides a digital X-ray imaging system. The digital X-ray imaging system comprises the analog-to-digital conversion device in the above embodiment.

[0088] The technical features of the above embodiments can be combined in any manner. To make the description concise, all possible combinations of the technical features in the above embodiments are not described, however, as long as the combinations of the technical features do not exist contradictions, they should be considered as the scope of the present application.

[0089] The above embodiments only express several implementation manners of the present application, and the description is relatively specific and detailed, however, it should not be understood as the limitation of the patent range. It should be noted that, for those skilled in the art, several modifications and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection range of the patent of the present application should be subject to the appended claims.

Claims

1. An analog-to-digital converter circuit, characterized in that, include: First reference voltage source and second reference voltage source; A first analog-to-digital converter is connected to the first reference voltage source; The second analog-to-digital converter is connected to the second reference voltage source; The connection circuit is connected to the first analog-to-digital converter and the second analog-to-digital converter, respectively. A negative temperature coefficient current source, comprising a negative temperature coefficient voltage buffer circuit, is connected to a first reference voltage source and a second reference voltage source respectively; the negative temperature coefficient voltage buffer circuit comprises a second operational amplifier, the inverting input terminal of the second operational amplifier is connected to a negative temperature coefficient voltage generating circuit, and the output terminal of the second operational amplifier is connected to the first reference voltage source, wherein the first reference voltage source and the second reference voltage source are connected. The negative temperature coefficient voltage buffer circuit is used to reduce the impact of temperature changes on the output voltage of the first reference voltage source and the output voltage of the second reference voltage source.

2. The analog-to-digital converter circuit as described in claim 1, characterized in that, The analog-to-digital conversion circuit is a two-stage analog-to-digital converter.

3. The analog-to-digital converter circuit as described in claim 1, characterized in that, The negative temperature coefficient current source also includes: A startup circuit is connected to the negative temperature coefficient voltage generating circuit.

4. The analog-to-digital converter circuit as described in claim 3, characterized in that, The negative temperature coefficient voltage generating circuit includes: A first operational amplifier, the output of which is connected to the startup circuit.

5. The analog-to-digital converter circuit as described in claim 4, characterized in that, The negative temperature coefficient voltage generating circuit also includes: The first branch is connected to the inverting input of the first operational amplifier and the startup circuit; The second branch is connected to the non-inverting input of the first operational amplifier and the startup circuit. By adjusting the first branch and the second branch, the output voltage of the negative temperature coefficient voltage generating circuit is adjusted to have a negative temperature characteristic.

6. The analog-to-digital converter circuit as described in claim 5, characterized in that, The first branch includes: transistor M5, transistor Q2, and resistor R1; The second branch includes: transistor M6, transistor Q3, and resistor R2; Specifically, by adjusting the ratio of resistor R2 to resistor R1, the output voltage of the negative temperature coefficient voltage generating circuit is adjusted to have a negative temperature coefficient characteristic.

7. The analog-to-digital converter circuit as described in claim 6, characterized in that, Both transistor M5 and transistor M6 are P-type MOS transistors.

8. The analog-to-digital converter circuit as described in any one of claims 1-7, characterized in that, The first reference voltage source and the second reference voltage source have the same circuit structure.

9. An analog-to-digital converter, characterized in that, The analog-to-digital converter circuit includes any one of claims 1-8.

10. A digital X-ray imaging system, characterized in that, Includes the analog-to-digital converter as described in claim 9.

Images