A system for accurately injecting voltage fluctuations in eMMC stress testing

Abstract

The application discloses a system for accurately injecting voltage fluctuation in eMMC pressure test, comprising a master control chip, a first PMIC, a second PMIC and an eMMC chip, wherein the master control chip is electrically connected with the first PMIC, the second PMIC and the eMMC chip, and the first PMIC and the second PMIC are electrically connected with the eMMC chip to output current to the eMMC chip. By setting the first PMIC and the second PMIC, accurate voltage fluctuation can be achieved, not only the voltage drop in reality can be simulated, but also the influence of voltage fluctuation on the work of the eMMC chip can be simulated.

Description

Technical Field

[0001] This invention relates to the field of chip testing technology, and more specifically to a system for accurately injecting voltage fluctuations in eMMC stress testing. Background Technology

[0002] Existing eMMC chips have two power supplies: a 3.3V VCC supply for the Nand Flash memory and a 1.8V VCCQ supply for the controller. As a passive semiconductor chip, a normal and stable power supply is theoretically a prerequisite for the normal operation of eMMC. However, in actual use, abnormal fluctuations and drops in the power supply voltage are inevitable due to power stability and environmental factors. This requires the eMMC to still ensure the security of user data and the normal operation of the firmware in scenarios with abnormal power supply. This scenario poses a significant challenge to the error handling capabilities and robustness of the firmware.

[0003] To address this issue, existing mature testing methods involve introducing voltage control circuits (GPIO signal control) to precisely control voltage drops and recovery during eMMC scenario testing. For example, it's possible to drop VCC (powering the Nand) from 3.3V to 0V and VCCQ from 1.8V to 0V, effectively simulating an abnormal power outage.

[0004] However, please refer to the existing practices. Figure 1 It can only achieve the following: Figure 2 The switching on and off of the voltage shown, for example Figure 3 The voltage fluctuations shown, such as VCC fluctuating between 3.3V and 0V, are not supported. However, voltage fluctuations are crucial during eMMC operation, especially during read / write operations involving NAND Flash. VCC fluctuations can cause significant data loss, making testing for this situation quite necessary. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a system for accurately injecting voltage fluctuations in eMMC stress testing, which can inject precise voltage fluctuations into eMMC chips.

[0006] To solve the above-mentioned technical problems, the present invention adopts the following technical solution: a system for accurately injecting voltage fluctuations in eMMC stress testing, comprising a main control chip, a first PMIC, a second PMIC and an eMMC chip, wherein the main control chip is electrically connected to the first PMIC, the second PMIC and the eMMC chip, and the first PMIC and the second PMIC are electrically connected to the eMMC chip to output current to the eMMC chip.

[0007] The beneficial effects of this invention are as follows: by setting the first PMIC and the second PMIC, precise voltage fluctuations can be generated, which can not only simulate the voltage drop situation in reality, but also simulate the impact of voltage fluctuations on the operation of the eMMC chip, thus achieving precise voltage fluctuation injection into the eMMC chip. Attached Figure Description

[0008] Figure 1 A waveform diagram of voltage switching that can be manufactured using existing technology;

[0009] Figure 2 A waveform diagram of voltage fluctuations that cannot be manufactured using existing technology;

[0010] Figure 3 This is a schematic diagram of the structure of a system for accurately injecting voltage fluctuations in eMMC stress testing according to the present invention;

[0011] Figure 4 This is a flowchart illustrating the workflow of a system for precisely injecting voltage fluctuations during eMMC stress testing according to the present invention.

[0012] Figure 5 This is a waveform diagram of the VCCQ voltage fluctuation involved in an embodiment of the present invention;

[0013] Figure 6 This is a waveform diagram of VCC voltage fluctuations according to an embodiment of the present invention. Detailed Implementation

[0014] To explain in detail the technical content, objectives, and effects of the present invention, the following description is provided in conjunction with the embodiments and accompanying drawings.

[0015] Please refer to Figure 3 This invention provides a system for accurately injecting voltage fluctuations during eMMC stress testing, comprising a main control chip, a first PMIC, a second PMIC, and an eMMC chip. The main control chip is electrically connected to the first PMIC, the second PMIC, and the eMMC chip, and the first PMIC and the second PMIC are electrically connected to the eMMC chip to output current to the eMMC chip.

[0016] As can be seen from the above description, the beneficial effects of the present invention are as follows: by setting the first PMIC and the second PMIC, precise voltage fluctuations can be manufactured, which can not only simulate the voltage drop situation in reality, but also simulate the impact of voltage fluctuations on the operation of the eMMC chip.

[0017] Furthermore, the main control chip is electrically connected to the first PMIC and the second PMIC via an IIC interface.

[0018] As described above, the main control chip connects to the first PMIC and the second PMIC via the IIC interface, enabling communication with the first PMIC and the second PMIC through fewer channels.

[0019] Furthermore, it also includes a power module, which is electrically connected to the main control chip, the first PMIC, and the second PMIC.

[0020] As described above, the power module can supply power to the main control chip, the first PMIC, and the second PMIC.

[0021] Furthermore, it also includes a memory chip, which is electrically connected to the main control chip.

[0022] As described above, memory chips are used to store test programs and test cases, enabling the storage of more test cases and more complex test programs.

[0023] Furthermore, the specific model of the first PMIC is TPS628610.

[0024] As described above, the TPS628610 output voltage range is 0.4V-1.9875V, with a step of 0.0125V. The slope of the voltage variation can be adjusted between 10mV / us and 0.1mV / us.

[0025] Furthermore, the specific model of the second PMIC is TPS63811.

[0026] As described above, the TPS63811 has an input voltage range of 2.2V-5.5V and an output voltage range of 1.8V-5.2V, with a step size of 0.025V. The slope of the voltage variation can be adjusted between 1.0V / ms and 10.0V / ms.

[0027] Furthermore, the main control chip and the eMMC are located on two separate PCBs.

[0028] As described above, the main control chip and eMMC are located on separate PCB boards, allowing for independent replacement and repair, which facilitates subsequent maintenance.

[0029] Furthermore, the eMMC is fixed to the PCB board by inserting it into a socket soldered onto the PCB board.

[0030] As described above, the eMMC chip is connected to the PCB board via a socket, which allows for easy replacement of different eMMC chips and enables the test carrier to be reused.

[0031] Furthermore, the main control chip outputs a control signal for the eMMC operation while simultaneously controlling the first PMIC and / or the second PMIC to inject voltage fluctuations into the eMMC.

[0032] As described above, this makes the injection of voltage fluctuations more targeted and improves testing efficiency.

[0033] The present invention discloses a system for precisely injecting voltage fluctuations in eMMC stress testing, which is used to test eMMC chips and generate precise voltage fluctuations during the testing process of eMMC chips to test the stability of eMMC chips under voltage fluctuation conditions.

[0034] Example 1

[0035] Please refer to Figure 3 This embodiment describes a system for accurately injecting voltage fluctuations during eMMC stress testing. It includes a main control chip, an IIC interface, a first PMIC (Power Management IC), a second PMIC, and an eMMC chip. The main control chip is communicatively connected to the first PMIC and the second PMIC via the IIC interface, and is electrically connected to the eMMC chip.

[0036] Therefore, while the main control chip controls the eMMC, it can also control the output voltage of the first and second PMICs via the IIC bus, thereby precisely controlling the input voltage of the eMMC chip and achieving output control for applications such as... Figure 3 The simulation of voltage fluctuations is shown.

[0037] Example 2

[0038] Please refer to Figure 3 This embodiment further defines the first embodiment, including a development board and an eMMC test carrier. The development board includes a first signal transmission interface, a first power interface, a power module, a main control chip, an IIC interface, a data transmission circuit, and a storage chip. The eMMC test carrier includes a second power interface, a second signal transmission interface, a first PMIC, a second PMIC, and the eMMC chip under test.

[0039] The main control chip is electrically connected to the first signal transmission interface, power module, storage chip, IIC interface, and data transmission circuit, respectively. The data transmission circuit is electrically connected to an external host computer to enable communication between the main control chip and the host computer. The first power interface is electrically connected to the second power interface, which in turn is electrically connected to the first PMIC and the second PMIC. The first and second PMICs are electrically connected to the eMMC chip, thereby drawing power from the power module and outputting a set voltage to the eMMC chip. The first and second PMICs are electrically connected to the IIC bus, allowing the main control chip to transmit signals through the IIC interface to control the output of the first and second PMICs. The first signal transmission interface is electrically connected to the second signal transmission interface, which is also electrically connected to the eMMC chip. The first and second signal transmission interfaces include multiple eMMC standard communication lines such as CMD, CLK, DAT0-7, data strobe, and RST_n, allowing the main control chip to transmit control signals and data to the eMMC chip through the first and second signal transmission interfaces to control the eMMC chip to complete the test.

[0040] In this embodiment, both the main control board and the eMMC test carrier are independently designed socket PCBs, which facilitates the replacement of the test program carried in the memory chip during testing. Furthermore, if any component is damaged, repair and replacement are more convenient, and it is also convenient to replace and test the eMMC chip.

[0041] In this embodiment, the first PMIC is specifically a TPS628610, with an output voltage range of 0.4V-1.9875V and a step of 0.0125V. The slope of the voltage variation can be adjusted between 10mV / us and 0.1mV / us. The second PMIC is specifically a TPS63811, with an input voltage range of 2.2V-5.5V and an output voltage range of 1.8V-5.2V and a step of 0.025V. The slope of the voltage variation can be adjusted between 1.0V / ms and 10.0V / ms.

[0042] During testing, please refer to Figure 4 :

[0043] First, the pre-written test program is burned into the storage chip via the host computer, and the eMMC chip to be tested is placed into the slot on the eMMC test carrier. The first power interface and the second power interface are electrically connected, the first signal transmission interface is electrically connected to the second signal transmission interface, and the IIC bus is electrically connected to the first PMIC and the second PMIC.

[0044] Next, power on the development board and load the test program. According to the test program, the main control chip will output IIC signals to the first PMIC and the second PMIC, so that the first PMIC outputs 1.8V and the second PMIC outputs 3.3V. After that, the main control chip sends a command to the eMMC to initialize it. After initialization, the eMMC can be tested. The logs generated in the above process will be transmitted to the host computer and displayed on the host computer.

[0045] After the tester sees the initialization process running on the host computer, they can input commands on the host computer to run the test program and start executing the test according to the corresponding test cases in the test program.

[0046] Then, the main control board sends control commands and reads / writes data to the eMMC according to the test cases, and controls the output voltage of the first PMIC and the second PMIC to fluctuate through IIC communication. This method can embed voltage fluctuations into the process of the main control chip controlling the eMMC, making the injection of voltage fluctuations more targeted and improving test efficiency.

[0047] The eMMC test is performed under voltage fluctuations, and the test results and logs are transmitted to the host computer for the testers to view.

[0048] In this embodiment, a reference test procedure is provided for understanding:

[0049]

[0050]

[0051]

[0052]

[0053]

[0054]

[0055]

[0056] The above test procedure produced the following specific results in practice: Figure 5 -6 voltage fluctuation.

[0057] In summary, the present invention provides a system for accurately injecting voltage fluctuations in eMMC stress testing. By setting a first PMIC and a second PMIC, it can generate precise voltage fluctuations, which can not only simulate the voltage drop situation in reality, but also simulate the impact of voltage fluctuations on the operation of eMMC chips.

[0058] The above description is merely an embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent modifications made based on the content of the present invention specification and drawings, or direct or indirect applications in related technical fields, are similarly included within the patent protection scope of the present invention.

Claims

1. A method for accurately injecting voltage fluctuations in eMMC stress testing, applied to a system for accurately injecting voltage fluctuations in eMMC stress testing, characterized in that: The system includes a main control chip, a first PMIC, a second PMIC, and an eMMC chip. The main control chip is electrically connected to the first PMIC, the second PMIC, and the eMMC chip. The first PMIC and the second PMIC are electrically connected to the eMMC chip to output current to the eMMC chip. The main control chip is electrically connected to the first PMIC and the second PMIC through an IIC interface. While outputting a control signal for the eMMC operation, the main control chip simultaneously controls the first PMIC and / or the second PMIC to inject voltage fluctuations into the eMMC. The first PMIC has an output voltage range of 0.4V-1.9875V, with a step of 0.0125V, and the voltage variation slope is adjustable between 10mV / us and 0.1mV / us; the second PMIC has an input voltage range of 2.2V-5.5V and an output voltage range of 1.8V-5.2V, with a step of 0.025V, and the voltage variation slope is adjustable between 1.0V / ms and 10.0V / ms.

2. The method for accurately injecting voltage fluctuations in eMMC stress testing according to claim 1, characterized in that: The system also includes a power module, which is electrically connected to the main control chip, the first PMIC, and the second PMIC.

3. The method for accurately injecting voltage fluctuations in eMMC stress testing according to claim 1, characterized in that: The system also includes a storage chip, which is electrically connected to the main control chip.

4. The method for accurately injecting voltage fluctuations in eMMC stress testing according to claim 1, characterized in that: The specific model of the first PMIC is TPS628610.

5. The method for accurately injecting voltage fluctuations in eMMC stress testing according to claim 1, characterized in that: The specific model of the second PMIC is TPS63811.

6. The method for accurately injecting voltage fluctuations in eMMC stress testing according to claim 1, characterized in that: The main control chip and the eMMC are located on two separate PCBs.

7. A method for accurately injecting voltage fluctuations in eMMC stress testing according to claim 6, characterized in that: The eMMC is fixed to the PCB board by inserting it into a socket soldered onto the PCB board.

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