Semiconductor device and method of manufacturing the same

Abstract

Disclosed are a semiconductor device and a manufacturing method thereof. The manufacturing method comprises: providing a semiconductor substrate; etching the substrate to form a trench in the substrate; filling the trench with insulating material; etching the insulating material to expose a sharp corner at the intersection of the trench sidewall and the upper surface of the substrate; and forming a field oxide layer on part of the upper surface of the substrate and the insulating material, wherein the sharp corner at the intersection of the trench sidewall and the upper surface of the substrate is oxidized in the step of forming the field oxide layer. The method exposes a sharp corner at the intersection of the shallow trench isolation structure and the substrate surface by etching back the shallow trench isolation structure, and eliminates the sharp corner in the step of forming the field oxide layer, thereby avoiding charge accumulation at the sharp corner and improving the breakdown voltage and reliability of the device.

Description

Technical Field

[0001] This invention generally relates to the field of semiconductor devices. More specifically, embodiments of this invention relate to a semiconductor device and a method for manufacturing the same, particularly a lateral double-diffused metal-oxide-semiconductor (LDMOS) transistor and a method for manufacturing the same. Background Technology

[0002] In the fabrication of LDMOS transistors, especially in the LOCOS process for field plates, there are numerous devices or designs where the field oxide layer meets the shallow trench isolation (STI) structure. Due to the unique characteristics of the LOCOS process, upward-protruding silicon spikes tend to form at these boundaries, such as... Figure 1 As shown, after the entire process is completed, charge will accumulate at the silicon sharp corners at the interface, reducing the thickness of the oxide layer between it and the poly layer. This can lead to oxide layer breakdown at the interface, causing gate oxide integrity (GOI) reliability issues. Summary of the Invention

[0003] The purpose of this invention is to provide a semiconductor device and a method for manufacturing the same, which can improve the silicon sharp corner morphology at the junction of the field oxide layer and the shallow trench isolation structure (STI).

[0004] According to one aspect of the present invention, a method for manufacturing a semiconductor device is provided, comprising: providing a semiconductor substrate; etching the substrate to form trenches in the substrate; filling the trenches with an insulating material; etching the insulating material to expose sharp corners at the junction of the trench sidewalls and the upper surface of the substrate; and forming a field oxide layer on a portion of the upper surface of the substrate and the insulating material, wherein the sharp corners at the junction of the trench sidewalls and the upper surface of the substrate are oxidized during the step of forming the field oxide layer.

[0005] Optionally, the field oxide layer is formed using the Localized Oxidation Separation (LOCOS) method.

[0006] Optionally, in the step of etching the insulating material to expose the sharp corner at the junction of the trench sidewall and the upper surface of the substrate, wet etching is used to etch back the insulating material.

[0007] Optionally, the wet etching solution may be hydrofluoric acid, buffered oxide etchant (BOE), or hydrofluoric acid in different proportions.

[0008] Optionally, the wet etching rate can be changed by altering the wet etching time or the concentration of the solution to control the degree of exposure of the sharp corners at the junction of the trench sidewalls and the substrate surface.

[0009] Optionally, between the steps of etching the insulating material and forming a field oxide layer on the insulating material, the method further includes: forming a body region and a drift region on a semiconductor substrate by an ion implantation process; forming a source region in the body region and a drain region in the drift region, wherein the insulating material is located in the drift region and the drain region is located on the side of the insulating material away from the source region.

[0010] Optionally, an oxidation process is performed using a high-pressure field oxygen furnace tube to form the field oxide layer, the thickness of which is between 300 angstroms and 1000 angstroms.

[0011] Optionally, the thickness of the field oxide layer is 800 angstroms.

[0012] Optionally, the insulating material is made of silicon dioxide, and the field oxide layer is made of silicon dioxide.

[0013] Optionally, after the step of forming a field oxide layer on the insulating material, the method further includes forming a gate structure on the surface of the field oxide layer and a portion of the substrate surface.

[0014] Optionally, the step of forming a gate structure on the surface of the field oxide layer and a portion of the substrate surface includes: depositing a gate oxide layer on the surface of the substrate; depositing a conductor layer on the surface of the field oxide layer and the gate oxide layer; and etching the gate oxide layer and the conductor layer through a patterned mask, wherein the gate oxide layer extends on the substrate surface between the source region and the field oxide layer; and the conductor layer extends on the gate oxide layer and a portion of the field oxide layer.

[0015] According to one aspect of the present invention, a semiconductor device prepared by the above-described semiconductor device preparation method is provided, the semiconductor device comprising: a substrate having trenches formed therein; an insulating material filling the trenches; and a field oxide layer formed on a portion of the upper surface of the substrate and the insulating material, wherein the junction between the trench sidewalls and the upper surface of the substrate is rounded.

[0016] Optionally, the semiconductor device further includes: a body region and a drift region located in the substrate; a source region located in the body region; and a drain region located in the drift region, wherein the insulating material layer is located in the drift region, and the drain region is located on the side of the insulating material away from the source region.

[0017] Optionally, the thickness of the field oxide layer is between 300 angstroms and 1000 angstroms.

[0018] Optionally, the thickness of the field oxide layer is 800 angstroms.

[0019] Optionally, the semiconductor device further includes: a gate structure comprising a gate oxide layer and a conductor layer, the gate oxide layer extending on a substrate surface between the source region and the field oxide layer; the conductor layer extending on the gate oxide layer and a portion of the field oxide layer.

[0020] According to the semiconductor device and manufacturing method of the above embodiments, after forming a shallow trench isolation structure, the shallow trench isolation structure is etched back by a wet process to expose the silicon sharp corner at the junction of the shallow trench isolation structure and the substrate surface. During the subsequent formation of the field oxide layer, the silicon sharp corner at the junction is also rapidly oxidized to form the field oxide layer, thereby eliminating the silicon sharp corner and forming a smooth junction between the field oxide layer and the shallow trench isolation structure, thereby improving the breakdown voltage and improving the reliability of the lateral double-diffused metal-oxide-semiconductor transistor. Attached Figure Description

[0021] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0022] Figure 1 A partial cross-sectional view of an LDMOS transistor according to the prior art is shown;

[0023] Figure 2 A structural diagram of an LDMOS transistor according to an embodiment of the present invention is shown;

[0024] Figures 3a to 3g Cross-sectional views are shown of each stage of a method for manufacturing an LDMOS transistor according to an embodiment of the present invention. Detailed Implementation

[0025] The invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown. For simplicity, the semiconductor structure obtained after several steps can be depicted in a single figure.

[0026] It should be understood that when describing the structure of a device, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above another layer or region, or that there are other layers or regions between it and another layer or region. Furthermore, if the device is flipped, that layer or region will be located "below" or "under" another layer or region.

[0027] To describe a situation where A is directly above another layer or region, this document will use the expressions "A is directly above B" or "A is above and adjacent to B". In this application, "A is directly located in B" means that A is located in B and A is directly adjacent to B, rather than A being located in a doped region formed in B.

[0028] In this application, the term "semiconductor structure" refers to the collective term for the entire semiconductor structure formed in the various steps of manufacturing a semiconductor device, including all layers or regions that have been formed. Many specific details of the invention, such as the structure, materials, dimensions, processing techniques, and methods of the device, are described below to provide a clearer understanding of the invention. However, as those skilled in the art will understand, the invention may be implemented without adhering to these specific details.

[0029] Figure 1 A partial cross-sectional view of an LDMOS transistor according to the prior art is shown; as follows: Figure 1 As shown, a partial cross-sectional view of this LDMOS transistor is, for example, a partial structure located within the drift region 120 of the substrate 110. The drift region 120 of the LDMOS transistor includes a field oxide layer 134 and a shallow trench isolation structure 130. On the surface of the substrate 110, a gate structure 140 is also included, with at least a portion of the gate structure 140 located on the surface of the field oxide layer 134.

[0030] refer to Figure 1 As can be seen in the dashed circle A, a sharp corner is formed at the junction of the upper surface of the substrate 110 and the trench sidewall. Charge tends to accumulate at this sharp corner, which reduces the thickness of the oxide layer between the charge and the gate structure 140. This leads to the oxide layer at the junction being broken down, reducing the reliability of the device.

[0031] While ideally, it is desirable for the sharp corner at the junction of the upper surface of substrate 110 and the sidewall of trench 101 to be as small as possible or absent, the substrate 110 at the junction of the upper surface of substrate 110 and the sidewall of trench 101 is not exposed during the formation of field oxide layer 134 in the field oxide layer region by the LOCOS method. Therefore, sharp corners are inevitably generated during the process, which in turn cause charge accumulation and lead to a decrease in device reliability.

[0032] Figure 2 A structural diagram of an LDMOS transistor according to an embodiment of the present invention is shown.

[0033] The LDMOS transistor 200 in this embodiment and Figure 1The difference between the prior art LDMOS transistor shown is that it eliminates the sharp corners at the junction of the trench sidewalls of the shallow trench isolation structure 230 and the surface of the substrate 110, thereby improving the reliability of the device.

[0034] refer to Figure 2 The LDMOS transistor 200 includes: a substrate 110, a body region 150 and a drift region 120 located in the substrate 110, a source region 151 located in the body region 150, a drain region 121 located in the drift region 120 and a shallow trench isolation structure 230, a field oxide layer 234 located on the surface of the shallow trench isolation structure 230 and a gate structure 140 located on the surface of the substrate 110.

[0035] In this embodiment, the body region 150 and the drift region 120 are separated by a certain distance. At least a portion of the gate structure 140 is located on the substrate surface between the source region 151 and the shallow trench isolation structure 230, and at least a portion of the gate structure 140 is located on the surface of the field oxide layer 234. In this embodiment, the gate structure 140 includes a gate oxide layer 141 and a conductor layer 142.

[0036] In this embodiment, the shallow trench isolation structure 230 and the drain region 121 are located in the drift region 120, and the field oxide layer 234 is located on the surface of the substrate 110 above the drift region 120 and on the surface of the shallow trench isolation structure 230. The drain region 121 is adjacent to the shallow trench isolation structure 230 and is located in the region of the shallow trench isolation structure 230 away from the source region 151.

[0037] In this embodiment, such as Figure 2 As shown at mark B, the junction between the trench sidewall and the substrate 110 surface is an obtuse arc, which avoids charge accumulation caused by small sharp angles, thereby improving the yield and reliability of the device.

[0038] Figures 3a to 3g Cross-sectional views are shown of each stage of a method for manufacturing an LDMOS transistor according to an embodiment of the present invention.

[0039] The method begins with a semiconductor substrate 110. The substrate 110 may be made of single-crystal silicon (Si), single-crystal germanium (Ge), silicon-germanium (GeSi), or silicon carbide (SiC), or other materials such as gallium arsenide or other III-V compounds.

[0040] Trench 101 is formed in substrate 110, and insulating material 231 is deposited in trench 101, such as Figure 3a and Figure 3b As shown.

[0041] In this step, as an example, the step of forming the shallow trench isolation structure 230 includes forming a photoresist layer on the surface of the semiconductor substrate 110. The pattern of the shallow trench isolation structure 230 is defined using photolithography, i.e., openings are formed in the photoresist layer corresponding to the shallow trench isolation structure 230, forming a photoresist mask (not shown). Then, the openings in the photoresist mask are etched downwards to form a trench 101 in the semiconductor substrate 110. By controlling the etching time, the openings in the semiconductor substrate 110 reach a desired depth, forming the trench 101. The sidewalls of the trench 101 are inclined outwards at an angle less than or equal to 90 degrees. In this embodiment, the trench 101 is an inverted trapezoid with a sidewall inclination angle of 65 to 70 degrees, because a large inclination angle would affect the effect of depositing the insulating material in the following steps. Then, insulating material 231 is deposited in the trench 101 to fill it.

[0042] The etching process forming the trench 101 can be performed using dry etching methods, such as ion milling, plasma etching, reactive ion etching, laser ablation, or selective wet etching using an etchant solution. After etching, the photoresist mask is removed by dissolving or ashing in a solvent. The deposition process for the insulating material 231 is, for example, selected from electron beam evaporation (EBM), physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or sputtering. As an example, this embodiment uses reactive ion etching and chemical vapor deposition to deposit the insulating material, which is silicon dioxide.

[0043] Further, insulating material 231 is etched back to obtain insulating material 232, such as... Figure 3c As shown. In this step, the deposited insulating material 231 is etched back using wet etching, exposing the sharp corners at the junction of the trench 101 and the upper surface of the substrate 110, as shown. Figure 3c As shown by the dashed circle B in the diagram.

[0044] In this embodiment, the wet etching solution used is, for example, hydrofluoric acid. By controlling the wet etching time, the degree of exposure of the sharp corners at the junction of the upper surface of the substrate 110 and the sidewall of the trench 101 can be controlled. In other embodiments, other oxide-removing solutions can also be used, i.e., solutions with high selectivity for oxides, such as BOE (Buffered Oxide Etch, a mixture of hydrofluoric acid (49%) and water or ammonium fluoride and water), or hydrofluoric acid in different ratios, such as 1:10, 1:100, etc. Furthermore, the wet etching solution concentration can be changed to change the wet etching rate, thereby changing the degree of exposure of the sharp corners at the junction.

[0045] In this embodiment, the etch-back insulating material 232 serves as, for example, a shallow trench isolation structure in the final device. Therefore, the term "shallow trench isolation structure" will be used to refer to the insulating material 232 below.

[0046] Furthermore, a body region 150 and a drift region 120 are formed in the substrate 110 via ion implantation, and a source region 151 is formed in the body region 150 and a drain region 121 is formed in the drift region 120, as follows: Figure 3d As shown.

[0047] In this step, as an example, the steps of forming the body region 150 and the drift region 120 include: forming a photoresist layer on the surface of the semiconductor substrate 110; using photolithography to define the pattern of the body region 150 and the drift region 120; forming a photoresist mask (not shown); and then performing ion implantation on the substrate 110 through the photoresist mask to form the body region 150 and the drift region 120. The implanted ions in the body region 150 are of a first doping type, and the implanted ions in the drift region 120 are of a second doping type. The first doping type is the opposite of the second doping type; therefore, two masking processes and two ion implantations are required to form the body region 150 and the drift region 120.

[0048] In this embodiment, the body region 150 and the drift region 120 are separated by a certain distance, and the trench and shallow trench isolation structure 230 is located in the drift region. The drift region 120 extends deeper in the substrate 110 than the body region 150 extends deeper in the substrate 110. This step can be achieved by controlling the energy and ion implantation time during ion implantation.

[0049] Further, in this step, the formation of source region 151 and drain region 121 includes: forming a photoresist layer on the semiconductor substrate 110, and using photolithography to define the pattern of the ion implantation region, i.e., forming an opening in the portion of the photoresist layer corresponding to the ion implantation region, to form a photoresist mask (not shown in the figure). Subsequently, ion implantation is performed using conventional bulk implantation and drive-in techniques to form a doped region in the semiconductor substrate 110, which is, for example, source region 151 and / or drain region 121.

[0050] Through multiple masking and ion implantation processes, a source region 151 is formed in the body region 150 of the substrate 110, and a drain region 121 is formed in the drift region 120. The drain region 121 is located in the drift region 120 on the side of the shallow trench isolation structure 230 away from the body region 150. Furthermore, by controlling the ion implantation parameters, such as implantation energy and dose, the desired depth and doping concentration can be achieved. Using an additional photoresist mask, the lateral extension region of the doped area can be controlled.

[0051] In this embodiment, a double diffusion process can also be used to form the source region 151 and the drain region 121. In the double diffusion process, the same region is implanted twice, followed by a high-temperature drive-through process. For example, when the LDMOS transistor is of N-type conductivity, to form the source region 151, the dopant implanted in the first ion implantation is, for example, arsenic, with a high doping concentration, while the dopant implanted in the second ion implantation is, for example, boron, with a low doping concentration. During the high-temperature drive-through process after the two ion implantations, since boron diffuses faster than arsenic, boron diffuses further in the horizontal direction than arsenic, resulting in a greater lateral extension distance of the low-doped region than the high-doped region, forming a lateral concentration gradient.

[0052] In this embodiment, the body region 150 and the drain region 151 have a first doping type, and the drift region 120 and the source region 151 have a second doping type, the first doping type being the opposite of the second doping type. For example, the first doping type is one of N-type and P-type, and the second doping type is the other of N-type and P-type.

[0053] To form an N-type semiconductor layer or region, N-type dopants (e.g., P, As) can be implanted into the semiconductor layer and region. To form a P-type semiconductor layer or region, P-type dopants (e.g., B) can be incorporated into the semiconductor layer and region.

[0054] Furthermore, a field oxide layer 234 is formed on the surface of a portion of the substrate 110 and the surface of the shallow trench isolation structure 230, such as... Figure 3e As shown.

[0055] In this step, a field oxide layer 234 is formed on a portion of the surface of the substrate 110 and the surface of the shallow trench isolation structure 230 using a LOCOS process, such as Figure 3e As shown, preferably, the field oxide layer 234 is an oxide layer. The field oxide layer 234 is located on the surface of the substrate 110 of the drift region 120 and extends laterally on the surface of the shallow trench isolation structure 230 to be adjacent to the drain region 121. The thickness of the field oxide layer 234 is adjusted according to the withstand voltage of the semiconductor device; for example, it can be between 300 Å and 1000 Å. Preferably, the thickness of the field oxide layer 234 is 800 Å. The field oxide layer 234 is not limited to a high-voltage field oxide layer; it can be applied to field oxide layers or gate oxide layers of any thickness.

[0056] Specifically, the LOCOS process for forming the field oxide layer 234 includes, for example, forming a nitride protective layer on the surface of the substrate 110; forming an opening in the nitride protective layer to expose a portion of the surface of the substrate 110 and the surface of the shallow trench isolation structure 230; and performing thermal oxidation, growing an oxide layer on a portion of the surface of the substrate 110 and the surface of the shallow trench isolation structure 230 through a high-pressure field oxide furnace tube, thereby forming the field oxide layer 234. The surface of the field oxide layer 234 is higher than the surface of the substrate 110.

[0057] In this embodiment, after the field oxide layer 234 is formed, the deposited insulating material and the field oxide layer 234 are seamlessly connected, forming an integral unit, thereby improving the quality of the shallow trench isolation structure 230. Simultaneously, since the sharp corner at the interface between the shallow trench isolation structure 230 and the substrate 110 surface is exposed, during the thermal oxidation step of the LOCOS process, the oxidation rate at the sharp corner increases rapidly due to the simultaneous oxidation of the upper and side surfaces, ultimately eliminating the sharp corner and forming a smooth interface. This significantly reduces the sharp corner charge, increases the oxide layer thickness at the interface, improves the breakdown voltage, and enhances device reliability.

[0058] Furthermore, a gate oxide layer 141 and a conductor layer 142 are formed on the surface of the substrate 110, such as... Figure 3f As shown.

[0059] In this step, the grid oxide layer 141 is formed by furnace tube oxidation process.

[0060] Then, a conductor layer 142 is formed on the surface of the gate oxide layer 141. The conductor layer 142 can be formed using the known deposition process described above. The conductor layer 142 can be, for example, a metal layer, a doped polysilicon layer, or a stacked gate conductor including a metal layer and a doped polysilicon layer, or other conductive materials, such as TaC, TiN, TaSiN, HfSiN, TiSiN, TiCN, TaAlC, TiAlN, TaN, PtSix, Ni3Si, Pt, Ru, W, and combinations of these conductive materials. Preferably, in this embodiment, the conductor layer 142 is a polysilicon layer.

[0061] Further, the gate oxide layer 141 and the conductor layer 142 are etched to form the gate structure 140, such as... Figure 3g As shown.

[0062] In this step, a photoresist mask is formed over the semiconductor structure. This photoresist mask defines the pattern of the gate structure 140, specifically forming openings in areas other than the portion of the photoresist layer corresponding to the gate structure 140. That is, the photoresist layer is only located on the surface of the gate structure 140, exposing the surface of the conductor layer 142 in other areas. Then, etching is performed downwards from the openings in the photoresist mask to remove the exposed portions of the conductor layer 142, thereby exposing the surface of the gate oxide layer 141. Further etching continues downwards from the openings in the photoresist mask, and the exposed portions of the gate oxide layer 141 are also etched, thereby exposing the surface of the substrate 110. After etching, the photoresist mask remains and can be removed by dissolving it in a solvent or ashing.

[0063] In this embodiment, the gate oxide layer 141 is located between the conductor layer 142 and the substrate 110, and the gate oxide layer 141 extends laterally on the surface of the substrate 110 between the source region 151 and the drift region 120. A portion of the conductor layer 142 is located on the surface of the gate oxide layer 141, and another portion is located on the surface of the field oxide layer 234. Further, at least a portion of the gate oxide layer 141 and the conductor layer 142 are located on the surface of the source region 151 in the body region 150.

[0064] In the method of the above embodiment, after forming the gate structure 140, an interlayer insulating layer, a via penetrating the interlayer insulating layer to reach the source region, drain region and conductor layer, wiring or electrodes located on the upper surface of the interlayer insulating layer can be formed on the obtained semiconductor structure, thereby completing the other parts of the LDMOS transistor.

[0065] According to the semiconductor device manufacturing method of the above embodiment, after forming a shallow trench isolation structure, the shallow trench isolation structure is etched by a wet process to expose the sharp corner at the junction of the shallow trench isolation structure and the upper surface of the substrate. During the subsequent formation of the field oxide layer, the sharp corner at the junction is also rapidly oxidized to form field oxide, thereby eliminating the sharp corner, improving the breakdown voltage, and improving the reliability of the lateral double-diffused metal oxide semiconductor transistor.

[0066] It should be noted that in the methods of the above embodiments, the formation order of the various doped regions is not limited, and doped regions with the same doping type can be formed simultaneously. The above embodiments schematically list the order of the various steps, but are not limited to the order of the steps listed in this embodiment. In alternative embodiments, transistors and other devices that are process-compatible can be added arbitrarily.

[0067] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0068] The embodiments of the present invention have been described above. However, these embodiments are merely illustrative and not intended to limit the scope of the invention. The scope of the invention is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of the invention, and all such substitutions and modifications should fall within the scope of the invention.

Claims

1. A method of manufacturing a semiconductor device, characterized by, The method comprises: providing a semiconductor substrate, etching the substrate to form a trench in the substrate; filling the trench with an insulating material; etching the insulating material to expose sharp corners at the junction of the trench sidewall and the upper surface of the substrate; forming a field oxide layer on part of the upper surface of the substrate and the insulating material by using a local oxidation isolation method, wherein the sharp corners at the junction of the trench sidewall and the upper surface of the substrate are oxidized and eliminated in the step of forming the field oxide layer, and after oxidation, the junction of the trench sidewall and the upper surface of the substrate forms a rounded obtuse angle.

2. The manufacturing method according to claim 1, wherein, In the step of etching the insulating material to expose the sharp corners at the junction of the trench sidewall and the upper surface of the substrate, the insulating material is etched by using a wet etching method.

3. The production method according to claim 2, characterized by The solution of the wet etching method uses a buffered oxide etching solution (BOE) or different proportions of hydrofluoric acid.

4. The production method according to claim 3, characterized by The exposure degree of the sharp corners at the junction of the trench sidewall and the substrate surface is controlled by changing the wet etching rate by changing the time or concentration of the solution of the wet etching method.

5. The production method according to claim 1, characterized by Between the steps of etching the insulating material to expose the sharp corners at the junction of the trench sidewall and the upper surface of the substrate and forming a field oxide layer on the insulating material, further comprising: forming a body region and a drift region on the semiconductor substrate by an ion implantation process; forming a source region in the body region and a drain region in the drift region, wherein the insulating material is located in the drift region, and the drain region is located on the side of the insulating material away from the source region.

6. The production method according to claim 1, characterized by The oxidation process is performed by a high-pressure field oxygen furnace tube to form the field oxide layer, and the thickness of the field oxide layer is between 300 angstroms and 1000 angstroms.

7. The production method according to claim 1, wherein The thickness of the field oxide layer is 800 angstroms.

8. The production method according to claim 1, wherein The material of the insulating material includes silicon dioxide, and the material of the field oxide layer includes silicon dioxide.

9. The production method according to claim 5, wherein After the step of forming a field oxide layer on the insulating material, further comprising: forming a gate structure on the surface of the field oxide layer and part of the substrate surface.

10. The manufacturing method according to claim 9, wherein The step of forming a gate structure on the surface of the field oxide layer and part of the substrate surface comprises: depositing a gate oxide layer on the surface of the substrate; depositing a conductor layer on the surface of the field oxide layer and the gate oxide layer; etching the gate oxide layer and the conductor layer through a patterned mask, wherein the gate oxide layer extends on the substrate surface between the source region and the field oxide layer; and the conductor layer extends on the gate oxide layer and part of the field oxide layer.

11. A semiconductor device produced by the production method of any one of claims 1 to 10, characterized by The semiconductor device comprises: a substrate having a trench formed therein; an insulating material filled in the trench; a field oxide layer formed on part of the upper surface of the substrate and the insulating material, and the junction of the trench sidewall and the upper surface of the substrate is a rounded obtuse angle.

12. The semiconductor device of claim 11, wherein, The semiconductor device further comprises: a body region and a drift region located in the substrate; a source region located in the body region; a drain region located in the drift region, wherein the insulating material layer is located in the drift region, and the drain region is located on the side of the insulating material away from the source region.

13. The semiconductor device of claim 11, wherein, The thickness of the field oxide layer is between 300 angstroms and 1000 angstroms.

14. The semiconductor device of claim 11, wherein, The thickness of the field oxide layer is 800 angstroms.

15. The semiconductor device of claim 12, wherein, The semiconductor device further includes a gate structure including a gate oxide layer and a conductor layer, the gate oxide layer extending over a surface of the substrate between the source region and the field oxide layer, the conductor layer extending over the gate oxide layer and a portion of the field oxide layer.

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