A method for preparing a self-aligned top-gate field effect transistor based on two-dimensional material

Abstract

The application belongs to the technical field of microelectronic process, and particularly relates to a preparation method of a self-aligned top gate field effect transistor based on two-dimensional material. The preparation method comprises the following steps: preparation of single-layer or multi-layer two-dimensional semiconductor material on a silicon / silicon dioxide or sapphire substrate, growth of an oxide dielectric layer, deposition of a top gate metal electrode on the oxide dielectric layer, selective etching of the oxide dielectric layer, and self-aligned deposition of a source-drain metal electrode in contact with the edge of the two-dimensional material. The metal material of the source-drain electrode is self-aligned deposited by using the microstructure formed by selective etching as a hard mask, and compared with a non-self-aligned process, the preparation method omits the step of source-drain patterning overlay, avoids the alignment deviation problem caused by size reduction, and is easier to prepare a short channel field effect transistor, so that the preparation method has a wide application prospect in advanced processes with continuously shrinking size.

Description

A method for fabricating a self-aligned top-gate field-effect transistor based on two-dimensional materials Technical Field

[0001] This invention belongs to the field of microelectronics process technology, specifically relating to a method for fabricating a self-aligned top-gate field-effect transistor based on two-dimensional materials. Background Technology

[0002] Traditional silicon-based integrated circuits (ICs) have brought tremendous improvements to the electronics industry in order to keep pace with Moore's Law's continuous miniaturization, but they have also brought challenges to device manufacturing processes. Especially as transistors shrink to sub-micron dimensions, the finer patterns inevitably lead to misalignment between photolithographic patterns at different levels, thus affecting device performance. To solve the alignment problem, self-aligned processes that utilize fundamental physical and chemical principles and the specific dimensional structures formed by different material properties can effectively address these issues. Examples include: polysilicon self-alignment (PSA) technology to reduce the transfer resistance of bipolar transistors, and multiple projection lithography (SADP / SAQP) technology, which began to be used at 22nm to solve the fine-line photolithography alignment problem.

[0003] Two-dimensional semiconductor materials, due to their ultrathin atomic layer structure, inherent dangling bond-free interlayer structure, and high theoretical mobility, can effectively overcome short-channel effects, and the transistors fabricated from them exhibit extremely high on / off ratios, attracting widespread attention in the microelectronics field. Furthermore, theoretical and experimental studies have confirmed that MoS2 exhibits lower gate leakage current and lower intralayer dielectric constant than Si in devices below the 5nm level; these characteristics make high-performance two-dimensional semiconductor materials strong candidates for 2nm node applications.

[0004] Due to the unique structural characteristics of two-dimensional materials, processes such as ion implantation and selective dry etching in Si-based materials cannot be directly applied. Therefore, in the fabrication of short-channel devices using two-dimensional materials, self-aligned processes cannot be directly applied to Si-based processes, requiring the development of new techniques. Currently, it is possible to fabricate single-cell devices based on MoS2 with channels up to 100 nm using nanowires as hard masks and with 1 nm channels using self-aligned edge contacts. However, these device fabrication methods suffer from limitations such as uncontrollable gate length and cumbersome procedures, hindering large-scale application.

[0005] Therefore, it is necessary to provide a novel method for fabricating self-aligned top-gate field-effect transistors based on two-dimensional materials. Summary of the Invention

[0006] The purpose of this invention is to provide a novel method for fabricating self-aligned top-gate field-effect transistors based on two-dimensional materials, in order to solve the existing technical problem mentioned in the background art of large-scale fabrication of two-dimensional material field-effect transistors at small sizes, thereby realizing the functions of complex large-scale digital logic circuits, as well as other analog circuits and radio frequency analog circuits.

[0007] The present invention provides a method for fabricating a self-aligned top-gate field-effect transistor based on two-dimensional materials, wherein the transistor structure includes an insulating substrate, a single or multiple two-dimensional semiconductor material active layer on the substrate, an oxide dielectric layer, a top metal gate electrode, and metal source and drain electrodes connected to the two-dimensional material.

[0008] The method for fabricating a self-aligned top-gate field-effect transistor based on two-dimensional materials according to the present invention comprises the following steps:

[0009] (1) A two-dimensional semiconductor material is prepared on the surface of an insulating substrate;

[0010] (2) Define the active channel region using a masking layer method, and etch the two-dimensional semiconductor material outside the channel using dry etching;

[0011] (3) Deposit an oxide dielectric layer in situ on the surface of a two-dimensional semiconductor material;

[0012] (4) A small gate electrode region is defined on the surface of the oxide dielectric layer using a masking layer method, and two metal layers are deposited as gate electrodes, with the top metal layer serving as an etching barrier layer.

[0013] (5) Dry etching is performed on the entire plane. After thinning the oxide dielectric layer, isotropic wet etching is performed. The dielectric layer not blocked by the gate electrode is completely etched and the two-dimensional semiconductor material is exposed. Etching is then stopped.

[0014] (6) Define the source and drain regions using a masking layer method, and use the gate electrode as a self-aligned hard mask to deposit metal electrodes on the exposed two-dimensional semiconductor material to complete the fabrication of the self-aligned transistor.

[0015] In step (1) of this invention, the two-dimensional material is MoS2, black phosphorus, MoSe2, PdSe2, MoTe2, WS2 or WSe2, and its preparation method is physical vapor deposition, chemical vapor deposition, metal-organic chemical vapor deposition, molecular beam epitaxy or atomic layer deposition; or the two-dimensional material wafer that has been grown is peeled off from its metal or insulating substrate and transferred to the target substrate by dry or wet method; or the two-dimensional material bulk material is mechanically peeled off to obtain a two-dimensional atomic crystal thin film material, and then transferred to the target substrate by dry method.

[0016] In steps (2), (4) and (6) of this invention, the masking layer is photoresist or a mask. The patterning method of the photoresist masking layer is to use photolithography to pattern the photoresist through exposure, development and other means; or to use a mask with a specific pattern to pattern the mask containing the electrode pattern by attaching it tightly to the surface of the two-dimensional semiconductor material.

[0017] In steps (2) and (5) of this invention, the dry etching method utilizes an F-containing... + The reactive plasma is used for capacitive plasma etching or inductively coupled plasma etching; the selective etching of the dielectric layer is performed using F... + Dry etching using Ar2, O2, or BCl3 plasma.

[0018] In step (3) of the present invention, the dielectric interlayer material used for the semiconductor two-dimensional material and the gate electrode is selected from silicon oxide, zirconium oxide, hafnium oxide, aluminum oxide or other high-K dielectric materials or BN-like two-dimensional insulating materials, and the growth method is atomic layer deposition, chemical vapor deposition or physical vapor deposition.

[0019] In steps (4) and (6) of this invention, the metal electrode material is selected from Au, Pt, Ni, and Ti, and the uppermost metal is selected from Al or Cr metal as an etching barrier layer.

[0020] In steps (4) and (6) of this invention, the metal deposition is achieved by creating a mask with the desired pattern on the metal precursor layer using methods such as ultraviolet light, electron beam lithography, or hard masking, and then depositing the metal electrode using physical vapor deposition, electron beam evaporation, or magnetron sputtering equipment. In step (6), when defining the source and drain regions, it is not necessary to align and mask the gate; instead, the gate and the source and drain regions are exposed, and the gate is used as a self-aligned hard mask to deposit metal, with its thickness controlled to not exceed the dielectric thickness.

[0021] In step (5) of this invention, the selective wet etching of the oxide dielectric layer is performed using a solution composed of one or more of H3PO4, HNO3, HF, and NH4F. The principle is to effectively etch the dielectric layer without damaging the two-dimensional semiconductor material.

[0022] The self-aligned top-gate field-effect transistor fabrication method based on two-dimensional materials designed in this invention has the following advantages and effects compared with the prior art:

[0023] By utilizing the mechanism of selective etching, the source and drain regions of an in-situ grown oxide dielectric layer are exposed. Self-aligned source and drain electrodes are then grown using a structure formed by the top-gate metal electrode, resulting in a top-gate transistor structure based on two-dimensional materials. This invention effectively applies self-aligned technology to the fabrication of two-dimensional material transistors. Simultaneously, it utilizes a unique microstructure to achieve large-scale, small-scale transistor array fabrication, effectively addressing the short-channel effect, improving integration density, reducing power consumption, and adapting to advanced processes. It has broad application prospects in the manufacturing of large-scale integrated circuits. Attached Figure Description

[0024] Figure 1 is a schematic diagram of a self-aligned top-gate field-effect transistor based on two-dimensional materials according to the present invention. The upper figure is a front view of the field-effect transistor, and the lower figure is a top view of the field-effect transistor, as shown in Embodiment 1.

[0025] Figure 2 is a schematic diagram of the process flow for fabricating a self-aligned transistor in Example 1 of the present invention, wherein (a) is the fabrication and etching process of two-dimensional semiconductor materials; (b) is the fabrication of oxide layer and gate electrode; and (c) is the selective etching of oxide layer and self-aligned growth of source, drain and gate metal electrodes.

[0026] Figure 3 is a schematic diagram of a two-dimensional material self-aligned T-type top-gate field-effect transistor with a dielectric layer isolation layer according to the present invention. The upper figure is the front view of the field-effect transistor and the lower figure is the top view of the field-effect transistor, which is shown in Embodiment 2.

[0027] Figure 4 illustrates the preparation process of Example 2, where (a) is the preparation and etching process of two-dimensional semiconductor materials; (b) is the preparation of a double oxide dielectric layer and a gate electrode; (c) is the preparation of a top oxide isolation layer; and (d) is the selective etching of the bottom oxide layer and the self-aligned growth of source, drain, and gate metal electrodes.

[0028] In the figure, the numbers are as follows: 1 is the substrate, 2 is the bottom two-dimensional semiconductor material, 3 is the oxide dielectric layer, 4 is the etching barrier metal, 5 is the drain gate electrode metal, and 6 is the oxide dielectric isolation layer. Detailed Implementation

[0029] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The accompanying drawings show specific embodiments and related figures of the present invention, used to explain the structure and fabrication method of the self-aligned two-dimensional material device of the present invention. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar materials or methods having the same or similar functions throughout. The specific embodiments described herein are only for explaining the present invention and are not intended to limit the scope of protection of the present invention. Furthermore, the present invention provides examples of various specific processes and materials, but those skilled in the art will recognize the applicability of other processes and / or the use of other materials.

[0030] Hereinafter, examples of the embodiments of the present invention will be described with reference to the accompanying drawings.

[0031] Example 1

[0032] The present invention provides a method for fabricating a self-aligned top-gate field-effect transistor based on two-dimensional materials. The performance controllable two-dimensional common-gate complementary field-effect transistor structure provided in Example 1 is shown in Figure 1, including 1 as a substrate, 2 as a bottom two-dimensional semiconductor material, 3 as an oxide dielectric layer, 4 as an etch barrier metal layer, and 5 as a self-aligned source drain gate electrode metal.

[0033] Figure 2 illustrates the preparation process of Example 1, where (1) is the preparation and etching process of the two-dimensional semiconductor material; (2) is the preparation of the oxide layer and the gate electrode; and (3) is the selective etching of the oxide layer and the self-aligned growth of the source, drain, and gate metal electrodes. The specific steps are as follows:

[0034] (1) Preparation and etching of two-dimensional semiconductor materials: Two-dimensional semiconductor material 2 is prepared on the surface of substrate 1. The substrate 1 is a commonly used substrate in the art, such as any one of sapphire substrate, quartz substrate, silicon substrate, glass substrate or flexible substrate; the preparation method of the two-dimensional semiconductor material includes "bottom-up" deposition; the two-dimensional material is a two-dimensional transition metal sulfide material, graphene, black phosphorus, etc., and its preparation method is to deposit it by physical, chemical or metal-organic compound vapor deposition methods; or the grown two-dimensional material wafer or bulk material is transferred to the target substrate by peeling. As a specific example, silicon is selected as the substrate in this embodiment 1, and a single layer of molybdenum disulfide two-dimensional semiconductor material is prepared by chemical vapor deposition; for the etching of molybdenum disulfide, the masking layer is photoresist or a mask. The patterning method of the masking layer is to use photolithography to pattern the photoresist by exposure, development and other means; or to use a mask to pattern the mask containing electrode patterns on the surface of the two-dimensional semiconductor material. As a specific example, in this embodiment, laser direct writing is used to expose the etch protection area in the direction of parallel source and drain electrodes. The remaining part is etched using inductively coupled plasma etching (ICP) with CF4 gas in the direction of parallel electrodes to form the transistor channel. The etching is stopped until the substrate is removed, and then the resist is removed.

[0035] (2) Fabrication of oxide layer and gate electrode: After the channel etching is completed, atomic layer deposition (ALD) is used to prepare 50 nm Al2O3 as the gate dielectric layer of the transistor. According to the required channel length of 100 nm, electron beam lithography with higher precision is selected to define the top gate pattern, and 50 nm Au is deposited using electron beam evaporation equipment. While maintaining a high vacuum state, 20 nm Al is deposited as an etching barrier layer. After the growth is completed, the resist is removed.

[0036] (3) Selective etching of oxide layer and self-aligned growth of source, drain and gate metal electrodes: The entire plane is dry etched using ICP method with SF6 gas to reduce the thickness of the dielectric oxide layer to within 10 nm. Then, isotropic wet etching is performed using phosphoric acid solution (volume ratio GR: phosphoric acid: H2O = 1:20). The dielectric layer not covered by the gate electrode is completely etched, and the dielectric under the gate is retained. Etching is stopped after the two-dimensional semiconductor material is exposed. The source and drain regions are defined by laser direct writing, and the gate electrode is used as a self-aligned hard mask. A 10 nm Au metal electrode is deposited on the exposed molybdenum disulfide using an electron beam evaporation device to complete the fabrication of the self-aligned transistor.

[0037] Example 2

[0038] The present invention provides a method for fabricating a self-aligned T-type top-gate field-effect transistor based on two-dimensional materials. The structure of the self-aligned top-gate field-effect transistor based on two-dimensional materials provided in Example 2 is shown in Figure 3. Compared with Example 1, the self-aligned structure of the T-type gate can better prevent the occurrence of source-drain-gate short circuit. The materials used in 1-5 are exactly the same as those in Example 1. The oxide dielectric isolation layer in 6 is SiO2.

[0039] Figure 4 illustrates the preparation process of Example 1, where (1) is the preparation and etching process of the two-dimensional semiconductor material; (2) is the preparation of the double oxide dielectric layer and the gate electrode; (3) is the preparation of the top oxide isolation layer; and (4) is the selective etching of the bottom oxide layer and the self-aligned growth of the source, drain, and gate metal electrodes. Steps (1) and (4) are consistent with steps (1) and (3) in Example 1. The specific steps (2) and (3) in Example 2 are as follows:

[0040] (2) Fabrication of double oxide dielectric layer and gate electrode: After the channel is etched, 50 nm Al2O3 is prepared by atomic layer deposition (ALD) as the gate dielectric layer of the transistor. 30 nm SiO2 is deposited on the surface using electron beam evaporation equipment. According to the required channel length of 100 nm, the top gate pattern is defined by electron beam lithography with higher precision. 50 nm Au is deposited using electron beam evaporation equipment, and 20 nm Al is deposited as an etching barrier layer while maintaining a high vacuum state. After the growth is completed, the resist is removed.

[0041] (3) Preparation of the top oxide isolation layer: The entire plane is dry etched by ICP method with SF6 gas. Since the etching ratio of SiO2 and Al2O3 is large, the upper SiO2 oxide dielectric layer that is not blocked by the gate electrode can be completely removed, and the top oxide isolation layer under the T-type gate structure is preserved.

[0042] The above provides a detailed description of the performance-controllable two-dimensional semiconductor transistor structure and its fabrication method according to the present invention. However, the present invention is not limited to the above examples, and various improvements and modifications can be made without departing from the spirit of the present invention.

Claims

1. A method for fabricating a self-aligned top-gate field-effect transistor based on two-dimensional materials, the field-effect transistor comprising: An insulating substrate, a single or multiple layers of two-dimensional semiconductor material on the substrate, an oxide dielectric layer, a top metal gate electrode, and metal source and drain electrodes connected to the two-dimensional material; characterized in that the specific preparation steps are as follows: (1) a two-dimensional semiconductor material is prepared on the surface of the insulating substrate; (2) an active channel region is defined by photolithography or masking and the two-dimensional semiconductor material outside the channel is etched by dry etching; (3) an oxide dielectric layer is deposited in situ on the surface of the two-dimensional semiconductor material; (4) a small-size gate electrode region is defined on the surface of the oxide dielectric layer by photolithography or masking, and two metal layers are deposited as gate electrodes, the top metal layer is used as an etching barrier layer, and then a resist removal process is performed; (5) the entire plane is dry etched to thin the oxide dielectric layer, and then isotropic wet etching is performed to form an undercut structure. The oxide dielectric layer not covered by the gate electrode is completely etched, and the etching is stopped after the two-dimensional semiconductor material is exposed; the dry etching is performed using F + Selective etching of the oxide dielectric layer using Ar2, O2 or BCl3; (6) Defining the source and drain regions using photolithography or masking, and using the gate electrode as a self-aligned hard mask, depositing metal electrodes on the exposed two-dimensional semiconductor material, controlling the thickness of the source and drain metal electrodes to not exceed the thickness of the oxide dielectric layer, and completing the fabrication of the self-aligned transistor.

2. The method for fabricating a self-aligned top-gate field-effect transistor based on two-dimensional materials according to claim 1, characterized in that, The insulating substrate in step (1) is any one of a glass substrate, a sapphire substrate, a quartz substrate, a silicon substrate, or a flexible substrate.

3. The method for fabricating a self-aligned top-gate field-effect transistor based on two-dimensional materials according to claim 1, characterized in that, The two-dimensional material mentioned in step (1) is MoS2, black phosphorus, MoSe2, PdSe2, MoTe2, WS2 or WSe2, which is formed by physical vapor deposition, chemical vapor deposition, metal-organic chemical vapor deposition, molecular beam epitaxy or atomic layer deposition; or by peeling the grown two-dimensional material wafer from its metal or insulating substrate and transferring it to the target substrate by dry or wet method; or by mechanically peeling off the two-dimensional material bulk material to obtain a two-dimensional atomic crystal thin film material, and then transferring it to the target substrate by dry method.

4. The method for fabricating a self-aligned top-gate field-effect transistor based on two-dimensional materials according to claim 1, characterized in that, The oxide dielectric layer material used for the two-dimensional semiconductor material and the gate electrode in step (3) is selected from silicon oxide, zirconium oxide, hafnium oxide, aluminum oxide or BN-like two-dimensional insulating materials.

5. The method for fabricating a self-aligned top-gate field-effect transistor based on two-dimensional materials according to claim 1, characterized in that, The metal electrode material mentioned in steps (4) and (6) is selected from Au, Al, Pt, Ni, Ti or Cr.

6. The method for fabricating a self-aligned top-gate field-effect transistor based on two-dimensional materials according to claim 1, characterized in that, In steps (4) and (6), when the electrode is made of metal, it is prepared by ultraviolet light, electron beam lithography or hard mask method, making a mask with the required pattern on the metal precursor layer, and depositing the metal electrode by physical vapor deposition, electron beam evaporation or magnetron sputtering equipment.

7. The method for fabricating a self-aligned top-gate field-effect transistor based on two-dimensional materials according to claim 2, characterized in that, In step (5), the selective wet etching of the oxide dielectric layer is performed using a solution composed of one or more of H3PO4, HNO3, HF, and NH4F.

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