An enhanced gallium nitride based transistor and method of fabrication thereof

Abstract

An enhanced gallium nitride-based transistor comprises, from bottom to top, a substrate, a composite buffer layer, a channel layer and a barrier layer, a P-type nitride cap layer, a passivation layer, a source electrode, a drain electrode and a gate electrode are arranged on the barrier layer, the P-type nitride cap layer is surrounded by the gate electrode on the side and top surface, the passivation layer is arranged between the gate electrode and the source electrode and between the gate electrode and the drain electrode; the gate electrode forms a Schottky contact with the barrier layer, and the source electrode and the drain electrode both form an ohmic contact with the barrier layer; a heterojunction is formed between the channel layer and the barrier layer, and a two-dimensional electron gas channel is formed on the channel layer side of the heterojunction interface by a polarization effect. The P-type nitride cap layer depletes part of the two-dimensional electron gas in the channel, increases the threshold voltage of the device, and achieves the purpose of an enhanced device. The gate electrode around the P-type nitride cap layer solves the problems of weak gate control ability and large on-resistance of conventional P-type nitride enhanced devices, and reduces the gate length and improves the frequency characteristics.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology, and specifically relates to an enhancement-enhanced gallium nitride-based transistor and its fabrication method. Background Technology

[0002] Gallium nitride (GaN), a typical material for third-generation semiconductors, possesses a large bandgap (3.4 eV), high electron mobility, and high electron saturation velocity, making it a promising candidate for applications in next-generation radio frequency devices and power electrical devices. In particular, GaN and other III-V group nitride materials (such as AlGaN) can form high electron mobility transistors (HEMTs) with heterojunction structures. This is because the unique spontaneous polarization and piezoelectric polarization effects of nitride materials create a high concentration (1 × 10⁻⁶) of electrons at the heterojunction interface. 13 cm -2 ), with a relatively high migration rate (2000cm). 2 Gallium nitride heterojunction structure (GaN) is used to fabricate high electron mobility transistors (HEMTs) with a two-dimensional electron gas of / V·s. HEMTs have characteristics such as high breakdown voltage, low on-resistance, high switching frequency, and small size. They are suitable for operation under high temperature, high frequency, strong radiation, and high power conditions. They are considered to be candidate core switching devices for next-generation power electronic systems and are suitable for applications in consumer electronics, data center power supplies, home appliances, electric vehicles, rail transportation, smart grids and other fields.

[0003] Because the two-dimensional electron gas is formed during the formation of the heterojunction structure, the conduction channel of this device is normally open. A certain reverse voltage needs to be applied to the gate to deplete the two-dimensional electron gas in the device channel and achieve the turn-off state. However, gallium nitride-based HEMTs are used as power electronic devices in various high-power applications. Normally off transistors are usually the first choice to ensure the safe operation of the power electronic system, reduce the need for negative voltage generation circuits and protection circuits, thereby simplifying circuit and system design and reducing static power consumption. All of these require the device to be in the off state at zero gate voltage. Such devices are also called enhancement-mode devices.

[0004] Currently, reported methods for realizing gallium nitride (GaN)-based enhancement-mode HEMT devices include thin barrier layers, trench gates, under-gate pn junctions, and under-gate fluorine plasma implantation. Among these, devices using p-type GaN as the gate cap layer have attracted widespread attention due to their superior performance, such as high threshold voltage (around 2V) and high gate voltage swing. The role of the p-type GaN layer is to raise the energy band and deplete the two-dimensional electron gas in the under-gate channel layer, thereby achieving enhancement mode. To date, p-type GaN gate technology has become the main method for realizing GaN-based enhancement-mode HEMT devices. However, this technology still has shortcomings. While introducing a p-type GaN structure under the gate electrode to achieve enhancement-mode devices, it also increases the distance between the gate metal and the channel layer, leading to a decrease in the device's transconductance peak and reduced gate control capability. At the same time, the two-dimensional electron gas in the channel region under the gate is completely depleted, increasing the on-resistance of the device. To solve this problem, the p-type GaN layer can generally be thinned, but excessive thinning will affect the device's threshold voltage, thus losing the enhancement-mode function. Summary of the Invention

[0005] To overcome the shortcomings of the prior art, the present invention aims to provide an enhancement-type gallium nitride-based transistor and its fabrication method. By utilizing the designed gate structure and P-type nitride cap layer, the threshold voltage of the device is improved, resulting in an enhancement-type GaN-based transistor. This solves the problems of weak gate control capability and high on-resistance of conventional P-type nitride enhancement-type devices, thereby improving their gate control capability and conduction characteristics. Furthermore, compared with traditional enhancement-type devices, the reduction in gate length of this structure improves the frequency characteristics of the device.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0007] An enhancement-mode gallium nitride-based transistor includes, from bottom to top, a substrate, a composite buffer layer, a channel layer, and a barrier layer. The composite buffer layer, channel layer, and barrier layer are all made of group III nitride semiconductors. A P-type nitride cap layer, a passivation layer, a source electrode, a drain electrode, and a gate electrode are disposed on the barrier layer. The P-type nitride cap layer is surrounded by the gate electrode on both its side and top surfaces. The passivation layer is disposed between the gate electrode and the source electrode, and between the gate electrode and the drain electrode. The gate electrode forms a Schottky contact with the barrier layer, and both the source electrode and the drain electrode form ohmic contacts with the barrier layer. A heterojunction is formed between the channel layer and the barrier layer, and a two-dimensional electron gas channel is formed on one side of the channel layer at the heterojunction interface due to polarization effects. The P-type nitride cap layer partially depletes the two-dimensional electron gas in the device channel, causing the device to be in a turn-off state without a gate voltage, thus achieving enhancement mode.

[0008] In one embodiment, the substrate is one of silicon, sapphire, silicon carbide, and diamond.

[0009] In one embodiment, the group III nitride semiconductor is gallium nitride, aluminum nitride, indium nitride, or a multi-component compound consisting of two or more of these.

[0010] In one embodiment, the composite buffer layer comprises three layers, from bottom to top: a nucleation layer, a transition layer, and a buffer layer. The nucleation layer is made of AlN or GaN and has a thickness of 100-300 nm. The transition layer is made of AlGaN and has a thickness of 200-1000 nm. The buffer layer is made of GaN or AlGaN and has a thickness of 100-3000 nm.

[0011] In one embodiment, the channel layer is made of GaN or InGaN and has a thickness of 50 nm-500 nm; the barrier layer is made of AlGaN or InAlN or AlN or InAlGaN and has a thickness of 2-40 nm; the passivation layer is made of SiN or SiO2 or Al2O3 and has a thickness of 10-300 nm; the p-type nitride cap layer is made of GaN or InGaN and is doped with Mg at a doping concentration of 1 × 10⁻⁶. 17 -7×10 19 The thickness is 50-200nm.

[0012] In one embodiment, the gate electrode uses two metal layers, with the bottom layer being made of Ti, Ni, Al, Ta, TiN, or TaN; the source electrode and the drain electrode use four metal layers, with the bottom two layers being made of Ti / Al, Ta / Al, or Mo / Al.

[0013] In one embodiment, an isolation layer is provided between the barrier layer and the channel layer. The isolation layer is made of AlN and has a thickness of 0.5-2 nm.

[0014] The present invention also provides a method for fabricating the aforementioned enhanced gallium nitride-based transistor, comprising the following steps:

[0015] S1: Group III nitrides are sequentially epitaxially grown on the substrate using metal-organic chemical vapor deposition (MOCVD) as a composite buffer layer;

[0016] S2: The channel layer, barrier layer and p-type nitride cap layer are epitaxially grown on the composite buffer layer using metal-organic chemical vapor deposition (MOCVD).

[0017] S3: Electrical isolation of the device is fabricated on the barrier layer and the channel layer;

[0018] S4: Part of the P-type nitride cap layer is removed from the surface of the barrier layer. The source electrode and drain electrode are prepared by vacuum evaporation or magnetron sputtering and then subjected to high-temperature thermal annealing to form an ohmic contact with the two-dimensional electron gas.

[0019] S5: The gate electrode is prepared by vacuum evaporation or magnetron sputtering, forming a Schottky contact with the barrier layer, and the gate electrode surrounds the P-type nitride cap layer;

[0020] S6: A nitride film is deposited between the source and drain electrodes on the surface of the barrier layer using PECVD deposition to form a passivation layer.

[0021] In one embodiment, in step S1, a group III nitride nucleation layer, a transition layer, and a buffer layer are grown sequentially as a composite buffer layer; in step S2, an isolation layer is also grown in the channel layer and the barrier layer.

[0022] In one embodiment, S1 employs metal-organic chemical vapor deposition (MOCVD), which involves first growing a nucleation layer at a low temperature of 500-650°C using MOCVD, and then raising the temperature to 1000-1100°C to grow a transition layer and a buffer layer using MOCVD.

[0023] Compared with the prior art, the beneficial effects of the present invention are:

[0024] First, the enhancement-mode device with a P-type gallium nitride cap layer surrounded by a gate electrode, as described in this invention, improves device performance by using a method of surrounding the gate cap layer on three sides without changing the thickness of the P-GaN cap layer:

[0025] (1) The distance between the gate electrode and the channel layer is reduced. This structure can better control the two-dimensional electron gas in the channel, thereby improving the transconductance of the device while achieving enhancement mode.

[0026] (2) Compared with traditional P-GaN enhancement devices, the channel depletion region of this structure is reduced by a portion (and is not as long as the upper gate), which reduces the on-resistance of the device.

[0027] (3) Compared with traditional P-GaN devices, the gate length of this structure is reduced, so the frequency characteristics are improved accordingly.

[0028] Second, the technology proposed in this invention is compatible with existing processes, the manufacturing process is relatively simple, and the device performance is significantly improved. Attached Figure Description

[0029] Figure 1 This is a schematic diagram (cross-sectional view) of the structure of the enhanced gallium nitride-based transistor of the present invention.

[0030] Figure 2 This is a schematic diagram (top view) of the structure of the enhanced gallium nitride-based transistor of the present invention.

[0031] Figure 3This is a schematic diagram illustrating the composite buffer layer and isolation layer structure in the enhanced gallium nitride-based transistor of the present invention.

[0032] Figure 4 This is a schematic diagram of the fabrication process of the enhanced gallium nitride-based transistor of the present invention. Detailed Implementation

[0033] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings and examples.

[0034] like Figure 1 and Figure 2 As shown, this invention relates to an enhancement-mode gallium nitride-based transistor, comprising, from bottom to top, a substrate 1, a composite buffer layer 2, a channel layer 3, and a barrier layer 4, wherein a source electrode 7, a drain electrode 8, and a gate electrode 9 are disposed on the barrier layer 4. The gate electrode 9 forms a Schottky contact with the barrier layer 4, and both the source electrode 7 and the drain electrode 8 form ohmic contacts with the barrier layer 4. A heterojunction is formed between the channel layer 3 and the barrier layer 4, and a two-dimensional electron gas channel is formed on one side of the channel layer 3 at the heterojunction interface due to polarization effects.

[0035] To improve the gate control capability, frequency characteristics and conduction characteristics of transistor devices, the present invention also provides a P-type nitride cap layer 6 on the barrier layer 4, improves the shape of the gate electrode 9, and adaptively adds a passivation layer 5.

[0036] In this design, the P-type nitride cap layer 6 is located in the middle of the upper surface of the barrier layer 4, and is surrounded by the gate electrode 9 on three sides (side and top). The source electrode 7 and drain electrode 8 are respectively arranged on both sides of the gate electrode 9. The P-type nitride cap layer 6 depletes part of the two-dimensional electron gas in the device channel, keeping the device in a turn-off state without a gate voltage, thus achieving enhancement mode. Specifically, the P-type nitride cap layer 6 raises the energy band of the barrier layer, depleting the two-dimensional electron gas in the channel layer 3 below it, thereby increasing the threshold voltage of the device and achieving enhancement mode.

[0037] Furthermore, compared to conventional enhancement-mode devices, without changing the thickness of the P-type nitride cap layer 6, the method of surrounding the P-type nitride cap layer 6 on three sides with the gate electrode 9 reduces the distance between the gate electrode 9 and the channel layer 3, shortens the channel depletion region, and reduces the gate length, thereby improving the transconductance, frequency, and conduction characteristics of the device.

[0038] In this invention, the substrate 1 may be one of silicon, sapphire, silicon carbide, or diamond.

[0039] In this invention, the composite buffer layer 2, the channel layer 3, and the barrier layer 4 are all made of group III nitride semiconductors, such as gallium nitride, aluminum nitride, indium nitride, or a multi-component compound consisting of two or more of them.

[0040] For example, in this invention, the composite buffer layer 2 may include three layers, such as... Figure 3 As shown, from bottom to top, the layers are a nucleation layer 21, a transition layer 22, and a buffer layer 23. The nucleation layer 21 can be made of AlN or GaN, with a thickness of 100-300 nm. The transition layer 22 can be made of AlGaN, with a thickness of 200-1000 nm. Preferably, it can be made of graded aluminum gallium nitride, with the composition gradually changing from 0.75 to 0.15. The buffer layer 23 can be made of GaN or AlGaN, with a thickness of 100-3000 nm.

[0041] For example, in this invention, the channel layer 3 can be made of GaN or InGaN, with a thickness of 50nm-500nm. The barrier layer 4 can be made of AlGaN or InAlN or AlN or InAlGaN, with a thickness of 2-40nm; the passivation layer 5 can be made of SiN or SiO2 or Al2O3, with a thickness of 10-300nm; the p-type nitride cap layer 6 can be made of GaN or InGaN, with Mg as the dopant and a doping concentration of 1×10⁻⁶. 17 -7×10 19 The thickness is 50-200nm.

[0042] For example, in this invention, the gate electrode 9 uses two metal layers, with the upper layer being Au and the lower layer being Ti, Ni, Al, Ta, TiN, or TaN; the source electrode 7 and the drain electrode 8 use four metal layers of Ti / Al / Ni / Au, with the bottom two layers being Ti / Al, Ta / Al, or Mo / Al.

[0043] For example, in this invention, an isolation layer 31 may be provided between the barrier layer 4 and the channel layer 3. The material of the isolation layer 31 may be AlN, and the thickness may be 0.5-2nm.

[0044] refer to Figure 4 The present invention provides a method for fabricating an enhanced gallium nitride-based transistor, comprising the following steps:

[0045] S1: A group III nitride is sequentially epitaxially grown on substrate 1 using metal-organic chemical vapor deposition (MOCVD) as a composite buffer layer 2. For example, a nucleation layer 21 is first grown using MOCVD at a low temperature of 500-650℃, and then a transition layer 22 and a buffer layer 23 are grown using MOCVD at a temperature of 1000-1100℃. The nucleation layer 21, the transition layer 22, and the buffer layer 23 are used as the composite buffer layer 2.

[0046] S2: A channel layer 3, a barrier layer 4, and a p-type nitride cap layer 6 are epitaxially grown on the composite buffer layer 2 using metal-organic chemical vapor deposition (MOCVD). For example, an isolation layer 31 may also be grown on the channel layer 3 and the barrier layer 4.

[0047] S3: Electrical isolation of the device is fabricated on barrier layer 4 and channel layer 3.

[0048] S4: Part of the P-type nitride cap layer 6 is removed from the surface of the barrier layer 4. The source electrode 7 and drain electrode 8 are prepared by vacuum evaporation or magnetron sputtering and then subjected to high-temperature thermal annealing to form an ohmic contact with the two-dimensional electron gas.

[0049] S5: The gate electrode 9 is prepared by vacuum evaporation or magnetron sputtering technology, forming a Schottky contact with the barrier layer 4, and the gate electrode 9 surrounds the P-type nitride cap layer 6.

[0050] S6: A nitride film is deposited on the surface of barrier layer 4 using PECVD deposition to form passivation layer 5.

[0051] The present invention provides the following three embodiments for fabricating the above-mentioned device:

[0052] Example 1: The substrate 1 is P-type silicon with a thickness of 725 μm. The nucleation layer 21 is aluminum nitride with a thickness of 200 nm. The transition layer 22 is aluminum gallium nitride with a thickness of 800 nm, and the aluminum composition gradually changes from 0.75 to 0.15. The buffer layer 23 is gallium nitride with a thickness of 1000 nm. The channel layer 3 is gallium nitride with a thickness of 300 nm. The barrier layer 4 is aluminum gallium nitride with an aluminum composition of 0.15 and a thickness of 10 nm. The isolation layer 31 is aluminum nitride with a thickness of 1 nm. The passivation layer 5 is SiN with a thickness of 100 nm. The P-type gallium nitride cap layer 6 is 100 nm thick. The bottom two layers of the source electrode 7 and drain electrode 8 are Ti / Al, and the bottom layer of the gate electrode 9 is Ni.

[0053] Step 1: Clean the silicon substrate, such as... Figure 4 As shown in Figure a.

[0054] At a high temperature of 1000℃, hydrogen gas is introduced into the reaction chamber to remove contaminants from the surface of substrate 1 and form a microscopic step structure on the substrate surface so that various epitaxial layers can be grown in subsequent epitaxial processes.

[0055] Step 2: Epitaxially grow composite buffer layer 2 on substrate 1, such as... Figure 4 As shown in b.

[0056] The composite buffer layer 2 consists of three layers: first, an aluminum nitride nucleation layer 21 with a thickness of 200 nm is grown on the substrate using the MOCVD method at a low temperature of 500℃.

[0057] Then, the temperature was raised to 1000℃, and a transition layer 22 with a thickness of 800 nm was grown on the nucleation layer 21 using the MOCVD method. The Al composition was gradually changed from 0.75 to 0.15. Then, a GaN buffer layer 23 with a thickness of 1000 nm was grown on the transition layer.

[0058] Step 3: Fabricate the channel layer 3, isolation layer 31, barrier layer 4, and p-type nitride cap layer 6, as follows: Figure 4 As shown in c.

[0059] Using the MOCVD method, a GaN channel layer 3 with a thickness of 300 nm was first grown on the buffer layer 23 at a temperature of 1000 °C.

[0060] Then, a 1 nm thick AlN isolation layer 31 is epitaxially formed on the channel layer 3, and a 10 nm thick AlGaN barrier layer 4 is epitaxially formed on the isolation layer 31, with an Al composition of 0.15.

[0061] Finally, a p-type nitride cap layer 6 is epitaxially grown on barrier layer 4. The material is gallium nitride, doped with Mg, and the doping concentration is 3x10⁻⁶. 19 cm -3 The thickness is 100nm.

[0062] Step four, cleaning.

[0063] After completing the above steps, the sample is first placed in acetone to remove organic contaminants from the surface, then placed in an acidic solvent to remove the surface oxide layer and inorganic contaminants, and finally the surface solvent is removed with deionized water and dried in a nitrogen atmosphere.

[0064] Step 5: Etch the platform to create an isolation layer, such as... Figure 4 As shown in d.

[0065] A photoresist mask is fabricated using photolithography to expose part of the surface of the P-type nitride cap layer 6. Reactive ion etching (RIE) is then used to etch away the P-type nitride cap layer 6, the AlGaN barrier layer 4, the GaN channel layer 3, and part of the buffer layer 23 that are not covered by the photoresist mask, creating a mesa with neat edges and steep sidewalls, forming an isolation region between different transistors.

[0066] Step six, fabricate the source electrode 7 and drain electrode 8, as follows: Figure 4 As shown in e.

[0067] A photoresist mask is fabricated using photolithography to expose part of the P-type nitride cap layer 6. Reactive ion etching (RIE) is then used to etch away the unmasked P-type nitride cap layer 6, and residual photoresist is cleaned away. For example... Figure 4 As shown in f.

[0068] Then, a photolithography process is used to create a photoresist mask, exposing the areas where the source electrode 7 and drain electrode 8 will be fabricated.

[0069] Then, a multilayer metal Ti / Al / Ni / Au layer is grown in this region by electron beam evaporation, namely, Ti with a thickness of 20 nm, Al with a thickness of 120 nm, Ni with a thickness of 40 nm, and Au with a thickness of 50 nm from bottom to top. After peeling, the source electrode 7 and the drain electrode 8 are formed.

[0070] Then, rapid thermal annealing is carried out in a nitrogen atmosphere at 850℃ for 30 seconds to form an ohmic contact between the source electrode 7, the drain electrode 8 and the barrier layer 4.

[0071] Step 7, fabricate gate electrode 9, as follows Figure 4 As shown in g.

[0072] A photoresist mask is fabricated using photolithography to expose the area where the gate electrode 9 will be fabricated.

[0073] The Ni / Au combined gate electrode metal was then fabricated using electron beam evaporation, with Ni having a thickness of 50 nm and Au a thickness of 280 nm. After peeling, the gate electrode 9 was formed. Figure 4 As shown in j.

[0074] Finally, the device is thermally annealed at 460°C for 10 minutes to form a Schottky contact between the gate electrode 9, the barrier layer 4, and the P-type nitride cap layer 6, thus completing the fabrication of the entire device.

[0075] Step 8: Create passivation layer 5.

[0076] A silicon nitride thin film with a thickness of 100 nm is deposited between the source electrode 7 and the drain electrode 8 on the surface of the barrier layer to form a passivation layer 5.

[0077] Example 2: A silicon carbide substrate 1, p-type doped, with a thickness of 300 μm. The nucleation layer 21 is gallium nitride, with a thickness of 200 nm. The transition layer 22 is aluminum gallium nitride, with a thickness of 500 nm and an aluminum composition of 0.55. The buffer layer 23 is aluminum gallium nitride, with an aluminum composition of 0.05 and a thickness of 1000 nm. The channel layer 3 is gallium nitride, with a thickness of 300 nm. The barrier layer 4 is aluminum gallium nitride, with a composition of 0.15 and a thickness of 15 nm. The isolation layer 31 is AlN, with a thickness of 1.5 nm. The passivation layer 5 is SiO2, with a thickness of 150 nm. The p-type nitride cap layer 6 is gallium nitride, with a thickness of 60 nm. The source electrode 7, drain electrode 8, and the bottom two layers are Ta / Al, while the gate electrode 9 has a Ti bottom layer, forming a transistor.

[0078] Step 1, clean the silicon carbide substrate 1, such as... Figure 4 As shown in Figure a.

[0079] The silicon carbide substrate 1 was placed in an organic acetone solution to wash away the grease and contaminants on its surface, then rinsed with flowing deionized water, and finally dried with high-purity nitrogen gas.

[0080] Step 2, epitaxially grow composite buffer layer 2 on substrate 1, such as Figure 4 As shown in b.

[0081] 2.1) An aluminum nitride nucleation layer 21 of 200 nm was grown on the surface of substrate 1 by MOCVD at a low temperature of 600 °C.

[0082] 2.2) The temperature was raised to 1000℃, and 500 nm Al atoms were sequentially grown on the aluminum nitride nucleation layer using MOCVD. 0.55 Ga 0.25 N transition layer 22 and Al with a thickness of 1000 nm 0.05 Ga 0.25 N buffer layer 23.

[0083] Step 3: Fabricate the channel layer 3, isolation layer 31, barrier layer 4, and p-type nitride cap layer 6, as follows: Figure 4 As shown in c.

[0084] 3.1) Using the MOCVD method, a GaN channel layer with a thickness of 300 nm was first grown on the buffer layer at a temperature of 1000 °C.

[0085] 3.2) A 1.5 nm thick AlN isolation layer is epitaxially deposited on channel layer 3. Finally, a 15 nm thick AlN isolation layer is epitaxially deposited on isolation layer 31. 0.15 Ga 0.25 N-barrier layer 4.

[0086] 3.3) A 60 nm P-type gallium nitride cap layer, doped with Mg, is epitaxially formed on barrier layer 4 with a doping concentration of 5 x 10⁻⁶ nm. 19 cm -3 .

[0087] Step 4, cleaning.

[0088] The specific implementation of this step is the same as step four in Example 1.

[0089] Step 5: Etch the platform to create an isolation layer, such as... Figure 4 As shown in d.

[0090] A photoresist mask is fabricated using photolithography to expose part of the surface of the P-type nitride cap layer 6. Reactive ion etching (RIE) equipment and technology are then used to etch away the P-type nitride cap layer 6, AlGaN barrier layer 4, GaN channel layer 3, and part of the buffer layer 23 that are not covered by the photoresist mask, creating a mesa with neat edges and steep sidewalls, forming an isolation region between different transistors.

[0091] Step 6, fabricate the source electrode 7 and drain electrode 8, as follows: Figure 4 As shown in e.

[0092] 6.1) A photoresist mask is fabricated using photolithography to expose part of the surface of the P-type nitride cap layer 6.

[0093] 6.2) The P-type nitride cap layer 6, which is not covered by a photoresist mask, is etched away using reactive ion etching equipment and technology (RIE) and the residual photoresist is cleaned away.

[0094] 6.3) Then, a photolithography process is used to create a photoresist mask to expose the area where the source electrode 7 and drain electrode 8 are to be fabricated.

[0095] 6.4) Then, a multilayer metal Ta / Al / Ni / Au layer is grown in this region by electron beam evaporation, namely, from bottom to top, a 20 nm thick Ta layer, a 120 nm thick Al layer, a 40 nm thick Ni layer, and a 50 nm thick Au layer, forming the source electrode 7 and the drain electrode 8. After stripping, the source electrode 7 and the drain electrode 8 are formed.

[0096] 6.5) Then, perform rapid thermal annealing for 30 seconds in a nitrogen atmosphere at 850°C to make the source electrode 7, drain electrode 8 and barrier layer 4 form ohmic contact.

[0097] Step 7, fabricate the gate electrode 9, as follows Figure 4 As shown in g.

[0098] 7.1) Use photolithography to create a photoresist mask to expose the area where the gate electrode 9 will be fabricated.

[0099] 7.2) A Ti / Au combined gate electrode metal was then fabricated using electron beam evaporation, wherein the Ti layer was 50 nm thick and the Au layer was 280 nm thick. After peeling, the gate electrode 9 was formed. Figure 4 As shown in g.

[0100] 7.3) Finally, the device is thermally annealed at 460°C for 10 minutes to form a Schottky contact between the gate electrode 9 and the barrier layer 4 and the cap layer 6, thus completing the fabrication of the entire device.

[0101] Step 8: Create passivation layer 5.

[0102] A 150 nm thick silicon dioxide film was deposited between the source and drain electrodes on the surface of the barrier layer using PECVD deposition to form a passivation layer 5.

[0103] Example 3: A sapphire substrate 1 with a thickness of 300 μm is used. The gallium nitride nucleation layer 21 has a thickness of 300 nm. The gallium nitride transition layer 22 has a thickness of 1000 nm, and the gallium nitride buffer layer 23 has a thickness of 500 nm. The gallium nitride channel layer 3 has a thickness of 200 nm. The barrier layer 4 is made of aluminum gallium nitride with an aluminum content of 0.2% and a thickness of 20 nm. The isolation layer 31 is made of AlN with a thickness of 0.5 nm. The passivation material is SiN with a thickness of 300 nm. The p-type nitride cap layer 6 is 80 nm thick. The bottom two layers of the source and drain electrodes are Ti / Al, and the bottom layer of the gate electrode is TiN.

[0104] Step A, clean sapphire substrate 1, as follows: Figure 4 As shown in Figure a.

[0105] The sapphire substrate is cleaned by removing oil, sweat, and other impurities from its surface using organic substances such as acetone, and then dried with nitrogen.

[0106] Step B, epitaxially grow composite buffer layer 2 on substrate 1, such as Figure 4 As shown in b.

[0107] First, a 300 nm gallium nitride nucleation layer 21 was grown on substrate 1 using the MOCVD method at a low temperature of 650 °C.

[0108] The temperature is then increased to 1100℃, and a 1000nm thick gallium nitride transition layer 22 is grown using the MOCVD method. A 500nm thick gallium nitride buffer layer 23 is then grown on the transition layer.

[0109] Step C, fabricate channel layer 3, isolation layer 31, barrier layer 4, and p-type nitride cap layer 6, as follows: Figure 4 As shown in c.

[0110] First, the MOCVD method was used to grow a GaN channel layer with a thickness of 200 nm on the buffer layer at a temperature of 1000℃.

[0111] Then, a 0.5 nm thick AlN isolation layer 31 is epitaxially formed on the channel layer 3, and finally, a 20 nm thick AlN layer is epitaxially formed on the isolation layer 31. 0.2 Ga 0.25 N-barrier layer 4.

[0112] Finally, a p-type nitride cap layer is epitaxially layered on barrier layer 4. The material is gallium nitride, doped with Mg, and the doping concentration is 4 x 10⁻⁶. 19 cm -3 The thickness is 80nm.

[0113] Step D, cleaning.

[0114] The specific implementation of this step is the same as step five in Example 1.

[0115] Step E: Etch the mesa to create an isolation layer, such as... Figure 4 As shown in d.

[0116] A photoresist mask is fabricated using photolithography to expose part of the surface of the P-type nitride cap layer 6. Reactive ion etching (RIE) equipment and technology are then used to etch away the P-type nitride cap layer 6, AlGaN barrier layer 4, GaN channel layer 3, and part of the buffer layer 23 that are not covered by the photoresist mask, creating a mesa with neat edges and steep sidewalls, forming an isolation region between different transistors.

[0117] Step F: Fabricate source electrode 7 and drain electrode 8, as follows Figure 4 As shown in ef.

[0118] A photoresist mask is fabricated using photolithography to expose part of the P-type nitride cap layer 6. Reactive ion etching (RIE) is then used to etch away the unmasked P-type nitride cap layer 6, and residual photoresist is cleaned away. Figure 4 As shown in e

[0119] Then, a photolithography process is used to create a photoresist mask, exposing the areas where the source electrode 7 and drain electrode 8 will be fabricated.

[0120] Then, a multilayer metal Ti / Al / Ni / Au layer is grown in this region by electron beam evaporation, consisting of a 20nm thick Ti layer, a 120nm thick Al layer, a 40nm thick Ni layer, and a 50nm thick Au layer from bottom to top. After peeling, the source electrode 7 and the drain electrode 8 are formed. Figure 4 As shown in f

[0121] Then, rapid thermal annealing is carried out in a nitrogen atmosphere at 850℃ for 30 seconds to form an ohmic contact between the source electrode 7, the drain electrode 8 and the barrier layer 4.

[0122] Step G, fabricate gate electrode 9, as follows Figure 4 As shown in g.

[0123] A 300 nm thick silicon nitride film was deposited between the source and drain electrodes on the surface of the barrier layer using PECVD deposition to form a passivation layer 5.

[0124] Next, a gate pattern is photolithographically etched onto the silicon nitride thin film in the middle region of the passivation layer, and the exposed passivation layer is removed using reactive ion etching. Then, a TiN / Au combined gate metal is fabricated using magnetron sputtering, where the TiN thickness is 50 nm and the Au thickness is 280 nm, forming gate electrode 9. Figure 4 As shown in g.

[0125] Finally, the device is thermally annealed at 460°C for 10 minutes to form a Schottky contact between the gate electrode and the barrier and cap layers, thus completing the fabrication of the entire device.

[0126] The above description is merely three specific examples of the present invention and does not constitute any limitation on the present invention. Obviously, those skilled in the art, after understanding the content and principle of the present invention, may make various modifications and changes in form and details without departing from the principle and structure of the present invention. For example, in addition to silicon, silicon carbide, and sapphire, the substrate 1 can also be a diamond substrate; in addition to gallium nitride, the buffer layer 23 can also be made of aluminum gallium nitride; in addition to aluminum gallium nitride, the barrier layer 4 can also be made of indium aluminum nitride, aluminum nitride, or indium aluminum gallium nitride; in addition to gallium nitride, the channel layer 4 can also be made of aluminum gallium nitride; in addition to gallium nitride, the cap layer 6 can also be made of aluminum gallium nitride; in addition to Ti / Al and Ta / Al, the bottom two metal layers of the source electrode 7 and drain electrode 8 can also be made of Mo / Al; in addition to Ti and TiN, the bottom layer of the gate electrode 9 can also be made of Al, Ta, Ni, or TaN. Furthermore, the thickness of each epitaxial layer only needs to meet the scope of the technical solution in the specification. However, these modifications and changes based on the concept of the present invention are still within the protection scope of the present invention.

Claims

1. An enhancement-mode gallium nitride-based transistor, comprising, from bottom to top, a substrate (1), a composite buffer layer (2), a channel layer (3), and a barrier layer (4), characterized in that, The composite buffer layer (2), channel layer (3), and barrier layer (4) are all made of group III nitride semiconductors. The composite buffer layer (2) includes three layers, from bottom to top: nucleation layer (21), transition layer (22), and buffer layer (23). The nucleation layer (21) is made of AlN or GaN and has a thickness of 100-300 nm. The transition layer (22) is made of AlGaN and has a thickness of 200-1000 nm. The buffer layer (23) is made of GaN or AlGaN and has a thickness of 100-3000 nm. A P-type nitride cap layer (6), a passivation layer (5), a source electrode (7), a drain electrode (8), and a gate electrode (9) are disposed on the barrier layer (4). The P-type nitride cap layer (6) is surrounded by the gate electrode (9) on both the side and top surfaces. The passivation layer (5) is disposed between the gate electrode (9) and the source electrode (7) and between the gate electrode (9) and the drain electrode (8). The gate electrode (9) forms a Schottky contact with the barrier layer (4), and the source electrode (7) and the drain electrode (8) both form an ohmic contact with the barrier layer (4). A heterojunction is formed between the channel layer (3) and the barrier layer (4), and a two-dimensional electron gas channel is formed on one side of the channel layer (3) at the heterojunction interface by polarization effect. The P-type nitride cap layer (6) causes the two-dimensional electron gas in the device channel to be partially depleted, so that the device is in the off state without gate voltage, thereby achieving the purpose of enhancement mode.

2. The enhanced gallium nitride-based transistor according to claim 1, characterized in that, The substrate (1) is one of silicon, sapphire, silicon carbide, and diamond.

3. The enhanced gallium nitride-based transistor according to claim 1, characterized in that, The group III nitride semiconductor is a multi-component compound composed of gallium nitride, aluminum nitride, indium nitride, or two or more of these.

4. The enhanced gallium nitride-based transistor according to claim 1, characterized in that, The channel layer (3) is made of GaN or InGaN and has a thickness of 50nm-500nm; the barrier layer (4) is made of AlGaN or InAlN or AlN or InAlGaN and has a thickness of 2-40nm; the passivation layer (5) is made of SiN or SiO2 or Al2O3 and has a thickness of 10-300nm; the p-type nitride cap layer (6) is made of GaN or InGaN and is doped with Mg at a doping concentration of 1×10⁻⁶. 17 -7×10 19 The thickness is 50-200nm.

5. The enhanced gallium nitride-based transistor according to claim 1, characterized in that, The gate electrode (9) uses two layers of metal, with the lower layer being made of Ti, Ni, Al, Ta, TiN, or TaN; the source electrode (7) and the drain electrode (8) use four layers of metal, with the bottom two layers being made of Ti / Al, Ta / Al, or Mo / Al.

6. The enhanced gallium nitride-based transistor according to claim 1, characterized in that, An isolation layer (31) is provided between the barrier layer (4) and the channel layer (3). The material of the isolation layer (31) is AlN, and the thickness is 0.5-2nm.

7. The method for fabricating the enhanced gallium nitride-based transistor according to claim 1, characterized in that, Includes the following steps: S1: Group III nitrides were epitaxially grown sequentially on the substrate (1) as a composite buffer layer (2) using metal-organic chemical vapor deposition (MOCVD). S2: A channel layer (3), a barrier layer (4), and a p-type nitride cap layer (6) are epitaxially grown on the composite buffer layer (2) using metal-organic chemical vapor deposition (MOCVD). S3: Electrical isolation of the device is fabricated on the barrier layer (4) and the channel layer (3); S4: Remove part of the P-type nitride cap layer (6) on the surface of the barrier layer (4), prepare the source electrode (7) and drain electrode (8) by vacuum evaporation or magnetron sputtering, and perform high-temperature thermal annealing to form an ohmic contact with the two-dimensional electron gas; S5: The gate electrode (9) is prepared by vacuum evaporation or magnetron sputtering technology, forming a Schottky contact with the barrier layer (4), and the gate electrode (9) surrounds the P-type nitride cap layer (6). S6: A nitride film is deposited between the source electrode (7) and the drain electrode (8) on the surface of the barrier layer (4) using the PECVD deposition method to form a passivation layer (5).

8. The enhanced gallium nitride-based transistor according to claim 7, characterized in that, In S1, a group III nitride nucleation layer (21), a transition layer (22) and a buffer layer (23) are grown sequentially to form a composite buffer layer (2); in S2, an isolation layer (31) is also grown in the channel layer (3) and the barrier layer (4).

9. The enhanced gallium nitride-based transistor according to claim 8, characterized in that, The S1 adopts the metal-organic chemical vapor deposition (MOCVD) method, which first grows a nucleation layer (21) at a low temperature of 500-650℃ using the MOCVD method, and then raises the temperature to 1000-1100℃ to grow a transition layer (22) and a buffer layer (23) using the MOCVD method.

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