Impedance matching circuit, method, integrated circuit, and electronic device

Abstract

The application discloses an impedance matching circuit, method, integrated circuit and electronic device. The impedance matching circuit comprises a reference module, a biasing module and a connecting module. The biasing module is configured to generate a first feedback signal according to a first node voltage of a first intermediate node and transmit the first feedback signal to a second end of the biasing module. The biasing module is further configured to generate a second feedback signal and transmit the second feedback signal to a third end of the biasing module. When the first node voltage is not equal to a preset reference voltage, the biasing module adjusts the first node voltage according to the first feedback signal, so that the first node voltage is equal to the preset reference voltage. The connecting module adjusts a voltage of a signal port according to the first feedback signal and the second feedback signal, so that the voltage of the signal port is equal to the preset reference voltage.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and more specifically, to an impedance matching circuit, method, integrated circuit, and electronic device. Background Technology

[0002] With the rapid development of technology, integrated circuits have been widely used in various electronic devices, such as mobile phones, tablets, and laptops. To meet the demands for faster operating speeds in electronic devices, modern integrated circuits feature increasingly faster system clock speeds.

[0003] However, transmission lines have characteristic impedance. As the system clock speed increases, problems such as reflection and crosstalk can occur, affecting signal integrity. Typically, impedance matching circuits are used to match the impedance of the device's input / output ports with the characteristic impedance of the transmission line, thus avoiding problems such as reflection and crosstalk.

[0004] However, existing impedance matching circuits suffer from technical challenges such as limited adjustment accuracy, impact on signal quality, occupation of system clock resources, and high application development difficulty, making further promotion and application difficult. Summary of the Invention

[0005] In view of the above problems, this application proposes an impedance matching circuit, method, integrated circuit, and electronic device to improve the above problems.

[0006] In a first aspect, embodiments of this application provide an impedance matching circuit. The circuit includes a reference module, a bias module, and a connection module. A first terminal of the reference module is connected to a first intermediate node, and a second terminal of the reference module is grounded. The first terminal of the bias module is connected to the first intermediate node, and the bias module is used to generate a first feedback signal based on the first node voltage of the first intermediate node, and transmit the first feedback signal to the second terminal of the bias module; the bias module is also used to generate a second feedback signal, and transmit the second feedback signal to a third terminal of the bias module. The first terminal of the connection module is connected to the second terminal of the bias module, the second terminal of the connection module is connected to the third terminal of the bias module, and the third terminal of the connection module is connected to a signal port. Wherein, when the first node voltage is not equal to a preset reference voltage, the bias module adjusts the first node voltage according to the first feedback signal to make the first node voltage equal to the preset reference voltage; and the connection module adjusts the voltage of the signal port according to the first feedback signal and the second feedback signal to make the voltage of the signal port equal to the preset reference voltage.

[0007] Secondly, embodiments of this application provide an impedance matching method, the method comprising: acquiring a first node voltage; when the node voltage is not equal to a preset reference voltage, adjusting the first node voltage according to a first feedback signal so that the first node voltage is equal to the preset reference voltage; and adjusting the voltage of a signal port according to a first feedback signal and a second feedback signal so that the voltage of the signal port is equal to the preset reference voltage.

[0008] Thirdly, embodiments of this application provide an integrated circuit that includes the impedance matching circuit described above.

[0009] Fourthly, embodiments of this application provide an electronic device that includes the impedance matching circuit or the integrated circuit described above.

[0010] The technical solution provided by this invention includes an impedance matching circuit comprising: a reference module, a bias module, and a connection module. The bias module generates a first feedback signal based on the first node voltage of a first intermediate node and transmits the first feedback signal to a second terminal of the bias module. The bias module also generates a second feedback signal and transmits the second feedback signal to a third terminal of the bias module. The connection module adjusts the voltage of a signal port based on the first and second feedback signals to make the voltage of the signal port equal to a preset reference voltage. When the node voltage is not equal to the preset reference voltage, this impedance matching circuit adjusts the first node voltage in real time based on the first feedback signal to make the first node voltage equal to the preset reference voltage. Then, it adjusts the voltage of the signal port based on the first and second feedback signals to make the voltage of the signal port equal to the preset reference voltage. This eliminates the need for clock resources, does not affect the normal operation of other modules, reduces application development difficulty, and achieves high-precision impedance matching, thereby accurately matching various transmission line characteristic impedances and ensuring signal quality. Attached Figure Description

[0011] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 A schematic diagram of an impedance matching circuit provided in an embodiment of the present invention is shown.

[0013] Figure 2 A schematic diagram of a reference module provided in an embodiment of the present invention is shown.

[0014] Figure 3A schematic diagram of a bias module provided in an embodiment of the present invention is shown.

[0015] Figure 4 A schematic diagram of a bias unit provided in an embodiment of the present invention is shown.

[0016] Figure 5 A schematic diagram of the structure of a first bias subunit provided in an embodiment of the present invention is shown.

[0017] Figure 6 A schematic diagram of the structure of a second bias subunit provided in an embodiment of the present invention is shown.

[0018] Figure 7 A schematic diagram of a pull-up component provided in an embodiment of the present invention is shown.

[0019] Figure 8 A schematic diagram of a pull-down component provided in an embodiment of the present invention is shown.

[0020] Figure 9 A schematic diagram of a comparison unit provided in an embodiment of the present invention is shown.

[0021] Figure 10 A schematic diagram of a connection module provided in an embodiment of the present invention is shown.

[0022] Figure 11 A schematic diagram of the structure of a first connection unit provided in an embodiment of the present invention is shown.

[0023] Figure 12 A schematic diagram of the structure of a second connecting unit provided in an embodiment of the present invention is shown.

[0024] Figure 13 A schematic flowchart of another impedance matching circuit provided by an embodiment of the present invention is shown.

[0025] Figure 14 A schematic diagram of an integrated circuit provided by an embodiment of the present invention is shown.

[0026] Figure 15 A schematic diagram of the structure of an electronic device provided by an embodiment of the present invention is shown.

[0027] Figure 16 A schematic diagram of another electronic device provided by an embodiment of the present invention is shown.

[0028] Figure Descriptions: 100, Impedance matching circuit; 110, Reference module, 110a, First terminal of the reference module, 110b, Second terminal of the reference module; 120, Bias module, 120a, First terminal of the bias module, 120b, Second terminal of the bias module, 120c, Third terminal of the bias module; 121, Bias unit, 121a, First terminal of the bias unit, 121b, Second terminal of the bias unit, 121c, Third terminal of the bias unit, 121d, Fourth terminal of the bias unit, 121e, Fifth terminal of the bias unit; 1211, First bias subunit, 1211a, First terminal of the first bias subunit, 1211b, Second terminal of the first bias subunit, 1211c, Third terminal of the first bias subunit. ; 12111, First switch transistor, 12111a, First terminal of the first switch transistor, 12111b, Second terminal of the first switch transistor, 12111c, Third terminal of the first switch transistor; 12112, Second switch transistor, 12112a, First terminal of the second switch transistor, 12112b, Second terminal of the second switch transistor, 12112c, Third terminal of the second switch transistor; 1212, Second bias subunit, 1212a, First terminal of the second bias subunit, 1212b, Second terminal of the second bias subunit, 1212c, Third terminal of the second bias subunit; 12121, Pull-up assembly, 12121a, First terminal of the pull-up assembly, 12121b, Second terminal of the pull-up assembly, 12121c, Third terminal of the pull-up assembly Three terminals; 121211, third switch transistor, 121211a, first terminal of the third switch transistor, 121211b, second terminal of the third switch transistor, 121211c, third terminal of the third switch transistor; 121212, fourth switch transistor, 121212a, first terminal of the fourth switch transistor, 121212b, second terminal of the fourth switch transistor, 121212c, third terminal of the fourth switch transistor; 12122, pull-down assembly, 12122a, first terminal of the pull-down assembly, 12122b, second terminal of the pull-down assembly, 12122c, third terminal of the pull-down assembly; 121221, fifth switch transistor, 121221a, first terminal of the fifth switch transistor, 121221b, second terminal of the fifth switch transistor, 1212... 21c, the third terminal of the fifth switch transistor; 121222, the sixth switch transistor, 121222a, the first terminal of the sixth switch transistor, 121222b, the second terminal of the sixth switch transistor, 121222c, the third terminal of the sixth switch transistor; 122, a comparator unit, 122a, the first terminal of the comparator unit, 122b, the second terminal of the comparator unit, 122c, the third terminal of the comparator unit; 1221, the first comparator, 1221a, the first terminal of the first comparator, 1221b, the second terminal of the first comparator, 1221c, the third terminal of the first comparator; 1222, the second comparator, 1222a, the first terminal of the second comparator, 1222b, the second terminal of the second comparator, 1222c, the third terminal of the second comparator;130. Connection module; 130a. First end of connection module; 130b. Second end of connection module; 130c. Third end of connection module; 131. First connection unit; 131a. First end of first connection unit; 131b. Second end of first connection unit; 131c. Third end of first connection unit; 1311. Seventh switch transistor; 1311a. First end of seventh switch transistor; 1311b. Second end of seventh switch transistor; 1311c. Third end of seventh switch transistor; 1312. Eighth switch transistor; 1312a. First end of eighth switch transistor; 1312b. Second end of eighth switch transistor; 1312c. Third end of eighth switch transistor; 132. Second connection unit; 132a. The first end of the second connection unit, 132b; the second end of the second connection unit, 132c; the third end of the second connection unit; 1321; the ninth switch, 1321a; the first end of the ninth switch, 1321b; the second end of the ninth switch, 1321c; the third end of the ninth switch; 1322; the tenth switch, 1322a; the first end of the tenth switch, 1322b; the second end of the tenth switch, 1322c; the third end of the tenth switch; A; the first intermediate node; B; the second intermediate node; C; the third intermediate node; D; the fourth intermediate node; VS; the power supply voltage; V1; the first reference voltage; V2; the second reference voltage; VA; the first control voltage; VB; the second control voltage. Detailed Implementation

[0029] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings.

[0030] With the rapid development of technology, integrated circuits have been widely used in various electronic devices, such as mobile phones, tablets, and laptops. The demand for high-speed, high-performance integrated circuits is urgent. In modern integrated circuits, the system clock speed is a crucial indicator of system operating speed, and therefore, the clock speed has become increasingly faster with each generation of integrated circuits. As system clock speeds increase, the characteristic impedance of transmission lines must be considered. If there is impedance mismatch in the integrated circuit, signal reflection and crosstalk will occur, which will adversely affect signal integrity. Therefore, impedance matching is a problem that must be considered when developing high-performance integrated circuits. Impedance matching can usually be achieved by placing impedance matching circuits within the integrated circuit.

[0031] However, the inventors discovered during their research that the commonly used traditional impedance matching circuits are not very suitable for high-speed, high-performance integrated circuits. Specifically, firstly, the adjustment accuracy of the switching transistor array and resistor array in traditional impedance matching circuits is limited, generally only achieving 10% accuracy, which inherently has a negative impact on signal quality; secondly, the layout area of ​​high-speed, high-performance integrated circuits is very precious, while the layout area of ​​the switching transistor array and resistor array in traditional impedance matching circuits is very large, which increases chip costs; finally, the introduction of a state machine mechanism in traditional impedance matching circuits consumes valuable system clock resources, thus affecting the performance release of the integrated circuit, and in order to enter the impedance calibration program, the normal operating state must be stopped, which also increases the difficulty of application development.

[0032] To address the aforementioned issues, the inventors have proposed an impedance matching circuit and method as described in this application. The impedance matching circuit includes a reference module, a bias module, and a connection module. The bias module generates a first feedback signal based on the first node voltage of a first intermediate node and transmits the first feedback signal to a second terminal of the bias module. The bias module also generates a second feedback signal and transmits the second feedback signal to a third terminal of the bias module. The connection module adjusts the voltage of a signal port based on the first and second feedback signals to make the voltage of the signal port equal to a preset reference voltage. During operation, this impedance matching circuit acquires the first node voltage in real time. When the node voltage is not equal to the preset reference voltage, it adjusts the first node voltage based on the first feedback signal to make it equal to the preset reference voltage. Then, it adjusts the voltage of the signal port based on the first and second feedback signals to make the voltage of the signal port equal to the preset reference voltage. This eliminates the need for clock resources, does not affect the normal operation of other modules, reduces application development difficulty, and achieves high-precision impedance matching, thereby accurately matching various transmission line characteristic impedances and ensuring signal quality.

[0033] The impedance matching circuit provided in this application will be described in detail below through specific embodiments.

[0034] Please see Figure 1 This application provides an impedance matching circuit 100, which includes a reference module 110, a bias module 120 and a connection module 130.

[0035] In the embodiments of this application, the first end 110a of the reference module 110 is connected to the first intermediate node A, and the second end 110b of the reference module 110 is grounded.

[0036] Optionally, the reference module 110 may be a resistor, wherein the impedance value of the resistor in the reference module 110 can be set according to the characteristic impedance value of the transmission line in order to match the impedance of the signal port E with that of the transmission line. Specifically, the impedance value of the resistor in the reference module 110 is equal to the characteristic impedance value of the transmission line.

[0037] Optionally, the reference module 110 may be a fixed resistor, and a fixed resistor with an appropriate impedance value may be selected according to the different characteristic impedance values ​​of the corresponding transmission line.

[0038] Optionally, the reference module 110 may be an adjustable resistor, whose impedance value can be adjusted according to the characteristic impedance value of the corresponding transmission line.

[0039] In the embodiments of this application, the first terminal 120a of the bias module 120 is connected to the first intermediate node A. The bias module 120 is used to generate a first feedback signal according to the first node voltage of the first intermediate node A and transmit the first feedback signal to the second terminal 120b of the bias module 120. The bias module 120 is also used to generate a second feedback signal and transmit the second feedback signal to the third terminal 120c of the bias module 120.

[0040] In some implementations, such as Figure 2 As shown, the bias module 120 includes a bias unit 121 and a comparison unit 122.

[0041] Specifically, the first terminal 121a of the bias unit 121 is connected to the power supply voltage VS, the second terminal 121b of the bias unit 121 is connected to the first intermediate node A, the third terminal 121c of the bias unit 121 is connected to the second intermediate node B, the fourth terminal 121d of the bias unit 121 is connected to the third intermediate node C, and the fifth terminal 121e of the bias unit 121 is connected to the fourth intermediate node D.

[0042] In some implementations, such as Figure 3 As shown, the bias unit 121 includes a first bias subunit 1211 and a second bias subunit 1212.

[0043] The first bias subunit 1211 has its first terminal 1211a connected to the power supply voltage VS, its second terminal 1211b connected to the first intermediate node A, and its third terminal 1211c connected to the second intermediate node B. The first bias subunit 1211 is used to adjust the voltage of the first node according to the first feedback signal.

[0044] In some implementations, such as Figure 4 As shown, the first bias subunit 1211 includes a first switching transistor 12111.

[0045] The first terminal 12111a of the first switch transistor 12111 is connected to the second intermediate node B, the second terminal 12111b of the first switch transistor 12111 is connected to the power supply voltage VS, and the third terminal 12111c of the first switch transistor 12111 is connected to the first intermediate node A.

[0046] Optionally, the first switching transistor 12111 can be a PMOS transistor, such as an enhancement-mode PMOS transistor.

[0047] In some implementations, such as Figure 4 As shown, the first bias subunit 1211 also includes a second switch transistor 12112.

[0048] The second switch 12112 is connected between the power supply voltage VS and the second terminal 12111b of the first switch 12111; the first terminal 12112a of the second switch 12112 is connected to the first control voltage VA, the second terminal 12112b of the second switch 12112 is connected to the power supply voltage VS, and the third terminal 12112c of the second switch 12112 is connected to the second terminal 12111b of the first switch 12111.

[0049] Optionally, the second switch 12112 can be an NMOS transistor, such as an enhancement-mode PMOS transistor.

[0050] In some implementations, such as Figure 5 As shown, the second bias subunit 1212 includes a pull-up component 12121 and a pull-down component 12122.

[0051] Wherein, the first end 12121a of the pull-up component 12121 is connected to the power supply voltage VS, the second end 12121b of the pull-up component 12121 is connected to the third intermediate node C, and the third end 12121c of the pull-up component 12121 is connected to the second intermediate node B; the pull-up component 12121 is used to adjust the voltage of the second node according to the first feedback signal.

[0052] In some implementations, such as Figure 6 As shown, the pull-up assembly 12121 includes a third switch transistor 121211.

[0053] Among them, the first terminal 121211a of the third switch 121211 is connected to the second intermediate node B, the second terminal 121211b of the third switch 121211 is connected to the power supply voltage VS, and the third terminal 121211c of the third switch 121211 is connected to the third intermediate node C.

[0054] Optionally, the third switch 121211 can be a PMOS transistor, such as an enhancement-mode PMOS transistor.

[0055] In some implementations, such as Figure 6 As shown, the pull-up assembly 12121 also includes a fourth switch transistor 121212.

[0056] The fourth switch 121212 is connected between the power supply voltage VS and the second terminal 1211b of the third switch 121211. The first terminal 121212a of the fourth switch 121212 is connected to the first control voltage VA. The second terminal 121212b of the fourth switch 121212 is connected to the power supply voltage VS. The third terminal 121212c of the fourth switch 121212 is connected to the second terminal 121211b of the third switch 121211.

[0057] Optionally, the fourth switch 121212 can be a PMOS transistor, such as an enhancement-mode PMOS transistor.

[0058] In the embodiments of this application, the third switch 121211 and the fourth switch 121212 are respectively replication units of the first switch 12111 and the second switch 12112.

[0059] Wherein, the first end 12122a of the pull-down component 12122 is connected to the third intermediate node C, the second end 12122b of the pull-down component 12122 is grounded, and the third end 12122c of the pull-down component 12122 is connected to the fourth intermediate node D; the pull-down component 12122 is used to adjust the voltage of the second node according to the second feedback signal.

[0060] In some implementations, such as Figure 7 As shown, the pull-down component 12122 includes a fifth switch transistor 121221.

[0061] Among them, the first terminal 121221a of the fifth switch transistor 121221 is connected to the fourth intermediate node D, the second terminal 121221b of the fifth switch transistor 121221 is grounded, and the third terminal 121221c of the fifth switch transistor 121221 is connected to the third intermediate node C.

[0062] Optionally, the fifth switch 121221 can be an NMOS transistor, such as an enhancement-mode NMOS transistor.

[0063] In some implementations, such as Figure 7 As shown, the pull-down assembly 12122 also includes a sixth switch transistor 121222.

[0064] The sixth switch 121222 is connected between ground and the second terminal 121221b of the fifth switch 121221. The first terminal 121222a of the sixth switch 121222 is connected to the second control voltage VB. The second terminal 121222b of the sixth switch 121222 is grounded. The third terminal 121222c of the sixth switch 121222 is connected to the second terminal 121221b of the fifth switch 121221.

[0065] Optionally, the sixth switch 121222 can be an NMOS transistor, such as an enhancement-mode NMOS transistor.

[0066] The comparison unit 122 has a first terminal 122a connected to a first reference voltage V1, a second terminal 122b connected to a first intermediate node A, a third terminal 122c connected to a second intermediate node B, a fourth terminal 122d connected to a third intermediate node C, and a fifth terminal 122e connected to a fourth intermediate node D. The comparison unit 122 is used to generate a first feedback signal based on the first node voltage and the first reference voltage V1. The comparison unit 122 is also used to generate a second feedback signal based on the second node voltage of the third intermediate node C and the second reference voltage V2, and transmit the second feedback signal to the fourth intermediate node D.

[0067] In some implementations, such as Figure 8 As shown, the comparison unit 122 includes a first comparator 1221 and a second comparator 1222.

[0068] The first terminal 1221a of the first comparator 1221 is connected to the first intermediate node A, the second terminal 1221b of the first comparator 1221 is connected to the first reference voltage V1, and the third terminal 1221c of the first comparator 1221 is connected to the second intermediate node B. The first comparator 1221 is used to generate a first feedback signal based on the first node voltage and the first reference voltage V1, and transmit the first feedback signal to the second intermediate node B.

[0069] In the embodiments of this application, the first feedback signal is a signal transmitted through the third terminal 1221c of the first comparator 1221, which compares the voltage values ​​of the first node voltage and the first reference voltage V1. Depending on the voltage value of the first node voltage, the first feedback signal can be selectively low or high. For example, when the voltage value of the first node voltage is higher than the voltage value of the first reference voltage V1, the first feedback signal is high; conversely, when the voltage value of the first node voltage is not higher than the voltage value of the first reference voltage V1, the first feedback signal is low.

[0070] In some implementations, the voltage value of the first reference voltage V1 is half the voltage value of the power supply voltage VS.

[0071] In other words, when the impedance matching circuit 100 loop is stable, the equivalent impedance value of the first bias sub-unit 1211, which is composed of the first switch transistor 12111 and the second switch transistor 12112, is equal to the impedance value of the reference resistor and consistent with the characteristic impedance of the transmission line, and the level value of the first node voltage is equal to the level value of the first reference voltage V1.

[0072] Wherein, the first terminal 1222a of the second comparator 1222 is connected to the third intermediate node C, the second terminal 1222b of the second comparator 1222 is connected to the second reference voltage V2, and the third terminal 1222c of the second comparator 1222 is connected to the fourth intermediate node D; the second comparator 1222 is used to generate a second feedback signal based on the second node voltage and the second reference voltage V2, and transmit the second feedback signal to the fourth intermediate node D.

[0073] In the embodiments of this application, the second feedback signal is a signal transmitted through the third terminal 1221c of the first comparator 1221, which compares the voltage values ​​of the second node voltage and the second reference voltage V2 via the second comparator 1222. Depending on the voltage value of the second node voltage, the second feedback signal can be selectively low or high. For example, when the voltage value of the second node voltage is higher than the voltage value of the second reference voltage V2, the second feedback signal is high; conversely, when the voltage value of the second node voltage is not higher than the voltage value of the second reference voltage V2, the second feedback signal is low.

[0074] In some implementations, the voltage value of the second reference voltage V2 is half the voltage value of the power supply voltage.

[0075] When the impedance matching circuit 100 loop is stable, the equivalent impedance value of the pull-down component 12122 composed of the fifth switch transistor 121221 and the sixth switch transistor 121222 is equal to the equivalent impedance value of the pull-up component 12121 composed of the third switch transistor 121211 and the fourth switch transistor 121212. That is to say, the equivalent impedance value of the pull-down component 12122 composed of the fifth switch transistor 121221 and the sixth switch transistor 121222 is equal to the impedance value of the reference resistor and is consistent with the characteristic impedance of the transmission line. The level value of the second node voltage is equal to the level value of the second reference voltage V2.

[0076] In an embodiment of the present invention, the first end 130a of the connection module 130 is connected to the second end 120b of the bias module 120, the second end 130b of the connection module 130 is connected to the third end 120c of the bias module 120, and the third end 130c of the connection module 130 is connected to the signal port E.

[0077] The second intermediate node B is connected to the first end 130a of the connection module 130, and the fourth intermediate node D is connected to the second end 130b of the connection module 130.

[0078] In some implementations, such as Figure 9 As shown, the connection module 130 includes a first connection unit 131 and a second connection unit 132.

[0079] Wherein, the first end 131a of the first connection unit 131 is connected to the power supply voltage VS, the second end 131b of the first connection unit 131 is connected to the signal port E, and the third end 131c of the first connection unit 131 is connected to the second intermediate node B; the first connection unit 131 is used to adjust the level value of the signal port E according to the first feedback signal.

[0080] In some implementations, such as Figure 10 As shown, the first connection unit 131 includes a seventh switch transistor 1311.

[0081] Among them, the first terminal 1311a of the seventh switch 1311 is connected to the second intermediate node B, the second terminal 1311b of the seventh switch 1311 is connected to the power supply voltage VS, and the third terminal 1311c of the seventh switch 1311 is connected to the signal port E.

[0082] Alternatively, the seventh switch 1311 may be a PMOS transistor, such as an enhancement-mode PMOS transistor.

[0083] In some implementations, such as Figure 10 As shown, the first connection unit 131 also includes an eighth switch 1312.

[0084] The eighth switch 1312 is connected between the power supply voltage VS and the second terminal 1311b of the seventh switch 1311. The first terminal 1312a of the eighth switch 1312 is connected to the first control voltage VA. The second terminal 1312b of the eighth switch 1312 is connected to the power supply voltage VS. The third terminal 1312c of the eighth switch 1312 is connected to the second terminal 1311b of the seventh switch 1311.

[0085] Alternatively, the eighth switch 1312 may be a PMOS transistor, such as an enhancement-mode PMOS transistor.

[0086] In the embodiments of this application, the seventh switch 1311 and the eighth switch 1312 are replica units of the first switch 12111 and the second switch 12112, respectively. That is, the equivalent impedance value of the first connection unit 131 composed of the seventh switch 1311 and the eighth switch 1312 when the circuit is stable is equal to the impedance value of the reference resistor and consistent with the characteristic impedance of the transmission line.

[0087] The first end 132a of the second connection unit 132 is connected to the signal port E, the second end 132b of the second connection unit 132 is grounded, and the third end 132c of the second connection unit 132 is connected to the fourth intermediate node D; the second connection unit 132 is used to adjust the voltage of the signal port E according to the second feedback signal.

[0088] In some implementations, such as Figure 11 As shown, the second connection unit 132 includes a ninth switch transistor 1321.

[0089] Among them, the first end 1321a of the ninth switch 1321 is connected to the fourth intermediate node D, the second end 1321b of the ninth switch 1321 is grounded, and the third end 1321c of the ninth switch 1321 is connected to the signal port E.

[0090] Alternatively, the ninth switch 1321 may be an NMOS transistor, such as an enhancement-mode NMOS transistor.

[0091] In some implementations, such as Figure 11 As shown, the second connection unit 132 also includes a tenth switch transistor 1322.

[0092] The tenth switch transistor 1322 is connected between ground and the second terminal 1321a of the ninth switch transistor 1321. The first terminal 1322a of the tenth switch transistor 1322 is connected to the second control voltage VB, the second terminal 1322b of the tenth switch transistor 1322 is grounded, and the third terminal 1322c of the tenth switch transistor 1322 is connected to the second terminal 1321b of the ninth switch transistor 1321.

[0093] Optionally, the tenth switch 1322 can be an NMOS transistor, such as an enhancement-mode NMOS transistor.

[0094] In the embodiments of this application, the ninth switch 1321 and the tenth switch 1322 are replica units of the fifth switch 121221 and the sixth switch 121222, respectively. That is, the second connection unit 132 composed of the ninth switch 1321 and the tenth switch 1322 has the same equivalent impedance value as the reference resistor when the circuit is stable, and the impedance value is consistent with the characteristic impedance of the transmission line.

[0095] When the circuit is stable, the equivalent impedance values ​​of the first connection unit 131 and the second connection unit 132 are equal and both are consistent with the characteristic impedance of the transmission line. Therefore, the impedance of the signal port E is matched with the characteristic impedance of the transmission line, and the voltage value of the signal port e is half of the power supply voltage VS.

[0096] like Figure 12As shown in the figure, this application provides a schematic diagram of another impedance matching circuit 100. In this embodiment, the impedance matching circuit includes: a reference module 110, a bias module 120, and a connection module 130.

[0097] In the embodiments of this application, the reference module 110 is a fixed resistor; wherein the impedance value of the resistor of the reference module is equal to the characteristic impedance of the transmission line.

[0098] In the embodiments of this application, the bias module 120 includes a bias unit and a comparison unit.

[0099] The bias unit includes a first bias subunit 1211 and a second bias subunit 1212.

[0100] In the embodiments of this application, the first bias sub-unit 1211 includes a first switch 12111 and a second switch 12112. The first switch 12111 is an enhancement-mode PMOS transistor, and the second switch 12112 is an enhancement-mode PMOS transistor.

[0101] The second bias subunit 1212 includes a pull-up component 12121 and a pull-down component 12122.

[0102] In the embodiments of this application, the pull-up component 12121 includes a third switch 121211 and a fourth switch 121212. The third switch 121211 and the fourth switch 121212 are respectively replication units of the first switch 12111 and the second switch 12112; the third switch 121211 is an enhancement-mode PMOS transistor, and the fourth switch 121212 is an enhancement-mode PMOS transistor.

[0103] In the embodiments of this application, the pull-down component 12122 includes a fifth switch 121221 and a sixth switch 121222. The fifth switch 121221 is an enhancement-mode NMOS transistor, and the sixth switch 121222 is an enhancement-mode NMOS transistor.

[0104] The comparison unit 122 includes a first comparator 1221 and a second comparator 1222.

[0105] In the embodiments of this application, the connection module 130 includes a first connection unit 131 and a second connection unit 132.

[0106] In the embodiments of this application, the first connection unit 131 includes a seventh switch 1311 and an eighth switch 1312. The seventh switch 1311 and the eighth switch 1312 are respectively replication units of the first switch 12111 and the second switch 12112; the seventh switch 1311 is an enhancement-mode PMOS transistor, and the eighth switch 1312 is an enhancement-mode PMOS transistor.

[0107] In the embodiments of this application, the second connection unit 132 includes a ninth switch 1321 and a tenth switch 1322. The ninth switch 1321 and the tenth switch 1322 are replication units of the fifth switch 121221 and the sixth switch 121222, respectively; the ninth switch 1321 is an enhancement-mode NMOS transistor, and the tenth switch 1322 is an enhancement-mode NMOS transistor.

[0108] In the embodiments of this application, the reference voltage values ​​of the first reference voltage V1 and the second reference voltage V2 are equal and are both half of the power supply voltage VS; when the circuit is stable, the equivalent impedance values ​​of the first connection unit 131 and the second connection unit 132 of the connection module 130 are equal and are both equal to the impedance value of the reference resistor 111, and the level value of the signal port E is half of the power supply voltage VS.

[0109] The operation of the impedance matching circuit 110 in the embodiments of this application will be described in detail below.

[0110] When the voltage level of the first intermediate node A is higher than the first reference voltage V1, the first comparator 1221 transmits a high-level first feedback signal to the second intermediate node B. The first switch 12111, the third switch 121211, and the seventh switch 1311 are turned off. The equivalent impedance of the first bias subunit 1211 will rise until it is equal to the impedance of the reference module 110. At this time, the voltage level of the first intermediate node A is equal to the voltage level of the first reference voltage V1. The equivalent impedance of the pull-up component 12121 of the second bias subunit 1212 and the first connection unit 131 will also rise.

[0111] If the voltage level of the third intermediate node C is greater than the second reference voltage V2, the second comparator 1222 transmits a high-level second feedback signal to the fourth intermediate node D. The fifth switch 121221 and the ninth switch 1321 are turned on. The equivalent impedance values ​​of the pull-down component 12122 of the second bias subunit 1212 and the second connection unit 132 both decrease until they are equal to the equivalent impedance values ​​of the pull-up component 12121 of the second bias subunit 1212 and the first bias subunit 1211, respectively, and both are the impedance values ​​of the reference module 110. At this time, the voltage level of the third intermediate node C is equal to the voltage level of the second reference voltage V2, and the voltage level of the signal port E is half the voltage level of the power supply voltage VS.

[0112] If the voltage level of the third intermediate node C is less than the second reference voltage V2, the second comparator 1222 transmits a low-level second feedback signal to the fourth intermediate node D. The fifth switch 121221 and the ninth switch 1321 are turned off. The equivalent impedance values ​​of the pull-down component 12122 of the second bias subunit 1212 and the second connection unit 132 both rise until they are equal to the equivalent impedance values ​​of the pull-up component 12121 of the second bias subunit 1212 and the first bias subunit 1211, respectively, and both are the impedance values ​​of the reference module 110. At this time, the voltage level of the third intermediate node C is equal to the voltage level of the second reference voltage V2, and the voltage level of the signal port E is half the voltage level of the power supply voltage VS.

[0113] When the voltage level of the first intermediate node A is lower than the first reference voltage V1, the first comparator 1221 transmits a low-level first feedback signal to the first intermediate node A. The first switch 12111, the third switch 121211, and the seventh switch 1311 are turned on, and the equivalent impedance of the first bias subunit 1211 decreases until it is equal to the impedance of the reference module 110. At this time, the voltage level of the first intermediate node A is equal to the voltage level of the first reference voltage V1. The equivalent impedance of the pull-up component 12121 of the second bias subunit 1212 and the first connection unit 131 also decrease.

[0114] If the voltage level of the third intermediate node C is greater than the second reference voltage V2, the second comparator 1222 transmits a high-level second feedback signal to the fourth intermediate node D. The fifth switch 121221 and the ninth switch 1321 are turned on. The equivalent impedance values ​​of the pull-down component 12122 of the second bias subunit 1212 and the second connection unit 132 both decrease until they are equal to the equivalent impedance values ​​of the pull-up component 12121 of the second bias subunit 1212 and the first bias subunit 1211, respectively, and both are the impedance values ​​of the reference module 110. At this time, the voltage level of the third intermediate node C is equal to the voltage level of the second reference voltage V2, and the voltage level of the signal port E is half the voltage level of the power supply voltage VS.

[0115] If the voltage level of the third intermediate node C is less than the second reference voltage V2, the second comparator 1222 transmits a low-level second feedback signal to the fourth intermediate node D. The fifth switch 121221 and the ninth switch 1321 are turned off. The equivalent impedance values ​​of the pull-down component 12122 of the second bias subunit 1212 and the second connection unit 132 both rise until they are equal to the equivalent impedance values ​​of the pull-up component 12121 of the second bias subunit 1212 and the first bias subunit 1211, respectively, and both are the impedance values ​​of the reference module 110. At this time, the voltage level of the third intermediate node C is equal to the voltage level of the second reference voltage V2, and the voltage level of the signal port E is half the voltage level of the power supply voltage VS.

[0116] like Figure 13 As shown in the embodiment of this application, an impedance matching method 200 is also provided, the method steps of which include:

[0117] Step 210: Obtain the voltage of the first node.

[0118] Step 220: When the node voltage is not equal to the preset reference voltage, adjust the first node voltage according to the first feedback signal so that the first node voltage is equal to the preset reference voltage.

[0119] Step 230: Adjust the voltage of the signal port according to the first feedback signal and the second feedback signal so that the voltage of the signal port is equal to the preset reference voltage.

[0120] The impedance matching method of this application can be applied to the impedance matching circuit in the above embodiments. For details, please refer to the description of the above embodiments, which will not be repeated here.

[0121] like Figure 14 As shown, this application embodiment also provides an integrated circuit 300, wherein the integrated circuit 300 includes the impedance matching circuit 100 described above.

[0122] like Figure 15 As shown, this application embodiment also provides an electronic device 400, wherein the electronic device 400 includes a housing 410 and the level conversion circuit 100 described above. Alternatively, as... Figure 16 As shown, the electronic device 400 includes a housing 410 and the aforementioned integrated circuit 300.

[0123] Optionally, the electronic device 400 can be a mobile phone, laptop, tablet, or other electronic device.

[0124] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. An impedance matching circuit, characterized by, The application relates to a reference module, a bias module, a connection module and a signal port. The first end of the reference module is connected to a first intermediate node, and the second end of the reference module is grounded. The first end of the bias module is connected to the first intermediate node. The bias module is used for generating a first feedback signal according to a first node voltage of the first intermediate node and transmitting the first feedback signal to the second end of the bias module. The bias module is also used for generating a second feedback signal and transmitting the second feedback signal to the third end of the bias module. The first end of the connection module is connected to the second end of the bias module. The second end of the connection module is connected to the third end of the bias module. The third end of the connection module is connected to the signal port. When the first node voltage is not equal to a preset reference voltage, the bias module adjusts the first node voltage according to the first feedback signal, so that the first node voltage is equal to the preset reference voltage. The bias module comprises a bias unit and a comparison unit. The first end of the bias unit is connected to a power supply voltage. The second end of the bias unit is connected to the first intermediate node. The third end of the bias unit is connected to a second intermediate node. The fourth end of the bias unit is connected to a third intermediate node. The fifth end of the bias unit is connected to a fourth intermediate node. The first end of the comparison unit is connected to a first reference voltage. The second end of the comparison unit is connected to the first intermediate node. The third end of the comparison unit is connected to the second intermediate node. The fourth end of the comparison unit is connected to the third intermediate node. The fifth end of the comparison unit is connected to the fourth intermediate node. The comparison unit is used for generating a first feedback signal according to the first node voltage and the first reference voltage. The comparison unit is also used for generating a second feedback signal according to a second node voltage of the third intermediate node and a second reference voltage and transmitting the second feedback signal to the fourth intermediate node. The second intermediate node is connected to the first end of the connection module. The fourth intermediate node is connected to the second end of the connection module. The reference voltage value of the first reference voltage is half of the power supply voltage. The reference voltage value of the second reference voltage is half of the power supply voltage. The comparison unit comprises a first comparator and a second comparator. The first end of the first comparator is connected to the first intermediate node. The second end of the first comparator is connected to the first reference voltage. The third end of the first comparator is connected to the second intermediate node. The first comparator is used for generating the first feedback signal according to the first node voltage and the first reference voltage and transmitting the first feedback signal to the second intermediate node. The first end of the second comparator is connected to the third intermediate node. The second end of the second comparator is connected to the second reference voltage. The third end of the second comparator is connected to the fourth intermediate node. The second comparator is used for generating the second feedback signal according to the second node voltage and the second reference voltage and transmitting the second feedback signal to the fourth intermediate node. A first end of the second comparator is connected to the third intermediate node, a second end of the second comparator is connected to the second reference voltage, and a third end of the second comparator is connected to the fourth intermediate node; the second comparator is configured to generate the second feedback signal according to the second node voltage and the second reference voltage, and transmit the second feedback signal to the fourth intermediate node.

2. The impedance matching circuit of claim 1, wherein, The biasing unit comprises a first biasing subunit and a second biasing subunit. A first end of the first biasing subunit is connected to the power supply voltage, a second end of the first biasing subunit is connected to the first intermediate node, and a third end of the first biasing subunit is connected to the second intermediate node; the first biasing subunit is configured to adjust the first node voltage according to the first feedback signal. A first end of the second biasing subunit is connected to the power supply voltage, a second end of the second biasing subunit is connected to the third intermediate node, a third end of the second biasing subunit is grounded, a fourth end of the second biasing subunit is connected to the fourth intermediate node, and a fifth end of the second biasing subunit is connected to the second intermediate node; the second biasing subunit is configured to adjust the second node voltage according to the first feedback signal and the second feedback signal. The first biasing subunit comprises a first switch tube, a first end of the first switch tube is connected to the second intermediate node, a second end of the first switch tube is connected to the power supply voltage, and a third end of the first switch tube is connected to the first intermediate node.

3. The impedance matching circuit of claim 2, wherein, The first biasing subunit further comprises a second switch tube, the second switch tube is connected between the power supply voltage and the second end of the first switch tube; a first end of the second switch tube is connected to a first control voltage, a second end of the second switch tube is connected to the power supply voltage, and a third end of the second switch tube is connected to the second end of the first switch tube.

4. The impedance matching circuit of claim 3, wherein, The second biasing subunit comprises a pull-up component and a pull-down component.

5. The impedance matching circuit of claim 2, wherein, A first end of the pull-up component is connected to the power supply voltage, a second end of the pull-up component is connected to the third intermediate node, and a third end of the pull-up component is connected to the second intermediate node; the pull-up component is configured to adjust the second node voltage according to the first feedback signal. A first end of the pull-down component is connected to the third intermediate node, a second end of the pull-down component is grounded, and a third end of the pull-down component is connected to the fourth intermediate node; the pull-down component is configured to adjust the second node voltage according to the second feedback signal. The pull-up component comprises a third switch tube, a first end of the third switch tube is connected to the second intermediate node, a second end of the third switch tube is connected to the power supply voltage, and a third end of the third switch tube is connected to the third intermediate node.

6. The impedance matching circuit of claim 5, wherein, ​ 7. The impedance matching circuit of claim 6, wherein, The pull-up component further comprises a fourth switch tube, a first end of the fourth switch tube is connected to a first control voltage, a second end of the fourth switch tube is connected to the power supply voltage, and a third end of the fourth switch tube is connected to the second end of the third switch tube.

8. The impedance matching circuit of claim 5, wherein, The pull-down component comprises a fifth switch tube, a first end of the fifth switch tube is connected to the fourth intermediate node, a second end of the fifth switch tube is grounded, and a third end of the fifth switch tube is connected to the third intermediate node.

9. The impedance matching circuit of claim 8, wherein, The pull-down component further comprises a sixth switch tube, the sixth switch tube is connected between the ground and the second end of the fifth switch tube, a first end of the sixth switch tube is connected to a second control voltage, a second end of the sixth switch tube is grounded, and a third end of the sixth switch tube is connected to the second end of the fifth switch tube.

10. The impedance matching circuit according to claim 1, wherein the connection module comprises a first connection unit and a second connection unit; a first end of the first connection unit is connected to the power supply voltage, a second end of the first connection unit is connected to a signal port, and a third end of the first connection unit is connected to a second intermediate node; the first connection unit is configured to adjust a level value of the signal port according to the first feedback signal; a first end of the second connection unit is connected to the signal port, a second end of the second connection unit is grounded, and a third end of the second connection unit is connected to a fourth intermediate node; the second connection unit is configured to adjust a voltage of the signal port according to the second feedback signal.

11. The impedance matching circuit of claim 10, wherein, The first connection unit comprises a seventh switch tube, a first end of the seventh switch tube is connected to the second intermediate node, a second end of the seventh switch tube is connected to the power supply voltage, and a third end of the seventh switch tube is connected to the signal port.

12. The impedance matching circuit of claim 11, wherein, The first connection unit further comprises an eighth switch tube, the eighth switch tube is connected between the power supply voltage and the second end of the seventh switch tube, a first end of the eighth switch tube is connected to the first control voltage, a second end of the eighth switch tube is connected to the power supply voltage, and a third end of the eighth switch tube is connected to the second end of the seventh switch tube.

13. The impedance matching circuit of claim 10, wherein, The second connection unit comprises a ninth switch tube, a first end of the ninth switch tube is connected to the fourth intermediate node, a second end of the ninth switch tube is grounded, and a third end of the ninth switch tube is connected to the signal port.

14. The impedance matching circuit of claim 13, wherein, The second connection unit further comprises a tenth switch tube, the tenth switch tube is connected between the ground and the second end of the ninth switch tube, a first end of the tenth switch tube is connected to the second control voltage, a second end of the tenth switch tube is grounded, and a third end of the tenth switch tube is connected to the second end of the ninth switch tube.

15. An impedance matching method, characterized by, The method is applied to the impedance matching circuit according to any one of claims 1-14, and the method comprises: acquiring a first node voltage; when the first node voltage is not equal to a preset reference voltage, adjusting the first node voltage according to a first feedback signal, so that the first node voltage is equal to the preset reference voltage; and when the first node voltage is equal to the preset reference voltage, acquiring a second node voltage; when the second node voltage is not equal to the preset reference voltage, adjusting the second node voltage according to a second feedback signal, so that the second node voltage is equal to the preset reference voltage. and adjusting the voltage of the signal port according to the first feedback signal and the second feedback signal, so that the voltage of the signal port is equal to the preset reference voltage.

16. An integrated circuit, comprising: An impedance matching circuit as claimed in any one of claims 1 to 14.

17. An electronic device, comprising: An integrated circuit comprising a housing and an impedance matching circuit as claimed in any one of claims 1 to 14 or an integrated circuit as claimed in claim 16 arranged in the housing.

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