A reconfigurable random number generator and its implementation method

Abstract

A reconfigurable random number generator and its implementation method, the generator comprises at least two ring oscillators, a sampling circuit, a counter and a logic control unit, the control end of the corresponding selector in each inverter group is electrically connected with the logic control unit, used for receiving the reconfiguration signal of the logic control unit, and completing the electrical signal channel conduction of the specified inverter in each inverter group and the selectors on both sides thereof; the output end of the at least two ring oscillators is coupled with the input end of the counter; the output end of the counter is connected with the logic control unit; the sampling circuit obtains a sampling electrical signal from the at least two ring oscillators, so as to output a random number according to the sampling electrical signal. The above-mentioned generator can improve the adaptability to the environment, and the circuit has optimal performance in power consumption, area, random number generation efficiency and the like.

Description

[Technical Field]

[0001] This invention relates to the field of random number generator technology, and in particular to a reconfigurable random number generator and its implementation method. [Background Technology]

[0002] Random numbers are widely used in cryptography, Monte Carlo simulation, spread spectrum communication, statistical research, artificial intelligence, neural networks, and other engineering and scientific research fields. Especially in cryptography, according to Shannon Theory, as long as the random numbers (keys) used are completely random, consistent with the length of the information to be encrypted, and used only once, the entire system will be absolutely secure and unbreakable. Therefore, how to generate secure and reliable random numbers is of paramount importance to the entire cryptographic system, and consequently to my country's national defense security, financial development, social stability, and personal privacy.

[0003] Currently, in the field of CMOS integrated circuits, true random number generators can be mainly divided into four categories based on their entropy sources: 1. Environmental noise-based; 2. Chaotic model-based; 3. Clock jitter-based; 4. Metastable circuit-based true random number generators. First, thermal noise is an excellent source of random entropy because its spectral distribution is relatively uniform and does not change with CMOS technology. Early integrated circuits mostly used this method to extract random numbers. However, thermal noise is difficult to obtain, usually requiring an ultra-wide bandwidth, high-gain amplifier to amplify the noise, making quantization difficult. The second category generates random numbers based on deterministic chaotic system equations. Due to its extreme sensitivity to initial conditions, the generated random numbers have long-term unpredictability. However, this high-entropy true random number generator generally has a large area and power consumption due to the need to implement the chaotic graph. The third category uses the jitter of a ring oscillator (RO) to generate true random numbers. The advantage of this method is that it can be easily and flexibly implemented on FPGAs or ASICs. The principle is to use a slow-jittering clock to sample a fast-jittering clock. The fourth type is a wideband amplifier, which has high resource consumption and power consumption. Secondly, latches or static random access memory (SRAM) in a metastable state can also be used to generate true random numbers; however, the true random number generator of this entropy source generally requires a complex post-processing unit.

[0004] As a widely used random number generator in industry, the ring oscillator-based random number generator has advantages such as ease of implementation and small area. However, this mechanism is susceptible to the effects of process variations, temperature, and voltage changes (PVT), which can cause the random number output to be biased and affect the entropy value.

[0005] Therefore, overcoming the shortcomings of the existing technology is an urgent problem to be solved in this technical field. [Summary of the Invention]

[0006] The technical problem to be solved by the embodiments of the present invention is that although the existing random number generator based on ring oscillator has advantages such as easy implementation and small area, the mechanism is easily affected by process differences, temperature and voltage changes, which leads to the bias of random number output and affects the entropy value.

[0007] The embodiments of the present invention adopt the following technical solutions:

[0008] In a first aspect, the present invention provides a reconfigurable random number generator, comprising at least two ring oscillators, a sampling circuit, a counter, and a logic control unit, specifically:

[0009] The ring oscillator includes n inverter groups, each inverter group consisting of at least two inverters arranged in parallel, and two selectors respectively arranged on the input side and the output side of the inverters; where n is a natural number.

[0010] The control terminal of the corresponding selector in each inverter group is electrically connected to the logic control unit to receive the reconstruction signal of the logic control unit and to complete the electrical signal channel connection between the specified inverter in each inverter group and the selectors on both sides.

[0011] The outputs of the at least two ring oscillators are coupled to the input of the counter; the output of the counter is connected to the logic control unit; the sampling circuit obtains a sampling electrical signal from the at least two ring oscillators in order to output a random number based on the sampling electrical signal.

[0012] Preferably, the logic control unit obtains the oscillation frequency difference between the at least two ring oscillators through the counter, and sends a reconstruction signal to each selector in the ring oscillator so that the oscillation frequency difference between the ring oscillators is less than a preset threshold by adjusting the selected inverter in the inverter group.

[0013] Preferably, the output terminals of the at least two ring oscillators are coupled to the input terminal of the counter, specifically including:

[0014] The outputs of the at least two ring oscillators are respectively connected to different input ports of the counter, so that the counter can count the oscillation frequencies corresponding to different ring oscillators; or,

[0015] The output terminals of the at least two ring oscillators are connected to at least two input terminals of the counting selector, and the output terminal of the counting selector is connected to the input terminal of the counter, so as to control the correspondence between the input and output terminals of the counting selector through the logic control unit, thereby realizing the sequential counting of the oscillation frequency of the ring oscillators.

[0016] Preferably, the ring oscillator further includes a NAND gate, and the inverter groups in the ring oscillator are cascaded, specifically:

[0017] The first input terminal of the NAND gate is connected to the enable signal; the second input terminal of the NAND gate is connected to the output port of the inverter group located at the end of the cascade; the output terminal of the NAND gate is used to connect to the input port of the inverter group located at the beginning of the cascade.

[0018] Preferably, the random number generator comprises a first ring oscillator and a second ring oscillator forming a random number source, and the sampling circuit comprises n D flip-flops, specifically:

[0019] The output of each inverter group in the first ring oscillator is also connected to the signal input port of a D flip-flop.

[0020] The output of each inverter group in the second ring oscillator is also connected to the clock input port of a D flip-flop.

[0021] The electrical signals at the output ports of the n D flip-flops in the sampling circuit constitute a random number.

[0022] Preferably, the ring oscillator further includes m ordinary inverters, specifically:

[0023] The m ordinary inverters and n inverter groups are cascaded in a preset arrangement order;

[0024] The preset arrangement order includes:

[0025] The m ordinary inverters are cascaded together, and the n inverter groups are cascaded together; the cascaded m ordinary inverters are then cascaded with the cascaded n inverters; or,

[0026] Ordinary inverters and inverter groups are cascaded in a manner that alternates between each other, wherein the distance between them is determined according to the proportional relationship between the m ordinary inverters and the n inverter groups; or,

[0027] The m ordinary inverters and n inverter groups are cascaded in a random order.

[0028] Preferably, the random number generator comprises a third ring oscillator and a fourth ring oscillator forming a random number source, and the sampling circuit comprises p D flip-flops, where n ≤ p ≤ m + n. Specifically:

[0029] Within the third ring oscillator, the outputs of the inverter and / or inverter group are each connected to the signal input port of a D flip-flop.

[0030] Within the fourth ring oscillator, the inverter group and / or the output of the inverter are each connected to the clock input port of a D flip-flop.

[0031] The electrical signals at the output ports of the n D flip-flops in the sampling circuit constitute a random number.

[0032] Preferably, when the random number generator operates in physically non-cloning function mode, the logic control unit is further configured to acquire excitation signals for one or more ring oscillators, specifically:

[0033] The logic control unit converts the excitation signal into a reconstruction signal for one or more corresponding ring oscillators;

[0034] The logic control unit acquires the output oscillation frequency of one or more ring oscillators triggered by the excitation signal, and calculates the physically unclonable output result based on the corresponding oscillation frequency or the difference between the oscillation frequencies.

[0035] Preferably, the excitation signal of the ring oscillator is specifically the output of a designated inverter group in the ring oscillator as the data source for calculating the physically unclonable output result.

[0036] Preferably, the step of calculating the physically unclonable output result based on the corresponding oscillation frequency or the difference between oscillation frequencies specifically includes:

[0037] If the difference in oscillation frequencies is greater than 0, output 0; if the difference in oscillation frequencies is less than 0, output 1; or...

[0038] If the difference in oscillation frequencies is greater than 0, output 1; if the difference in oscillation frequencies is less than 0, output 0; or...

[0039] The oscillation frequency is decimaled to a specified length and output as an integer value.

[0040] Preferably, the inverter is one or more of the following: a TTL NOT gate inverter, a CMOS inverter, an HPM scrambling effect inverter, or a starved inverter.

[0041] Preferably, when the at least two ring oscillators include a first ring oscillator, a second ring oscillator, and a third ring oscillator,

[0042] The first and second ring oscillators constitute a random number source, and the second and third ring oscillators constitute a random number source; or,

[0043] The first and third ring oscillators constitute a random number source, and the second and third ring oscillators constitute a random number source; or,

[0044] The first ring oscillator and the second ring oscillator constitute a random number source, and the first ring oscillator and the third ring oscillator constitute a random number source.

[0045] In a second aspect, the present invention provides a method for implementing a reconfigurable random number generator, using the reconfigurable random number generator as described in the first aspect, the method comprising:

[0046] The logic control unit obtains the oscillation frequency of the at least two ring oscillators through the counter;

[0047] The logic control unit determines a first ring oscillator and a second ring oscillator as a random number source, and analyzes the difference in oscillation frequencies between the first ring oscillator and the second ring oscillator.

[0048] If the oscillation frequency is greater than a preset threshold, the logic control unit sends a reconstruction signal to the first ring oscillator and / or the second ring oscillator to control the selectors in the first ring oscillator and the second ring oscillator to complete the conduction operation of the specified inverter signal channel in the corresponding inverter group.

[0049] By adjusting the reconstructed signal once or multiple times through the logic control unit, the difference in oscillation frequency between the first ring oscillator and the second ring oscillator is made less than a preset threshold.

[0050] Preferably, the adjustment of the reconstructed signal by the logic control unit one or more times, so that the difference in oscillation frequency between the first ring oscillator and the second ring oscillator is less than a preset threshold, specifically includes:

[0051] By repeatedly adjusting the reconstructed signal, the selection control of the inverters used for electrical signal conduction in each inverter group is completed one by one.

[0052] In each adjustment of the reconstructed signal, if the difference in oscillation frequency between the first ring oscillator and the second ring oscillator is reduced, the reconstructed signal at this time is retained as the reconstructed signal of the current state. The oscillation frequency difference corresponding to the reconstructed signal of the current state is used to compare with the oscillation frequency difference under the reconstructed signal after the next adjustment, and the reconstructed signal with the smaller oscillation frequency difference is updated as the reconstructed signal of the current state.

[0053] The traversal process stops when the difference in oscillation frequencies between the first and second ring oscillators is less than a preset threshold.

[0054] Preferably, if the method further includes a third ring oscillator, and the first and third ring oscillators constitute another random number source, the method further includes:

[0055] After the logic control unit adjusts the reconstructed signal once or multiple times to make the difference between the oscillation frequencies of the first and second ring oscillators less than a preset threshold, the logic control unit then adjusts the reconstructed signal of the third ring oscillator once or multiple times to make the difference between the oscillation frequencies of the first and third ring oscillators less than a preset threshold.

[0056] Compared with the prior art, the beneficial effects of the embodiments of the present invention are as follows:

[0057] The reconfigurable ring oscillator proposed in this invention can calculate the oscillation frequency difference between the output signals of different ring oscillators through a counter, and pass the result to the logic control unit. The logic control unit then further adjusts the inverter group in the associated ring oscillator to obtain the ring oscillator output that meets the conditions.

[0058] Furthermore, in a preferred embodiment of the present invention, a solution is proposed to achieve physically unclonable output results based on the reconfigurable ring oscillator. The implementation of the solution still relies on the core innovation of the present invention, namely the inverter group structure and the reconfiguration control of each inverter group in the ring oscillator by the logic control unit.

[0059] In this invention, the reconfigurable function of each inverter group can be used to keep the difference in the oscillation frequency of the output data of at least two ring oscillators that output random numbers within a preset threshold, thereby reducing the bias of generating random sequences, improving the adaptability to the environment, and making the circuit perform optimally in terms of power consumption, area, and efficiency in generating random numbers. [Attached Image Description]

[0060] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0061] Figure 1 This is a schematic diagram of a reconfigurable random number generator structure provided in an embodiment of the present invention;

[0062] Figure 2 This is a schematic diagram of the inverter group structure in a reconfigurable random number generator provided in an embodiment of the present invention;

[0063] Figure 3 This is a schematic diagram of the working state structure of the inverter group in a reconfigurable random number generator provided by an embodiment of the present invention;

[0064] Figure 4 This is a schematic diagram of the working state structure of the inverter group in a reconfigurable random number generator provided by an embodiment of the present invention;

[0065] Figure 5 This is a schematic diagram of another reconfigurable random number generator structure provided in an embodiment of the present invention;

[0066] Figure 6 This is a schematic diagram of another reconfigurable random number generator structure provided in an embodiment of the present invention;

[0067] Figure 7 This is a schematic diagram of a ring oscillator structure provided in an embodiment of the present invention;

[0068] Figure 8 This is a schematic diagram of another ring oscillator structure provided in an embodiment of the present invention;

[0069] Figure 9 This is a schematic diagram of another reconfigurable random number generator structure provided in an embodiment of the present invention;

[0070] Figure 10 This is a schematic diagram of another reconfigurable random number generator structure provided in an embodiment of the present invention;

[0071] Figure 11 This is a schematic flowchart of a reconfigurable random number generator implementation method provided by an embodiment of the present invention;

[0072] Figure 12 This is a schematic flowchart of a reconfigurable random number generator implementation method provided by an embodiment of the present invention;

[0073] Figure 13 This is a schematic flowchart of a reconfigurable random number generator implementation method provided by an embodiment of the present invention;

[0074] Figure 14 This is a schematic diagram of a specific reconfigurable random number generator structure provided in an embodiment of the present invention;

[0075] Figure 15 This is a schematic diagram of a current-starved inverter structure provided in an embodiment of the present invention;

[0076] Figure 16This is a structural diagram of a D flip-flop provided in an embodiment of the present invention;

[0077] Figure 17 This is a timing diagram of a D flip-flop provided in an embodiment of the present invention;

[0078] Figure 18 This is a schematic diagram of a process for completing reconstructed signal locking according to an embodiment of the present invention.

Detailed Implementation Methods

[0079] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0080] In the description of this invention, the terms "inner", "outer", "longitudinal", "lateral", "upper", "lower", "top", "bottom", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and do not require that this invention must be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0081] Furthermore, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0082] Example 1:

[0083] Embodiment 1 of the present invention provides a reconfigurable random number generator, such as Figure 1 As shown, it includes at least two ring oscillators ( Figure 1 The example illustrates a system comprising a first to a y-th ring oscillator, a sampling circuit, a counter, and a logic control unit. The description of at least two ring oscillators is because, in this specific implementation, two ring oscillators represent the minimum configuration requirement for generating a random number. However, as an optional implementation, if the actual application requires the reconfigurable random number generator proposed in this embodiment to simultaneously output two or more random numbers, then two or more ring oscillators are needed. The more ring oscillators configured, the more random numbers can be generated concurrently. In this embodiment, the reconfigurable random number generator includes:

[0084] The ring oscillator includes n inverter groups, such as Figure 2 As shown, each inverter group consists of at least two inverters arranged in parallel, and inverters respectively located on the input side of the inverters (i.e., ...). Figure 2The left side of the parallel-arranged inverters shown) and the output side (i.e. Figure 2 The two selectors (on the right side of the parallel inverters shown) constitute the structure; where n is a natural number. The value of n is related to the number of digits in the random number to be generated; generally, the more digits in the random number, the larger the value of n will be.

[0085] The parallel inverters described here refer to the technical meaning that, by using selectors on both sides of the inverters, the electrical signal path of one of at least two parallel inverters can be selectively turned on. In an inverter group, the other inverters will be in a state of electrical signal path blockage relative to the inverter with the electrical signal turned on, because the selectors located before and after the corresponding inverters have not specified the interface to be turned on.

[0086] The control terminal of the corresponding selector in each inverter group is electrically connected to the logic control unit, used to receive the reconstruction signal from the logic control unit and to complete the electrical signal channel connection between the specified inverter in each inverter group and the selectors on both sides. For example, Figure 3 In the inverter group shown, a selector controls the selection of inverter number 1, which is then in the electrically connected state, while the other inverters numbered 2 to x are in the electrically blocked state; for example... Figure 4 As shown, in the inverter group, the inverter labeled 2 is selected by a selector to enter the electrical channel conducting state, while the other inverters labeled 1, 3 to x are in the electrical channel blocking state. It should be noted that, in this embodiment of the invention, the control function of the selector is a mature technology in the field, while the innovation of this invention lies in its application to the overall structural technical solution described in this embodiment.

[0087] The outputs of the at least two ring oscillators are coupled to the input of the counter; the output of the counter is connected to the logic control unit; the sampling circuit obtains a sampling electrical signal from the at least two ring oscillators in order to output a random number based on the sampling electrical signal.

[0088] The reconfigurable ring oscillator proposed in this embodiment of the invention can calculate the oscillation frequency difference between the output signals of different ring oscillators through a counter, and pass the result to the logic control unit. The logic control unit then further adjusts the inverter group in the associated ring oscillator (which can be understood as a control signal used to output a random number) to obtain the ring oscillator output that meets the conditions.

[0089] In this embodiment of the invention, the reconfigurable function of each inverter group can be used to keep the difference in the oscillation frequency of the output data of at least two ring oscillators that output random numbers within a preset threshold, thereby reducing the bias of generating random sequences, improving the adaptability to the environment, and making the circuit perform optimally in terms of power consumption, area, and efficiency in generating random numbers.

[0090] In this embodiment of the invention, the logic control unit obtains the oscillation frequency difference between the at least two ring oscillators through the counter, and sends a reconstruction signal to each selector in the ring oscillators (the reconstruction signal selects the parallel inverters configured in each inverter group; when a single inverter group has more than two inverters, the reconstruction signal sent to each inverter group should be greater than 1 bit). This is to adjust the selected inverters in the inverter group to ensure that the oscillation frequency difference between the ring oscillators is less than a preset threshold or the minimum value within the range. The preset threshold here is an empirical value, which can be verified by testing the repeatability of random numbers. The oscillation frequency difference obtained when the repeatability of random numbers meets the specified requirements can be set as the parameter value of the preset threshold. Specifically, the random numbers generated within a certain range of the frequency difference between the two inverters can be tested using a random number standard (e.g., the NIST random number test standard).

[0091] In this embodiment of the invention, there are various ways to couple the output terminals of the at least two ring oscillators with the input terminal of the counter. For example, the counter itself may contain multiple counting input ports, similar to... Figure 1 The connection structure shown allows the counter to simultaneously count the output oscillation frequencies of at least two ring oscillators. The output terminals of these at least two ring oscillators are connected to different input ports of the counter, enabling the counter to count the oscillation frequencies of the corresponding ring oscillators. In practical applications, the number of counters is not directly related to the output of the random number to be generated; one counter can be provided for each random number output (e.g., ...). Figure 1 As shown in the image, if the counter function is sufficiently powerful, a single counter can be used to handle multiple random numbers. However, as a more practical and cost-effective solution, the corresponding counter tends to use a device with a single counting input port. In this case, another feasible solution exists, such as... Figure 5 Specifically, it includes:

[0092] The output terminals of the at least two ring oscillators are connected to at least two input terminals of the counting selector, and the output terminal of the counting selector is connected to the input terminal of the counter, so as to control the correspondence between the input and output terminals of the counting selector through the logic control unit, thereby realizing the sequential counting of the oscillation frequency of the ring oscillators.

[0093] like Figure 1 and Figure 5 As shown, in order to enable and control the ring oscillator, a NAND gate is usually provided on the input port side of the ring oscillator, and the inverter groups in the ring oscillator are cascaded, specifically:

[0094] The first input terminal of the NAND gate is connected to an enable signal; the second input terminal of the NAND gate is connected to an inverter group located at the end of the cascade (e.g., ...). Figure 5 The output port of the inverter group located on the far right of the cascade is connected; the output of the NAND gate is used to connect to the input port of the inverter group located at the beginning of the cascade (e.g., ...). Figure 5 The inverter group located on the far left in the middle.

[0095] In this embodiment of the invention, a random number source is formed by a first ring oscillator and a second ring oscillator in the random number generator, and the sampling circuit is composed of n D flip-flops, such as... Figure 6 As shown, specifically:

[0096] The output of each inverter group in the first ring oscillator is also connected to the signal input port of a D flip-flop; the output of each inverter group in the second ring oscillator is also connected to the clock input port of a D flip-flop; the electrical signals of the output ports of the n D flip-flops in the sampling circuit constitute a random number.

[0097] In specific implementations of this invention, in addition to those similar to the above... Figure 1 , Figure 5 and Figure 6 In addition to the example implementation using a single cascaded inverter group, embodiments of the present invention also provide similar... Figure 7 and Figure 8 The diagram illustrates an implementation of a ring oscillator, which further includes m ordinary inverters (i.e., ...). Figure 8 and Figure 7 In the above, a common inverter is cascaded with the aforementioned inverter group, specifically:

[0098] The m ordinary inverters and n inverter groups are cascaded in a preset arrangement order;

[0099] The preset arrangement order includes:

[0100] Method 1, such as Figure 7 As shown, the m ordinary inverters are cascaded together, and the n inverter groups are cascaded together; the cascaded m ordinary inverters are then cascaded with the cascaded n inverters.

[0101] Method 2, such as Figure 8 As shown, ordinary inverters and inverter groups are cascaded with alternating intervals. The interval between them is determined by the proportional relationship between the m ordinary inverters and the n inverter groups. It should be noted that m and n are both natural numbers, and n is related to the corresponding... Figure 5 The value of n can be adjusted according to the needs of each application scenario, and does not necessarily mean that the values ​​of the two need to be consistent in their respective scenarios.

[0102] Method 3: The m ordinary inverters and n inverter groups are cascaded in a random order. It should be noted that, compared to the regular, interleaved cascading structure of Method 2, Method 3 does not adhere to a specified rule. From a certain implementation perspective, Method 3 offers more possibilities. It can be understood as further mitigating the uncertainties in the manufacturing process through the random ordering, potentially allowing the discovery of a ring oscillator with oscillation frequency characteristics that surpasses the regularly interleaved arrangement during later testing. Here, random ordering is relative to the designed circuit; for the completed reconfigurable random number generator, the arrangement of the inverter groups and ordinary inverters in the corresponding ring oscillator is a deterministic relationship.

[0103] To address the aforementioned proposal of introducing ordinary inverters into the cascaded inverter group structure to form a composite cascaded structure, the random number generator, in which a third and fourth ring oscillator constitute a random number source, further includes a sampling circuit. This sampling circuit is composed of p D flip-flops, where n ≤ p ≤ m + n. Figure 9 As shown, specifically:

[0104] Within the third ring oscillator, the outputs of designated inverters and / or inverter groups are each connected to the signal input port of a D flip-flop; within the fourth ring oscillator, the outputs of designated inverter groups and / or inverters are each connected to the clock input port of a D flip-flop; the electrical signals from the output ports of the n D flip-flops in the sampling circuit constitute a random number. Figure 9 It can be seen that its structure adopts the implementation method where p equals n, that is, it still uses the electrical signals brought out from the output ports of each inverter group as the basis for generating random numbers; while for the implementation method of p = m + n, please refer to Figure 10 The structure shown. It should be noted that, similar to... Figure 9 Figure 10 The structure shown is merely a feasible solution implemented to present the key structural differences in the most concise possible way, similar to... Figure 9 and Figure 10The structure can be extended by adding NAND gates to achieve enable signal control, or a similar approach can be used. Figure 5 The single-input port counter extension implementation scheme shown is such that the optional schemes proposed in each extension scheme in the embodiments of the present invention can be organically combined in each implementation scheme of the present invention, and will not be described in detail here.

[0105] It should be further explained that the designations of the first, second, third, and fourth in the embodiments of the present invention are merely for the convenience of expression and, to a certain extent, to distinguish the objects and individuals being described. Apart from this, they do not have any special limiting meaning and should not be over-interpreted to narrow the scope of protection of the present invention.

[0106] As a novel information security mechanism, Physically Unclonable Functions (PUFs) have attracted widespread attention in industry and have already been commercialized. PUFs can be widely used in security authentication and key generation mechanisms, and can resist various physical attacks, including invasive attacks, offering advantages such as low cost and high security.

[0107] In fact, the industry has begun to integrate true random number generators and physically unclonable function modules as independent circuits into a single chip as the security foundation of security modules, such as the "ChipDNA" security chip launched by Maxim Integrated.

[0108] This invention enables the reconfigurable random number generator described above to be further reused as a physically unclonable function, achieving circuit reuse and saving resources. This invention can also reconfigure ring oscillators to adjust the relative frequencies of two ring oscillators, removing deterministic noise (such as manufacturing variations) or inherent bias caused by PVT, thereby ensuring the randomness of the output random numbers. Furthermore, when the reconfigurable random number generator proposed in this embodiment is further reused as a physically unclonable function, specifically:

[0109] The logic control unit is also used to acquire excitation signals for one or more ring oscillators (e.g., directly inputting one or more excitation signals for ring oscillators to the logic control unit via a host computer; the excitation signal can be expressed as the selection of the working output of a specified reflector group in each ring oscillator, thereby dynamically changing the combination of the working reflector groups in the ring oscillator by adjusting the excitation signal, so that the ring oscillator meets the requirements of a specific environment), and the logic control unit converts the excitation signal into a reconstruction signal for the corresponding one or more ring oscillators;

[0110] The logic control unit acquires the output oscillation frequency of one or more ring oscillators triggered by the excitation signal, and calculates the physically unclonable output result based on the corresponding oscillation frequency or the difference between the oscillation frequencies.

[0111] In the above preferred implementation of the present invention, a solution is proposed to achieve physically unclonable output results based on the reconfigurable ring oscillator. The implementation of the solution still relies on the core innovation of the present invention, namely the inverter group structure and the reconfiguration control of each inverter group in the ring oscillator by the logic control unit.

[0112] In practical implementation, to achieve the expected physically unclonable output result, it is usually necessary to use a counter and logic control unit to reconstruct each inverter group in the ring oscillator, so that the oscillation frequencies of the two ring oscillators used to form the oscillation frequency difference are significantly different. This is because, at this point, the relative frequency difference no longer originates from jitter, but from fixed factors such as manufacturing variations. Therefore, this conforms to the characteristics of a physically unclonable function (PUF) circuit. For a 64-stage reconfigurable ring oscillator (i.e., including 64 inverter groups), the configuration signal combination is 2... 64 The fixed output generated by the configuration signal with a fixed output can be used for mechanisms such as key generation.

[0113] The physical non-cloning output result is calculated based on the corresponding oscillation frequency or the difference between oscillation frequencies, specifically including:

[0114] If the difference in oscillation frequencies is greater than 0, output 0; if the difference in oscillation frequencies is less than 0, output 1; or...

[0115] If the difference in oscillation frequencies is greater than 0, output 1; if the difference in oscillation frequencies is less than 0, output 0; or...

[0116] The oscillation frequency is decimaled to a specified length and output as an integer value.

[0117] As a presentation of a relatively complete implementation of the present invention, such as Figure 11 As shown, the method incorporates both true random number mode and physically unclonable mode, and the working mode can be selected between the two during the specific method implementation. Figure 11 As shown, the corresponding method process includes:

[0118] In step 101, the logic control unit performs frequency statistics on at least two ring oscillators using a counter to obtain the frequency difference. At this point, depending on the operating mode set in the logic control unit, if it is a true random number mode, then proceed to step 102; if it is a physically unclonable mode, then proceed to step 104.

[0119] In step 102, the reconstructed signal is adjusted by the logic control unit once or multiple times, and different inverters are selected so that the difference in oscillation frequency between the first ring oscillator and the second ring oscillator is less than a preset threshold.

[0120] In step 103, the oscillator jitter caused by the phase noise of the two ring oscillators is sampled to generate random numbers.

[0121] In step 104, the logic control unit adjusts the reconstructed signal multiple times, selects different inverters, and obtains the oscillation frequency or frequency difference of the ring oscillator for each time.

[0122] In step 105, the physically unclonable output result is calculated based on the corresponding oscillation frequency or the difference between the oscillation frequencies.

[0123] The specific methods and processes for each mode will be elaborated in Example 2, and will not be repeated in the embodiments of this invention.

[0124] Example 2:

[0125] This invention proposes a method for implementing a reconfigurable random number generator, using the reconfigurable random number generator described in Embodiment 1, such as... Figure 12 As shown, the implementation methods include:

[0126] In step 201, the logic control unit obtains the oscillation frequency of the at least two ring oscillators through the counter.

[0127] In step 202, the logic control unit determines a first ring oscillator and a second ring oscillator as a random number source, and analyzes the difference in oscillation frequencies between the first ring oscillator and the second ring oscillator.

[0128] In step 203, if the oscillation frequency is greater than a preset threshold, the logic control unit sends a reconstruction signal to the first ring oscillator and / or the second ring oscillator to control the selectors in the first and second ring oscillators to complete the conduction operation of the specified inverter signal channel in the corresponding inverter group.

[0129] In step 204, the reconstructed signal is adjusted by the logic control unit once or multiple times so that the difference in oscillation frequency between the first ring oscillator and the second ring oscillator is less than a preset threshold.

[0130] The reconfigurable ring oscillator implementation method proposed in this invention can calculate the oscillation frequency difference between the output signals of different ring oscillators using a counter, and pass the result to the logic control unit. The logic control unit then further adjusts the inverter group in the associated ring oscillator to obtain the ring oscillator output that meets the conditions.

[0131] In conjunction with embodiments of the present invention, the adjustment of the reconstructed signal by the logic control unit once or multiple times ensures that the frequency difference between the first and second ring oscillators is less than a preset threshold. Figure 12 As shown, it specifically includes:

[0132] In step 2041, the selection control of the inverters used for electrical signal conduction in each inverter group is completed one by one by adjusting the reconstructed signal.

[0133] In step 2042, each adjustment to the reconstructed signal reduces the frequency difference between the first and second ring oscillators. The reconstructed signal at this time is then retained as the reconstructed signal of the current state. The frequency difference corresponding to the reconstructed signal of the current state is compared with the frequency difference of the reconstructed signal after the next adjustment, and the reconstructed signal with the smaller frequency difference is updated as the reconstructed signal of the current state.

[0134] In step 2043, the traversal process stops when the difference in oscillation frequencies between the first and second ring oscillators is less than a preset threshold.

[0135] It is worth noting that the information interaction and execution process between the modules and units in the above-mentioned device are based on the same concept as the processing method embodiment of the present invention. For details, please refer to the description in the method embodiment of the present invention, and will not be repeated here.

[0136] Example 3:

[0137] Based on Embodiments 1 and 2, this invention will further illustrate the detailed implementation process of the complete solution by combining a specific example in the implementation process with corresponding accompanying drawings. Compared to the structure in Embodiment 1 that uses at least two inverters to form an inverter group, this invention further uses current-starved inverters to form the corresponding inverter group, thereby further improving performance.

[0138] This configurable random number generator circuit structure is as follows: Figure 14As shown. It mainly includes two ring oscillators (ring oscillator RO1 and ring oscillator RO2), a counter, a set of D flip-flops, a parallel-to-serial interface circuit (it can be seen that the parallel-to-serial interface circuit is not directly introduced in the implementation scheme of Embodiment 1, because, as an optional implementation scheme, the parallel-to-serial interface circuit does not necessarily have to be integrated into the technical solution of this embodiment of the invention; it can also be implemented by combining it with peripheral circuits), and a set of control logic (C0~C...). 2n-1 ,EN…).

[0139] The control logic is responsible for switching the operating modes of the ring oscillator. The reconfigurable random number generator in this embodiment has two operating modes: a random number generator mode and a physically unclonable function mode.

[0140] like Figure 14 As shown, the two ring oscillators RO1 and RO2 each consist of one NAND gate (NAND1, NAND2) and n inverter groups (IVs0~IVsn-1, IVsn~IVs2n-1); each inverter group consists of a multiplexer (a 2-to-1 multiplexer is used as an example in the figure, but it can be any multiplexer) and a current-starved inverter, which can be configured according to the reconstructed signal (C0~C... 2n-1 The circuit is reconfigured to reduce the impact of process variations, voltage variations, and temperature variations (PVT) on the circuit, ensuring the high entropy of the random number generator and the high reliability of the physically unclonable function circuit; n D flip-flops (D0~D10) n-1 The sampling circuit samples the oscillator jitter caused by the phase noise of the two ring oscillators to generate random numbers; the counting selection circuit is used to detect the operating state of the ring oscillators in random number generator mode and to generate a physically non-cloning function output in physically non-cloning function mode; the logic control unit is used to configure the circuit operating state (random number mode or physically non-cloning function mode) and, based on the output of the counting circuit, to reconstruct the signal (C0~C...). 2n-1 Reconfigurable ring oscillators. Through logic processing control circuitry, two reconfigurable current-starved ring oscillators can be used as high-entropy random number generators or physically unclonable functions. A parallel-to-serial interface output circuit is used to serially output the random numbers generated by the random number generator.

[0141] In true random number generation mode, the jitter noise of two current-starved ring oscillators operating in the subthreshold region is sampled from each other to generate high-entropy random numbers. The current-starved ring oscillators operate in the subthreshold region, where the noise at each stage is higher, resulting in higher entropy values ​​for the generated random numbers. Furthermore, operating in the subthreshold region facilitates control of the inverter's operating current, thereby controlling the inverter's charging and discharging time and achieving frequency control of the ring oscillator, while simultaneously reducing power consumption. The random number generation process is as follows: The subthreshold ring oscillator can reconstruct signals C0 to C... 2n-1 Reconstructing inverter group (IVs0~IVs) n-1 IVs n ~IVs 2n-1 By selecting different current-starved inverters to form an oscillator, the oscillation frequency f of the ring oscillator can be adjusted. RO1 f RO2 The frequencies f of the two sets of ring oscillators RO1 f RO2 The frequency difference is calculated by a bidirectional counter; the logic processing control circuit analyzes this frequency difference, and if the frequency difference does not meet the preset threshold, the reconstructed signals C0 to C1 are changed. 2n-1 This adjusts the output frequency of the ring oscillator; when f RO1 f RO2 If the frequency count difference is less than a preset threshold, the reconstructed signal is fixed; then, the output of each stage of the reconstructed inverter of the two sets of ring oscillators is used as a D flip-flop (D0~D1). n-1 The data signal and clock signal are used to complete the sampling; the oscillator jitter caused by phase noise is utilized to activate the D flip-flop (D0~D1). n-1 The system will continuously output random numbers in parallel; then, through the parallel-to-serial interface circuit, it will output a serial true random number bit stream.

[0142] When operating in the physically non-clonable function mode, C0~C 2n-1 This will serve as the excitation for a physically unclonable function; due to random deviations during integrated circuit manufacturing, the difference in oscillation frequencies at the outputs of two cascaded oscillators will be extracted using a counter; thus, the output of the physically unclonable function will be obtained; by changing the excitation C0 to C in the exponential space... 2n-1， Physically unclonable functions are based on a certain excitation C0 to C 2n-1 Generate a unique response.

[0143] Random number generators are an indispensable component of existing information security systems, and physically unclonable functions (PFCs) are used for security authentication or key generation, replacing existing key storage and security authentication mechanisms based on volatile memory, and effectively resisting various physical attacks such as intrusive attacks. This invention enables the same circuit to be configured as a random number generator or a PFC, achieving circuit reuse and saving resources. This invention can reconfigure ring oscillators to adjust the relative frequencies of two ring oscillators, removing deterministic noise (such as manufacturing differences) or inherent bias caused by PVT, thereby ensuring the randomness of the output random numbers. Embodiments of this invention use current-starved inverters to construct the random number generator, resulting in superior energy efficiency. Embodiments of this invention operate the current-starved inverters at zero temperature (Zero-TC), further reducing the impact of temperature.

[0144] Examples of embodiments of the present invention Figure 14 The reconfigurable random number generator shown is further illustrated by the following explanation of the implementation principle of the parallel interface circuit described above:

[0145] The parallel-to-serial interface circuit includes n D flip-flops and (n-1) data selectors (MUX);

[0146] The clock control terminal CLK of N D flip-flops is connected to the clock signal Nf0, and the data selection control terminal of (N-1) data selectors MUX is connected to the clock signal f0.

[0147] The input D of the first D flip-flop is connected to the parallel input signal P0, and the output Q is connected to one input of the first data selector MUX. The output of the first data selector is connected to the input D of the second D flip-flop, and the output of the second D flip-flop is connected to one input of the second data selector, and so on. The output of the (N-1)th D flip-flop is connected to one input of the (N-1)th data selector MUX, and the output of the (N-1)th data selector MUX is connected to the input D of the Nth D flip-flop. The output Q of the Nth D flip-flop is a serial output signal. The parallel output signals P1, P2...PN are connected to the other input of the (N-1)th data selector MUX in sequence.

[0148] By adjusting Figure 15 The inverter shown is a current-starved inverter used in this embodiment of the invention, comprising two PMOS devices M1 and M2, and two NMOS devices M3 and M4; the source of M1 is connected to a high supply voltage V. dd The drain of M1 is connected to the source of M2, the drain of M2 is connected to the drain of M3, the source of M3 is connected to the drain of M4, and the source of M4 is grounded; the gate of M1 is connected to the bias voltage V. p The gate of M4 is biased by voltage V. nThe gates of M2 and M3 are the input terminals V. i The drain of M2 and M3 is the output terminal V. o Among them, the bias voltage V P With V n This allows the inverters to operate at zero temperature (Zero-Tc), making the random number generator less susceptible to temperature effects. The underlying principle is that the frequencies of the ring oscillators RO1 and RO2 are determined by the delay of each inverter stage.

[0149]

[0150] Where C0 is the total circuit load, V dd Where η is the power supply voltage, η is the inverter circuit constant, and I is the power supply voltage. D This is the saturation current; further, the saturation current I D for

[0151]

[0152] Among them, the channel length W, the channel width L, and the gate-source voltage V GS Gate capacitance C OX Threshold voltage V t The channel length, channel width, gate-source voltage, gate capacitance, threshold voltage, and carrier mobility μ are respectively given by the channel length, channel width, gate-source voltage, gate capacitance, threshold voltage, and carrier mobility; furthermore, the temperature coefficient of the switching current at temperature T for the saturation current is:

[0153]

[0154] This coefficient needs to be as small as possible to reduce the effect of temperature on the saturation current. Therefore, in the design, the bias voltage V P With V n The following principle must be followed: Under the premise that the circuit can switch normally, V must be... GS As small as possible.

[0155] like Figure 16 As shown, this is a D flip-flop (D0~) provided in an embodiment of the present invention. Dn-1 The schematic diagram shows that the D flip-flop includes two AND gates (AND_1, AND_2), two NOR gates (NOR_1, NOR_2), one inverter, one capacitor C, and one resistor R.

[0156] The clock control signal CLK is input to one input terminal of AND gate AND_1 and one input terminal of AND gate AND_2 through capacitor C. A resistor R is connected to the line between capacitor C and AND gates AND_1 and AND_2. The other end of resistor R is grounded.

[0157] The inverter's input is connected to the input signal D, and its output is connected to AND gate AND_1. The inputs of AND gate AND_1 are connected to the output of the inverter and one input of AND gate AND_2. The inputs of AND gate AND_2 are connected to the input signal D and AND gate AND_1, and its output is connected to one input of NOR gate NOR_2. The inputs of NOR gate NOR_1 are connected to the outputs of AND gate AND_1 and NOR gate NOR_2, and its output is connected to one input of NOR gate NOR_2, simultaneously outputting the output signal Q of the D flip-flop. The inputs of NOR gate NOR_2 are connected to the outputs of AND gate AND_2 and NOR gate NOR_1.

[0158] The output terminal is connected to one input of a NOR_1 gate, and simultaneously outputs the output signal of a D flip-flop.

[0159] The timing diagram for a D flip-flop generating a random signal is as follows: Figure 17 As shown. During the first clock cycle, two oscillators generate trigger signals and clock control signals with similar frequencies, which are input to terminals D and CLK respectively. Due to the deviation caused by jitter noise, the signals on CLK and D do not correspond perfectly. In the first clock cycle, the rising edge of CLK corresponds to a high level on D, outputting 1, and the falling edge of CLK corresponds to a low level on D, outputting 0. The rising edge of the next clock cycle corresponds to a low level on D, outputting 0.

[0160] The frequencies of the two ring oscillators need to be as close as possible to generate sufficient frequency jitter and produce high-entropy random numbers. The control logic unit searches for the optimal reconstructed signal C0-C. 2n-1 Flowchart as follows Figure 18 As shown. In the initial stage, C0-C 2n-1 A set of initial values ​​is preset. A counter counts the ring oscillator RO1 in the forward direction within time t, and then counts the ring oscillator RO2 in the reverse direction at the next time t to obtain ΔN = N1 - N2, where N1 is the oscillation frequency count value of ring oscillator R01, and N2 is the oscillation frequency count value of ring oscillator R02. A variable i is defined and initialized to 0. The first step is to invert the reconstructed signal C0 for i = 0, obtaining C0', which means selecting another inverter in the inverter group. The reconstructed signals C0' to C... 2n-1 Repeat the counting process above to obtain ΔN′; determine whether ΔN is smaller than ΔN′, and if so, retain C0 to C1. 2n-1 If the difference is less than 1, then keep the changed C0' and increment i by 1. If the difference is less than 1, then keep the changed C0' and increment i by 1. Finally, check if i is equal to n-1. If it is, then the local optimum has been obtained by traversing the first n-1 inverters.

[0161] In the physically non-cloning function mode, this C0~C 2n-1 It can be directly input from the outside, and by comparing the frequency values ​​of two oscillators, a unique response is generated under each input excitation; a typical response generation method is: if f RO1 >f RO2 If f RO1 ≤f RO2 The output will be 1 if the frequency difference is large enough, and vice versa. Unlike a true random number generator, the frequency difference is fed into the control logic. Only outputs with sufficiently large frequency differences are marked as stable bit outputs; otherwise, they are discarded. This improves the stability of the designed physically unclonable function.

[0162] In terms of circuit design, the goal is to achieve high speed and low power consumption. Based on the characteristics of this circuit, a delay unit is proposed as the basic structure of the oscillator, and an E-TSPC type flip-flop is proposed as the counting unit of the bidirectional counter.

[0163] Example 4:

[0164] In this embodiment of the invention, a test result is also provided:

[0165]

[0166] To preliminarily verify the actual effect of the present invention, the circuit of the present invention was implemented in pure digital circuit on a Xilinx Artix-7 FPGA (using ordinary inverters instead of current-starved inverters, since only ordinary inverters are available in FPGAs). The frequencies of the two ring oscillators RO were tested using an oscilloscope to observe whether the reconstruction of the circuit of the present invention can achieve the expected effect.

[0167] The table shows the frequency and frequency difference of the ring oscillator RO for automatic layout and routing in the first row.

[0168] The second row shows the frequency difference of the ring oscillator RO after the reconstruction process in the automatic placement and routing process.

[0169] The third row shows the frequency difference of the ring oscillator RO after the reconstruction process using manual layout wiring.

[0170] The results show that the reconstruction process can significantly reduce the frequency difference between the two ring oscillators RO (ring oscillators RO1 and RO2), thereby improving the randomness of the output. Good results can be achieved even under automatic placement and routing.

[0171] Further testing revealed that the randomness of its output successfully passed the NIST randomness test suit, meeting the randomness requirements.

[0172] Those skilled in the art will understand that all or part of the steps in the various methods of the embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, which may include: read-only memory (ROM), random access memory (RAM), magnetic disk or optical disk, etc.

[0173] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A reconfigurable random number generator, characterized by, The random number generator comprises at least two ring oscillators, a sampling circuit, a counter and a logic control unit, in particular: The ring oscillator comprises n inverter groups, each inverter group being composed of at least two inverters arranged in parallel and two selectors arranged at the input side and the output side of the inverters respectively; wherein n is a natural number; The control end of the corresponding selector in each inverter group is electrically connected with the logic control unit, for receiving the reconstruction signal of the logic control unit, and completing the electrical signal channel conduction of the designated inverter in each inverter group and the selectors on both sides thereof; The output end of the at least two ring oscillators is coupled with the input end of the counter; the output end of the counter is connected with the logic control unit; and the sampling circuit obtains sampling electrical signals from the at least two ring oscillators, so as to output random numbers according to the sampling electrical signals.

2. The reconfigurable random number generator of claim 1, wherein, The logic control unit obtains the difference of the oscillation frequencies of the at least two ring oscillators through the counter, for sending the reconstruction signal to each selector in the ring oscillator, so as to complete the adjustment of the selected inverter in the inverter group, and complete the adjustment of the selected inverter in the inverter group, so as to complete the adjustment of the selected inverter in the inverter group, so as to complete the adjustment of the selected inverter in the inverter group, so as to complete the adjustment of the selected inverter in the inverter group, so as to complete the adjustment of the selected inverter in the inverter group, so as to complete the adjustment of the selected inverter in the inverter group, so as to complete the adjustment of the selected inverter in the inverter group, so as to complete the adjustment of the selected inverter in the inverter group, so as to complete the adjustment of the selected inverter in the inverter group, so as to complete the adjustment of the selected inverter in the inverter group, so as to complete the adjustment of the selected inverter in the inverter group, so as to complete the adjustment of the selected inverter in the inverter group, so as to complete the adjustment of the selected inverter in the inverter group, so as to complete the adjustment of the selected inverter in the inverter group, so as to complete the adjustment of the selected inverter in the inverter group, so as to complete the adjustment of the selected inverter in the inverter group, so as to complete the adjustment of the selected inverter in the inverter group, so as to complete the adjustment of the selected inverter in the inverter group, so as to complete the adjustment of the selected inverter in the inverter group, so as to complete the adjustment of the selected inverter in the inverter group, so as to complete the adjustment of the selected inverter in the inverter group, so as to complete the adjustment of the selected inverter in the inverter group, so as to complete the adjustment of the selected inverter in the inverter group, so as to complete the adjustment of the selected inverter in the inverter group, so as to complete the adjustment of the selected inverter in the inverter group, so as to complete the adjustment of the selected inverter in the inverter group, so as to complete the adjustment of the selected inverter in the inverter group, so as to complete the adjustment of the selected inverter in the inverter group, so as to complete the adjustment of the selected inverter in the inverter group, so as to complete the adjustment of the selected inverter in the inverter group, so as to complete the adjustment of the selected inverter in the inverter group, so as to complete the adjustment of the selected inverter in the inverter group, so as to complete the adjustment of the selected inverter in the inverter group, so as to complete the adjustment of the selected inverter in the inverter group, so as to complete the adjustment of the selected inverter in the inverter group, so as to complete the adjustment of the selected inverter in the inverter group, so as to complete the adjustment of the selected inverter in the inverter group, so as to complete the adjustment of the selected inverter in the inverter group, so as to complete the adjustment of the selected inverter in the inverter group, so as to complete the adjustment of the selected inverter in the inverter group, so as to complete the adjustment of the selected inverter in the inverter group, so as to complete the adjustment of the selected inverter in the inverter group, so as to complete the adjustment of the selected inverter in the inverter group, so as to complete the adjustment of the selected inverter in the inverter group, so as to complete the adjustment of the selected inverter in the inverter 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group, so as to complete the adjustment of the selected inverter in the inverter group, so as to complete the adjustment of the selected inverter in the inverter group, so as to complete the adjustment of the selected inverter in the inverter group, so as to complete the adjustment of the selected inverter in the inverter group, so as to complete the adjustment of the selected inverter in the inverter group, so as to complete the adjustment of the selected inverter in the inverter group, so as to complete the adjustment of the selected inverter in the inverter group, so as to complete the adjustment of the selected inverter in the inverter group, so as to complete the adjustment of the selected inverter in the inverter group, so as to complete the adjustment of the selected inverter in the inverter group, so as to complete the adjustment of the selected inverter in the inverter group, so as to complete the adjustment of the selected inverter in the inverter group, so as to complete the adjustment of the selected inverter in the inverter group, so as to complete the adjustment of the selected inverter in the inverter group, so as to complete the adjustment of the selected inverter in the inverter group, so as to complete the adjustment of the selected inverter in the inverter group, so as to complete the adjustment of the selected inverter in the inverter group, so as to complete the adjustment of the selected inverter in the inverter group, so as to complete the adjustment of the selected inverter in the inverter group, so as to complete the adjustment of the selected inverter in the inverter group, so as to complete the adjustment of the selected inverter in the inverter group, so as to complete the adjustment of the selected inverter in the inverter group, so as to complete the adjustment of the selected inverter in the inverter group, so as to complete the adjustment of the selected inverter 3. The reconfigurable random number generator of claim 1, wherein, ​ ​ ​ 4. The reconfigurable random number generator of claim 1, wherein, ​ ​ 5. The reconfigurable random number generator of claim 4, wherein, ​ ​ ​ ​ 6. The reconfigurable random number generator according to any of claims 1-3, characterized in that, ​ ​ ​ The m normal inverters are cascaded, and the n inverter groups are cascaded; the m normal inverters after cascading are cascaded with the n inverter groups after cascading; or, The m normal inverters and the n inverter groups are cascaded in a mutually spaced manner, wherein the mutual spacing distance is determined according to the proportional relationship between the m normal inverters and the n inverter groups; or, The m normal inverters and the n inverter groups are cascaded in a random order.

7. The reconfigurable random number generator of claim 6, wherein, The random number generator comprises a random number source formed by a third ring oscillator and a fourth ring oscillator, and the sampling circuit comprises p D flip-flops, wherein n≤p≤m+n, and specifically: The output end of the specified inverter and / or inverter group in the third ring oscillator is further connected to the signal input port of a D flip-flop; The output end of the specified inverter group and / or inverter in the fourth ring oscillator is further connected to the clock input port of a D flip-flop; The electrical signals at the output ports of the n D flip-flops in the sampling circuit form a random number.

8. The reconfigurable random number generator of claim 1, wherein, When the random number generator works in a physically unclonable function mode, the logic control unit is further configured to obtain an excitation signal of one or more ring oscillators, and specifically: The logic control unit converts the excitation signal into a reconstruction signal of the corresponding one or more ring oscillators; The logic control unit obtains the output oscillation frequencies of the one or more ring oscillators triggered by the excitation signal, and calculates a physically unclonable output result according to the corresponding oscillation frequencies or the difference between the oscillation frequencies.

9. The reconfigurable random number generator of claim 8, wherein, The excitation signal of the ring oscillator is specifically the data source for calculating the physically unclonable output result, which is output by the specified inverter group in the ring oscillator.

10. The reconfigurable random number generator according to claim 8 or 9, characterized in that, The calculation of the physically unclonable output result according to the corresponding oscillation frequencies or the difference between the oscillation frequencies specifically includes: If the difference between the oscillation frequencies is greater than 0, 0 is output, and if the difference between the oscillation frequencies is less than 0, 1 is output; or If the difference between the oscillation frequencies is greater than 0, 1 is output, and if the difference between the oscillation frequencies is less than 0, 0 is output; or The specified length parameter value after the decimal point of the oscillation frequency is taken as an integer value output.

11. The reconfigurable random number generator of claim 1, wherein, The inverter is specifically one or more of a TTL NAND gate inverter, a CMOS inverter, an HPM disturbance effect inverter, or a starvation type inverter.

12. The reconfigurable random number generator of claim 1, wherein, When the at least two ring oscillators include a first ring oscillator, a second ring oscillator, and a third ring oscillator, The first ring oscillator and the second ring oscillator form a random number source, and the second ring oscillator and the third ring oscillator form a random number source; or The first ring oscillator and the third ring oscillator form a random number source, and the second ring oscillator and the third ring oscillator form a random number source; or The first ring oscillator and the second ring oscillator form a random number source, and the first ring oscillator and the third ring oscillator form a random number source.

13. A method of implementing a reconfigurable random number generator, characterized by, The method for using the reconfigurable random number generator according to any one of claims 1-12 comprises: The logic control unit acquires the oscillation frequencies of the at least two ring oscillators through the counter; The logic control unit determines the first ring oscillator and the second ring oscillator as a random number source, and analyzes the difference between the oscillation frequencies of the first ring oscillator and the second ring oscillator; If the oscillation frequency is greater than a preset threshold, the logic control unit sends a reconstruction signal to the first ring oscillator and / or the second ring oscillator, so as to control the selector in the first ring oscillator and the second ring oscillator, and complete the on operation of the designated inverter signal channel in the corresponding inverter group; Through one or more times of adjustment of the reconstruction signal by the logic control unit, the difference between the oscillation frequencies of the first ring oscillator and the second ring oscillator is less than the preset threshold.

14. The method of claim 13, wherein, The adjustment of the reconstruction signal by the logic control unit one or more times, so that the difference between the oscillation frequencies of the first ring oscillator and the second ring oscillator is less than the preset threshold, specifically includes: Through multiple adjustments of the reconstruction signal, the selection control of the inverter for the on operation of the electrical signal in each inverter group is completed one by one. If the adjustment of the reconstruction signal can reduce the difference between the oscillation frequencies of the first ring oscillator and the second ring oscillator, the reconstruction signal at this time is retained as the current state reconstruction signal, and the oscillation frequency difference corresponding to the current state reconstruction signal is used to compare with the oscillation frequency difference under the reconstruction signal after the next adjustment, and the reconstruction signal with the smaller oscillation frequency difference is updated as the current state reconstruction signal. Until the difference between the oscillation frequencies of the first ring oscillator and the second ring oscillator is less than the preset threshold, the iteration process is stopped.

15. The method of claim 14, wherein, If a third ring oscillator is further included, and another random number source is formed by the first ring oscillator and the third ring oscillator, the method further includes: After the one or more times of adjustment of the reconstruction signal by the logic control unit, so that the difference between the oscillation frequencies of the first ring oscillator and the second ring oscillator is less than the preset threshold, the reconstruction signal of the third ring oscillator is further adjusted by the logic control unit one or more times, so that the difference between the oscillation frequencies of the first ring oscillator and the third ring oscillator is less than the preset threshold.

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