Circuit and method for generating a temperature-stable clock using a common oscillator

Abstract

The present disclosure provides a circuit for generating a temperature stable clock, the circuit comprising a first crystal oscillator, a second crystal oscillator, an input for a reference clock source, a clock output, a first phase acquisition circuit coupled to the first crystal oscillator and the second crystal oscillator, a second phase acquisition circuit coupled to the input for the reference clock source and the second crystal oscillator, a first DPLL coupled to the first phase acquisition circuit, a crystal oscillator variation estimator coupled to the first DPLL, a second DPLL coupled to the second phase acquisition circuit and comprising: a phase-frequency detector having an input coupled to the second phase acquisition circuit; a loop filter; a frequency subtractor having an input coupled to the loop filter and an input coupled to the crystal oscillator variation estimator; and a DCO coupled to the frequency subtractor and driving the input of the phase-frequency detector.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to U.S. Provisional Patent Application Serial No. 62 / 959,074, filed January 9, 2020, and U.S. Non-Provisional Patent Application Serial No. 16 / 816,113, filed March 11, 2020, the full contents of each of which are incorporated herein by reference. Background Technology

[0003] This invention relates to clock generation. More specifically, this invention relates to circuits and methods for generating temperature-stable clocks using a common oscillator.

[0004] Many circuit applications require clock circuits with stable frequency and low jitter characteristics. Currently, the cost of temperature-compensated crystal oscillators (TCXOs) and / or oven-controlled crystal oscillators (OCXOs) required to meet such requirements is very high. Therefore, it is advantageous to provide solutions that allow TCXOs or OCXOs to be replaced with ordinary crystal oscillators (XOs). Summary of the Invention

[0005] According to one aspect of the present invention, a circuit for generating a temperature-stable clock includes a first crystal oscillator, a second crystal oscillator, an input terminal for a reference clock source, a clock output terminal, a first phase acquisition circuit coupled to the output terminals of the first and second crystal oscillators, a second phase acquisition circuit coupled to the input terminal for the reference clock source and the output terminal of the second crystal oscillator, a first digital phase-locked loop (DPLL) coupled to the output terminal of the first phase acquisition circuit, a crystal oscillator change estimator coupled to the output terminal of the first DPLL, and a second crystal oscillator coupled to the second crystal oscillator. The second DPLL at the output of the phase acquisition circuit includes: a phase-frequency detector having a first input coupled to the output of the second phase acquisition circuit; a loop filter; a frequency subtractor having a first input coupled to the output of the loop filter and a second input coupled to the output of the crystal oscillator change estimator; and a digitally controlled oscillator (DCO) coupled to the output of the frequency subtractor, the output of the DCO being coupled to the second input of the phase-frequency detector and coupled to the clock output.

[0006] According to one aspect of the invention, the circuit further includes a synthesizer coupled to the output of the DCO and driving the clock output.

[0007] According to one aspect of the invention, the DCO is a software DCO.

[0008] According to one aspect of the invention, a first crystal oscillator and a second crystal oscillator are disposed in a single package.

[0009] According to one aspect of the invention, the crystal oscillator variation estimator includes a multiplier having an input coupled to the output of the first DPLL and a second input coupled to a memory storing polynomial coefficients of the first and second crystal oscillators generated during initial production and characterization, obtained by curve fitting of the frequency variation of the second crystal oscillator with temperature relative to the frequency difference between the first and second crystal oscillators.

[0010] According to one aspect of the invention, the memory is one of a non-volatile memory and a one-time programmable memory.

[0011] According to one aspect of the invention, a first crystal oscillator, a second crystal oscillator, and a memory are disposed in a single package.

[0012] According to one aspect of the invention, the crystal oscillator variation estimator includes a multiplier having an input coupled to the output of the first DPLL and a second input coupled to a memory storing polynomial coefficients of the first and second crystal oscillators generated during initial production and characterization, obtained by curve fitting of the frequency variation of the second crystal oscillator with temperature relative to the frequency difference between the first and second crystal oscillators.

[0013] According to one aspect of the invention, the first DPLL is a high-bandwidth DPLL, and the second DPLL is a low-bandwidth DPLL.

[0014] According to one aspect of the invention, the loop filter has one of first-order and second-order low-pass characteristics.

[0015] According to one aspect of the invention, a method for generating a temperature-stable clock includes: providing a first crystal oscillator and a second crystal oscillator; providing a memory storing temperature characterization polynomial coefficients of the first and second crystal oscillators, obtained by fitting a curve of the frequency change of the second crystal oscillator with respect to the frequency difference between the first and second crystal oscillators with varying temperatures; measuring a phase difference between the first and second crystal oscillators; phase-locking a high-bandwidth first digital phase-locked loop (DPLL) to the measured phase difference between the first and second crystal oscillators; estimating a frequency change of the second crystal oscillator in response to frequency information based on the measured phase difference and in response to the stored temperature characterization polynomial coefficients; providing a reference clock signal from a reference clock source; measuring the phase difference between the reference clock signal and the second crystal oscillator; phase-locking a second DPLL to the phase difference between the reference clock signal and the second crystal oscillator; adjusting the frequency of the second DPLL by the estimated frequency change of the second crystal oscillator; and providing an output from the second DPLL.

[0016] According to one aspect of the invention, the method further includes providing the output of the second DPLL to a frequency synthesizer.

[0017] According to one aspect of the invention, providing a first crystal oscillator and a second crystal oscillator includes providing the first crystal oscillator and the second crystal oscillator in the same package.

[0018] According to one aspect of the invention, measuring the phase difference between a first crystal oscillator and a second crystal oscillator includes measuring the phase difference between the first crystal oscillator and the second crystal oscillator in a first phase acquisition circuit.

[0019] According to one aspect of the invention, measuring the phase difference between a reference clock signal and a second crystal oscillator includes measuring the phase difference between the reference clock signal and the second crystal oscillator in a second phase acquisition circuit.

[0020] According to one aspect of the invention, adjusting the frequency of the second DPLL by means of the estimated frequency variation with temperature of the second crystal oscillator includes adjusting the frequency of the second DPLL using a frequency subtractor circuit.

[0021] According to one aspect of the invention, providing the output of the second DPLL includes providing the output of the second DPLL from a numerically controlled oscillator in the second DPLL.

[0022] According to one aspect of the invention, the method further includes providing the output of a numerically controlled oscillator to a synthesizer. Attached Figure Description

[0023] The invention will now be explained in more detail with reference to the embodiments and accompanying drawings, in which:

[0024] Figure 1 This is a block diagram of a circuit according to one aspect of the invention for generating a temperature-stable, low-jitter clock of any frequency using a common oscillator; and

[0025] Figure 2 This is a flowchart illustrating an illustrative method for generating a temperature-stable, low-jitter clock of any frequency using a common oscillator, according to one aspect of the invention. Detailed Implementation

[0026] Those skilled in the art will recognize that the following description is merely illustrative and not intended to be limiting in any way. Other embodiments will readily occur to those skilled in the art.

[0027] This invention allows the generation of temperature-stable clocks using ordinary oscillators that do not exhibit high frequency stability with temperature changes, while simultaneously maintaining low jitter performance. According to the invention, when using a first XO 14 and a second XO 16, each having a frequency stability of approximately 10 parts per million (ppm) to approximately 300 ppm, disposed in the same package, a frequency stability of approximately 300 parts per billion (ppb) with a temperature change of 0.2°C / minute over a temperature range of -40°C to 85°C can be achieved. For the purposes of this invention, a temperature-stable clock signal is a temperature-stable clock signal having a frequency stability of no more than approximately 400 ppb. According to the invention, when using a first XO 14 and a second XO 16 disposed in the same package, a jitter of approximately 150 femtoseconds (fs) RMS can be achieved, with each of the first XO and the second XO having a jitter of approximately 50 fs to approximately 150 fs RMS. For the purposes of this invention, the low-jitter output clock signal from the clock generation circuit is a low-jitter output clock signal with a maximum value of approximately 250 fs RMS, and as disclosed herein, this low-jitter output clock signal is achieved when a synthesizer is used to generate the output clock.

[0028] To achieve this high stability with temperature variations, the present invention can be implemented as part of the synthesized firmware of a timing device and is capable of generating clocks of any frequency. The invention utilizes the unique characteristic that the frequency difference between two crystal oscillators (XOs) changes linearly with temperature to predict the temperature characteristics of one of the two oscillators as the temperature changes. Each crystal oscillator is first characterized with temperature variations, and then appropriate polynomial coefficients representing the characterization are stored for use in the invention. Specifically, the polynomial coefficients are obtained by curve fitting of the temperature-varying frequency variation of the second XO 16 relative to the temperature-varying frequency difference between the first XO 14 and the second XO 16. The frequency difference between the two oscillators is transferred to a relatively high bandwidth DPLL (on the order of approximately 20 Hz to approximately 100 Hz) and used in conjunction with the stored polynomial coefficients to replicate the temperature-varying frequency drift of the second XO 16, which serves as the master clock. The replicated temperature-varying frequency drift is used to compensate for the actual frequency drift with temperature variations. The master clock on line 28 is used to synthesize a clock to be programmed to output any frequency. Temperature variations in each of the two crystal oscillators (first XO 14 and second XO 16) cause variations in the frequency at the output of each of the two crystal oscillators. This invention predicts the temperature-based variation of the second XO 16, used as the master clock, based on the frequency difference between the two crystal oscillators, and accordingly corrects the output clock frequency, thereby minimizing the variation of the output clock frequency with temperature. Using ordinary XOs with jitter of approximately 50 fs RMS to approximately 150 fs RMS, as described herein, allows the synthesis of clock signals with jitter below approximately 150 fs RMS to approximately 250 fs RMS when the output clock is generated using a synthesizer.

[0029] One possible application of this invention is as a companion oscillator for network synchronization PLLs; however, the invention can be extended to replace standalone TCXOs or OCXOs. This invention uses a common, inexpensive XO crystal oscillator to replace expensive TCXOs or OCXOs, and provides faster startup times and consumes less power than TCXOs or OCXOs.

[0030] This invention can utilize a programmable system-on-chip (SoC) based PLL circuit to process ordinary oscillator signals and generate a temperature-stable clock.

[0031] First refer to Figure 1The block diagram illustrates a circuit 10 according to one aspect of the invention for generating a temperature-stable, low-jitter clock using a common oscillator. The circuit 10 includes an oscillator module 12 comprising a first crystal oscillator (XO) 14 and a second XO 16 disposed in a single package. As will be understood by those skilled in the art, each of the first XO 14 and the second XO 16 typically takes the form of a module containing a crystal, along with a driver and decoupling capacitors (not explicitly shown). Each of the first XO 14 and the second XO 16 is capable of generating a clock with a specific frequency and a specified accuracy (approximately 10 ppm to 300 ppm). Frequency stability with temperature is an important property of oscillators used as clock sources for synthesizers generating high-temperature stable clocks, and common crystals do not exhibit extremely high frequency stability with temperature (typically several hundred ppm in the following industrial temperature range: -40°C to 85°C). Temperature-controlled XO (TCXO) and isothermal XO (OCXO) exhibit improved stability with temperature variations. TCXOs typically include a temperature sensor and control circuitry that corrects for frequency changes due to temperature variations, while OCXOs incorporate an oven to maintain a constant XO temperature. This invention allows the use of crystal oscillators XO14 and XO16 while simultaneously providing temperature-dependent output clock frequency stability, which is typically required with TCXOs or OCXOs.

[0032] The clock generation circuit 18 includes a first phase acquisition module 20 and a second phase acquisition module 22. The first phase acquisition module 20 receives the output of the first XO 14 on line 24, and the second phase acquisition module 22 receives a reference clock signal from a reference clock source 26 (shown in dashed lines because it is external to the clock generation circuit 18 and provided by the user). The input reference clock source should have a frequency within the telecommunications range (i.e., between approximately 0.5 Hz and 1 GHz) and may be derived from a primary reference source (e.g., an atomic clock or GPS). When the reference clock source 26 is present, the output of the clock generation circuit 18 is frequency- and phase-locked relative to the reference clock source 26.

[0033] According to one aspect of the invention, the master clock signal output from the second XO 16 on line 28 serves as the basis for comparison in the first phase acquisition module 20 and the second phase acquisition module 22. The first phase acquisition module 20 measures the phase difference between the output of the first XO 14 and the master clock on line 28, and outputs information about the measured phase difference. The second phase acquisition module 22 measures the phase difference between the output of the input reference clock source and the master clock on line 28, and outputs information about the measured phase difference. Circuitry for providing this functionality is known in the art. According to the invention, even if the input clock signal and the master clock signal do not have the same nominal frequency, the first phase acquisition module 20 and the second phase acquisition module 22 are capable of comparing the input clock signal with the master clock signal on line 28. For example, the master clock signal on line 28 may be 20 MHz, and the input reference clock signal may be at 19.44 MHz, 1.544 MHz, or any frequency.

[0034] The master clock 28 provides nominal frequency information to the first digital phase-locked loop (DPLL) 30. The output of the first phase acquisition module 20 is presented to the first DPLL 30 to lock the output to the phase difference generated by the first phase acquisition circuit 20. The first DPLL 30 has a low-pass transfer function with relatively high bandwidth (angular frequency in the range of approximately 20 Hz to approximately 100 Hz). The output of the first DPLL 30 is frequency information representing the frequency difference between the first XO 14 and the second XO 16. The master clock 28 also provides nominal frequency information to the second DPLL 32. The output of the second phase acquisition module 22 is presented to the second DPLL 32 to lock the output to the phase difference generated by the second phase acquisition circuit 22. The second DPLL 32 has a low-pass transfer function with relatively low bandwidth (angular frequency in the range of approximately 0.001 Hz to approximately 0.3 Hz).

[0035] Frequency information representing the frequency difference between the first XO 14 and the second XO 16 at the output of the first DPLL 30 is presented to the XO change estimator 34. This XO change estimator 34 is a module that estimates the frequency change of the master clock signal output from the second XO 16 on line 28 and provides the estimated frequency change information to the second DPLL 32 to correct the output frequency of the second DPLL 32, thereby eliminating the frequency change of the master clock signal output from the second XO 16 on line 28 caused by temperature variations.

[0036] The input to the XO variation estimator 34 is frequency information representing the frequency difference between the first XO 14 and the second XO 16, provided by the phase acquisition module 20 and transmitted through the first DPLL 30. The high bandwidth of the first DPLL 30 provides a fast response to frequency difference changes due to sudden temperature variations. The XO variation estimator 34 includes a multiplier 36 that multiplies the frequency difference information from the first DPLL 30 with polynomial coefficients generated during the initial production and characterization of the package including XO 14 and 16 and stored in memory 38. In some embodiments of the invention, memory 38 may be non-volatile memory (NVM) or one-time programmable (OTP) memory, and in some embodiments of the invention, memory 38 may be included in the package 12 including the first XO 14 and the second XO 16. The polynomial coefficients are obtained by curve fitting of the temperature-varying frequency change of the second XO 16 relative to the temperature-varying frequency difference between the first XO 14 and the second XO 16. In an embodiment of the present invention using the Microchip Vectron PX-502-0002-24M57624.576MHz dual XO package 12, the frequency difference between the two XOs occurs linearly with temperature.

[0037] The second DPLL 32 includes a phase detector (PFD) 40 (implemented as, for example, a subtractor), a loop filter 42, a frequency subtractor 46, and a digitally controlled oscillator (DCO) 44 (which in some embodiments may be a software DCO (SDCO)). In the presence of a reference clock signal, the phase detector 40, together with the loop filter 42, converts the phase difference between the reference clock source 26 and the master clock 28 into frequency information related to the frequency difference between the reference clock source 26 and the master clock 28. The second DPLL 32 has the capability to subtract the frequency difference between the loop filter 42 and the XO change estimator 34 by the frequency subtractor 46. The output of the loop filter 42 is fed to a first input of the frequency subtractor 46, and the output of the XO change estimator 34 is fed to a second input of the frequency subtractor 46. By subtracting the output of the XO change estimator 34 from the output of the loop filter 42, any changes in the frequency of the master clock signal on the master clock signal output line 28 due to temperature variations are compensated. When reference clock 26 is present, the output of clock generation circuit 18 follows the reference clock, and the compensation provided by frequency subtractor 46 minimizes any drift of output clock 48 caused by variations in the master clock due to temperature changes; that is, it minimizes the drift generation of the output of clock generation circuit 18. When the reference clock signal is no longer present, the output of loop filter 42 depends only on master clock 28 and will have all the frequency variations exhibited by master clock 28 with temperature changes. These frequency variations are compensated in frequency subtractor 46 to improve the temperature stability of clock generation circuit 18.

[0038] Loop filter 42 is the module that primarily determines the transfer function—or loop bandwidth—of the second DPLL 32 (the transfer function of the second DPLL 32 is also affected by other modules such as DCO 44, but these modules are considered immutable and are generally ignored for the purpose of specifying the loop bandwidth). Loop filter 42 is preferably a low-pass filter with a 3dB attenuation point at the specified bandwidth frequency. It typically has first-order or second-order low-pass characteristics.

[0039] In some implementations, DCO 44 can be implemented in software. As is well known in the art, DCO 44 typically consists of an accumulator with a frequency control word (FCW) from a programmable register inside the DCO as its output. The FCW determines the nominal frequency of the clock at the DCO output. In addition to the FCW, DCO 44 includes another control input for fine-tuning the DCO output frequency, and the input is... Figure 1The output of DCO 44 is shown to be driven by the output of frequency subtractor 46. Therefore, when the optional synthesizer 52 is not used, the output of DCO 44 is a temperature-compensated output clock signal, which can be used as the output 48 of clock generation circuit 18 via dashed connection 50.

[0040] The output of DCO 44 may optionally be presented to synthesizer 52, shown by dashed lines. Synthesizer 52 is a module that synthesizes an output clock signal at a desired frequency from the master clock on line 28 on clock output line 48. The desired output clock signal is phase- and frequency-locked to the output of DCO 44. Essentially, synthesizer 52 performs a low-jitter frequency conversion between the master clock signal on line 28 and the desired output frequency, thereby allowing the generation of any frequency with low phase noise (low jitter) within the telecommunications range (e.g., between about 0.5 Hz and about 1 GHz) at its output on clock output line 48. The phrase “any frequency” as used herein should be interpreted as meaning any frequency within the telecommunications range (e.g., between about 0.5 Hz and about 1 GHz).

[0041] In embodiments where DCO 44 is configured as a hardware element, the present invention provides a frequency output from DCO 44 or optional synthesizer 52 using a common oscillator that does not have high frequency stability with temperature variations, which is highly frequency stable with temperature variations. When DCO 44 is implemented as a software DCO (SDCO), the present invention provides a clock output from synthesizer 52.

[0042] The master clock signal from the second XO 16 on line 28 is connected to and drives each internal block in circuit 18. When used in the circuit, the master clock signal on line 28 is connected to synthesizer 52. Output clock 48 is always dependent on the master clock because it is synthesized directly from the master clock on line 28 using hardware form of synthesizer 52 or DCO44. In an embodiment where output clock 50 is driven by synthesizer 52, fine frequency control of synthesizer 52, relating to the phase and frequency difference between reference clock source 26 and master clock 28, is performed by the output of DCO 44. When reference clock source 26 is no longer present, the fine frequency control of synthesizer 52 performed by DCO44 relates to frequency variations in master clock 28 caused by temperature fluctuations compensated by XO variation estimator 34. In embodiments of the invention that do not employ synthesizer 52, the invention provides high-frequency stability as disclosed herein as per temperature variations, but does not provide sufficiently low jitter required for most telecommunications applications. The use of conventional synthesizers will provide low jitter as disclosed herein.

[0043] Once the DPLL 32 is locked to the reference clock source 26 using the second phase acquisition circuit 22, the output clock 48 will have the stability inherited from the input reference clock source 26. Using this invention, temperature variations of the master clock signal on line 28 of the second XO 16 are eliminated, thereby minimizing drift generation of the output clock 48. In the absence of the reference clock source 26, the stability of the output on the clock output line 48 is determined solely by the stability of the master clock signal on line 28. Using this invention, temperature variations of the master clock signal on line 28 of the second XO 16 are eliminated, thus allowing the output clock 48 to have good stability even in the absence of the reference clock source 26.

[0044] Now for reference Figure 2 The flowchart illustrates an exemplary method 60 for generating a temperature-stable, low-jitter clock using a common oscillator according to one aspect of the invention. The method begins at reference numeral 62.

[0045] At reference numeral 64, a first crystal oscillator and a second crystal oscillator are provided. In some embodiments of the invention, the first crystal oscillator and the second crystal oscillator may be disposed together in the same package.

[0046] At reference numeral 66, a memory (e.g., in the same package as the first and second crystal oscillators) is provided, which stores temperature characterization polynomial coefficients of the first and second crystal oscillators generated during initial production and characterization, obtained by fitting a curve of the frequency change of the second crystal oscillator with respect to the frequency difference between the first and second crystal oscillators with temperature variation.

[0047] At reference numeral 68, for example, the phase difference between the first crystal oscillator and the second crystal oscillator is measured in the first phase acquisition circuit. At reference numeral 70, a high-bandwidth first digital phase-locked loop (DPLL) is phase-locked to the measured phase difference between the first crystal oscillator and the second crystal oscillator.

[0048] At reference numeral 72 in the figure, the frequency change of the second crystal oscillator is estimated in response to frequency difference information representing the frequency difference between the first crystal oscillator and the second crystal oscillator, and in response to the temperature characteristics of the frequency of the second crystal oscillator relative to the frequency difference between the first crystal oscillator and the second crystal oscillator as the temperature changes.

[0049] At reference numeral 74 in the attached figure, a reference clock signal is provided to the clock generation circuit.

[0050] At reference numeral 76, for example, the phase difference between the reference clock signal and the second crystal oscillator is measured in the second phase acquisition circuit.

[0051] At reference numeral 78, the second DPLL is phase-locked to the phase difference between the reference clock signal and the second crystal oscillator. At reference numeral 80, the frequency of the second DPLL is adjusted (e.g., using a frequency subtractor) by the estimated temperature-dependent frequency variation of the second crystal oscillator (obtained, for example, by an XO variation estimator). At reference numeral 82, the output of the second DPLL is provided as a clock output.

[0052] At reference numeral 84, the output of the second DPLL can optionally be provided to the frequency synthesizer to provide the ability to generate a low-jitter clock output with the desired frequency. The method ends at reference numeral 86.

[0053] Because the clock generation circuit can generate a clock with any frequency within the telecommunications range based on the master clock signal on line 28, this invention allows for the generation of temperature-stable clocks of any frequency. This invention provides clock stability comparable to that achieved using a temperature-compensated crystal oscillator as the master clock of the same clock generation circuit. In contrast to using significantly more expensive TCXOs or oven-controlled crystal oscillators (OCXOs), this invention provides a cost-effective solution for generating temperature-stable clocks of any frequency using two inexpensive oscillators. Furthermore, prior art applications requiring both high frequency stability and good jitter necessitate the use of very expensive low-jitter TCXOs or OCXOs. The solution provided by this invention satisfies both low jitter and temperature stability requirements using two common oscillators, which is significantly cheaper than the two aforementioned prior art solutions. This invention can be further extended to be used with any two oscillating devices where the frequency difference between the two oscillating devices has a fixed and definite relationship with the temperature change if the temperature change can be measured and characterized to produce appropriate polynomial coefficients. Such oscillating devices can be, but are not limited to, microelectromechanical systems (MEMS).

[0054] This invention can be employed in frequency synthesis firmware, using an additional PLL (first DPLL 30) to correct for frequency variations due to temperature. Then, existing hardware (first phase acquisition circuit 20 and second phase acquisition circuit 22) is used in the clock generation circuit to measure the frequency difference between the two crystal oscillators, and this frequency difference is then passed to the first DPLL 30, which performs compensation for the frequency variation caused by temperature-induced changes in the master clock frequency. The polynomial coefficients used to replicate one of the oscillator temperature variations relative to the frequency difference between the two oscillators can be stored in a small memory (OTP, EEPROM, or Flash) during oscillator characterization.

[0055] This invention allows for packaging using groupings of different components. Two crystal oscillators (or resonators) can be packaged together with a driver and a small memory in a single package. The master clock signal on line 28 of the second XO 16 of the dual oscillator (dual XO) device is fed to the oscillator input of synthesizer 52, and the output of the first XO 14 on line 24 is fed to one of the inputs of the first phase acquisition circuit 20. This solution requires relatively simple dual XO temperature characterization to obtain the desired polynomial coefficients.

[0056] In another variation, multiple dies of the clock generation circuit (including non-volatile memory), along with the resonator and passive components, can be housed in a single package. The polynomial coefficients can be stored in non-volatile memory used for other processor code storage. This solution is compact but presents a challenge in characterizing the oscillator at multiple temperature points due to the high cost of test equipment required for testing complex packages, which includes clock generation circuitry with multiple dies employing a larger number of I / O pins compared to test equipment for XO TCXOs or OCXOs with 4 to 6 I / O pins. More I / O pins can be mounted on a single test board for testing.

[0057] In another variation, a pre-packaged and characterized dual XO containing a small memory for coefficients is packaged together with a clock generation circuit die in a single package. This is a compact solution that requires a simple characterization procedure for the crystal oscillator, but the packaging complexity is increased because the pre-packaged dual XO is not small enough to be easily fitted into another package.

[0058] While embodiments and applications of the invention have been shown and described, it will be apparent to those skilled in the art that further modifications can be made without departing from the inventive concept herein. Therefore, the invention is not limited except in the spirit of the appended claims.

Claims

1. A circuit for generating a temperature-stable clock, the circuit comprising: First crystal oscillator; Second crystal oscillator; Input terminal for reference clock source; Clock output terminal; A first phase acquisition circuit is coupled to the output terminal of the first crystal oscillator and the output terminal of the second crystal oscillator. A second phase acquisition circuit is coupled to the input terminal of the reference clock source and the output terminal of the second crystal oscillator; The first digital phase-locked loop (DPLL) is coupled to the output of the first phase acquisition circuit. A crystal oscillator variation estimator is coupled to the output of the first DPLL and acquires the temperature characterization polynomial coefficients. as well as A second DPLL, coupled to the output of the second phase acquisition circuit, the second DPLL comprising: A phase-frequency detector having a first input terminal coupled to the output terminal of the second phase acquisition circuit; Loop filter; A frequency subtractor having a first input coupled to the output of the loop filter and a second input coupled to the output of the crystal oscillator change estimator; and A digitally controlled oscillator (DCO) is coupled to the output of the frequency subtractor. The output of the DCO is coupled to the second input of the phase-frequency detector and to the clock output.

2. The circuit according to claim 1, further comprising a synthesizer coupled to the output terminal of the DCO and driving the clock output terminal.

3. The circuit according to claim 1, wherein the DCO is a software DCO.

4. The circuit of claim 1, wherein the first crystal oscillator and the second crystal oscillator are disposed in a single package.

5. The circuit of claim 1, wherein the crystal oscillator variation estimator includes a multiplier having an input coupled to the output of the first DPLL and a second input coupled to a memory storing polynomial coefficients of the first and second crystal oscillators generated during initial production and characterization, obtained by curve fitting of the frequency variation of the second crystal oscillator with temperature relative to the frequency difference between the first and second crystal oscillators.

6. The circuit of claim 5, wherein the memory is one of a non-volatile memory and a one-time programmable memory.

7. The circuit of claim 5, wherein the first crystal oscillator, the second crystal oscillator, and the memory are disposed in a single package.

8. The circuit of claim 1, wherein the first DPLL is a high-bandwidth DPLL and the second DPLL is a low-bandwidth DPLL.

9. The circuit according to claim 1, wherein the loop filter has one of a first-order and a second-order low-pass characteristic.

10. A method for generating a temperature-stable clock, the method comprising: Provide a first crystal oscillator and a second crystal oscillator; A memory is provided that stores temperature characterization polynomial coefficients of the first and second crystal oscillators generated during the initial production and characterization of the first and second crystal oscillators, obtained by fitting a curve of the frequency change of the second crystal oscillator with respect to the frequency difference between the first and second crystal oscillators with respect to temperature. Measure the phase difference between the first crystal oscillator and the second crystal oscillator; The high-bandwidth first digital phase-locked loop (DPLL) is phase-locked to the measured phase difference between the first crystal oscillator and the second crystal oscillator; The frequency change of the second crystal oscillator is estimated in response to frequency information based on the measured phase difference and in response to the stored temperature characterization polynomial coefficients. A reference clock signal is provided from a reference clock source; Measure the phase difference between the reference clock signal and the second crystal oscillator; The second DPLL is phase-locked to the phase difference between the reference clock signal and the second crystal oscillator; The frequency of the second DPLL is adjusted by the estimated frequency change of the second crystal oscillator; and Provides output from the second DPLL.

11. The method of claim 10, further comprising providing the output of the second DPLL to a frequency synthesizer.

12. The method of claim 10, wherein providing the first crystal oscillator and the second crystal oscillator comprises providing the first crystal oscillator and the second crystal oscillator in the same package.

13. The method of claim 10, wherein measuring the phase difference between the first crystal oscillator and the second crystal oscillator comprises measuring the phase difference between the first crystal oscillator and the second crystal oscillator in a first phase acquisition circuit.

14. The method of claim 10, wherein measuring the phase difference between the reference clock signal and the second crystal oscillator comprises measuring the phase difference between the reference clock signal and the second crystal oscillator in a second phase acquisition circuit.

15. The method of claim 10, wherein adjusting the frequency of the second DPLL by means of a frequency variation with temperature estimated by the second crystal oscillator comprises adjusting the frequency of the second DPLL using a frequency subtractor circuit.

16. The method of claim 10, wherein providing the output of the second DPLL comprises providing the output of the second DPLL from a numerically controlled oscillator in the second DPLL.

17. The method of claim 16, further comprising providing the output of the numerically controlled oscillator to a synthesizer.

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