A heat sink design method for chip passive heat dissipation based on three-dimensional topology optimization

Abstract

The invention proposes a heat sink design method for chip passive heat dissipation based on three-dimensional topology optimization, comprising the following steps: 1. selecting a design domain of a heat sink according to the geometric size of a chip, a layout on a PCB board, and the distribution of a heat source Q; 2. establishing a geometric model and a mathematical model of three-dimensional topology optimization; 3. selecting an optimization solver to solve the mathematical model of three-dimensional topology optimization, and obtaining an optimized three-dimensional topological structure of a chip heat sink; 4. filtering and projecting the three-dimensional topological structure of the chip heat sink obtained by optimization, establishing a topological boundary, and establishing an optimized three-dimensional geometric model of the chip heat sink; 5. performing mesh repair according to a geometric mesh model of a three-dimensional topology optimization heat sink result; 6. using finite element software to solve a maximum temperature and a temperature gradient cloud map when the chip works to a steady state; 7. judging whether the heat sink meets the heat dissipation requirements according to the maximum temperature of the chip, and adopting this solution if it meets the requirements; otherwise, modifying the upper and lower dimensions of the heat sink design domain and the filling ratio of the thermal conductive material in the design domain, and repeating steps 3-7 until the requirements are met.

Description

Technical Field

[0001] The invention relates to a heat sink design method for passive heat dissipation of a chip based on three-dimensional topology optimization, and belongs to the technical field of electronic equipment thermal design. Background Art

[0002] In recent years, the miniaturization and increasing functionality of electronic devices have led to an increase in overall power consumption. The increase in power consumption will inevitably lead to an increase in the demand for device heat dissipation, which poses a more stringent challenge to the structural design of thermal management devices. The optimized design of the heat dissipation device geometry and the heat dissipation device with better performance have always been the goals pursued by academia and industry.

[0003] Topology optimization is a mathematical method that optimizes material distribution within a given design domain based on load conditions, constraints and performance indicators. Topology optimization design can more efficiently utilize the design space of the heat sink, and can even design a heat sink with close to optimal heat dissipation performance under given boundary conditions. Topology optimization is a systematic and universal method with the highest degree of design freedom. In actual operation, the difficulty lies mainly in the large amount of calculation workload. Especially for topology optimization of three-dimensional space, or considering convection heat transfer, the calculation time may be very lengthy. Therefore, it is usually necessary to limit the topology optimization process, such as only considering the case of heat conduction, to reduce the difficulty of optimization. Summary of the invention

[0004] The purpose of the present invention is to provide a heat sink design method for chip passive heat dissipation based on three-dimensional topology optimization, which reduces the calculation amount of topology optimization design, and at the same time, the design optimization of the design domain improves the overall heat dissipation effect of the heat sink.

[0005] The present invention provides a heat sink design method for chip passive heat dissipation based on three-dimensional topology optimization, the method comprising the following steps:

[0006] Step 1: Select the design domain of the heat sink based on the chip's geometric dimensions, PCB layout, and the distribution of heat source Q;

[0007] Step 2: According to the highest filling ratio of the thermal conductive material in the design domain in step 1, the heat generation power of the chip and other parameters, a geometric model and a mathematical model of three-dimensional topology optimization are established;

[0008] Step 3: According to the mathematical model of the three-dimensional topology optimization in step 2, an optimization solver is selected to solve the problem and obtain the optimized three-dimensional topology structure of the chip heat sink;

[0009] Step 4: According to the three-dimensional topological structure of the chip heat sink optimized in step 3, filtering and projection processing are performed on it, the topological boundary is established, and the three-dimensional geometric model of the optimized chip heat sink is established;

[0010] Step 5: According to the geometric mesh model of the three-dimensional topology optimization heat sink result in step 4, perform mesh repair so that it can be used for finite element software simulation analysis;

[0011] Step 6: Use finite element software to solve the maximum temperature and temperature gradient cloud map when the chip works to a steady state, that is, to perform heat transfer analysis on the heat sink;

[0012] Step 7: Based on the maximum temperature of the chip, determine whether the heat sink meets the heat dissipation requirements. If so, adopt this solution; otherwise, modify the upper and lower dimensions of the heat sink design domain, the filling ratio of the thermal conductive material in the design domain, and repeat steps 3 to 7 until the requirements are met.

[0013] Further technical solutions of the present invention:

[0014] In the aforementioned heat sink design method for chip passive heat dissipation based on three-dimensional topology optimization, the chip heat source Q in step 1 is the heat generation power, and the distribution includes information such as the size, position, and material of the chip; the determination of the optimal design domain needs to refer to whether the last optimization result has achieved the optimization goal, and the shape of the design domain needs to satisfy that the radius of the bottom surface (in contact with the heat source) is more than 140% of the chip radius and the angle between the side and the bottom surface is less than 90°, so as to balance the heat dissipation balance between the heat transfer channel of the heat dissipation trunk and the fork.

[0015] In the aforementioned heat sink design method for passive heat dissipation of a chip based on three-dimensional topology optimization, the boundary conditions in step 2 include the maximum filling ratio γ of the thermal conductive material in the design domain, and the establishment of the three-dimensional topology optimization model includes the following steps:

[0016] Step 2-1: Since the shape of the heat sink cannot be determined before the topology optimization begins, the boundary between the heat sink and the air cannot be manually distinguished in the initial design domain. The thermal conductive material can be approximated as a fluid with high viscosity.

[0017] The heat conduction equation for this problem can be expressed as the fluid heat transfer equation:

[0018]

[0019] is the convective heat transfer term of air. In order to simplify the problem and save calculation cost, this design only considers the heat conduction of air and ignores the convection of air. Therefore, the air velocity u=0. is the heat conduction term, Q on the right side of the equation is the heat source term, Q P is the pressure work, Q vd is viscous dissipation. Since there is no air flow, Q P and Q vd Ignore;

[0020] Step 2-2: Using SIMP interpolation, the physical value in the design domain can be defined as:

[0021]

[0022] x is the location of the design variable, ρ s is the density of the thermally conductive material, ρ 0 is the air density, ρ is the unit slice material density, and p is the penalty factor, which penalizes the intermediate value of the unit slice material density. Here, 3 is taken, k s is the thermal conductivity of the thermally conductive material, k 0 is the thermal conductivity of air, C P_s is the specific heat of the thermally conductive material, C P_0 is the specific heat of air;

[0023] Step 2-3: Based on the topology optimization method, a topology optimization mathematical model is established. The problem to be solved is a standard nonlinear optimization problem:

[0024]

[0025] subject to 0≤∫ Ω ρ(x)dV≤γM;

[0026] x∈X={x 1 , x 2 , x 3 , …x N};

[0027] 0≤γ≤1;

[0028] The objective function in this optimization problem is to minimize the total temperature change of the design domain during the heating process of a constant heat source (chip), and M is the total mass when the design domain is filled with thermal conductive materials.

[0029] The aforementioned heat sink design method for chip passive heat dissipation based on three-dimensional topology optimization is characterized in that: the finite element solution value in step 3 includes:

[0030] Step 3-1: Perform finite element meshing based on the topology optimization mathematical model established in step 2;

[0031] Step 3-2: Select the MMA algorithm as the optimization algorithm, set the maximum number of iterations to 1000, and the optimization tolerance to 0.001.

[0032] The aforementioned heat sink design method for passive heat dissipation of chips based on three-dimensional topology optimization, filtering and projecting in step 4 to obtain a manufacturable model includes the following steps:

[0033] Step 4-1: Filter the result using the Helmholtz filter formula:

[0034]

[0035] θ c is the design variable before filtering, θ f is the design variable after filtering, R min is the filtering radius, and the filtering radius needs to be not less than the mesh size;

[0036] Step 4-2: There may be a large number of regions with intermediate values in the design variables after filtering, and a hyperbolic tangent projection needs to be used to reduce these regions without physical meaning:

[0037]

[0038] Step 4-3: According to the result output in Step 4-2, create a mesh model of the heat sink from the finite element software. Since the mesh of the heat sink obtained by topology optimization is prone to very small structures, resulting in problems such as excessive mesh inversion, too large difference in mesh size, and mesh folding, the mesh needs to be repaired.

[0039] For the aforementioned heat sink design method for chip passive heat dissipation based on three-dimensional topology optimization, in Step 5, the repair method includes: directly deleting the tiny mesh structures, deleting the folded parts in size, deleting the parts with network inversion, and repairing a flat mesh.

[0040] For the aforementioned heat sink design method for chip passive heat dissipation based on three-dimensional topology optimization, in Step 6, perform a heat transfer analysis on the heat sink, including the following steps:

[0041] Step 6-1: Re-import the repaired mesh into the finite element software, and set the air domain, heat source position, heating power, and materials of the heat sink and the heat source;

[0042] Step 6-2: Apply the remaining boundary conditions according to the actual situation, including the initial air velocity and the ambient temperature;

[0043] Step 6-3: Re-divide the mesh of the heat sink system to obtain a finite element model;

[0044] Step 6-4: Solve the finite element model to obtain the temperature field distribution and the sectional temperature gradient nephogram of the model.

[0045] For the aforementioned heat sink design method for chip passive heat dissipation based on three-dimensional topology optimization, calculate the highest value T of the chip temperature steady state in Step 6 - Step 7 max , the steady state temperature of the chip working is T, and determine whether the heat dissipation requirement is met: If T max < T, then the heat dissipation requirement is met; otherwise, modify the upper and lower dimensions of the heat sink design domain, the filling ratio of the heat conduction material in the design domain and other parameters, and repeat Step 3 - Step 7 until the requirements are met.

[0046] Compared with the prior art, the present invention adopts the above technical solution and has the following technical effects: 1. In view of the shortcomings of low design freedom, low efficiency and poor effect of traditional heat sink design and its optimization method, topology optimization design can more efficiently utilize the design space of the heat sink. Compared with other optimization methods such as shape optimization and parameter optimization, topology optimization is a systematic and universal method with the highest design freedom. Under given boundary conditions, a heat sink with close to optimal heat dissipation performance can even be designed. 2. Compared with two-dimensional topology optimization design, two-dimensional design methods use more approximations, and there is often a large room for improvement in actual production and manufacturing. The intuitive heat sink topology structure is directly obtained by the three-dimensional topology optimization method, which is more accurate and the upper limit of the optimization effect becomes higher. 3. Compared with traditional three-dimensional topology optimization design, this design method takes into account the optimization of the design domain, and improves the upper limit of the heat dissipation effect of the optimized heat sink without changing the total amount of thermal conductive material. At the same time, the air flow part with strong nonlinearity and large calculation amount but small impact on overall heat dissipation is not considered, so that the calculation resources required for heat sink design are greatly reduced, which not only makes the optimization result more accurate, but also helps to reduce costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 A flow chart of a heat sink for passive heat dissipation of a chip based on three-dimensional topology optimization of the present invention;

[0048] Figure 2 They are schematic diagrams of the three design domains of topology optimized heat sinks;

[0049] Figure 3 They are schematic diagrams of topology optimized heat sink geometry under three design domains;

[0050] Figure 4 These are the temperature gradient cloud maps of the topology optimized heat sink cross section under three design domains. DETAILED DESCRIPTION

[0051] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention is described in detail below with reference to the accompanying drawings and specific implementation examples.

[0052] like Figure 1 The present embodiment provides a heat sink design method for chip passive heat dissipation based on three-dimensional topology optimization, the method comprising the following steps:

[0053] Step 1: Select the design domain of the heat sink based on the chip's geometric dimensions, PCB layout, and the distribution of heat source Q;

[0054] The chip heat source Q in step 1 is the heat generation power, and the distribution includes information such as the chip size, position, and material. The determination of the optimal design domain needs to refer to whether the last optimization result has achieved the optimization goal. The shape of the design domain needs to satisfy the requirement that the radius of the bottom surface (in contact with the heat source) is more than 140% of the chip radius and the angle between the side and the bottom surface is less than 90°, so as to balance the heat dissipation balance between the main heat transfer channel and the fork.

[0055] Step 2: According to the highest filling ratio of the thermal conductive material in the design domain in step 1, the heat generation power of the chip and other parameters, a geometric model and a mathematical model of three-dimensional topology optimization are established;

[0056] The boundary conditions in step 2 include the maximum filling ratio γ of the thermal conductive material in the design domain. The establishment of the three-dimensional topology optimization model includes the following steps:

[0057] Step 2-1: Since the shape of the heat sink cannot be determined before the topology optimization begins, the boundary between the heat sink and the air cannot be manually distinguished in the initial design domain. The thermal conductive material can be approximated as a fluid with high viscosity.

[0058] The heat conduction equation for this problem can be expressed as the fluid heat transfer equation:

[0059]

[0060] is the convective heat transfer term of air. In order to simplify the problem and save calculation cost, this design only considers the heat conduction of air and ignores the convection of air. Therefore, the air velocity u=0. is the heat conduction term, Q on the right side of the equation is the heat source term, Q P is the pressure work, Q vd is viscous dissipation. Since there is no air flow, Q P and Q vd Ignore;

[0061] Step 2-2: Using SIMP interpolation, the physical value in the design domain can be defined as:

[0062]

[0063] x is the location of the design variable, ρ s is the density of the thermally conductive material, ρ 0 is the air density, ρ is the unit slice material density, and p is the penalty factor, which penalizes the intermediate value of the unit slice material density. Here, 3 is taken, k s is the thermal conductivity of the thermally conductive material, k 0 is the thermal conductivity of air, C P_s is the specific heat of the thermally conductive material, C P_0 is the specific heat of air;

[0064] Step 2-3: Based on the topology optimization method, a topology optimization mathematical model is established. The problem to be solved is a standard nonlinear optimization problem:

[0065]

[0066] subject to 0≤∫ Ω ρ(x)dV≤γM;

[0067] x∈X={x 1 , x 2 , x 3 , …x N};

[0068] 0≤γ≤1;

[0069] The objective function in this optimization problem is to minimize the total temperature change of the design domain during the heating process of a constant heat source (chip), and M is the total mass when the design domain is filled with thermal conductive materials.

[0070] Step 3: According to the mathematical model of the three-dimensional topology optimization in step 2, an optimization solver is selected to solve the problem and obtain the optimized three-dimensional topology structure of the chip heat sink;

[0071] Step 3-1: Perform finite element meshing based on the topology optimization mathematical model established in step 2;

[0072] Step 3-2: Select the MMA algorithm as the optimization algorithm, set the maximum number of iterations to 1000, and the optimization tolerance to 0.001.

[0073] Step 4: According to the three-dimensional topological structure of the chip heat sink optimized in step 3, filtering and projection processing are performed on it, the topological boundary is established, and the three-dimensional geometric model of the optimized chip heat sink is established;

[0074] Step 4-1: Filter the result using the Helmholtz filter formula:

[0075]

[0076] θ c is the design variable before filtering, θ f is the filtered design variable, R min is the filter radius, which needs to be no less than the grid size;

[0077] Step 4-2: After filtering, the design variables may have a large number of regions with intermediate values. Hyperbolic tangent projection is needed to reduce these regions that have no physical meaning:

[0078]

[0079] Step 4-3: According to the results output in Step 4-2, create a mesh model of the heat sink in the finite element software. Since the mesh of the heat sink obtained by topology optimization is prone to very small structures, resulting in problems such as excessive mesh inversion, too large differences in mesh sizes, and mesh folding, it is necessary to repair the mesh.

[0080] The repair methods include: directly deleting the tiny mesh structures, deleting the folded parts of the sizes, deleting the parts with network inversion, and repairing a flat mesh.

[0081] Step 5: According to the geometric mesh model of the heat sink obtained from the three-dimensional topology optimization result in Step 4, perform mesh repair so that it can be used for finite element software simulation analysis.

[0082] Step 6: Use the finite element software to solve the highest temperature and the temperature gradient cloud map when the chip works to a steady state, that is, perform heat transfer analysis on the heat sink.

[0083] Step 6-1: Re-import the repaired mesh into the finite element software, and set the air domain, heat source position, heating power, and materials of the heat sink and the heat source.

[0084] Step 6-2: Apply the remaining boundary conditions according to the actual situation, including the initial air velocity and the ambient temperature.

[0085] Step 6-3: Re-divide the mesh of the heat sink system to obtain a finite element model.

[0086] Step 6-4: Solve the finite element model to obtain the temperature field distribution and the sectional temperature gradient cloud map of the model.

[0087] Step 7: According to the highest temperature of the chip, determine whether the heat sink meets the heat dissipation requirements. If it meets, adopt this solution; otherwise, modify the upper and lower sizes of the heat sink design domain and the filling ratio of the heat-conducting material in the design domain, and repeat Steps 3 - 7 until the requirements are met.

[0088] Calculate the highest value T of the chip temperature at steady state max , the steady-state temperature of the chip working is T, and determine whether it meets the heat dissipation requirements: If T max < T, then it meets the heat dissipation requirements; otherwise, modify parameters such as the upper and lower sizes of the heat sink design domain and the filling ratio of the heat-conducting material in the design domain, and repeat Steps 3 - 7 until the requirements are met.

[0089] The beneficial effects of the present invention can be further illustrated by the following simulation cases:

[0090] 1. Model parameter settings:

[0091] The cylindrical design domain has a radius of 3cm and a height of 6cm; the upper radius of the inverted cone design domain is 4cm and the lower radius is 1.873cm; the upper radius of the positive cone design domain is 1.873cm and the lower radius is 4cm. Under the design domain, there is a LED chip with a radius of 1cm and a height of 0.1cm. The heat load Q is 2.25W. The ambient temperature is 20℃ and the density of the thermal conductive material is 3.132g / cm 3 , the thermal conductivity of the thermal conductive material is 113.412W / (m·K), and the specific heat of the thermal conductive material is 770J / (kg·K).

[0092] At the same time, a traditional heat sink control group model with similar size was set up, and the same boundary conditions were applied to compare the results.

[0093] 2. Comparison of simulation results:

[0094] The simulation results of the three-dimensional topology optimized heat sink and the traditional heat sink model in the three different design domains of the present invention in the finite element software are as follows:

[0095]

[0096] Table 1 Performance comparison between three-dimensional topology optimized heat sinks and traditional heat sinks in three different design domains;

[0097] It can be seen from Table 1 that the maximum chip temperatures of the three heat sinks obtained by the method of the present invention are significantly higher than those of traditional heat sinks, and the design domain of the positive cone meets the characteristics of large size at the top and small size at the bottom, so the heat dissipation effect is better than the topological optimization heat sinks with cylindrical and inverted cone design domains.

[0098] The above description is only a specific implementation of the present invention, but the protection scope of the present invention is not limited thereto. Any person familiar with the technology can understand and think of any changes or substitutions within the technical scope disclosed by the present invention, which should be included in the scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A heat sink design method for chip passive heat dissipation based on three-dimensional topology optimization, characterized in that: The method comprises the following steps: Step 1: Select the design domain of the heat sink based on the chip's geometric dimensions, PCB layout, and the distribution of heat source Q; Step 2: According to the maximum filling ratio of the thermal conductive material in the design domain of step 1 and the heat generation power parameters of the chip, a geometric model and a mathematical model of three-dimensional topology optimization are established. The boundary conditions in step 2 include the maximum filling ratio γ of the thermal conductive material in the design domain. The establishment of the three-dimensional topology optimization model includes the following steps: Step 2-1: Since the shape of the heat sink cannot be determined before the topology optimization begins, the boundary between the heat sink and the air cannot be manually distinguished in the initial design domain. The thermal conductive material can be approximated as a fluid with high viscosity. The heat conduction equation for this problem can be expressed as the fluid heat transfer equation: is the convective heat transfer term of air. In order to simplify the problem and save calculation cost, this design only considers the heat conduction of air and ignores the convection of air. Therefore, the air velocity u=0. is the heat conduction term, Q on the right side of the equation is the heat source term, Q P is the pressure work, Q vd is viscous dissipation. Since there is no air flow, Q P and Q vd Ignore; Step 2-2: Using SIMP interpolation, the physical value in the design domain can be defined as: x is the position of the design variable, ρs is the density of the thermal conductive material, ρ0 is the air density, ρ is the unit slice material density, and p is the penalty factor, which penalizes the intermediate value of the unit slice material density. Here, 3 is taken, and k s is the thermal conductivity of the thermally conductive material, k0 is the thermal conductivity of air, C P_s is the specific heat of the thermally conductive material, C P_0 is the specific heat of air; Step 2-3: Based on the topology optimization method, a topology optimization mathematical model is established. The problem to be solved is a standard nonlinear optimization problem: subject to 0≤∫ Ω ρ(x)dv≤γM; x∈X={x1,x2,x3,…x N }; 0≤γ≤1; The objective function in this optimization problem is to minimize the total temperature change of the design domain during the heat generation process of a constant heat source (chip), and M is the total mass when the design domain is filled with thermal conductive materials; Step 3: According to the mathematical model of the three-dimensional topology optimization in step 2, an optimization solver is selected to solve the problem and obtain the optimized three-dimensional topology structure of the chip heat sink; Step 4: According to the three-dimensional topological structure of the chip heat sink optimized in step 3, filtering and projection processing are performed on it, the topological boundary is established, and the three-dimensional geometric model of the optimized chip heat sink is established. The filtering and projection in step 4 to obtain a manufacturable model includes the following steps: Step 4-1: Filter the result using the Helmholtz filter formula: θ c is the design variable before filtering, θ f is the filtered design variable, R min is the filter radius, which needs to be no smaller than the grid size; Step 4-2: After filtering, the design variables may have a large number of regions with intermediate values. Hyperbolic tangent projection is needed to reduce these regions that have no physical meaning: Step 4-3: Based on the output of step 4-2, create a mesh model of the heat sink from the finite element software. Since the heat sink mesh obtained by topology optimization is prone to very tiny structures, resulting in excessive mesh inversion, large mesh size differences, and mesh folding, the mesh needs to be repaired; Step 5: According to the geometric mesh model of the three-dimensional topology optimization heat sink result in step 4, perform mesh repair so that it can be used for finite element software simulation analysis; Step 6: Use finite element software to solve the maximum temperature and temperature gradient cloud map when the chip works to a steady state, that is, to perform heat transfer analysis on the heat sink; Step 7: Based on the maximum temperature of the chip, determine whether the heat sink meets the heat dissipation requirements. If so, adopt this solution; otherwise, modify the upper and lower dimensions of the heat sink design domain, the filling ratio of the thermal conductive material in the design domain, and repeat steps 3 to 7 until the requirements are met.

2. The heat sink design method for chip passive heat dissipation based on three-dimensional topology optimization according to claim 1 is characterized in that: The chip heat source Q in step 1 is the heat generation power, and the distribution includes the chip size, position, and material information; the determination of the optimal design domain needs to refer to whether the last optimization result has achieved the optimization goal. The shape of the design domain needs to satisfy the requirement that the bottom radius is more than 140% of the chip radius and the angle between the side and the bottom is less than 90°, so as to balance the heat dissipation balance between the main heat transfer channel and the fork.

3. The heat sink design method for chip passive heat dissipation based on three-dimensional topology optimization according to claim 1 is characterized in that: The finite element solution values ​​in step 3 include: Step 3-1: Perform finite element meshing based on the topology optimization mathematical model established in step 2; Step 3-2: Select the MMA algorithm as the optimization algorithm, set the maximum number of iterations to 1000, and the optimization tolerance to 0.

001.

4. The heat sink design method for chip passive heat dissipation based on three-dimensional topology optimization according to claim 1 is characterized in that: In step 5, the repairing method includes: directly deleting tiny grid structures, deleting folded parts, deleting network inversion parts, and repairing a flat grid.

5. The heat sink design method for chip passive heat dissipation based on three-dimensional topology optimization according to claim 1 is characterized in that: The heat transfer analysis of the heat sink in step 6 includes the following steps: Step 6-1: Import the repaired mesh back into the finite element software, set the air domain, heat source position, heating power, and materials of the heat sink and heat source; Step 6-2: Apply other boundary conditions according to actual conditions, including air initial velocity and ambient temperature; Step 6-3: Re-mesh the heat sink system to obtain a finite element model; Step 6-4: Solve the finite element model to obtain the temperature field distribution and cross-sectional temperature gradient cloud map of the model.

6. The heat sink design method for chip passive heat dissipation based on three-dimensional topology optimization according to claim 1 is characterized in that: The maximum value T of the steady state of the chip temperature is calculated in steps 6-7 max , the steady state temperature of the chip is T, and it is judged whether the heat dissipation requirement is met: if T max < T, the heat dissipation requirement is met, otherwise the upper and lower dimensions of the heat sink design domain and the filling ratio parameter of the heat conducting material in the design domain are modified, and steps 3-7 are repeated until the requirements are met.

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