Display panel and display device

Abstract

The present invention provides a display panel and a display device, comprising a substrate, a plurality of binding pins disposed on one side of the substrate, and a plurality of insulating layers: the substrate comprises a display area and a binding area arranged along a first direction; the plurality of binding pins are arranged along a second direction and located in the binding area of the substrate; the plurality of insulating layers and the binding pins are disposed on the same side of the substrate; at least one of the plurality of insulating layers comprises at least one first opening, the first opening being disposed on a side of the binding area away from the display area; the orthographic projection of the first opening on the substrate overlaps with the orthographic projection of the binding pins on the substrate in the first direction. By providing the first opening in an area where the binding pins are away from the display area, the first opening can prevent cracks and warping at the edge of the display panel from propagating toward the binding pins, thereby ensuring the flatness of the binding pins and thereby improving the bonding yield between the display panel and the integrated circuit board / flexible circuit board.

Description

Technical field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. [Background Technology]

[0002] As consumers' demand for displays increases, full-screen displays have become a focus of current research. Full-screen displays have an extremely high screen-to-body ratio and can greatly improve user experience.

[0003] When implementing full-screen displays, the design of the lower bezel of the display panel is a critical issue, as it houses numerous signal lines and circuits. Existing technologies for full-screen lower bezels often suffer from film cracking and warping, which primarily impacts the binding pins near the edge of the lower bezel. [Summary of the invention]

[0004] In view of this, embodiments of the present application provide a display panel and a display device to solve the above problems.

[0005] In a first aspect, an embodiment of the present application provides a display panel, comprising:

[0006] A base substrate, comprising a display area and a binding area arranged along a first direction;

[0007] a plurality of binding pins arranged along a second direction, disposed on one side of the base substrate and located in the binding area of the base substrate; wherein the first direction and the second direction intersect;

[0008] A plurality of insulating layers are arranged on the same side of the substrate as the binding pins;

[0009] At least one insulating layer among the multiple insulating layers includes at least one first opening, and the first opening is arranged on a side of the binding area away from the display area; the orthographic projection of the first opening on the base substrate overlaps with the orthographic projection of the binding pin on the base substrate in the first direction.

[0010] In a second aspect, an embodiment of the present application provides a display device, comprising the display panel provided in the first aspect.

[0011] In an embodiment of the present application, by providing a first opening in the insulating layer provided in the area where the binding pin is away from the display area, the first opening can prevent cracks and warping at the edge of the display panel from developing toward the binding pin, thereby ensuring the flatness of the binding pin, and thereby improving the bonding yield between the display panel and the integrated circuit board / flexible circuit board.

Brief Description of the Drawings

[0012] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0013] Figure 1 A schematic diagram of a display panel provided in an embodiment of the present application;

[0014] Figure 2 for Figure 1 A schematic diagram of a local cross section along the MM' direction;

[0015] Figure 3 for Figure 1 Another partial cross-sectional diagram along the MM' direction;

[0016] Figure 4 for Figure 1 Another partial cross-sectional schematic diagram along the MM' direction;

[0017] Figure 5 A schematic diagram of a display panel provided in an embodiment of the present application;

[0018] Figure 6 for Figure 1 A partial enlarged schematic diagram of the middle C1 area;

[0019] Figure 7 for Figure 1 A partial enlarged schematic diagram of the middle C1 area;

[0020] Figure 8 for Figure 1 A partial enlarged schematic diagram of the middle C1 area;

[0021] Figure 9 for Figure 1 A partial enlarged schematic diagram of the middle C1 area;

[0022] Figure 10 for Figure 1 A partial enlarged schematic diagram of the middle C1 area;

[0023] Figure 11 for Figure 1 A partial enlarged schematic diagram of the middle C1 area;

[0024] Figure 12 for Figure 1 A partial enlarged schematic diagram of the middle C1 area;

[0025] Figure 13 for Figure 1 A partial enlarged schematic diagram of the middle C1 area;

[0026] Figure 14 for Figure 1 A partial enlarged schematic diagram of the middle C1 area;

[0027] Figure 15 for Figure 1 A partial enlarged schematic diagram of the middle C1 area;

[0028] Figure 16 for Figure 1 A partial enlarged schematic diagram of the middle C1 area;

[0029] Figure 17 for Figure 1 A partial enlarged schematic diagram of the middle C1 area;

[0030] Figure 18 for Figure 1 A partial enlarged schematic diagram of the middle C1 area;

[0031] Figure 19 for Figure 1 A partial enlarged schematic diagram of the middle C1 area;

[0032] Figure 20 for Figure 1 A partial enlarged schematic diagram of the middle C1 area;

[0033] Figure 21 for Figure 1 A partial enlarged schematic diagram of the middle C1 area;

[0034] Figure 22 A schematic diagram of another display panel provided in an embodiment of the present application;

[0035] Figure 23 for Figure 22 A partial enlarged schematic diagram of the middle C2 area;

[0036] Figure 24 for Figure 22 A partial enlarged schematic diagram of the middle C2 area;

[0037] Figure 25 for Figure 22 A partial enlarged schematic diagram of the middle C2 area;

[0038] Figure 26 for Figure 22 A partial enlarged schematic diagram of the middle C2 area;

[0039] Figure 27 for Figure 22 A partial enlarged schematic diagram of the middle C2 area;

[0040] Figure 28 for Figure 22 A partial enlarged schematic diagram of the middle C2 area;

[0041] Figure 29 for Figure 22 A partial enlarged schematic diagram of the middle C2 area;

[0042] Figure 30 for Figure 22 A partial enlarged schematic diagram of the middle C2 area;

[0043] Figure 31 for Figure 22 A partial enlarged schematic diagram of the middle C2 area;

[0044] Figure 32 for Figure 22 A partial enlarged schematic diagram of the middle C2 area;

[0045] Figure 33 for Figure 22 A partial enlarged schematic diagram of the middle C2 area;

[0046] Figure 34 A schematic diagram of a display device provided in an embodiment of the present application. [Specific implementation method]

[0047] In order to better understand the technical solution of the present application, the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0048] It should be clear that the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0049] The terms used in the embodiments of the present application are for the purpose of describing specific embodiments only and are not intended to limit the present application. The singular forms "a", "an", "the" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms unless the context clearly indicates otherwise.

[0050] It should be understood that the term "and / or" as used herein is merely a description of the relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A exists alone, A and B exist simultaneously, or B exists alone. Furthermore, the character " / " in this document generally indicates that the associated objects are in an "or" relationship.

[0051] In the description of this specification, it is necessary to understand that the words "substantially", "approximately", "approximately", "about", "roughly", "generally" and the like described in the claims and embodiments of this application refer to what can be generally recognized within a reasonable process operation range or tolerance range, rather than an exact value.

[0052] It should be understood that although the terms "first," "second," and "third," etc. may be used in embodiments of the present application to describe signal lines, pins, etc., these signal lines, pins, etc. should not be limited to these terms. These terms are merely used to distinguish signal lines, pins, etc. from one another. For example, a first signal line may also be referred to as a second signal line, and similarly, a second signal line may also be referred to as a first signal line, without departing from the scope of the embodiments of the present application.

[0053] The applicant in this case has provided a solution to the problems existing in the prior art through careful and in-depth research.

[0054] Figure 1 A schematic diagram of a display panel provided in an embodiment of the present application is shown. Figure 2 for Figure 1 A schematic diagram of a local cross-section along the MM' direction.

[0055] Please combine Figure 1 and Figure 2 The display panel provided in an embodiment of the present application includes a substrate 10, which includes a display area AA and a binding area B1. For example, the substrate 10 includes a non-display area BB surrounding the display area AA, and the binding area B1 is provided within the non-display area BB. A plurality of pixels are provided at the display area AA for image display; a plurality of binding pins 20 are provided at the binding area B1 for binding to an integrated circuit board or a flexible circuit board.

[0056] The display area AA and the binding area B1 are arranged along the first direction Y. After the binding pins 20 are bound to the integrated circuit board / flexible circuit board, the binding pins 20 can transmit signals between the integrated circuit board / flexible circuit board and the pixels / touch electrodes.

[0057] The binding pins 20 are provided on one side of the base substrate 10 and located in the binding area B1 of the base substrate 10, and the plurality of binding pins 20 in the binding area B1 are arranged along the second direction X. The first direction Y intersects the second direction X, for example, Figure 1 As shown, the first direction Y may be perpendicular to the second direction X.

[0058] In addition, the display panel further includes a plurality of insulating layers 30, and the plurality of insulating layers 30 and the binding pins 20 are arranged on the same side of the base substrate 10. It should be noted that, for the convenience of description, Figure 2 Only one insulating layer 30 is shown in the figure, and an actual display panel may include multiple insulating layers 30.

[0059] At least one of the multiple insulating layers 30 included in the display panel includes a first opening 40. The first opening 40 is disposed on a side of the binding region B1 away from the display region AA, and the insulating layer 30 including the first opening 40 includes at least one first opening 40. The first opening 40 is disposed on a side of the binding region B1 away from the display region AA, and the orthographic projection of the first opening 40 on the base substrate 10 is located on a side of the orthographic projection of the binding pin 20 on the base substrate 10 away from the display region AA.

[0060] In the embodiment of the present application, the orthographic projection of the first opening 40 on the base substrate 10 overlaps with the orthographic projection of the binding pin 20 on the base substrate 10 in the first direction Y. That is, along the first direction Y, the orthographic projection of a portion of the first opening 40 on the base substrate 10 coincides with the orthographic projection of a portion of the binding pin 20 on the base substrate 10.

[0061] During lamination of the display panel to the integrated circuit board / flexible circuit board, during pressure and temperature shock tests, and after the motherboard is cut into display panels, the insulating layer near the bonding area B1 may crack and warp, which in turn may cause cracks and warping in the bonding pins 20, leading to misalignment during lamination. This problem is particularly prominent in display panels with narrow bezels.

[0062] During the process of analyzing the above-mentioned issues, the inventors discovered that when cracks and warping appeared in the insulating layer 30 near the binding area B1, cracks and warping also occurred near the edge of the display panel, and the cracks and warping at the edge were continuous with the cracks and warping near the binding area B1. Therefore, the inventors inferred that the cracks and warping in the insulating layer 30 near the binding area B1 actually originated at the edge of the display panel.

[0063] In the embodiment of the present application, by providing a first opening 40 in the insulating layer 30 disposed in an area away from the display area AA where the binding pins 20 are located, cracks and warpage in the insulating layer 20 corresponding to the edge of the display panel are stopped at the first opening 40 when they propagate toward the binding area B1. This blocks the path for cracks and warpage in the insulating layer 30 corresponding to the edge of the display panel to propagate toward the binding pins 20 via the side of the binding pins 20 near the edge of the display panel. Furthermore, if cracks and warpage in the insulating layer 30 propagate inward from the edge of the display panel, they will need to bypass the first opening 40. This means that the propagation path of cracks and warpage in the insulating layer 30 before reaching the binding pins 20 is extended, significantly reducing the probability of cracks and warpage in the insulating layer 30 reaching the binding pins 20.

[0064] The first opening 40 in the display panel provided in the embodiment of the present application can prevent the warping at the edge of the display panel from developing toward the binding pins 20, thereby ensuring the flatness of the binding pins 20 and thereby improving the bonding yield between the display panel and the integrated circuit board / flexible circuit board.

[0065] In addition, as can be seen from the above analysis of the technical problem, the cracks and warping in the insulating layer 30 are mainly caused by uneven bonding pressure, cutting stress, etc. near the binding pins 20 in the binding area. Setting the first opening 40 near the binding pins 20 and the starting position of the cracks and warping can effectively avoid the occurrence of cracks and warping.

[0066] It should be noted that the insulating layer 30 where the first opening 40 is provided may be an insulating layer extending from the display area AA to the non-display area BB, and the portion of the insulating layer 30 may further include a portion provided in the binding area B1 .

[0067] In one embodiment of this application, please refer to Figure 2 In a direction Z perpendicular to the plane where the display panel is located, at least one insulating layer 30 including the first opening 40 is an inorganic layer and is located between the film layer where the binding pins 20 are located and the base substrate 10 .

[0068] For example, Figure 2 As shown, the insulating layer 31 / 30 between the film layer where the binding pins 20 are located and the base substrate 10 is an inorganic insulating layer and includes a first opening 41 / 40.

[0069] The inventors further analyzed the problem of warping of the insulating layer 30 near the binding area B1 and found that the main film layer where warping occurs is mainly concentrated in the inorganic insulating layer. This embodiment effectively improves the bonding yield between the display panel and the integrated circuit board / flexible circuit board by setting a first opening 40 in the inorganic insulating layer that carries the binding pin 20.

[0070] Figure 3 for Figure 1 Another schematic diagram of a local cross section along the MM' direction.

[0071] In one embodiment of this application, please refer to Figure 3 At least two of the multiple insulating layers 30 included in the display panel include first openings 40; in a direction Z perpendicular to the plane where the display panel is located, the first openings 40 located in different insulating layers 30 overlap.

[0072] For example, Figure 3As shown, the multiple insulating layers 30 include a first insulating layer 31 / 30 and a second insulating layer 32 / 30, the insulating layer 31 / 30 includes a first opening 41 / 40 and the insulating layer 32 / 30 includes a first opening 42 / 40, and along the thickness direction Z of the display panel, the first opening 41 / 40 overlaps with the first opening 42 / 40, that is, the first opening 41 / 40 and the second opening 42 / 40 pass through along the thickness direction Z of the display panel.

[0073] In this embodiment, by providing the first openings 40 in more insulating layers 30 , the warping at the edge of the display panel can be more effectively prevented from developing toward the binding pins 20 .

[0074] In one implementation of this embodiment, please continue to refer to Figure 3 Among the at least two insulating layers 30 including the first opening 40, at least one insulating layer 30 is located between the film layer where the binding pin 20 is located and the base substrate 10, and at least one insulating layer 20 is located on the side of the film layer where the binding pin 20 is located away from the base substrate.

[0075] For example, Figure 3 As shown, the insulating layer 31 / 30 including the first opening 41 / 40 is located between the film layer where the binding pins 20 are located and the base substrate 10 , and the insulating layer 32 / 30 including the first opening 42 / 40 is located on the side of the film layer where the binding pins 20 are located away from the base substrate 10 .

[0076] In this embodiment, first openings 40 are provided in the insulating layer 30 above and below the film layer where the binding pins 20 are located. On the one hand, providing the first openings 40 in the insulating layer 30 below the film layer where the binding pins 20 are located ensures that the binding pins 20 have a flat supporting surface. On the other hand, providing the first openings 40 in the insulating layer 30 above the film layer where the binding pins 20 are located prevents the insulating layer 30 secured to the integrated circuit board / flexible circuit board from cracking and warping due to uneven bonding stress, which could cause cracks and warping in the insulating layer 30 below, leading to cracks and warping in the binding pins 20.

[0077] In one embodiment of the present application, Figure 2 and Figure 3 As shown, the binding pin 20 may be formed from a portion of a conductive film layer.

[0078] Figure 4 for Figure 1 Another partial cross-sectional schematic diagram along the MM' direction.

[0079] In another embodiment of the present application, Figure 4 As shown, the binding pin 20 may be composed of parts located in at least two conductive film layers. Figure 4 As shown, the binding pin 20 includes a first portion 21 located in one conductive film layer and a second portion 22 located in another conductive film layer.

[0080] In this embodiment, if Figure 4 As shown, along the thickness direction Z of the display panel, an insulating layer 32 / 30 is included between the first portion 21 and the second portion 22 constituting the binding pin 20. In this embodiment, the insulating layer 32 / 30 includes a first opening 42 / 40, and in the direction Z perpendicular to the plane of the display panel, the first opening 42 / 40 included in the insulating layer 32 / 30 can overlap with the first opening 40 included in the other insulating layer 30.

[0081] Figure 5 A schematic diagram of a display panel provided in an embodiment of the present application.

[0082] like Figure 5 As shown, a transistor 50, a capacitor 60 and a light emitting device 70 are provided on one side of the base substrate 10. In addition, the base substrate 10 may also include signal lines and other devices, which are not shown to clearly illustrate the inventive concept of this application.

[0083] Please refer to Figure 5 The transistor 50 includes a semiconductor layer 51, a gate 52, a source 53, and a drain 54. The capacitor includes a first plate 61 and a second plate 62. The source 53 and the drain 54 can be provided on the same layer. The first plate 61 of the capacitor can be provided on the same layer as the gate 52 or the source 53 and the drain 54. The second plate 62 can be provided on a different layer from the gate 52, the source 53, and the drain 54.

[0084] like Figure 5 As shown, an intermediate insulating layer 32 / 32a is included between the first electrode 61 and the second electrode 62, a gate insulating layer 31 / 30 is included between the semiconductor layer 51 and the gate 52, an interlayer dielectric layer 32 / 32b is included between the second electrode 62 and the gate 52 or the source 53 / drain 54, and in addition, a passivation layer 33 / 33a and a planarization layer 33 / 33b are included between the capacitor 60 and the transistor 70 and the light-emitting device 70.

[0085] In the embodiment of the present application, when the binding pin 20 is composed of a portion in a conductive film layer, the portion can be provided in the same layer as any one of the gate 52 , the source 53 , the drain 54 , and the second electrode 62 .

[0086] For example, please combine Figure 2 and Figure 5 , the binding pin 20 can be set on the same layer as the gate 52.

[0087] In an embodiment of the present application, when the binding pin 20 is composed of parts of at least two conductive film layers, one of the conductive film layers may include any one of the gate 52, the source 53, the drain 54, and the second electrode 62, and the other conductive film layer may also include any one of the gate 52, the source 53, the drain 54, and the second electrode 62.

[0088] For example, please combine Figure 3 and Figure 5 The first portion 21 of the binding pin 20 is disposed on the same layer as the gate 52 , and the second portion 22 is disposed on the same layer as the second electrode plate 62 .

[0089] For example, please refer to Figure 5 The first portion 21 of the binding pin 20 is provided on the same layer as the gate 52 , and the second portion 22 is provided on the same layer as the source 53 / drain 54 .

[0090] In addition, the insulating layer 30 including the first opening 40 is at least one of the gate insulating layer 31 / 30 , the intermediate insulating layer 32 / 32 a , the interlayer dielectric layer 32 / 32 b , the passivation layer 33 / 33 a and the planarization layer 33 / 33 b .

[0091] Figure 6 for Figure 1 A partial enlarged schematic diagram of the C1 area in the middle. Figure 7 for Figure 1 A partial enlarged schematic diagram of the C1 area in the middle. Figure 8 for Figure 1 A partial enlarged schematic diagram of the C1 area in the middle. Figure 9 for Figure 1 A partial enlarged schematic diagram of the middle C1 area.

[0092] In one embodiment of the present application, Figure 6-Figure 9 As shown, at least one insulating layer 30 among the multiple insulating layers 30 includes a plurality of first openings 40 arranged along the second direction X, and the orthographic projections of the gaps 400 between adjacent first openings 40 along the second direction X on the base substrate 10 are located between the orthographic projections of adjacent binding pins 20 on the base substrate 10.

[0093] During the patterning process of the conductive film layer, conductive film residue is likely to form within and around the first opening 40. In the embodiment of the present application, along the first direction Y, the binding pins 20 overlap with the first opening 40, and the portion between adjacent binding pins 20 does not overlap with the first opening 40. This reduces the probability of conductive film residue forming between adjacent binding pins 20 due to the first opening 40, thereby avoiding the risk of electrical short circuits between adjacent binding pins 20 due to the conductive film residue.

[0094] Figure 10 for Figure 1A partial enlarged schematic diagram of the C1 area in the middle. Figure 11 for Figure 1 A partial enlarged schematic diagram of the C1 area in the middle. Figure 12 for Figure 1 A partial enlarged schematic diagram of the C1 area in the middle. Figure 13 for Figure 1 A partial enlarged schematic diagram of the C1 area in the middle. Figure 14 for Figure 1 A partial enlarged schematic diagram of the C1 area in the middle. Figure 15 for Figure 1 A partial enlarged schematic diagram of the middle C1 area.

[0095] In one embodiment of this application, please refer to Figure 10-15 The orthographic projections of at least two adjacent first openings 40 in the second direction X on the base substrate 10 are connected. Optionally, the at least two second openings 40 arranged along the second direction X are connected. The at least two first openings 40 connected in orthographic projection overlap with at least two binding pins 20 in the first direction Y.

[0096] By providing the first openings 40 that are connected in orthographic projection, the cracks and warping of the insulating layer 30 can be effectively blocked from developing from the edge of the display panel to the binding pins 20 in the first direction Y.

[0097] In one implementation of this embodiment, please refer to Figure 10-12 The orthographic projections of some of the first openings 40 adjacently arranged along the second direction X are connected, and the orthographic projections of some of the first openings 40 adjacently arranged along the second direction X include gaps therebetween.

[0098] For example, Figure 10-12 As shown, the orthographic projections of every two first openings 40 adjacently arranged along the second direction X are connected together, and a gap is included between the two first openings 40 connected together by orthographic projection and their respective adjacent first openings 40 .

[0099] In one implementation of this embodiment, please refer to Figure 13-15 , the orthographic projections of the adjacent first openings 40 along the second direction X are all connected together, which can effectively prevent cracks and warping at the edge of the display panel from developing toward the location of the binding pins 20 .

[0100] Figure 16 for Figure 1 A partial enlarged schematic diagram of the C1 area in the middle. Figure 17 for Figure 1 A partial enlarged schematic diagram of the C1 area in the middle. Figure 18 for Figure 1 Schematic diagram of a partial enlargement of the middle C1 region.

[0101] In one embodiment of the present application, Figure 16-18 As shown, adjacent first openings 40 along the second direction X partially overlap in the first direction Y. That is, the plurality of second openings 40 arranged along the second direction X are not connected, but two adjacent second openings overlap in the first direction Y.

[0102] In the display panel provided in the present application, the projection shape of the first opening 40 on the base substrate 10 is at least one of a broken line, a curve, a straight line, and a dot. Figure 6 、 Figure 10 、 Figure 13 and Figure 16 As shown, the projection shape of the first opening 40 on the base substrate 10 is a straight line; Figure 8 、 Figure 12 、 Figure 15 and Figure 18 As shown, the projection shape of the first opening 40 on the base substrate 10 is a curve; Figure 7 、 Figure 11 、 Figure 14 and Figure 17 As shown, the projection shape of the first opening 40 on the base substrate 10 is a broken line; Figure 9 As shown, the projection shape of the first opening 40 on the base substrate 10 is a point shape.

[0103] It should be noted that the projection shape of the multiple first openings 40 included in the same display panel on the base substrate 10 can be one of the above shapes; the projection shape of the multiple first openings 40 included in the same display panel on the base substrate 10 can also be at least two of the above shapes.

[0104] Figure 19 for Figure 1 A partial enlarged schematic diagram of the middle C1 area.

[0105] In one embodiment of the present application, Figure 19 As shown, the edge of at least one first opening 40 away from the display area AA coincides with at least one cutting edge of the display panel. That is, the edge of the binding area B1 away from the display area AA overlaps with the at least one first opening 40. This edge of the at least one first opening 40 can serve as the cutting position when cutting the motherboard to form a display panel.

[0106] In one implementation of this embodiment, the projections of the first openings 40 on the base substrate 10 that overlap the edge of the binding region B1 away from the display region AA are all linear. Furthermore, there are multiple first openings 40 overlapping the edge of the binding region B1 away from the display region AA, and these first openings 40 are interconnected. These first openings 40 form a large transverse groove structure, effectively reducing the risk of cracks in the insulation layer and warping at the edge of the display panel.

[0107] In addition, in one embodiment of the present application, Figure 19 As shown, the plurality of first openings 40 arranged along the second direction X are regarded as an opening group, and the binding area B1 of the display panel may include at least two opening groups.

[0108] Figure 20 for Figure 1 A partial enlarged schematic diagram of the middle C1 area.

[0109] In one embodiment of this application, please refer to Figure 20 At least one insulating layer 30 of the multiple insulating layers 30 includes at least one second opening 40a, the second opening 40a is set on the side of the binding area B1 away from the display area AA, and the number of the second openings 40a included in the insulating layer 30 including the second opening 40a is at least one.

[0110] In this embodiment, the orthographic projection of the second opening 40a on the base substrate 10 overlaps the orthographic projection of the gap between adjacent binding pins 20 on the base substrate 10 in the first direction Y. That is, along the first direction Y, the orthographic projection of at least a portion of the second opening 40a on the base substrate 10 is located on a side of the gap between adjacent binding pins 20 that is away from the display area AA.

[0111] At least a portion of the first opening 40 is disposed on a side of the binding pin 20 away from the display area AA, and at least a portion of the second opening 40a is disposed in the gap between the binding pins 20. Thus, the first opening 40 and the second opening 40a can effectively prevent the insulating layer of the display panel from warping along the first direction Y. Furthermore, the plurality of first openings 40 arranged along the second direction X can be dispersed to avoid the risk of residual conductive film near the first openings 40 causing electrical conduction of the binding pins 20.

[0112] In one embodiment of the present application, at least a portion of the insulating layer 30 including the second opening 40 a is the same as at least a portion of the insulating layer 30 including the first opening 40. That is, at least a portion of the insulating layer 30 may include both the first opening 40 and the second opening 40 a. Thus, the first opening 40 and the second opening 40 a may be formed simultaneously during the preparation process of the insulating layers 30.

[0113] For example, when the gate insulation layer 31 / 30 includes a first opening 40, it may also include a second opening 40a; when the intermediate insulation layer 32 / 32a includes a first opening 40, it may also include a second opening 40a; when the interlayer dielectric layer 32 / 32b includes a first opening 40, it may also include a second opening 40a; when the passivation layer 33 / 33a includes a first opening 40, it may also include a second opening 40a; when the planarization layer 33 / 33b includes a first opening 40, it may also include a second opening 40a.

[0114] In one implementation of this embodiment, please continue to refer to Figure 20 The orthographic projections of the first openings 40 on the base substrate 10 and the orthographic projections of the second openings 40 a on the base substrate 10 are alternately arranged along the first direction X.

[0115] Figure 21 for Figure 1 A partial enlarged schematic diagram of the middle C1 area.

[0116] In one embodiment of this application, please continue to refer to Figure 21 The display panel includes a plurality of pull-down metal wires 200, which are located on a side of the binding pins 20 away from the display area AA and connected to the binding pins 20. The pull-down metal wires 200 and the binding pins 20 may be an integral structure.

[0117] In the direction perpendicular to the plane where the base substrate 10 is located, as shown in FIG. Figure 21 As shown, the first opening 40 overlaps the pull-down metal wire 200. That is, along the thickness direction Z of the display panel, the first opening 40 overlaps the pull-down metal wire 200. Typically, the pull-down metal wire 200 and the binding pin 20 are integrally formed. The overlapping portion of the first opening 40 and the pull-down metal wire 200 can serve as a stress relief point for the pull-down metal wire 200, thereby blocking the path of cracks and warping in the pull-down metal wire 200 toward the binding pin 20.

[0118] In addition, when the display panel further includes the second opening 40 a , along the second direction Y, the second opening 40 a is located between adjacent pull-down metal lines 200 .

[0119] Figure 22 A schematic diagram of another display panel provided in an embodiment of the present application, Figure 23 for Figure 22 A partial enlarged schematic diagram of the middle C2 area.

[0120] Please combine Figure 22 and Figure 23 The display panel includes a plurality of binding pins 20 arranged along the second direction X, and at least one of the plurality of insulating layers 30 includes at least one third opening 40 b. The third opening 40 b and the binding pins 20 are arranged along the second direction X.

[0121] Exemplarily, the second direction X is parallel to the row direction, the plurality of binding pins 20 in the binding area B1 are arranged along the row direction, and the third openings 40 b and the binding pins 20 are arranged along the row direction.

[0122] In the embodiment of the present application, the third opening 40 b can be provided to prevent cracks and warping of the display panel from developing toward the binding pins 20 in a direction substantially the same as the second direction X.

[0123] It should be noted that at least the portion of the insulating layer 30 including the third opening 40b may be the same as at least the portion of the insulating layer 30 including the first opening 40, or may be the same as at least the portion of the insulating layer 30 including the second opening 40a. That is, at least the portion of the insulating layer 30 may include both the first opening 40 and the third opening 40b, or at least the portion of the insulating layer 30 may include both the second opening 40a and the third opening 40b.

[0124] For example, when the gate insulation layer 31 / 30 includes the first opening 40, it may also include the third opening 40b; when the intermediate insulation layer 32 / 32a includes the first opening 40, it may also include the third opening 40b; when the interlayer dielectric layer 32 / 32b includes the first opening 40, it may also include the third opening 40b; when the passivation layer 33 / 33a includes the first opening 40, it may also include the third opening 40b; when the planarization layer 33 / 33b includes the first opening 40, it may also include the third opening 40b.

[0125] Figure 24 for Figure 22 A partial enlarged schematic diagram of the middle C2 area.

[0126] In one implementation of this embodiment, Figures 22 to 24 As shown, the third opening 40b is located outside the binding area B1. In other words, if the binding pins 20 are considered as a whole, the third opening 40b arranged along the second direction X with the binding pins 20 is outside the whole, and the third opening 40b is located outside all the binding pins 20. In this implementation, cracks and warpage outside the binding area B1 along the second direction X can be effectively blocked by the third opening 40b outside the binding area B1.

[0127] Among them, please refer to Figure 22 and Figure 23 , the third opening 40 b extends along the first direction Y. Optionally, the first opening 4 extends substantially along the second direction X, and the first opening 40 and the third opening 40 b extend perpendicularly, and the two can cooperate to effectively prevent the binding pin 20 from warping.

[0128] Among them, please refer to Figure 24 The third opening 40b extends along a third direction, and the third direction intersects the first direction Y and the second direction X.

[0129] Figure 25 for Figure 22 A partial enlarged schematic diagram of the middle C2 area, Figure 26 for Figure 22 A partial enlarged schematic diagram of the middle C2 area.

[0130] In one embodiment of the present application, Figure 25 and Figure 26 As shown, among the plurality of first openings 40 included on the base substrate 10, at least two first openings 40 may be arranged along the first direction Y; and among the plurality of third openings 40b included on the base substrate 10, at least two third openings 40b may be arranged along the first direction Y. In addition, when the base substrate 10 includes a plurality of second openings 40a, at least two second openings 40a may be arranged along the second direction X.

[0131] Figure 27 for Figure 22 A partial enlarged schematic diagram of the middle C2 area, Figure 28 for Figure 22 A partial enlarged schematic diagram of the middle C2 area.

[0132] In one embodiment of the present application, Figure 27 and Figure 28 As shown, the orthographic projection of the at least one third opening 40 b on the base substrate 10 is connected to the orthographic projection of the at least one first opening 40 on the base substrate 10 .

[0133] Optionally, multiple first openings 40 arranged along the second direction X are connected and then connected to the third opening 40b, so that the first openings 40 and the third openings 40b form a semi-enclosed structure for the binding pins in the binding area B1, and the first openings 40 and the third openings 40b can jointly block the cracks and openings in the insulating layer 30 from developing along the first direction Y and the second direction X toward the binding pins 20.

[0134] Figure 29 for Figure 22 A partial enlarged schematic diagram of the middle C2 area, Figure 30 for Figure 22 A partial enlarged schematic diagram of the middle C2 area, Figure 31 for Figure 22 A partial enlarged schematic diagram of the middle C2 area.

[0135] In one embodiment of the present application, Figure 29-Figure 31 As shown, the display panel further includes a plurality of dummy pins, including a first dummy pin 20a. The first dummy pin 20a is located on a side of the binding area B1 away from the binding pin 20. Optionally, the dummy pin can be prepared simultaneously with the binding pin 20, that is, the dummy pin and the binding pin are formed of the same conductive film layer.

[0136] Among them, the dummy pins are not bonded and welded to the integrated circuit board and the flexible circuit board. Therefore, during the bonding and welding process of the binding pins 20 to the integrated circuit board and the flexible circuit board, the dummy pins can bear part of the bonding stress and reduce the film cracks and warping caused by the bonding stress.

[0137] In one implementation of this embodiment, Figure 29 As shown, the orthographic projection of the third opening 40b on the base substrate 10 is located between the orthographic projections of adjacent first dummy pins 20a on the base substrate 10. That is, at least part of the insulating layer 30 located adjacent to the first dummy pins 20a includes the third opening 40b.

[0138] In one implementation of this embodiment, Figure 30 and Figure 31 As shown, the first dummy pin 20a overlaps the third opening 40b in the direction Z perpendicular to the plane of the display panel, that is, at least part of the insulating layer 30 in the area where the first dummy pin 20a is located includes the third opening 40b.

[0139] Figure 32 for Figure 22 A partial enlarged schematic diagram of the middle C2 area, Figure 33 for Figure 22 A partial enlarged schematic diagram of the middle C2 area.

[0140] In one embodiment of the present application, Figure 32 and Figure 33 As shown, the display panel further includes an alignment block 80 , which serves as an alignment mark when the display panel is attached to other jigs or devices.

[0141] In one implementation of this embodiment, Figure 32 As shown, the third opening 40b may be located between the alignment block 80 and the binding pin 20. That is, along the second direction X, the area where the third opening 40b is located is between the area where the alignment block 80 is located and the area where the binding pin 20 is located.

[0142] In one implementation of this embodiment, Figure 33 As shown, the alignment block 80 may be located between the third opening 40b and the binding pin 20. That is, along the second direction X, the area where the alignment block 80 is located is between the area where the third opening 40b is located and the area where the binding pin 20 is located.

[0143] Figure 34 A schematic diagram of a display device provided in an embodiment of the present application.

[0144] The embodiment of the present application provides a display device, such as Figure 34As shown, it includes a display panel 001 provided in any of the above embodiments. The display device provided in the embodiment of the present application can be a mobile phone. In addition, the display device provided in the embodiment of the present application can also be a display device such as a computer or a television.

[0145] In the embodiment of the present application, by providing a first opening 40 in the insulating layer 30 provided in the area where the binding pin 20 is away from the display area AA, the first opening 40 can prevent cracks and warping at the edge of the display panel from developing toward the binding pin 20, thereby ensuring the flatness of the binding pin 20, and thereby improving the bonding yield between the display panel and the integrated circuit board / flexible circuit board in the display device.

[0146] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A display panel, characterized in that: include: A base substrate, comprising a display area and a binding area arranged along a first direction; a plurality of binding pins arranged along a second direction, disposed on one side of the base substrate and located in the binding area of the base substrate; wherein the first direction and the second direction intersect; A plurality of insulating layers are arranged on the same side of the substrate as the binding pins; At least one of the plurality of insulating layers includes at least one first opening, the first opening being arranged on a side of the binding area away from the display area; an orthographic projection of the first opening on the base substrate overlaps with an orthographic projection of the binding pin on the base substrate in the first direction; A gate insulating layer, an interlayer dielectric layer, an insulating intermediate layer, a passivation layer and a planarization layer are provided on one side of the substrate; The insulating layer including the first opening is at least one of a gate insulating layer, an interlayer dielectric layer, an intermediate insulating layer, a passivation layer, and a planarization layer.

2. The display panel according to claim 1, wherein: In a direction perpendicular to the plane where the display panel is located, at least one insulating layer including the first opening is an inorganic layer and is located between the film layer where the binding pins are located and the base substrate.

3. The display panel according to claim 1, wherein: At least two of the plurality of insulating layers include a first opening; in a direction perpendicular to the plane where the display panel is located, the first openings located in different insulating layers overlap; Among the at least two insulating layers including the first opening, at least one insulating layer is located between the film layer where the binding pins are located and the base substrate, and at least one insulating layer is located on a side of the film layer where the binding pins are located away from the base substrate.

4. The display panel according to claim 1, wherein: At least one of the plurality of insulating layers comprises a plurality of first openings arranged along the second direction; The orthographic projection of the gap between the adjacent first openings along the second direction on the base substrate is located between the orthographic projections of the adjacent binding pins on the base substrate.

5. The display panel according to claim 1, wherein: Along the first direction, orthographic projections of at least two first openings adjacent to each other in the second direction on the base substrate overlap.

6. The display panel according to claim 1, wherein: Orthographic projections of at least two adjacent first openings along the second direction are connected together.

7. The display panel according to claim 6, wherein: Orthographic projections of the first openings adjacent to each other along the second direction are connected together.

8. The display panel according to claim 1, wherein: An edge of at least one of the first openings that is away from the display area coincides with at least one cut edge of the display panel.

9. The display panel according to claim 1, wherein: The projection shape of the first opening on the base substrate is at least one of a broken line, a curve, a straight line, and a point.

10. The display panel according to claim 1, wherein The display panel includes a plurality of pull-down metal wires, wherein the pull-down metal wires are located on a side of the binding pins away from the display area and connected to the binding pins; In a direction perpendicular to a plane where the base substrate is located, the first opening overlaps with the pull-down metal line.

11. The display panel according to claim 1, wherein At least one insulating layer of the plurality of insulating layers comprises at least one second opening, wherein the second opening is arranged on a side of the binding area away from the display area; An orthographic projection of the second opening on the base substrate overlaps with an orthographic projection of a gap between adjacent binding pins on the base substrate in the first direction.

12. The display panel according to claim 11, wherein: The orthographic projections of the first openings on the base substrate and the orthographic projections of the second openings on the base substrate are alternately arranged along the first direction.

13. The display panel according to claim 11, wherein: The display panel includes a plurality of pull-down metal wires, wherein the pull-down metal wires are located on a side of the binding pins away from the display area and connected to the binding pins; Along the second direction, the second opening is located between adjacent pull-down metal lines.

14. The display panel according to claim 11, wherein: At least a portion of the insulating layer including the second opening is the same as at least a portion of the insulating layer including the first opening.

15. The display panel according to claim 1, wherein The plurality of binding pins are arranged along the second direction; At least one insulating layer among the plurality of insulating layers includes at least one third opening, and the third opening and the binding pin are arranged along the second direction.

16. The display panel according to claim 15, wherein: The third opening is located outside the binding area; The third opening extends along a third direction, and the third direction intersects with the first direction and the second direction.

17. The display panel according to claim 15, wherein: The third opening extends along the first direction.

18. The display panel according to claim 15, wherein: An orthographic projection of at least one of the third openings on the base substrate is connected to an orthographic projection of at least one of the first openings on the base substrate.

19. The display panel according to claim 15, wherein: The display panel further includes a plurality of dummy pins, wherein the plurality of dummy pins include a first dummy pin, and the first dummy pin is located on a side of the binding area away from the binding pin; The orthographic projection of the third opening on the base substrate is located between the orthographic projections of adjacent first dummy pins on the base substrate.

20. The display panel according to claim 15, wherein The display panel further includes a plurality of dummy pins, wherein the plurality of dummy pins include a first dummy pin, and the first dummy pin is located on a side of the binding area away from the binding pin; In a direction perpendicular to the plane where the display panel is located, the first dummy pin overlaps with the third opening.

21. The display panel according to claim 15, wherein The display panel further includes an alignment block; The third opening is located between the alignment block and the binding pin; or, The alignment block is located between the third opening and the binding pin.

22. The display panel according to claim 15, wherein: At least a portion of the insulating layer including the third opening is the same as at least a portion of the insulating layer including the first opening.

23. A display device, characterized in that: Comprising the display panel according to any one of claims 1-22.

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