Special-shaped thin film transistor and array substrate

Abstract

The present application discloses a special-shaped thin-film transistor and an array substrate. The special-shaped thin-film transistor includes a first gate portion, a first compensation electrode and a first source electrode. The first compensation electrode is located on one side of the first gate portion and is connected to the first gate portion; the first source electrode and the first gate portion are arranged in different layers, and the first source electrode and the first compensation electrode are arranged in different layers. The first source electrode includes a first extension portion, a first source portion and a second extension portion connected in sequence, and the first source portion is located between the first gate portion and the first compensation electrode; the first extension portion is arranged on a side of the first source portion close to the first gate portion, and a part of the first extension portion is overlapped with the first gate portion; the second extension portion is arranged on a side of the first source portion close to the first compensation electrode, and a part of the second extension portion is overlapped with the first compensation electrode, which can solve the technical problem of parasitic capacitance change caused by process deviation of the array substrate.

Description

Technical Field

[0001] The present application relates to the field of display, and in particular to a special-shaped thin film transistor and an array substrate. Background Art

[0002] Liquid Crystal Display (LCD) is the most widely used display at present. Compared with traditional CRT displays, it has the advantages of thin body, low power consumption, and low voltage drive. The display area of ​​​​the LCD includes multiple pixel areas. Each pixel area is an area defined by two gate lines and two data lines, and a thin film transistor and a pixel electrode as a switching component are installed in it.

[0003] like Figure 1 As shown, the array substrate of the liquid crystal display panel is provided with a thin film transistor, which includes a gate 1, an active layer 2, a drain 3 and a source 4. The active layer 2 is provided above the gate 1, and the drain 3 and the source 4 are provided above the active layer 2. The drain 3 and the source 4 are respectively connected to the active layer 2. The overlapping portion of the source 4 and the gate 1 generates a parasitic capacitance. The relationship between the parasitic capacitance and the feed voltage is as follows:

[0004]

[0005] Where ΔV is the feed voltage, C gs is the parasitic capacitance generated by the source 4 and the gate 1, C lc is the capacitance on both sides of the liquid crystal layer of the liquid crystal display panel, C st is the storage capacitor, V gh is the turn-on voltage of the thin film transistor, V gl is the off-state voltage of the thin film transistor.

[0006] From the above formula, we can know that parasitic capacitance will affect the magnitude of the feed voltage. In the process of manufacturing the array substrate, due to process deviation, the source 4 will shift left and right, such as Figure 1 As shown, when the source 4 shifts to the left, the overlapping area of ​​the source 4 and the gate 1 will increase. At this time, the parasitic capacitance will also increase. According to the above formula, the feed voltage will also increase. At this time, an AC voltage component will appear in the liquid crystal display panel, which may easily cause screen flickering and afterimage problems.

[0007] Therefore, a technical solution that can solve the above problems is urgently needed. Summary of the Invention

[0008] The embodiments of the present application provide a special-shaped thin film transistor and an array substrate, which can solve the technical problem of parasitic capacitance variation of the array substrate due to process deviation.

[0009] An embodiment of the present application provides a special-shaped thin film transistor, the special-shaped thin film transistor comprising:

[0010] a first grid portion;

[0011] a first compensation electrode, located on one side of the first gate portion, the first compensation electrode being connected to the first gate portion;

[0012] A first source electrode, the first source electrode and the first gate electrode are arranged in a different layer, the first source electrode and the first compensation electrode are arranged in a different layer, the first source electrode includes a first extension portion, a first source portion and a second extension portion, the first extension portion is connected to the first source portion, and the second extension portion is connected to the first source portion; a part of the first extension portion is overlapped with the first gate portion; a part of the second extension portion is overlapped with the first compensation electrode.

[0013] Under this structure, when the first source electrode shifts left or right due to the process, the total overlapping area of ​​the first gate portion and the first compensation electrode with the first source electrode can always remain unchanged, thereby solving the technical problem of parasitic capacitance changes caused by process deviations.

[0014] Optionally, in some embodiments of the present application, the extending direction of the first extending portion is parallel to the extending direction of the second extending portion, and the extending direction of the first extending portion is opposite to the extending direction of the second extending portion.

[0015] In this structure, the shape of the first source electrode is simple and easy to manufacture, and the manufacturing process difficulty of the special-shaped thin film transistor is not increased.

[0016] Optionally, in some embodiments of the present application, in a direction perpendicular to the extension direction of the first extension portion or the second extension portion, the width of the first extension portion is equal to the width of the second extension portion.

[0017] Under this structure, even if the first source electrode is shifted left or right due to process deviation, it can be ensured that the change in the overlapping area between the first extension portion and the first gate portion is equal to the change in the overlapping area between the second extension portion and the first compensation electrode, so that the parasitic capacitance of the special-shaped thin film transistor remains unchanged.

[0018] Optionally, in some embodiments of the present application, in the extension direction of the first extension portion or the second extension portion, the first extension portion and the second extension portion are at least partially overlapped or staggered.

[0019] Under this structure, when the first extension portion and the second extension portion at least partially overlap in the first direction, the space occupied by the first source can be reduced, which is conducive to the miniaturization design of the special-shaped thin-film transistor; when the first extension portion and the second extension portion are staggered in the first direction, the area of ​​the first source can be increased, thereby reducing the contact resistance of the first source, reducing energy loss, and improving the performance of the special-shaped thin-film transistor.

[0020] Optionally, in some embodiments of the present application, the special-shaped thin film transistor further includes:

[0021] a second compensation electrode, provided in a different layer from the first source electrode, and connected to the first gate portion;

[0022] a third compensation electrode disposed in a different layer from the first source electrode, the third compensation electrode being connected to the first gate portion, the third compensation electrode being disposed on one side of the second compensation electrode in a direction perpendicular to an extension direction of the first extension portion or the second extension portion, and the first source portion being disposed between the second compensation electrode and the third compensation electrode;

[0023] The first source electrode also includes a third extension portion and a fourth extension portion, the third extension portion is connected to the first source portion, and a portion of the third extension portion is overlapped with the second compensation electrode; the fourth extension portion is connected to the first source portion, and a portion of the fourth extension portion is overlapped with the third compensation electrode.

[0024] Under this structure, when the first source electrode is shifted up and down due to the process, the total area of ​​the first gate portion and the first compensation electrode overlapping with the first source electrode can always remain unchanged, and the total area of ​​the second compensation electrode and the third compensation electrode overlapping with the first source electrode can always remain unchanged, thereby solving the technical problem of parasitic capacitance changes caused by process deviations.

[0025] Optionally, in some embodiments of the present application, the extension direction of the third extension portion is parallel to the extension direction of the fourth extension portion, and the extension direction of the third extension portion is opposite to the extension direction of the fourth extension portion; the extension direction of the third extension portion intersects with the extension direction of the first extension portion.

[0026] In this structure, the shape of the first source electrode is simple and easy to manufacture, and the manufacturing process difficulty of the special-shaped thin film transistor is not increased.

[0027] Optionally, in some embodiments of the present application, the first extension portion is arranged between the first compensation electrode and the edge of the first gate portion on the side away from the first compensation electrode, and the second extension portion is arranged between the first gate portion and the edge of the first compensation electrode on the side away from the first gate portion.

[0028] With this structure, it can be ensured that the total overlapping area of ​​the first gate portion and the first compensation electrode with the first source electrode can always remain unchanged.

[0029] An embodiment of the present application also provides an array substrate, which includes the special-shaped thin film transistor as described above, and the array substrate also includes a gate line and a data line, the first gate portion and the first compensation electrode are arranged on the same side of the gate line, the first compensation electrode is arranged on one side of the first gate portion along the extension direction of the gate line, the first compensation electrode is connected to the first gate portion through the gate line, and the data line is connected to the first source.

[0030] Under this structure, when the first source electrode shifts left or right due to the process, the total overlapping area of ​​the first gate portion and the first compensation electrode with the first source electrode can always remain unchanged, thereby solving the technical problem of parasitic capacitance changes caused by process deviations.

[0031] Optionally, in some embodiments of the present application, the array substrate is provided with a sub-pixel area, and the sub-pixel area includes a first area and a second area;

[0032] The array substrate further includes a first pixel electrode and a second pixel electrode, wherein the first pixel electrode is arranged corresponding to the first area, and the second pixel electrode is arranged corresponding to the second area;

[0033] The array substrate includes two special-shaped thin film transistors, which are a first special-shaped thin film transistor and a second special-shaped thin film transistor. The first source of the first special-shaped thin film transistor and the first source of the second special-shaped thin film transistor are electrically connected to the first pixel electrode and the second pixel electrode respectively.

[0034] Under this structure, the voltage driving the first pixel electrode is independently controlled by the first special-shaped thin-film transistor, and the voltage driving the second pixel electrode is independently controlled by the second special-shaped thin-film transistor. This arrangement makes the voltages of the first pixel electrode and the second pixel electrode different, which is conducive to realizing multi-domain display.

[0035] Optionally, in some embodiments of the present application, the first gate portion of the first special-shaped thin film transistor is connected to the gate line through the first gate portion of the second special-shaped thin film transistor; the extension direction of the first extension portion of the first special-shaped thin film transistor intersects with the extension direction of the first extension portion of the second special-shaped thin film transistor.

[0036] With this structure, the space of the array substrate can be reasonably allocated, and the structures of the first special-shaped thin film transistor and the second special-shaped thin film transistor are compact, which is beneficial to improving the aperture ratio.

[0037] The present invention employs a special-shaped thin-film transistor and array substrate. A first compensation electrode is disposed on one side of a first gate portion, connected to the first gate portion. A first source portion is disposed between the first gate portion and the first compensation electrode. The first source portion extends toward the first gate portion to form a first extension portion, partially overlapping the first gate portion. The first source portion also extends toward the first compensation electrode to form a second extension portion, partially overlapping the first compensation electrode. If the first source electrode shifts left or right due to manufacturing process variations, the total overlapping area of ​​the first gate portion, the first compensation electrode, and the first source electrode remains constant, thereby resolving the technical issue of parasitic capacitance variations caused by manufacturing process variations. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0039] Figure 1 It is a structural diagram of an array substrate of conventional technology;

[0040] Figure 2 This is a structural diagram of a first array substrate provided in an embodiment of the present application;

[0041] Figure 3 is a structural diagram of a second array substrate provided in an embodiment of the present application;

[0042] Figure 4 is a structural diagram of a third array substrate provided in an embodiment of the present application;

[0043] Figure 5 Schematic diagram of equivalent circuit principles of the first, second and third types of array substrates;

[0044] Figure 6 is a structural diagram of a fourth array substrate provided in an embodiment of the present application;

[0045] Figure 7 is a structural schematic diagram of the fifth array substrate provided in an embodiment of the present application;

[0046] Figure 8 is a structural diagram of a sixth array substrate provided in an embodiment of the present application;

[0047] Figure 9 is a structural schematic diagram of a seventh array substrate provided in an embodiment of the present application;

[0048] Figure 10is a schematic diagram of the equivalent circuit principles of the fourth, fifth, sixth and seventh array substrates;

[0049] Figure 11 is a schematic structural diagram of a display panel provided in an embodiment of the present application;

[0050] Figure 12 It is a structural schematic diagram of the display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0051] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, unless otherwise specified, the directional words used, such as "upper" and "lower", generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the accompanying drawings; and "inside" and "outside" refer to the outline of the device.

[0052] The embodiments of the present application provide a special-shaped thin-film transistor and an array substrate. Detailed descriptions are provided below. It should be noted that the order in which the following embodiments are described does not limit the preferred order of the embodiments.

[0053] See also Figure 2 An embodiment of the present application provides an array substrate 100, including a special-shaped thin film transistor T1, which includes a first gate portion 111 and a first compensation electrode 112. The first compensation electrode 112 is located on one side of the first gate portion 111, and the first compensation electrode 112 is connected to the first gate portion 111, that is, the first compensation electrode 112 is electrically connected to the first gate portion 111.

[0054] In the embodiment of the present application, the first compensation electrode 112 is spaced apart from the first gate portion 111, with a gap therebetween, and the first compensation electrode 112 and the first gate portion 111 are located in the same layer. Of course, depending on actual circumstances and specific requirements, the first compensation electrode 112 and the first gate portion 111 can be located in different layers, as long as the first compensation electrode 112 is connected to the first gate portion 111 and a gap is therebetween in a direction parallel to the array substrate 100. This is not a strict limitation.

[0055] Specifically, the special-shaped thin-film transistor T1 further includes a first source electrode 140. The first source electrode 140 is disposed in a different layer from the first gate portion 111. The first source electrode 140 is also disposed in a different layer from the first compensation electrode 112. That is, the first gate portion 111 and the first compensation electrode 112 are located in different layers from the first source electrode 140. The first source electrode 140 includes a first extension portion 142, a first source portion 141, and a second extension portion 143. The first extension portion 142 is connected to the first source portion 141, and the second extension portion 143 is connected to the first source portion 141. The first source portion 141 is located between the first gate portion 111 and the first compensation electrode 112. The first extension portion 142 partially overlaps with the first gate portion 111, and the second extension portion 143 partially overlaps with the first compensation electrode 112. In this embodiment, the first extension portion 142 is disposed on a side of the first source portion 141 close to the first gate portion 111 , and the second extension portion 143 is disposed on a side of the first source portion 141 close to the first compensation electrode 112 .

[0056] In the array substrate 100 of the embodiment of the present application, a first compensation electrode 112 is disposed on one side of the first gate portion 111, the first compensation electrode 112 being connected to the first gate portion 111. A first source portion 141 is disposed between the first gate portion 111 and the first compensation electrode 112. The first source portion 141 extends toward the first gate portion 111 to form a first extension portion 142, with a portion of the first extension portion 142 overlapping the first gate portion 111. The first source portion 141 extends toward the first compensation electrode 112 to form a second extension portion 143, with a portion of the second extension portion 143 overlapping the first compensation electrode 112. In this structure, the parasitic capacitance of the special-shaped thin-film transistor T1 is equal to the capacitance between the first extension portion 142 and the first gate portion 111 plus the capacitance between the second extension portion 143 and the first compensation electrode 112.

[0057] When the first source electrode 140 shifts to the left due to the manufacturing process, the overlapping area between the first extension portion 142 and the first gate portion 111 increases, and the capacitance between the first extension portion 142 and the first gate portion 111 increases. The overlapping area between the second extension portion 143 and the first compensation electrode 112 decreases, and the capacitance between the second extension portion 143 and the first compensation electrode 112 decreases. The change in capacitance between the first extension portion 142 and the first gate portion 111 is equal to the change in capacitance between the second extension portion 143 and the first compensation electrode 112, thereby keeping the parasitic capacitance of the shaped thin-film transistor T1 unchanged. Similarly, when the first source electrode 140 shifts to the right due to the manufacturing process, the parasitic capacitance of the shaped thin-film transistor T1 remains unchanged. Therefore, the technical solution of the present application can solve the technical problem of increased parasitic capacitance due to process deviation.

[0058] Specifically, the first extension portion 142 is disposed between the first compensation electrode 112 and an edge of the first gate portion 111 away from the first compensation electrode 112, and the second extension portion 143 is disposed between the first gate portion 111 and an edge of the first compensation electrode 112 away from the first gate portion 111. Preferably, in the extension direction of the first extension portion 142, a gap exists between the first extension portion 142 and an edge of the first gate portion 111 away from the first compensation electrode 112, and a gap exists between the second extension portion 143 and an edge of the first compensation electrode 112 away from the first gate portion 111. With this structure, the total overlapping area of ​​the first gate portion 111 and the first compensation electrode 112 with the first source electrode 140 can be ensured to remain constant.

[0059] Specifically, such as Figure 2 As shown, the special-shaped thin-film transistor T1 further includes a first active layer 120 and a first drain electrode 130. The first active layer 120 and the first gate portion 111 are provided in a different layer, and the first active layer 120 and the first gate portion 111 are at least partially overlapped. The first drain electrode 130 is provided in a different layer from the first gate portion 111 and is also provided in a different layer from the first compensation electrode 112. The first drain electrode 130 and the first source electrode 140 are respectively connected to the first active layer 120.

[0060] In the embodiment of the present application, the first active layer 120 is arranged above the first gate portion 111, and the first source 140 and the first drain 130 are arranged in the same layer and above the first active layer 120. Of course, according to the actual selection and specific needs, the stacking order of the first gate portion 111, the first active layer 120, the first source 140 and the first drain 130 can be appropriately modified, and no sole limitation is made here.

[0061] Specifically, such as Figure 2 As shown, the array substrate 100 further includes a first pixel electrode P1, which is connected to the first source electrode 140. Specifically, the first pixel electrode P1 can be connected to the first source portion 141 of the first source electrode 140 through a via hole, thereby transmitting voltage to the first pixel electrode P1.

[0062] Specifically, such as Figure 2As shown, the array substrate 100 further includes a gate line SL and a data line DL. The gate line SL is provided in the same layer as the first gate portion 111, and the data line DL is provided in the same layer as the first source electrode 140. The gate line SL extends along a first direction X, and the data line DL extends along a second direction Y, with the first direction X and the second direction Y intersecting. In the embodiment of the present application, the first direction X and the second direction Y can be perpendicular to each other. Of course, depending on the actual situation and specific needs, the first direction X and the second direction Y can be arranged at other angles, which is not limited here. In this embodiment, the first drain electrode 130 is connected to the data line DL, that is, the first drain electrode 130 is electrically connected to the data line DL.

[0063] Specifically, such as Figure 2 As shown, the first gate portion 111 and the first compensation electrode 112 are disposed on the same side of the gate line SL. The first compensation electrode 112 is disposed on one side of the first gate portion 111 along the first direction X. The first compensation electrode 112 is connected to the first gate portion 111 via the gate line SL. With this structure, the space of the array substrate 100 can be reasonably allocated, which is conducive to the miniaturization of the special-shaped thin film transistor T1.

[0064] Specifically, the first extension portion 142 and the second extension portion 143 are both strip-shaped, wherein the extension direction of the first extension portion 142 and the extension direction of the second extension portion 143 are both parallel to the first direction X, and the extension direction of the first extension portion 142 and the extension direction of the second extension portion 143 are opposite. With this structure, the shape of the first source electrode 140 is simple and easy to manufacture, without increasing the difficulty of the process of manufacturing the special-shaped thin film transistor T1.

[0065] Specifically, in the second direction Y, the width of the first extension portion 142 is equal to the width of the second extension portion 143. With this structure, even if the first source electrode 140 shifts left or right due to process variations, the change in the overlapping area between the first extension portion 142 and the first gate portion 111 is ensured to be equal to the change in the overlapping area between the second extension portion 143 and the first compensation electrode 112, thereby maintaining the parasitic capacitance of the special-shaped thin-film transistor T1.

[0066] Specifically, such as Figure 2 As shown, in the first direction X, the first extension portion 142 and the second extension portion 143 completely overlap, that is, the first extension portion 142 is located on the extension line of the second extension portion 143. This structure can reduce the space occupied by the first source electrode 140, which is conducive to the miniaturization of the special-shaped thin-film transistor T1. Of course, depending on the actual situation and specific requirements, the first extension portion 142 and the second extension portion 143 can also partially overlap in the first direction X, and this is not a strict limitation here.

[0067] In another embodiment of the present application, Figure 3As shown, in the first direction X, the first extension portion 142 and the second extension portion 143 are staggered, that is, the first extension portion 142 is arranged to avoid the extension line of the second extension portion 143. With this structure, the area of ​​the first source electrode 140 can be increased, thereby reducing the contact resistance of the first source electrode 140, reducing energy loss, and improving the performance of the special-shaped thin film transistor T1.

[0068] Specifically, such as Figure 4 As shown, the special-shaped thin film transistor T1 further includes a second compensation electrode 113, which is arranged in a different layer from the first source electrode 140, and the second compensation electrode 113 is connected to the first gate portion 111. Specifically, the second compensation electrode 113 is connected to the gate line SL, and the second compensation electrode 113 is connected to the first gate portion 111 through the gate line SL.

[0069] The special-shaped thin film transistor T1 also includes a third compensation electrode 114, which is arranged in a different layer from the first source electrode 140. The third compensation electrode 114 is connected to the first gate portion 111. The third compensation electrode 114 is arranged on one side of the second compensation electrode 113 along the second direction Y, and the first source portion 141 is arranged between the second compensation electrode 113 and the third compensation electrode 114.

[0070] The first source electrode 140 further includes a third extension portion 144 and a fourth extension portion 145. The third extension portion 144 is connected to the first source portion 141, and a portion of the third extension portion 144 overlaps with the second compensation electrode 113. The fourth extension portion 145 is connected to the first source portion 141, and a portion of the fourth extension portion 145 overlaps with the third compensation electrode 114. In this embodiment, the third extension portion 144 is connected to a side of the first source portion 141 that is close to the second compensation electrode 113, and the fourth extension portion 145 is connected to a side of the first source portion 141 that is close to the third compensation electrode 114.

[0071] In the array substrate 100 of the present embodiment, a second compensation electrode 113 is disposed on a side of the first source portion 141 close to the gate line SL, and a third compensation electrode 114 is disposed on a side of the first source portion 141 facing away from the gate line SL. This allows the first source portion 141 to be positioned between the second compensation electrode 113 and the third compensation electrode 114. The first source portion 141 extends toward the second compensation electrode 113 to form a third extension 144, which partially overlaps with the second compensation electrode 113. The first source portion 141 extends toward the third compensation electrode 114 to form a fourth extension 145, which partially overlaps with the third compensation electrode 114. In this structure, the sum of the capacitance between the first extension 142 and the first gate portion 111, the capacitance between the second extension 143 and the first compensation electrode 112, the capacitance between the third extension 144 and the second compensation electrode 113, and the capacitance between the fourth extension 145 and the third compensation electrode 114 is the parasitic capacitance of the special-shaped thin-film transistor T1.

[0072] When the first source electrode 140 shifts upward due to the manufacturing process, the overlapping area between the third extension 144 and the second compensation electrode 113 increases, increasing the capacitance between the third extension 144 and the second compensation electrode 113. The overlapping area between the fourth extension 145 and the third compensation electrode 114 decreases, reducing the capacitance between the fourth extension 145 and the third compensation electrode 114. The change in capacitance between the third extension 144 and the second compensation electrode 113 is equal to the change in capacitance between the fourth extension 145 and the third compensation electrode 114, thereby maintaining the parasitic capacitance of the special-shaped thin-film transistor T1. Similarly, when the first source electrode 140 shifts downward due to the manufacturing process, the parasitic capacitance of the special-shaped thin-film transistor T1 also remains unchanged. Therefore, the technical solution of the present application can solve the technical problem of increased parasitic capacitance due to manufacturing process deviations.

[0073] Specifically, such as Figure 4 As shown, the third extension portion 144 and the fourth extension portion 145 are both strip-shaped, wherein the extension direction of the third extension portion 144 and the extension direction of the fourth extension portion 145 are both parallel to the second direction Y, and the extension direction of the third extension portion 144 is opposite to the extension direction of the fourth extension portion 145. With this structure, the shape of the first source electrode 140 is simple and easy to manufacture, without increasing the difficulty of the process of manufacturing the special-shaped thin film transistor T1.

[0074] Specifically, such as Figure 4As shown, the width of the third extension portion 144 is equal to the width of the fourth extension portion 145 in the first direction X. With this structure, even if the first source electrode 140 shifts up or down due to process variations, the change in the overlapping area between the third extension portion 144 and the second compensation electrode 113 is ensured to be equal to the change in the overlapping area between the fourth extension portion 145 and the third compensation electrode 114, thereby maintaining the parasitic capacitance of the special-shaped thin-film transistor T1.

[0075] Specifically, such as Figure 4 As shown, in the second direction Y, the third extension portion 144 and the fourth extension portion 145 completely overlap, that is, the third extension portion 144 is located on the extension line of the fourth extension portion 145. This structure can reduce the space occupied by the first source electrode 140, facilitating the miniaturization of the special-shaped thin-film transistor T1. Of course, depending on actual selection and specific requirements, the third extension portion 144 and the fourth extension portion 145 can also partially overlap or be staggered in the second direction Y, and this is not a strict limitation here.

[0076] Figure 5 for Figures 2 to 4 The equivalent circuit principle diagram of the array substrate 100 of the embodiment shown is as follows. When the array substrate 100 is applied to the display panel 10, the data signal is transmitted from the data line DL to the first drain 130 of the special-shaped thin film transistor T1. When the switching signal is transmitted from the gate line SL to the first gate portion 111 of the special-shaped thin film transistor T1, the data signal is transmitted from the first drain 130 to the first source 140. The first source 140 then transmits the data signal to the first pixel electrode P1. When there is a voltage difference between the first pixel electrode P1 and the common electrode, the liquid crystal can be driven to deflect, thereby displaying the picture. Figures 2 to 4 The array substrate 100 of the illustrated embodiment can be applied to, but is not limited to, an array substrate 100 with a four-domain pixel design.

[0077] Specifically, Figures 6 to 9 Schematic diagrams of the structures of the fourth to seventh array substrates 100 provided in the embodiments of the present application, Figures 6 to 9 The structure of the array substrate 100 shown is similar to Figures 2 to 4The structural differences of the array substrate 100 shown are primarily as follows: Array substrate 100 is provided with a sub-pixel region SP, which includes a first region sp1 and a second region sp2. Array substrate 100 also includes a second pixel electrode P2, with the first pixel electrode P1 disposed corresponding to the first region sp1, the first source electrode 140 connected to the first pixel electrode P1, and the second pixel electrode P2 disposed corresponding to the second region sp2. Array substrate 100 also includes a sub-thin-film transistor T2, which is electrically connected to the second pixel electrode P2. In this structure, the voltage driving the first pixel electrode P1 is independently controlled by the special-shaped thin-film transistor T1, while the voltage driving the second pixel electrode P2 is independently controlled by the sub-thin-film transistor T2. This arrangement results in different voltages for the first pixel electrode P1 and the second pixel electrode P2, facilitating multi-domain display.

[0078] Specifically, such as Figures 6 to 8 As shown, the sub-thin-film transistor T2 includes a second gate portion 211 and a second source electrode 240. The second gate portion 211 is provided on the same layer as the first gate portion 111, and the second source electrode 240 is provided on the same layer as the first source electrode 140. A portion of the second source electrode 240 is connected to the second gate portion 211. The parasitic capacitance of the second region sp2 (the parasitic capacitance of the sub-thin-film transistor T2) is the capacitance between the second gate portion 211 and the second source electrode 240. The parasitic capacitance of the first region sp1 (the parasitic capacitance of the special-shaped thin-film transistor T1) is equal to the capacitance between the first extension portion 142 and the first gate portion 111 plus the capacitance between the second extension portion 143 and the first compensation electrode 112. Therefore, compared to the parasitic capacitance of the second region sp2, the parasitic capacitance of the first region sp1 also includes the capacitance between the second extension portion 143 and the first compensation electrode 112. This portion can compensate for the capacitance difference between the parasitic capacitance of the first region sp1 and the parasitic capacitance of the second region sp2, thereby resolving image flicker and afterimage issues.

[0079] Specifically, such as Figure 9As shown, the array substrate 100 includes two special-shaped thin-film transistors, namely a first special-shaped thin-film transistor and a second special-shaped thin-film transistor. The first special-shaped thin-film transistor and the second special-shaped thin-film transistor are electrically connected to the first pixel electrode and the second pixel electrode, respectively. For ease of description, the first special-shaped thin-film transistor is named special-shaped thin-film transistor T1, and the second special-shaped thin-film transistor is named sub-thin-film transistor T2. Sub-thin-film transistor T2 includes a second gate portion 211 and a fourth compensation electrode 212. The second gate portion 211 is connected to the gate line SL. The fourth compensation electrode 212 is located on one side of the second gate portion 211 and is connected to the second gate portion 211. In other words, the fourth compensation electrode 212 is electrically connected to the second gate portion 211. In this embodiment, the first gate portion 111 is connected to the second gate portion 211, and the first gate portion 111 is connected to the gate line SL through the second gate portion 211, that is, the first gate portion 111 and the second gate portion 211 are an integrally connected structure, and there is no gap between the first gate portion 111 and the second gate portion 211, which can make the structure of the special-shaped thin film transistor T1 and the sub-thin film transistor T2 more compact, which is conducive to miniaturization design.

[0080] In the embodiment of the present application, the second gate portion 211 can be, but is not limited to, disposed on the same layer as the first gate portion 111. The second gate portion 211 and the fourth compensation electrode 212 are spaced apart, with a gap between them, and the second gate portion 211 and the fourth compensation electrode 212 are located in the same layer structure. Of course, depending on actual selection and specific requirements, the second gate portion 211 and the fourth compensation electrode 212 can be located in different layers of the structure, as long as the second gate portion 211 and the fourth compensation electrode 212 are connected and a gap is left between them in a direction parallel to the array substrate 100. This is not a strict limitation here.

[0081] Specifically, the array substrate 100 further includes a second source electrode 240, which is disposed in a different layer from the second gate portion 211 and the fourth compensation electrode 212. The second source electrode 240 includes a fifth extension 242, a second source portion 241, and a sixth extension 243. The fifth extension 242 is connected to the second source portion 241, and the sixth extension 243 is connected to the second source portion 241. The second source portion 241 is located between the second gate portion 211 and the fourth compensation electrode 212. A portion of the fifth extension 242 overlaps with the second gate portion 211, and a portion of the sixth extension 243 overlaps with the fourth compensation electrode 212. In this embodiment, the second source electrode 240 is disposed in the same layer as the first source electrode 140 and is connected to the second pixel electrode P2. In this embodiment, the fifth extension portion 242 is disposed on a side of the second source portion 241 close to the second gate portion 211 , and the sixth extension portion 243 is located on a side of the second source portion 241 close to the fourth compensation electrode 212 .

[0082] In the array substrate 100 of the present embodiment, a fourth compensation electrode 212 is disposed on one side of the second gate portion 211, the fourth compensation electrode 212 being connected to the second gate portion 211. A second source portion 241 is disposed between the second gate portion 211 and the fourth compensation electrode 212. The second source portion 241 extends toward the second gate portion 211 to form a fifth extension portion 242, with a portion of the fifth extension portion 242 overlapping the second gate portion 211. The second source portion 241 extends toward the fourth compensation electrode 212 to form a sixth extension portion 243, with a portion of the sixth extension portion 243 overlapping the fourth compensation electrode 212. In this structure, the parasitic capacitance of the sub-thin-film transistor T2 is equal to the capacitance between the fifth extension portion 242 and the second gate portion 211 plus the capacitance between the sixth extension portion 243 and the fourth compensation electrode 212.

[0083] When the second source electrode 240 shifts downward due to the manufacturing process, the overlapping area between the fifth extension 242 and the second gate portion 211 increases, increasing the capacitance between the fifth extension 242 and the second gate portion 211. The overlapping area between the sixth extension 243 and the fourth compensation electrode 212 decreases, reducing the capacitance between the sixth extension 243 and the fourth compensation electrode 212. The change in capacitance between the fifth extension 242 and the second gate portion 211 is equal to the change in capacitance between the sixth extension 243 and the fourth compensation electrode 212, thereby maintaining the parasitic capacitance of the sub-thin-film transistor T2. Similarly, when the second source electrode 240 shifts upward due to the manufacturing process, the parasitic capacitance of the sub-thin-film transistor T2 remains unchanged. Therefore, the technical solution of the present application can solve the technical problem of increased parasitic capacitance due to manufacturing process deviations.

[0084] Specifically, the secondary thin-film transistor T2 further includes a second active layer 220 and a second drain electrode 230. The second active layer 220 and the second gate portion 211 are disposed in a separate layer, and the second active layer 220 and the second gate portion 211 at least partially overlap. The second drain electrode 230 and the second gate portion 211 are disposed in a separate layer, and the second drain electrode 230 is also disposed in a separate layer from the fourth compensation electrode 212. The second drain electrode 230 and the second source electrode 240 are respectively connected to the second active layer 220. In this embodiment, the first active layer 120 and the second active layer 220 are connected, that is, the first active layer 120 and the second active layer 220 are connected as an integral structure, with no gap between the first active layer 120 and the second active layer 220. This makes the structures of the special-shaped thin-film transistor T1 and the secondary thin-film transistor T2 more compact, facilitating miniaturization.

[0085] In an embodiment of the present application, the second active layer 220 is arranged on the same layer as the first active layer 120 and is arranged above the second gate portion 211, and the second source 240 and the second drain 230 are arranged on the same layer and are arranged above the second active layer 220. Of course, according to the actual selection and specific needs, the stacking order of the second gate portion 211, the second active layer 220, the second source 240 and the second drain 230 can be appropriately modified, and is not limited here.

[0086] Specifically, the fourth compensation electrode 212 is disposed on one side of the second gate portion 211 along the second direction Y. Under this structure, the space of the array substrate 100 can be reasonably allocated, which is conducive to the miniaturization design of the sub-thin film transistor T2.

[0087] Specifically, the fifth extension portion 242 and the sixth extension portion 243 are both strip-shaped, wherein the extension direction of the fifth extension portion 242 and the extension direction of the sixth extension portion 243 are both parallel to the second direction Y, and the extension direction of the fifth extension portion 242 is opposite to the extension direction of the sixth extension portion 243. With this structure, the shape of the second source electrode 240 is simple and easy to manufacture, without increasing the difficulty of the manufacturing process of the secondary thin-film transistor T2.

[0088] Specifically, the width of the fifth extension 242 is equal to the width of the sixth extension 243 in the first direction X. With this structure, even if the second source electrode 240 shifts up or down due to process variations, the change in the overlapping area between the fifth extension 242 and the second gate portion 211 is ensured to be equal to the change in the overlapping area between the sixth extension 243 and the fourth compensation electrode 212, thereby maintaining the parasitic capacitance of the sub-thin-film transistor T2.

[0089] Specifically, such as Figure 6As shown, in the second direction Y, the fifth extension portion 242 and the sixth extension portion 243 completely overlap, that is, the fifth extension portion 242 is located on the extension line of the sixth extension portion. This structure can reduce the space occupied by the second source electrode 240, facilitating the miniaturization of the secondary thin-film transistor T2. Of course, depending on actual circumstances and specific requirements, the fifth extension portion 242 and the sixth extension portion 243 may also partially overlap in the second direction Y, and this is not a strict limitation here.

[0090] In another embodiment of the present application, Figure 7 As shown, in the second direction Y, the fifth extension portion 242 and the sixth extension portion 243 are staggered, that is, the fifth extension portion 242 is arranged to avoid the extension line of the sixth extension portion 243. With this structure, the area of ​​the second source electrode 240 can be increased, thereby reducing the contact resistance of the second source electrode 240, reducing energy loss, and improving the performance of the secondary thin film transistor T2.

[0091] Specifically, such as Figure 9 As shown, the sub-thin-film transistor T2 further includes a fifth compensation electrode 213 and a sixth compensation electrode 214. The fifth compensation electrode 213 is disposed in a separate layer from the second source electrode 240. The second gate portion 211 is connected to the fifth compensation electrode 213, i.e., the second gate portion 211 is electrically connected to the fifth compensation electrode 213. The sixth compensation electrode 214 is disposed in a separate layer from the second source electrode 240. The second gate portion 211 is connected to the sixth compensation electrode 214, i.e., the second gate portion 211 is electrically connected to the sixth compensation electrode 214. The sixth compensation electrode 214 is disposed on one side of the fifth compensation electrode 213 along the first direction X, with the second source portion 241 disposed between the fifth compensation electrode 213 and the sixth compensation electrode 214. In this embodiment, the fourth compensation electrode 212 is connected to the second gate portion 211 via the fifth compensation electrode 213 and the sixth compensation electrode 214.

[0092] The second source electrode 240 further includes a seventh extension portion 244 and an eighth extension portion 245. The seventh extension portion 244 is connected to the second source portion 241, and a portion of the seventh extension portion 244 overlaps with the fifth compensation electrode 213. The eighth extension portion 245 is connected to the second source portion 241, and a portion of the eighth extension portion 245 overlaps with the sixth compensation electrode 214. In this embodiment, the seventh extension portion 244 is connected to a side of the second source portion 241 that is close to the fifth compensation electrode 213, and the eighth extension portion 245 is connected to a side of the second source portion 241 that is close to the sixth compensation electrode 214.

[0093] In the array substrate 100 of the present embodiment, the fifth compensation electrode 213 is disposed on one side of the second source portion 241 along the first direction X, and the sixth compensation electrode 214 is disposed on the side of the second source portion 241 facing away from the fifth compensation electrode 213. This allows the second source portion 241 to be positioned between the fifth compensation electrode 213 and the sixth compensation electrode 214. The second source portion 241 extends toward the fifth compensation electrode 213 to form a seventh extension portion 244, which partially overlaps with the fifth compensation electrode 213. The second source portion 241 extends toward the sixth compensation electrode 214 to form an eighth extension portion 245, which partially overlaps with the sixth compensation electrode 214. In this structure, the sum of the capacitance between a portion of the fifth extension portion 242 and the second gate portion 211, the capacitance between the sixth extension portion 243 and the fourth compensation electrode 212, the capacitance between the seventh extension portion 244 and the fifth compensation electrode 213, and the capacitance between the eighth extension portion 245 and the sixth compensation electrode 214 constitutes the parasitic capacitance of the sub-thin-film transistor T2.

[0094] When the second source electrode 240 shifts to the left due to manufacturing process variations, the overlapping area between the seventh extension 244 and the fifth compensation electrode 213 increases, increasing the capacitance between the seventh extension 244 and the fifth compensation electrode 213. The overlapping area between the eighth extension 245 and the sixth compensation electrode 214 decreases, reducing the capacitance between the eighth extension 245 and the sixth compensation electrode 214. The change in capacitance between the seventh extension 244 and the fifth compensation electrode 213 equals the change in capacitance between the eighth extension 245 and the sixth compensation electrode 214, thereby maintaining the parasitic capacitance of the sub-thin-film transistor T2. Similarly, when the second source electrode 240 shifts to the right due to manufacturing process variations, the parasitic capacitance of the sub-thin-film transistor T2 remains unchanged. Therefore, the technical solution of the present application can address the technical issue of increased parasitic capacitance due to manufacturing process variations.

[0095] Specifically, such as Figure 9 As shown, the seventh extension portion 244 and the eighth extension portion 245 are both strip-shaped. The extension directions of the seventh extension portion 244 and the eighth extension portion 245 are both parallel to the first direction X, and the extension directions of the seventh extension portion 244 and the eighth extension portion 245 are opposite to each other. With this structure, the second source electrode 240 has a simple shape and is easy to manufacture, without increasing the manufacturing process complexity of the secondary thin-film transistor T2.

[0096] Specifically, such as Figure 9As shown, the width of the seventh extension portion 244 is equal to the width of the eighth extension portion 245 in the second direction Y. With this structure, even if the second source electrode 240 shifts left or right due to process variations, the change in the overlapping area between the seventh extension portion 244 and the fifth compensation electrode 213 is ensured to be equal to the change in the overlapping area between the eighth extension portion 245 and the sixth compensation electrode 214, thereby maintaining the parasitic capacitance of the sub-thin-film transistor T2.

[0097] Specifically, such as Figure 9 As shown, in the first direction X, the seventh extension portion 244 and the eighth extension portion 245 completely overlap, that is, the seventh extension portion 244 is located on the extension line of the eighth extension portion 245. This structure can reduce the space occupied by the second source electrode 240, facilitating the miniaturization of the secondary thin-film transistor T2. Of course, depending on actual conditions and specific requirements, the seventh extension portion 244 and the eighth extension portion 245 can also partially overlap or be staggered in the first direction X, and this is not a strict limitation here.

[0098] It can be understood that the sub-thin film transistor T2 in the embodiment of the present application is a second special-shaped thin film transistor, and the second gate portion 211, the fourth compensation electrode 212, the fifth compensation electrode 213, the sixth compensation electrode 214, the fifth extension portion 242, the second source portion 241, the sixth extension portion 243, the seventh extension portion 244 and the eighth extension portion 245 of the sub-thin film transistor T2 are respectively the first gate portion, the first compensation electrode, the second compensation electrode, the third compensation electrode, the first extension portion, the first source portion, the second extension portion, the third extension portion and the fourth extension portion of the second special-shaped thin film transistor, and the first gate portion of the first special-shaped thin film transistor is connected to the gate line through the first gate portion of the second special-shaped thin film transistor; the extension direction of the first extension portion of the first special-shaped thin film transistor intersects with the extension direction of the first extension portion of the second special-shaped thin film transistor.

[0099] Specifically, such as Figures 6 to 9As shown, the array substrate 100 further includes a shared thin-film transistor T3, which includes a third gate portion 310, a third active layer 320, a third drain electrode 330, and a third source electrode 340. The third gate portion 310 is connected to the gate line SL, the third active layer 320 is disposed above the third gate portion 310, and the third drain electrode 330 and the third source electrode 340 are disposed above the third active layer 320. The third drain electrode 330 and the third source electrode 340 are respectively connected to the third active layer 320. In this embodiment, the third source electrode 340 is connected to the second pixel electrode P2. In this embodiment, the third gate portion 310 is connected to the first compensation electrode 112, that is, the third gate portion 310 and the first compensation electrode 112 are integrally connected. There is no gap between the third gate portion 310 and the first compensation electrode 112, which can make the structures of the special-shaped thin-film transistor T1 and the shared thin-film transistor T3 more compact, facilitating miniaturization.

[0100] Figure 10 for Figures 6 to 9 The equivalent circuit principle diagram of the array substrate 100 of the embodiment shown is as follows. When the above-mentioned array substrate 100 is applied to the display panel 10, the data signal is transmitted from the data line DL to the first drain 130 of the special-shaped thin film transistor T1. When the switching signal is transmitted from the gate line SL to the first gate portion 111 of the special-shaped thin film transistor T1, the data signal is transmitted from the first drain 130 to the first source 140. The first source 140 then transmits the data signal to the first pixel electrode P1. When the first pixel electrode P1 has a voltage difference with the corresponding common electrode, the liquid crystal in the first region sp1 can be driven to deflect.

[0101] The data signal is transmitted from the data line DL to the second drain 230 of the secondary thin-film transistor T2. When the switching signal is transmitted from the gate line SL to the second gate portion 211 of the secondary thin-film transistor T2, the data signal is transmitted from the second drain 230 to the second source 240, and the second source 240 then transmits the data signal to the second pixel electrode P2. At the same time, when the switching signal is transmitted from the gate line SL to the third gate portion 310 of the shared thin-film transistor T3, the second source 240 distributes a portion of the data signal to the shared thin-film transistor T3. The shared thin-film transistor T3 can play a voltage dividing role, thereby reducing the voltage applied to the second pixel electrode P2, so that the voltages of the first pixel electrode P1 and the second pixel electrode P2 are different, thereby realizing multi-domain display.

[0102] It can be seen that the voltage received by the first pixel electrode P1 is different from the voltage received by the second pixel electrode P2, which is beneficial to multi-domain display. Figures 6 to 9 The array substrate 100 of the illustrated embodiment can be, but is not limited to, applied to an array substrate 100 with an eight-domain pixel design.

[0103] See also Figure 11The embodiment of the present application further provides a display panel 10 , including an opposite substrate 200 and the array substrate 100 as described above, wherein the opposite substrate 200 is arranged opposite to the array substrate 100 .

[0104] See also Figure 12 An embodiment of the present application further provides a display device, including a backlight module 20 and the display panel 10 as described above, wherein the backlight module 20 is disposed on one side of the display panel 10 .

[0105] The above is a detailed introduction to a special-shaped thin-film transistor and an array substrate provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core idea of ​​the present application. At the same time, for those skilled in the art, based on the ideas of the present application, there may be changes in the specific implementation methods and application scopes. In summary, the contents of this specification should not be understood as limiting the present application.

Claims

1. A special-shaped thin film transistor, characterized in that: The special-shaped thin film transistor includes: a first grid portion; a first compensation electrode, located on one side of the first gate portion, the first compensation electrode being connected to the first gate portion; a first source electrode, wherein the first source electrode and the first gate portion are provided in different layers, and the first source electrode and the first compensation electrode are provided in different layers, the first source electrode comprising a first extension portion, a first source portion, and a second extension portion, the first extension portion being connected to the first source portion, and the second extension portion being connected to the first source portion; a portion of the first extension portion being overlapped with the first gate portion; and a portion of the second extension portion being overlapped with the first compensation electrode; The special-shaped thin film transistor further includes: a second compensation electrode, provided in a different layer from the first source electrode, and connected to the first gate portion; a third compensation electrode disposed in a different layer from the first source electrode, the third compensation electrode being connected to the first gate portion, the third compensation electrode being disposed on one side of the second compensation electrode in a direction perpendicular to an extension direction of the first extension portion or the second extension portion, and the first source portion being disposed between the second compensation electrode and the third compensation electrode; The first source electrode also includes a third extension portion and a fourth extension portion, the third extension portion is connected to the first source portion, and a portion of the third extension portion is overlapped with the second compensation electrode; the fourth extension portion is connected to the first source portion, and a portion of the fourth extension portion is overlapped with the third compensation electrode.

2. The special-shaped thin film transistor according to claim 1, wherein: An extending direction of the first extending portion is parallel to an extending direction of the second extending portion, and the extending direction of the first extending portion is opposite to an extending direction of the second extending portion.

3. The special-shaped thin film transistor according to claim 2, wherein: In a direction perpendicular to an extending direction of the first extending portion or the second extending portion, a width of the first extending portion is equal to a width of the second extending portion.

4. The special-shaped thin film transistor according to claim 2, wherein: In an extending direction of the first extending portion or the second extending portion, the first extending portion and the second extending portion are at least partially overlapped or staggered.

5. The special-shaped thin film transistor according to claim 2, wherein: The width of the third extension portion is equal to the width of the fourth extension portion.

6. The special-shaped thin film transistor according to claim 5, wherein: An extending direction of the third extending portion is parallel to an extending direction of the fourth extending portion, and is opposite to an extending direction of the fourth extending portion; and an extending direction of the third extending portion intersects with an extending direction of the first extending portion.

7. The special-shaped thin film transistor according to claim 1, wherein: The first extension portion is provided between the first compensation electrode and an edge of the first gate portion away from the first compensation electrode, and the second extension portion is provided between the first gate portion and an edge of the first compensation electrode away from the first gate portion.

8. An array substrate, characterized in that: The array substrate includes the special-shaped thin film transistor according to any one of claims 1 to 7, and the array substrate also includes a gate line and a data line, the first gate portion and the first compensation electrode are arranged on the same side of the gate line, the first compensation electrode is arranged on one side of the first gate portion along the extension direction of the gate line, the first compensation electrode is connected to the first gate portion through the gate line, and the data line is connected to the first source.

9. The array substrate according to claim 8, wherein: The array substrate is provided with a sub-pixel area, and the sub-pixel area includes a first area and a second area; The array substrate further includes a first pixel electrode and a second pixel electrode, wherein the first pixel electrode is arranged corresponding to the first area, and the second pixel electrode is arranged corresponding to the second area; The array substrate includes two special-shaped thin film transistors, which are a first special-shaped thin film transistor and a second special-shaped thin film transistor. The first source of the first special-shaped thin film transistor and the first source of the second special-shaped thin film transistor are electrically connected to the first pixel electrode and the second pixel electrode respectively.

10. The array substrate according to claim 9, wherein: The first gate portion of the first special-shaped thin film transistor is connected to the gate line through the first gate portion of the second special-shaped thin film transistor; an extending direction of the first extending portion of the first special-shaped thin film transistor intersects with an extending direction of the first extending portion of the second special-shaped thin film transistor.

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