A driving circuit and a bridge circuit

Abstract

This invention discloses a driving circuit and a bridge circuit. The driving circuit includes a first driving loop, a second driving loop, and a falling edge delay circuit unit. The first driving loop includes a first switch, a second switch, and a third switch. The first terminal of the first switch is connected to a first power supply signal. The control terminal of the first switch is electrically connected to the control terminal of the second switch, the second terminal of the first switch is electrically connected to the first terminal of the second switch, the second terminal of the second switch is electrically connected to the first terminal of the third switch, the control terminal of the third switch is electrically connected to the control terminal of the first switch, and the first terminal of the third switch is electrically connected to the control terminal of the switch to be driven. The input terminal of the falling edge delay circuit unit is connected to a driving control signal, and the output terminal of the falling edge delay circuit unit is electrically connected to the control terminal of the first switch. The driving circuit and bridge circuit provided by this invention can improve driving capability.

Description

Technical Field

[0001] The embodiments of the present invention relate to power electronics technology, and more particularly to a drive circuit and a bridge circuit. Background Technology

[0002] In switching devices, novel semiconductor devices such as silicon carbide (SiC) and gallium nitride (GaN) have significant application value in improving the efficiency and power density of power electronic converters. In particular, GaN FETs are promising high-speed switching devices, and silicon-based GaN FETs are cheaper than SiC field-effect transistors. Since the switching characteristics, driving techniques, and loss mechanisms of GaN FETs differ significantly from those of Si MOSFETs, achieving rapid driving of GaN FETs is crucial to maximizing their advantages and improving overall system performance.

[0003] Currently, in existing driver circuits and bridge circuits, the delay time of the control electrode drive signal during the switching process of the switching transistor typically accounts for a large proportion of the switching cycle, even leading to logic errors and thus limiting the improvement of switching frequency. Furthermore, when using the original PWM driving method in bridge circuits, the conduction loss of the device during the dead time affects the circuit efficiency. These special factors necessitate special considerations when driving GaN devices, meaning that traditional driver circuits used for silicon-based MOSFETs cannot be directly applied to enhancement-mode GaN FETs, thus affecting the circuit's driving capability. Summary of the Invention

[0004] This invention provides a driving circuit and a bridge circuit to prevent the generation of voltage spikes that could affect the performance of the switching transistors, and to avoid the switching transistors being mistakenly turned on during the turn-off period due to interference factors such as ringing and parasitic parameters, thereby improving the driving capability.

[0005] In a first aspect, embodiments of the present invention provide a driving circuit for driving a switch transistor to be driven, comprising: a first driving circuit, a second driving circuit, and a falling edge delay circuit unit; the first driving circuit includes a first switch transistor, a second switch transistor, and a third switch transistor;

[0006] The first terminal of the first switching transistor is connected to the first power signal. The control terminal of the first switching transistor is electrically connected to the control terminal of the second switching transistor. The second terminal of the first switching transistor is electrically connected to the first terminal of the second switching transistor. The second terminal of the second switching transistor is electrically connected to the first terminal of the third switching transistor. The control terminal of the third switching transistor is electrically connected to the control terminal of the first switching transistor. The first terminal of the third switching transistor is electrically connected to the control terminal of the switching transistor to be driven.

[0007] The input terminal of the second drive circuit is connected to the drive control signal, and the output terminal of the second drive circuit is electrically connected to the second pole of the third switch.

[0008] The input terminal of the falling edge delay circuit unit is connected to the drive control signal, and the output terminal of the falling edge delay circuit unit is electrically connected to the control electrode of the first switching transistor. The falling edge delay circuit unit is used to delay the falling edge of the drive control signal.

[0009] Optionally, the above-mentioned driving circuit further includes a rising edge delay circuit unit; the input terminal of the rising edge delay circuit unit is connected to the driving control signal, and the output terminal of the rising edge delay circuit unit is electrically connected to the input terminal of the second driving loop. The rising edge delay circuit unit is used to delay the rising edge of the driving control signal.

[0010] Optionally, the second drive circuit includes a fourth switch and a fifth switch. The control terminals of the fourth and fifth switches are both connected to the drive control signal. The first terminal of the fourth switch is electrically connected to the second terminal of the first switch. The second terminal of the fourth switch is electrically connected to the second terminal of the third switch. The first terminal of the fifth switch is electrically connected to the second terminal of the fourth switch. The second terminal of the fifth switch is connected to the first reference ground.

[0011] Optionally, the first and fourth switching transistors are both PMOS, while the second, third, and fifth switching transistors are all NMOS.

[0012] Optionally, the above-mentioned driving circuit further includes a first bootstrap power supply circuit and / or a second bootstrap power supply circuit. The first bootstrap power supply circuit includes a first capacitor and a first Zener diode, and the second bootstrap power supply circuit includes a second capacitor and a second Zener diode.

[0013] The first terminal of the first capacitor is electrically connected to the second terminal of the first switching transistor. The second terminal of the first capacitor is connected to the first reference ground. The anode of the first Zener diode is electrically connected to the second terminal of the first capacitor, and the cathode of the first Zener diode is electrically connected to the first terminal of the first capacitor.

[0014] The first terminal of the second capacitor is electrically connected to the second electrode of the switch transistor to be driven, the second terminal of the second capacitor is electrically connected to the second electrode of the fifth switch transistor, the anode of the second Zener diode is electrically connected to the second terminal of the second capacitor, and the cathode of the second Zener diode is electrically connected to the first terminal of the second capacitor.

[0015] Optionally, the above-mentioned driving circuit further includes a first resistor, a second resistor, a third resistor, a fourth resistor, and a fifth resistor; the second terminal of the first switching transistor is electrically connected to the first terminal of the second switching transistor through the first resistor, the first terminal of the third switching transistor is electrically connected to the control terminal of the switching transistor to be driven through the second resistor, the first terminal of the second switching transistor is electrically connected to the control terminal of the first switching transistor through the third resistor, the second terminal of the first switching transistor is electrically connected to the first terminal of the first capacitor through the fourth resistor, and the first terminal of the second capacitor is electrically connected to the first terminal of the fourth switching transistor through the fifth resistor.

[0016] Optionally, the driving circuit further includes a first diode and a second diode. The anode of the first diode is electrically connected to the second terminal of the first switching transistor, and the cathode of the first diode is electrically connected to the first terminal of the first capacitor through a fourth resistor. The anode of the second diode is electrically connected to the first terminal of the fourth switching transistor, and the cathode of the second diode is electrically connected to the first terminal of the second capacitor through a fifth resistor.

[0017] Secondly, embodiments of the present invention also provide a bridge circuit, including the driving circuit as described in the first aspect, and further including a sixth switch and a seventh switch to be driven; the input terminal of the first driving circuit corresponding to the sixth switch is connected to a first driving signal, the first output terminal of the first driving circuit is electrically connected to the control electrode of the sixth switch, and the second output terminal of the first driving circuit is electrically connected to the second electrode of the sixth switch; the input terminal of the second driving circuit corresponding to the seventh switch is connected to a second driving signal, the first output terminal of the second driving circuit is electrically connected to the control electrode of the seventh switch, the second output terminal of the second driving circuit is electrically connected to the second electrode of the seventh switch, and the second electrode of the sixth switch is electrically connected to the second electrode of the seventh switch through an inductor and an impedance.

[0018] Optionally, the first terminal of the sixth switch is connected to the second power supply signal, the second terminal of the sixth switch is electrically connected to the first terminal of the seventh switch, and the second terminal of the seventh switch is connected to the second reference ground.

[0019] Optionally, both the sixth and seventh switching transistors are gallium nitride semiconductor switching transistors.

[0020] The driving circuit and bridge circuit provided in this embodiment of the invention include a first driving circuit, a second driving circuit, and a falling edge delay circuit unit. The first driving circuit includes a first switch, a second switch, and a third switch. The first terminal of the first switch is connected to a first power supply signal, the control terminal of the first switch is electrically connected to the control terminal of the second switch, the second terminal of the first switch is electrically connected to the first terminal of the second switch, the second terminal of the second switch is electrically connected to the first terminal of the third switch, the control terminal of the third switch is electrically connected to the control terminal of the first switch, and the first terminal of the third switch is electrically connected to the control terminal of the switch to be driven. The input terminal of the second driving circuit is connected to a driving control signal, and the output terminal of the second driving circuit is electrically connected to the second terminal of the third switch. The input terminal of the falling edge delay circuit unit is connected to the driving control signal, and the output terminal of the falling edge delay circuit unit is electrically connected to the control terminal of the first switch. The falling edge delay circuit unit is used to delay the falling edge of the driving control signal. The driving circuit and bridge circuit provided in this embodiment of the invention delay the falling edge of the driving control signal through the falling edge delay circuit unit to drive the switch to be driven, preventing the generation of voltage spikes that could affect the performance of the switch, and making the voltage between the control electrode and the second electrode of the switch to be driven a negative voltage turn-off signal, thus avoiding the switch to be driven from being mistakenly turned on by interference factors such as ringing and parasitic parameters during the turn-off period, thereby improving the driving capability. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of a driving circuit provided in Embodiment 1 of the present invention;

[0022] Figure 2 This is a schematic diagram of a driving waveform provided in Embodiment 1 of the present invention;

[0023] Figure 3 This is a schematic diagram of another driving circuit provided in Embodiment 1 of the present invention;

[0024] Figure 4 This is another schematic diagram of the driving waveform provided in Embodiment 1 of the present invention;

[0025] Figure 5 This is a schematic diagram of a bridge circuit provided in Embodiment 2 of the present invention;

[0026] Figure 6 This is a schematic diagram of a driving waveform provided in Embodiment 2 of the present invention;

[0027] Figure 7 This is a schematic diagram of another bridge circuit provided in Embodiment 2 of the present invention;

[0028] Figure 8 This is another driving waveform diagram provided in Embodiment 2 of the present invention. Detailed Implementation

[0029] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, and not all of the structures.

[0030] Example 1

[0031] Figure 1 This is a schematic diagram of a driving circuit provided in Embodiment 1 of the present invention. This embodiment can be applied to driving switching transistors, etc. The driving circuit is used to drive the switching transistor to be driven. The driving circuit 100 includes: a first driving circuit, a second driving circuit and a falling edge delay circuit unit; the first driving circuit includes a first switching transistor Q1, a second switching transistor Q2 and a third switching transistor Q3.

[0032] In this circuit, the first terminal of the first switching transistor Q1 is connected to the first power supply signal Vcc; the control terminal of the first switching transistor Q1 is electrically connected to the control terminal of the second switching transistor Q2; the second terminal of the first switching transistor Q1 is electrically connected to the first terminal of the second switching transistor Q2; the second terminal of the second switching transistor Q2 is electrically connected to the first terminal of the third switching transistor Q3; the control terminal of the third switching transistor Q3 is electrically connected to the control terminal of the first switching transistor Q1; and the first terminal of the third switching transistor Q3 is electrically connected to the control terminal of the switching transistor S to be driven. The input terminal of the second driving circuit is connected to the driving control signal Vpwm; the output terminal of the second driving circuit is electrically connected to the second terminal of the third switching transistor Q3. The input terminal of the falling edge delay circuit unit is connected to the driving control signal Vpwm; the output terminal of the falling edge delay circuit unit is electrically connected to the control terminal of the first switching transistor Q1. The falling edge delay circuit unit is used to delay the falling edge of the driving control signal Vpwm.

[0033] Specifically, Figure 2 This is a schematic diagram of a driving waveform provided in Embodiment 1 of the present invention, combined with... Figure 1 and Figure 2The switch to be driven can be a gallium nitride (GaN) FET. When the drive control signal Vpwm is high, the high-level drive control signal is transmitted to the control electrode of the first switch Q1 through the delay circuit unit. If the first switch Q1 is a PMOS and the second switch Q2 and the third switch Q3 are both NMOS, then the first switch Q1 is quickly turned off and the third switch Q3 is quickly turned on. The control electrode of the second switch Q2 is also connected to a resistor. Due to the delay effect of the resistor, the second switch Q2 is turned on with a delay. At this time, the input capacitor of the switch to be driven S discharges quickly through the third switch Q3 and the second drive circuit. The second electrode of the switch to be driven S is also connected to the first reference ground through a parallel capacitor and a Zener diode. The capacitor and the Zener diode form an auxiliary circuit to clamp the potential of the second electrode of the switch to be driven S. The voltage between the control electrode and the second electrode of the switch to be driven S, i.e., the gate-source voltage V, is... GS A negative voltage turn-off signal is used to prevent the driven switch S from being mistakenly turned on during the turn-off period due to interference from factors such as ringing and parasitic parameters. Since the input capacitance of the driven switch S is much lower than that of the second switch Q2, after the input capacitance of the driven switch S has completely discharged, the input capacitance of the second switch Q2 is still charging. Once fully charged, the second switch Q2 turns on. When the drive control signal Vpwm goes low, the drive control signal Vpwm, after a falling edge delay, obtains the following... Figure 2 The waveform shown in Vpwm' causes the voltage V at the control electrode and the second electrode of the switch S to be driven to be... GS During the falling edge delay of the drive control signal Vpwm, the voltage is less than the threshold voltage to prevent voltage V from being lowered. GS A large voltage spike can occur, affecting the performance of the switching transistor S.

[0034] It should be noted that the driving circuit consisting of the first driving circuit, the second driving circuit, and the falling edge delay circuit unit can drive the switch transistor to be driven.

[0035] The driving circuit provided in this embodiment delays the falling edge of the driving control signal by using a falling edge delay circuit unit to drive the switch transistor to be driven, preventing the generation of voltage spikes that could affect the performance of the switch transistor. It also ensures that the voltage between the control electrode and the second electrode of the switch transistor to be driven is a negative voltage turn-off signal, thus avoiding the switch transistor from being mistakenly turned on by interference factors such as ringing and parasitic parameters during the turn-off period, thereby improving the driving capability.

[0036] Figure 3This is a schematic diagram of another driving circuit provided in Embodiment 1 of the present invention. Optionally, the driving circuit 100 further includes a rising edge delay circuit unit; the input terminal of the rising edge delay circuit unit is connected to the driving control signal Vpwm, and the output terminal of the rising edge delay circuit unit is electrically connected to the input terminal of the second driving loop. The rising edge delay circuit unit is used to delay the rising edge of the driving control signal Vpwm.

[0037] Specifically, if only the falling edge delay circuit unit is set, the dead time during the process of the lower transistor turning off and the upper transistor turning on in the bridge circuit can only be set to be very short; otherwise, there will still be some reverse conduction loss. Figure 4 This is a schematic diagram of another driving waveform provided in Embodiment 1 of the present invention. Based on the setting of a falling edge delay circuit unit, a rising edge delay circuit unit is added to the driving circuit. The driving circuit 101 after adding the rising edge delay circuit unit is as follows: Figure 3 As shown, combined with Figure 3 and Figure 4 The drive control signal Vpwm is obtained after being delayed by the falling edge and the rising edge, respectively. Figure 4 The waveforms shown in Vpwm' and Vpwm" indicate that the voltage V at the control electrode and the second electrode of the switch S to be driven is... GS If the voltage is less than the threshold voltage during the falling edge and rising edge delay of the drive control signal Vpwm, the dead time of the switching transistor can be extended without generating reverse conduction loss.

[0038] Optionally, the second drive circuit includes a fourth switch Q4 and a fifth switch Q5. The control terminals of the fourth switch Q4 and the fifth switch Q5 are both connected to the drive control signal. The first terminal of the fourth switch Q4 is electrically connected to the second terminal of the first switch Q1. The second terminal of the fourth switch Q4 is electrically connected to the second terminal of the third switch Q3. The first terminal of the fifth switch Q5 is electrically connected to the second terminal of the fourth switch Q4. The second terminal of the fifth switch Q5 is connected to the first reference ground.

[0039] Specifically, in combination Figure 1 and Figure 2When the drive control signal Vpwm is high, the high-level drive control signal is transmitted to the control terminals of the fourth switch Q4 and the fifth switch Q5 in the second drive circuit. If the fourth switch Q4 is a PMOS and the fifth switch Q5 and the third switch Q3 are both NMOS, then the fourth switch Q4 is turned off, and the fifth switch Q5 and the third switch Q3 are both turned on. The input capacitor of the switch S to be driven discharges quickly through the third switch Q3 and the fifth switch Q5. When the drive control signal Vpwm becomes low, the fourth switch Q4 turns on quickly, and the fifth switch Q5 turns off quickly. The falling edge of the drive control signal output by the falling edge delay circuit unit is delayed, the first switch Q1 is still turned off, and the second switch Q2 and the third switch Q3 are still turned on. At this time, the voltage between the control terminal and the second terminal of the switch S to be driven is about the voltage difference VAB between the electrical connection points A and B, similar to the gate-source voltage of GaNFETs. The voltage VAB is lower than the threshold voltage Vth of GaNFETs.

[0040] Optionally, the first switch Q1 and the fourth switch Q4 are both PMOS, and the second switch Q2, the third switch Q3 and the fifth switch Q5 are all NMOS.

[0041] Specifically, the PMOS transistor is turned off when its gate is high, and the NMOS transistor is turned on when its gate is high. Each switch is configured as either a PMOS or an NMOS transistor based on the specific connection relationship of the components in the drive circuit. They exhibit different switching states when the drive control signal is high or low to meet the drive requirements. For example, when the drive control signal is low, both the first switch Q1 and the fourth switch Q4 are turned on, while the second switch Q2, the third switch Q3, and the fifth switch Q5 are turned off. The switch S to be driven is charged through the turned-on first switch Q1. Furthermore, by using the parasitic capacitance of the NMOS transistor, an accelerating capacitor function can be implemented, increasing the switching frequency of the switch S to be driven, reducing circuit size, and improving circuit reliability.

[0042] Optionally, the drive circuit 100 further includes a first bootstrap power supply circuit and / or a second bootstrap power supply circuit. The first bootstrap power supply circuit includes a first capacitor C1 and a first Zener diode Z1, and the second bootstrap power supply circuit includes a second capacitor C2 and a second Zener diode Z2. The first terminal of the first capacitor C1 is electrically connected to the second terminal of the first switching transistor Q1, and the second terminal of the first capacitor C1 is connected to a first reference ground. The anode of the first Zener diode Z1 is electrically connected to the second terminal of the first capacitor C1, and the cathode of the first Zener diode Z1 is electrically connected to the first terminal of the first capacitor C1. The first terminal of the second capacitor C2 is electrically connected to the second electrode of the switching transistor S to be driven, and the second terminal of the second capacitor C2 is electrically connected to the second electrode of the fifth switching transistor Q5. The anode of the second Zener diode Z2 is electrically connected to the second terminal of the second capacitor C2, and the cathode of the second Zener diode Z2 is electrically connected to the first terminal of the second capacitor C2.

[0043] Specifically, both the first capacitor C1 and the second capacitor C2 can be considered constant voltage sources. Based on the above analysis, when the drive control signal Vpwm goes low, the voltage between the control electrode and the second electrode of the switch S to be driven, such as the gate-source voltage of GaN FETs, is approximately the voltage difference VAB between electrical connection points A and B. The value of the voltage difference VAB is actually determined by the voltage value at point A of the auxiliary circuit composed of the first capacitor C1 and the first Zener diode Z1, and the voltage value at point B of the auxiliary circuit composed of the second capacitor C2 and the second Zener diode Z2. The voltage of the first capacitor C1 and the voltage of the second capacitor C2 can be set according to the actual situation so that the voltage value of the voltage difference VAB is lower than the threshold voltage of the switch S to be driven. At this time, the switch S to be driven is in a pre-charging state.

[0044] Optionally, the driving circuit 100 further includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, and a fifth resistor R5; the second terminal of the first switching transistor Q1 is electrically connected to the first terminal of the second switching transistor Q2 through the first resistor R1, the first terminal of the third switching transistor Q3 is electrically connected to the control terminal of the switching transistor S to be driven through the second resistor R2, the first terminal of the second switching transistor Q2 is electrically connected to the control terminal of the first switching transistor Q1 through the third resistor R3, the second terminal of the first switching transistor Q1 is electrically connected to the first terminal of the first capacitor C1 through the fourth resistor R4, and the first terminal of the second capacitor C2 is electrically connected to the first terminal of the fourth switching transistor Q4 through the fifth resistor R5.

[0045] In this circuit, the third resistor R3 serves as an auxiliary delay resistor, delaying the turn-on of the second switch Q2. When the control signal output from the falling edge delay circuit goes low, the first switch Q1 turns on, and the third switch Q3 turns off. Due to the delay effect of the third resistor R3, the turn-off of the second switch Q2 is delayed. At this time, a higher conduction current flows to the GaN FETs through the branches of the first switch Q1 → first resistor R1 and the third resistor R3 → second switch Q2, providing the gate-source of the GaN FETs with drive charge from the first power supply signal Vcc. The gate of the GaN FETs quickly charges to the threshold voltage. Due to the third resistor R3 → second switch Q2 branch in the drive circuit, the drive circuit 100 causes the gate voltage of the GaN FETs to rise rapidly during the turn-on phase. Furthermore, due to the clamping effect of the gate-source capacitance of the second switch Q2 and the current limiting effect of the first resistor R1, there is no significant gate oscillation during the turn-on process of the GaN FETs.

[0046] Optionally, the driving circuit 100 further includes a first diode D1 and a second diode D2. The anode of the first diode D1 is electrically connected to the second terminal of the first switching transistor Q1, and the cathode of the first diode D1 is electrically connected to the first terminal of the first capacitor C1 through a fourth resistor R4. The anode of the second diode D2 is electrically connected to the first terminal of the fourth switching transistor Q4, and the cathode of the second diode D2 is electrically connected to the first terminal of the second capacitor C2 through a fifth resistor R5.

[0047] Specifically, based on the unidirectional conduction characteristic of diodes, when the first diode D1 is forward-biased, the current in the circuit containing the first diode D1 is transmitted from the anode to the cathode of the first diode D1, preventing the current in the circuit between the cathode of the first diode D1 and the first capacitor C1 from flowing back to the second terminal of the first switch Q1 and the first terminal of the second switch Q2; when the second diode D2 is forward-biased, the current in the circuit containing the second diode D2 is transmitted from the anode to the cathode of the second diode D2, preventing the current in the circuit between the cathode of the second diode D2 and the second capacitor C2 from flowing back to the first terminal of the fourth switch Q4.

[0048] It should be noted that the specific voltage regulation range of the first Zener diode Z1 and the second Zener diode Z2 can be set according to the actual situation, and is not limited here.

[0049] Example 2

[0050] Figure 5This is a schematic diagram of a bridge circuit according to Embodiment 2 of the present invention. The bridge circuit includes a driving circuit as described in any of the above embodiments, and further includes a sixth switch transistor SH and a seventh switch transistor SL to be driven. The input terminal of the first driving circuit 110 corresponding to the sixth switch transistor is connected to a first driving signal. The first output terminal of the first driving circuit 110 is electrically connected to the control electrode of the sixth switch transistor SH, and the second output terminal of the first driving circuit 110 is electrically connected to the second electrode of the sixth switch transistor SH. The input terminal of the second driving circuit 120 corresponding to the seventh switch transistor SL is connected to a second driving signal. The first output terminal of the second driving circuit 120 is electrically connected to the control electrode of the seventh switch transistor SL, and the second output terminal of the second driving circuit 120 is electrically connected to the second electrode of the seventh switch transistor SL. The second electrode of the sixth switch transistor SH is electrically connected to the second electrode of the seventh switch transistor SL through an inductor L0 and an impedance RL.

[0051] Specifically, Figure 6 This is a schematic diagram of a driving waveform provided in Embodiment 2 of the present invention, combined with... Figure 5 and Figure 6 The input terminal of the first driving circuit 110 is connected to the first driving signal Vpwm1, and the input terminal of the second driving circuit 120 is connected to the second driving signal Vpwm2. GS1 V is the voltage between the control electrode and the second electrode of the sixth switching transistor SH. GS2 The voltages at the control and second terminals of the seventh switch SL are connected to the power supply signals Vcc1 and Vcc2, respectively. In the half-bridge circuit, since the freewheeling diode is the lower diode (the seventh switch SL), only the delay circuit unit in the lower diode's drive circuit needs to be configured, such as... Figure 6 The time period t1 to t2 corresponds to the freewheeling time of the lower transistor. During this period, the lower transistor is reverse-conducting, and the gate-source voltage of the lower transistor is V. GS2 The voltage drop is greater than zero. Compared with the traditional driving method, the conduction voltage drop Vsd = Vgd - Vgs (Vgs ≤ 0) is significantly smaller, so the reverse conduction loss can be reduced across the entire range.

[0052] in addition, Figure 7 This is a schematic diagram of another bridge circuit provided in Embodiment 2 of the present invention. Figure 8 This is another driving waveform diagram provided in Embodiment 2 of the present invention, combined with Figure 7 and Figure 8 The driver circuit in the bridge circuit includes not only a falling edge delay circuit unit but also a rising edge delay circuit unit. Similarly, only the delay circuit unit in the driver circuit of the lower transistor, i.e., the seventh switching transistor SL, is included. Figure 8The two time periods t1~t2 and t1'~t2' correspond to the freewheeling time of the lower tube. The reverse conduction loss of the switching tube is further reduced, and the shoot-through situation caused by the dead time being set too short will not occur.

[0053] Optionally, the first terminal of the sixth switch SH is connected to the second power supply signal V. dc The second terminal of the sixth switch SH is electrically connected to the first terminal of the seventh switch SL, and the second terminal of the seventh switch SL is connected to the second reference ground.

[0054] In this configuration, the second terminal of the sixth switch transistor SH is electrically connected to the first terminal of the seventh switch transistor SL, forming a configuration as follows: Figure 7 In the bridge circuit shown, the current in the line containing inductor L0 is i0, that is, the current transmitted through the second terminal of the sixth switch SH through the line containing inductor L0 is i0. The bridge circuit formed by the sixth switch SH and the seventh switch SL is as follows: Figure 7 The bridge circuit shown is a half-bridge circuit.

[0055] Optionally, both the sixth and seventh switching transistors are gallium nitride semiconductor switching transistors.

[0056] Specifically, novel semiconductor devices such as silicon carbide (SiC) and gallium nitride (GaN) have significant application value in improving the efficiency and power density of power electronic converters. In particular, GaN FETs are promising high-speed switching devices, and their cost is lower than that of SiC field-effect transistors. Gallium nitride semiconductor switches, due to their high power density, high switching speed, low power consumption, and low cost, will have broad application prospects.

[0057] The bridge circuit provided in this embodiment belongs to the same inventive concept as the driving circuit provided in any embodiment of the present invention and has corresponding beneficial effects. For technical details not covered in this embodiment, please refer to the driving circuit provided in any embodiment of the present invention.

[0058] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, combinations, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A driving circuit for driving a switching transistor to be driven, characterized in that, include: The system comprises a first driving circuit, a second driving circuit, and a falling edge delay circuit unit; the first driving circuit includes a first switching transistor, a second switching transistor, and a third switching transistor. The first terminal of the first switch is connected to a first power signal, the control terminal of the first switch is electrically connected to the control terminal of the second switch, the second terminal of the first switch is electrically connected to the first terminal of the second switch, the second terminal of the second switch is electrically connected to the first terminal of the third switch, the control terminal of the third switch is electrically connected to the control terminal of the first switch, and the first terminal of the third switch is electrically connected to the control terminal of the switch to be driven. The input terminal of the second drive circuit is connected to the drive control signal, and the output terminal of the second drive circuit is electrically connected to the second pole of the third switch. The input terminal of the falling edge delay circuit unit is connected to the drive control signal, and the output terminal of the falling edge delay circuit unit is electrically connected to the control electrode of the first switching transistor. The falling edge delay circuit unit is used to delay the falling edge of the drive control signal. The driving circuit further includes a rising edge delay circuit unit; the input terminal of the rising edge delay circuit unit is connected to the driving control signal, and the output terminal of the rising edge delay circuit unit is electrically connected to the input terminal of the second driving loop. The rising edge delay circuit unit is used to delay the rising edge of the driving control signal. The second drive circuit includes a fourth switch and a fifth switch. The control terminals of the fourth switch and the fifth switch are both connected to the output terminal of the rising edge delay circuit unit. The first terminal of the fourth switch is electrically connected to the second terminal of the first switch, the second terminal of the fourth switch is electrically connected to the second terminal of the third switch, the first terminal of the fifth switch is electrically connected to the second terminal of the fourth switch, and the second terminal of the fifth switch is connected to the first reference ground.

2. The driving circuit according to claim 1, characterized in that, The first and fourth switching transistors are both PMOS, while the second, third, and fifth switching transistors are all NMOS.

3. The driving circuit according to claim 2, characterized in that, It also includes a first bootstrap power supply circuit and / or a second bootstrap power supply circuit, wherein the first bootstrap power supply circuit includes a first capacitor and a first Zener diode, and the second bootstrap power supply circuit includes a second capacitor and a second Zener diode; The first terminal of the first capacitor is electrically connected to the second terminal of the first switching transistor, the second terminal of the first capacitor is connected to the first reference ground, the anode of the first Zener diode is electrically connected to the second terminal of the first capacitor, and the cathode of the first Zener diode is electrically connected to the first terminal of the first capacitor. The first terminal of the second capacitor is electrically connected to the second electrode of the switch to be driven, the second terminal of the second capacitor is electrically connected to the second electrode of the fifth switch, the anode of the second Zener diode is electrically connected to the second terminal of the second capacitor, and the cathode of the second Zener diode is electrically connected to the first terminal of the second capacitor.

4. The driving circuit according to claim 3, characterized in that, It also includes a first resistor, a second resistor, a third resistor, a fourth resistor, and a fifth resistor; the second terminal of the first switching transistor is electrically connected to the second terminal of the second switching transistor through the first resistor, the first terminal of the third switching transistor is electrically connected to the control terminal of the switching transistor to be driven through the second resistor, the control terminal of the second switching transistor is electrically connected to the control terminal of the first switching transistor through the third resistor, the second terminal of the first switching transistor is electrically connected to the first terminal of the first capacitor through the fourth resistor, and the first terminal of the second capacitor is electrically connected to the first terminal of the fourth switching transistor through the fifth resistor.

5. The driving circuit according to claim 4, characterized in that, It also includes a first diode and a second diode. The anode of the first diode is electrically connected to the second terminal of the first switching transistor, and the cathode of the first diode is electrically connected to the first terminal of the first capacitor through the fourth resistor. The anode of the second diode is electrically connected to the first terminal of the fourth switching transistor, and the cathode of the second diode is electrically connected to the first terminal of the second capacitor through the fifth resistor.

6. A bridge circuit, characterized in that, The circuit includes the driving circuit as described in any one of claims 1-5, and further includes a sixth switch and a seventh switch to be driven; the input terminal of the first driving circuit corresponding to the sixth switch is connected to a first driving signal, the first output terminal of the first driving circuit is electrically connected to the control electrode of the sixth switch, and the second output terminal of the first driving circuit is electrically connected to the second electrode of the sixth switch; the input terminal of the second driving circuit corresponding to the seventh switch is connected to a second driving signal, the first output terminal of the second driving circuit is electrically connected to the control electrode of the seventh switch, the second output terminal of the second driving circuit is electrically connected to the second electrode of the seventh switch, and the second electrode of the sixth switch is electrically connected to the second electrode of the seventh switch through an inductor and an impedance.

7. The bridge circuit according to claim 6, characterized in that, The first terminal of the sixth switch is connected to the second power supply signal, the second terminal of the sixth switch is electrically connected to the first terminal of the seventh switch, and the second terminal of the seventh switch is connected to the second reference ground.

8. The bridge circuit according to claim 6, characterized in that, Both the sixth and seventh switching transistors are gallium nitride semiconductor switching transistors.

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