A spaceborne PMT detector gate control circuit and control method

Abstract

The present invention provides a gating circuit and control method for a satellite-borne PMT detector, comprising a high-voltage generating unit, a PMT detection unit, and a gated pulse unit. The high-voltage generating unit generates an operating bias voltage for the PMT detection unit and a gated high voltage for the gated pulse unit. The gated pulse unit generates a gated high-voltage pulse of a certain amplitude under timing control, which enables or disables the PMT detector by changing the multiplication stage voltage of the PMT detector. The present invention solves the problem of low reliability of satellite-borne high-voltage MOSFETs. The voltage divider circuit of the PMT detector changes the interstage voltage of the PMT detector's multiplication stage by charging and discharging an RC circuit, thereby achieving gating control of the PMT detector. The present invention effectively reduces the duration of the influence of close-range scattered light and background light in satellite-borne applications of the PMT detector, avoiding the resulting problems of hardware damage, nonlinearity, and reduced detection performance, thereby extending the operating life of the PMT detector and providing reliability assurance for its space applications.

Description

Technical Field

[0001] The present invention relates to the technical field, and in particular to a gating circuit and a control method for a satellite-borne PMT detector. Background Art

[0002] LiDAR is a new type of active remote sensing instrument. In the 1960s, when LiDAR (Light Detection And Ranging-LIDAR) appeared, it was quickly applied to active distance measurement, wind field measurement, atmospheric remote sensing and other fields.

[0003] Avalanche photodiodes (APDs) and photomultiplier tubes (PMTs) are commonly used receiving detectors in atmospheric lidar. PMTs offer significantly higher gain than APDs, a relatively low dark current, and extremely high sensitivity, capable of detecting weak signals at the photon level. Therefore, PMTs offer certain advantages in atmospheric laser detection.

[0004] To improve the range and accuracy of atmospheric laser detection, atmospheric lidars often use high transmission power. The strong scattered light signals received by the receiving telescope at close range can easily saturate the PMT, leading to a spatial accumulation of charge in the final stages of the dynodes. Prolonged exposure to this intense light can lead to fatigue in the PMT, increasing noise levels and causing smearing due to a period of delay after the injection of intense light. This ultimately affects the PMT's linear response to long-range detection signals. For high-energy, high-repetition-rate laser sources, the strong scattered light at close range can even damage the PMT hardware, rendering it unusable.

[0005] To avoid this phenomenon, for close-range strong scattered light signals, the PMT response is controlled to be cut off; for long-range weak signals, the PMT response is controlled to be turned on, thereby avoiding the influence of strong light signals on the PMT linear output. Based on this, the technical requirement of operating the PMT detector (21) in gated mode is proposed. Summary of the Invention

[0006] The present invention aims to address the issue of the effects of close-range scattered light and background light in spaceborne PMT detector applications. It provides a gating circuit and control method for a spaceborne PMT detector. This circuit utilizes a low-voltage, high-speed MOS transistor to achieve rapid on-off control of high-voltage pulses, resolving the issue of low reliability of spaceborne high-voltage MOS transistors. Furthermore, the PMT detector's voltage divider circuit utilizes an RC charge-discharge circuit design. By charging and discharging the RC circuit, the interstage voltage of the PMT detector's multiplication stage is altered, thereby achieving gating control of the PMT detector. This invention effectively reduces the duration of the effects of close-range scattered light and background light in spaceborne PMT detector applications, avoiding the resulting hardware damage, nonlinearity, and reduced detection performance. This method, therefore, extends the PMT detector's operating life and provides reliability assurance for its space applications.

[0007] The present invention provides a satellite-borne PMT detector gating circuit, comprising a high-voltage generating unit, a PMT detecting unit electrically connected to the high-voltage generating unit, and a gated pulse unit, wherein the PMT detecting unit is electrically connected to the gated pulse unit;

[0008] The PMT detection unit includes a PMT detector and a voltage divider circuit module electrically connected to the PMT detector. The voltage divider circuit module is electrically connected to the high voltage generating unit and the gated pulse unit. The PMT detector is used to receive the laser radar's echo light signal and output the echo electrical signal after performing photoelectric conversion.

[0009] The high-voltage generating unit is used to output high voltage to the voltage divider circuit module and the gated pulse unit. The gated pulse unit is used to generate a low-voltage gated pulse signal under synchronous triggering and convert it into a high-voltage gated pulse signal and then output it to the voltage divider circuit module. The voltage divider circuit module is used to change the inter-stage voltage of the PMT detector multiplication stage after receiving the high-voltage gated pulse signal. The voltage divider circuit module is used to enable the PMT detector to operate under the gated timing of the high-voltage gated pulse signal.

[0010] In a preferred embodiment of the present invention, a satellite-borne PMT detector gating circuit comprises a high-voltage generating unit comprising a high-voltage module A electrically connected to a voltage divider circuit module and a high-voltage module B electrically connected to a gate pulse unit. The high-voltage module A is used to provide a high-voltage power supply to the voltage divider circuit module, and the high-voltage module B is used to provide a high-voltage power supply to the MOS transistor switch module. The output voltage value of the high-voltage module B is the amplitude of the high-voltage gate pulse signal.

[0011] The gate pulse unit includes an FPGA module, a level conversion module and a MOS tube switch module which are electrically connected in sequence, and the MOS tube switch module is electrically connected to the voltage divider circuit module;

[0012] The FPGA module is used to generate a low-voltage gate pulse signal under synchronous triggering. The low-voltage gate pulse signal is a pulse signal with a timing sequence. The level conversion module is used to convert the low-voltage gate pulse signal and output the MOS tube control signal to the MOS tube switch module. The MOS tube switch module is used to receive the MOS tube control signal and convert it into a high-voltage gate pulse signal to output to the voltage divider circuit module.

[0013] The present invention discloses a satellite-borne PMT detector gating circuit. As a preferred embodiment, the PMT detector is a photomultiplier tube, the PMT detector has 10 multiplication levels, an operating bias voltage of -800V to -1100V, and a response wavelength of 230nm to 870nm.

[0014] In a preferred embodiment of the present invention, the voltage divider circuit module includes a first RC circuit, a second RC circuit, and a third RC circuit connected in parallel to the output end of the MOS transistor switch module, a DY connection connected to the output ends of the first RC circuit, the second RC circuit, and the third RC circuit, a voltage divider resistor electrically connected to the DY connection, and a capacitor electrically connected to the DY connection.

[0015] The DY connection includes a K stage, DY1, DY2, DY3, DY4, DY5, DY6, DY7, DY8, DY9, DY10 and GND arranged in parallel, DY1 is connected to the resistance output end of the first RC circuit, DY2 is connected to the capacitance output end of the first RC circuit, DY3 is connected to the resistance output end of the second RC circuit, DY4 is connected to the capacitance output end of the second RC circuit, DY5 is connected to the resistance output end of the third RC circuit, and DY6 is connected to the capacitance output end of the third RC circuit. Voltage dividing resistors are respectively arranged between the K stage and DY1, DY7 and DY8, DY8 and DY9, DY9 and DY10, and DY10 and GND, voltage dividing resistors are respectively arranged between DY1 and DY3, DY3 and DY5, and DY5 and DY7, and capacitors are respectively connected in parallel between DY8 and DY9, DY9 and DY10, and DY10 and GND.

[0016] In the satellite-borne PMT detector gating circuit described in the present invention, as a preferred embodiment, the voltage divider resistors between level K and DY1, DY7 and DY8, DY8 and DY9, DY9 and DY10, and DY10 and GND are 330K, the voltage divider resistors between DY1 and DY3, DY3 and DY5, and DY5 and DY7 are 660K, the capacitor arranged between DY8 and DY9 is 0.2μF / 300V, the capacitor arranged between DY9 and DY10 is 0.5μF / 300V, and the capacitor arranged between DY10 and GND is 1μF / 300V.

[0017] The present invention discloses a satellite-borne PMT detector gating circuit. As a preferred embodiment, the high-voltage module A is a continuously and linearly adjustable high-voltage module. The input voltage of the high-voltage module A is 10V to 16V, the control voltage is 0 to 2.4V, the output voltage of the high-voltage module A is 0V to -1200V, the output current is 4mA, and the power supply ripple is ≤200mVpp.

[0018] The present invention discloses a satellite-borne PMT detector gating circuit. As a preferred embodiment, the high-voltage module B is a continuously and linearly adjustable high-voltage module. The input voltage of the high-voltage module B is 10V to 16V, the control voltage is 0 to 2.4V, the output voltage of the high-voltage module B is 0V to 150V, the output current is 30mA, and the power supply ripple is ≤50mVpp.

[0019] In the gating circuit of a space-borne PMT detector described in the present invention, as a preferred embodiment, the FPGA module is an anti-fuse FPGA, which is used to reduce the influence of space radiation and single-event upsets. The low-voltage gating pulse signal is a negative pulse signal with a pulse width of 200us, a frequency of 20Hz, and a voltage of 5V. The MOS tube control signal is 5V.

[0020] The MOS tube switch module includes four N-channel MOS tubes of the same model. Two MOS tubes are connected in parallel and then connected in series with the other two parallel MOS tubes. The D-level input voltage of the MOS tube switch module is 100V, and the high-voltage gate pulse signal is a 100V positive pulse signal.

[0021] The present invention provides a method for controlling a gating of a spaceborne PMT detector, comprising the following steps:

[0022] S1. Low-voltage gate pulse signal generation: The FPGA module generates a low-voltage gate pulse signal under synchronous triggering and outputs it to the level conversion module;

[0023] S2, high-voltage gate pulse signal generation: the level conversion module converts the low-voltage gate pulse signal into a level and controls the MOS tube switch module to output the high-voltage gate pulse signal to the voltage divider circuit module;

[0024] S3. PMT detector gate control operation: After receiving the high-voltage gate pulse signal, the voltage divider circuit module changes the inter-stage voltage of the PMT detector multiplication stage through the parallel multi-stage RC circuit, DY connection and voltage divider resistor. The voltage divider circuit module enhances the continuous current capability of the PMT detector working under the gate timing through the capacitors set in sequence.

[0025] In the gating control method for a satellite-borne PMT detector described in the present invention, as a preferred embodiment, in step S1, the low-voltage gating pulse signal has a pulse width of 200 μs and a frequency of 20 Hz, and the low-voltage gating pulse signal is a negative pulse signal;

[0026] In step S2, the level conversion module converts the low-voltage gate pulse signal from 3.3V to 5V, the high-voltage gate pulse signal is a 100V positive pulse signal, and the MOS tube switch module is set to redundancy;

[0027] In step S3, the high-voltage gate pulse signal is input between DY1 and DY2, DY3 and DY4, DY5 and DY6 respectively through the first RC circuit, the second RC circuit and the third RC circuit connected in parallel. The inter-stage voltages of DY1 and DY2, DY3 and DY4, DY5 and DY6 are controlled by the charge and discharge characteristics of the first RC circuit, the second RC circuit and the third RC circuit to perform gate control on the PMT detector. At the same time, the capacitance values ​​of the capacitors connected in parallel between DY8 and DY9, DY9 and DY10, and DY10 and GND are increased in a conical manner to enhance the freewheeling capability of the output signal of the PMT detector.

[0028] The technical solution of the present invention is: a satellite-borne PMT detector gating circuit, comprising a high-voltage generating unit, a PMT detection unit, and a gated pulse unit. The high-voltage generating unit comprises a high-voltage module A and a high-voltage module B; the PMT detection unit comprises a PMT detector and a voltage divider circuit module; and the gated pulse unit comprises an FPGA module, a level conversion module, and a MOS transistor switch module. The FPGA module generates a low-voltage gated pulse with a certain timing sequence under synchronous triggering. This signal, after passing through the level conversion module, drives the MOS transistor switch module to output a gated high-voltage pulse with a certain amplitude. This pulse acts on the PMT detector voltage divider circuit module, thereby changing the interstage voltage of the PMT detector's multiplication stage, thereby enabling the PMT detector to operate stably under the gated timing sequence. The high-voltage module B provides a high-voltage power supply to the MOS transistor switch module, the amplitude of which is the same as the amplitude of the gated high-voltage pulse. The output of the high-voltage module A, after being divided by the voltage divider circuit module, provides an operating voltage for each multiplication stage of the PMT detector. The interstage voltage and the gated high-voltage pulse work together to put the PMT detector into a gated operating mode. The PMT detector is used to receive the laser radar echo light signal, perform photoelectric conversion, and output a current signal.

[0029] High-voltage module A is a continuously and linearly adjustable high-voltage module with an input voltage of 10V to 16V, a control voltage of 0 to 2.4V, a corresponding output voltage of 0V to -1200V, an output current of 4mA, and a power supply ripple of ≤200mVpp.

[0030] High-voltage module B is a continuously and linearly adjustable high-voltage module with an input voltage of 10V to 16V, a control voltage of 0 to 2.4V, a corresponding output voltage of 0V to 150V, an output current of 30mA, and a power supply ripple ≤50mVpp.

[0031] The PMT detector is a photomultiplier tube with 10 multiplication levels, an operating bias voltage of -800V to -1100V, and a response wavelength of 230nm to 870nm.

[0032] The voltage divider module consists of a three-stage RC circuit and an eight-stage voltage divider circuit. The voltage divider resistors between stage K and DY1, DY7 and DY8, DY8 and DY9, DY9 and DY10, and DY10 and GND are 330K. The voltage divider resistors between DY1 and DY3, DY3 and DY5, and DY5 and DY7 are 660K. The gate-control high-voltage pulse is input through the three-stage RC network between DY1 and DY2, DY3 and DY4, and DY5 and DY6, respectively. The charge and discharge characteristics of the RC circuits are used to control the interstage voltages between DY1 and DY2, DY3 and DY4, and DY5 and DY6, thereby achieving gate control of the PMT detector. Furthermore, parallel capacitors are connected between DY8 and DY9, DY9 and DY10, and DY10 and GND, with the capacitance values ​​increasing in a tapered pattern, to ensure the linearity of the PMT detector output signal.

[0033] The gate pulse unit consists of an FPGA module, a level conversion module, and a MOS transistor switch module. The FPGA module utilizes an anti-fuse FPGA, effectively reducing the impact of space radiation and single-event upsets. During operation, the FPGA generates a low-voltage negative pulse gating signal with a pulse width of 200µs and a frequency of 20Hz under external synchronous triggering. The level conversion module achieves level conversion from 3.3V to 5V. The MOS transistor switch module consists of four N-channel MOS transistors of the same model connected in series and parallel. The D-level input voltage is 100V, and the low-voltage gate signal is input from the G-level, converting a 5V negative pulse signal to a 100V positive pulse signal. The redundant design of the MOS transistors effectively prevents gate failure caused by short circuits or open circuits in a single MOS transistor, thereby improving the reliability of the onboard product.

[0034] In this technical solution, the high-voltage generating unit is used to generate two high voltages: one is used to provide a working bias voltage for the PMT detection unit, and the other is used to provide a gated high voltage for the gated pulse unit; the PMT detection unit is used for the photoelectric conversion of the laser radar echo light signal; the gated pulse unit is used to generate a gated high-voltage pulse of a certain amplitude under timing control, and enables or disables the operation of the PMT detector by changing the multiplication stage voltage of the PMT detector.

[0035] The present invention has the following advantages:

[0036] (1) Each level of the PMT voltage divider circuit of the present invention is connected in parallel with a capacitor, and in particular, the capacitance of the last three levels of the capacitor is designed to be tapered and progressively increased, thereby ensuring the linearity of the output signal of the PMT detector (21), and the middle three levels of the voltage divider circuit are added with an RC network. By selecting a suitable RC, the rise time and fall time of the high-voltage gate pulse signal can be changed;

[0037] (2) The MOS transistor switch circuit of the present invention adopts a redundant design of two parallel and two series transistors to prevent the gate control function failure caused by a single-point MOS transistor short circuit or open circuit, thereby improving the reliability of the satellite-borne product;

[0038] (3) The MOS tube switch circuit of the present invention uses a low-voltage MOS tube to achieve high-voltage switch control, solving the problem of low reliability of satellite-borne high-voltage MOS tubes. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 This is a schematic diagram of the structure of a gating circuit for a spaceborne PMT detector;

[0040] Figure 2 This is a schematic diagram of the design of the MOS tube switch module and PMT voltage divider circuit module of a satellite-borne PMT detector gate control circuit;

[0041] Figure 3 The figure is a flow chart of a gating control method of a spaceborne PMT detector 21.

[0042] Reference numerals:

[0043] 1. High-voltage generating unit; 11. High-voltage module A; 12. High-voltage module B; 2. PMT detection unit; 21. PMT detector; 22. Voltage divider circuit module; 221. First RC circuit; 222. Second RC circuit; 223. Third RC circuit; 224. DY connection; 225. Voltage divider resistor; 226. Capacitor; 3. Gate pulse unit; 31. FPGA module; 32. Level conversion module; 33. MOS tube switch module. DETAILED DESCRIPTION

[0044] The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments.

[0045] Example 1

[0046] like Figure 1-2 As shown, a satellite-borne PMT detector gating circuit includes a high-voltage generating unit 1, a PMT detecting unit 2 electrically connected to the high-voltage generating unit 1, and a gated pulse unit 3, wherein the PMT detecting unit 2 is electrically connected to the gated pulse unit 3;

[0047] The PMT detection unit 2 includes a PMT detector 21 and a voltage divider circuit module 22 electrically connected to the PMT detector 21. The voltage divider circuit module 22 is electrically connected to the high voltage generating unit 1 and the gated pulse unit 3. The PMT detector 21 is used to receive the laser radar's echo light signal and output the echo electrical signal after performing photoelectric conversion.

[0048] The high-voltage generating unit 1 is used to output high voltage electricity to the voltage divider circuit module 22 and the gated pulse unit 3. The gated pulse unit 3 is used to generate a low-voltage gated pulse signal under synchronous triggering and convert it into a high-voltage gated pulse signal and then output it to the voltage divider circuit module 22. The voltage divider circuit module 22 is used to change the interstage voltage of the multiplication stage of the PMT detector 21 after receiving the high-voltage gated pulse signal. The voltage divider circuit module 22 is used to make the PMT detector 21 operate under the gated timing of the high-voltage gated pulse signal;

[0049] The gate pulse unit 3 includes an FPGA module 31, a level conversion module 32 and a MOS transistor switch module 33 which are electrically connected in sequence. The MOS transistor switch module 33 is electrically connected to the voltage divider circuit module 22.

[0050] The FPGA module 31 is used to generate a low-voltage gate pulse signal under synchronous triggering. The low-voltage gate pulse signal is a pulse signal with a timing sequence. The level conversion module 32 is used to convert the low-voltage gate pulse signal and output the MOS transistor control signal to the MOS transistor switch module 33. The MOS transistor switch module 33 is used to receive the MOS transistor control signal and convert it into a high-voltage gate pulse signal to output to the voltage divider circuit module 22.

[0051] The PMT detector 21 is a photomultiplier tube, and the multiplication level of the PMT detector 21 is 10, the working bias voltage is -800V to -1100V, and the response wavelength is 230nm to 870nm;

[0052] The voltage divider circuit module 22 includes a first RC circuit 221, a second RC circuit 222, and a third RC circuit 223 connected in parallel to the output end of the MOS transistor switch module 33, a DY connection 224 connected to the output ends of the first RC circuit 221, the second RC circuit 222, and the third RC circuit 223, a voltage divider resistor 225 electrically connected to the DY connection, and a capacitor 226 electrically connected to the DY connection 224.

[0053] The DY connection 224 includes a K stage, DY1, DY2, DY3, DY4, DY5, DY6, DY7, DY8, DY9, DY10 and GND arranged in parallel, DY1 is connected to the resistance output end of the first RC circuit 221, DY2 is connected to the capacitance output end of the first RC circuit 221, DY3 is connected to the resistance output end of the second RC circuit 222, DY4 is connected to the capacitance output end of the second RC circuit 222, and DY5 is connected to the third The resistance output terminal of the RC circuit 223 is connected, DY6 is connected to the capacitance output terminal of the third RC circuit 223, voltage divider resistors are respectively set between the K level and DY1, DY7 and DY8, DY8 and DY9, DY9 and DY10, and DY10 and GND, voltage divider resistors are respectively set between DY1 and DY3, DY3 and DY5, and DY5 and DY7, and parallel capacitors are respectively connected between DY8 and DY9, DY9 and DY10, and DY10 and GND;

[0054] The voltage divider resistor 225 between K level and DY1, DY7 and DY8, DY8 and DY9, DY9 and DY10, and DY10 and GND is 330K, the voltage divider resistor 225 between DY1 and DY3, DY3 and DY5, and DY5 and DY7 is 660K, the capacitor 226 set between DY8 and DY9 is 0.2μF / 300V, the capacitor 226 set between DY9 and DY10 is 0.5μF / 300V, and the capacitor 226 set between DY10 and GND is 1μF / 300V;

[0055] The high-voltage module A11 is a continuously and linearly adjustable high-voltage module. The input voltage of the high-voltage module A11 is 10V~16V, the control voltage is 0~2.4V, the output voltage of the high-voltage module A11 is 0V~-1200V, the output current is 4mA, and the power supply ripple is ≤200mVpp;

[0056] The high-voltage module B12 is a continuously and linearly adjustable high-voltage module. The input voltage of the high-voltage module B12 is 10V~16V, the control voltage is 0~2.4V, the output voltage of the high-voltage module B12 is 0V~150V, the output current is 30mA, and the power supply ripple is ≤50mVpp;

[0057] The FPGA module 31 is an anti-fuse FPGA, which is used to reduce the impact of space radiation and single-event upsets. The low-voltage gate pulse signal is a negative pulse signal with a pulse width of 200us, a frequency of 20Hz, and a voltage of 5V. The MOS tube control signal is 5V.

[0058] The MOS transistor switch module 33 includes four N-channel MOS transistors of the same model. Two MOS transistors are connected in parallel and then in series with the other two parallel MOS transistors. The D-level input voltage of the MOS transistor switch module 33 is 100V, and the high-voltage gate pulse signal is a 100V positive pulse signal.

[0059] Example 2

[0060] like Figure 1 The figure shows a principle block diagram of a satellite-borne PMT detector gate control circuit of the present invention. Figure 1 It can be seen that it includes: a high-voltage generating unit 1, a PMT detection unit 2, and a gated pulse unit 3. Among them, the high-voltage generating unit 1 includes a high-voltage module A11 and a high-voltage module B12; the PMT detection unit 2 includes a PMT detector 21 and a voltage divider circuit module 22; and the gated pulse unit 3 includes an FPGA module 31, a level conversion module 32, and a MOS tube switch module 33. Under synchronous triggering, the FPGA module 31 generates a low-voltage gated pulse with a certain timing. After passing through the level conversion module 32, this signal drives the MOS tube switch module 33 to output a gated high-voltage pulse with a certain amplitude. This pulse acts on the voltage divider circuit module 22 of the PMT detector 21, which is used to change the inter-stage voltage of the multiplication stage of the PMT detector 21, so that the PMT detector 21 can operate stably under the gated timing; the high-voltage module B12 provides a high-voltage power supply for the MOS tube switch module 33, and its magnitude is the amplitude of the gated high-voltage pulse; the output of the high-voltage module A11 is divided by the voltage divider circuit module 22 to provide an operating voltage for each multiplication stage of the PMT detector 21. The inter-stage voltage and the gated high-voltage pulse work together to put the PMT detector 21 into a gated working mode; the PMT detector 21 is used to receive the laser radar echo light signal, complete the photoelectric conversion, and output the current signal.

[0061] The high-voltage generating unit 1 in this embodiment includes a high-voltage module A11 and a high-voltage module B12. Two TI 12-bit DACTLV5638MJGB chips are used to receive external SPI remote control commands, outputting analog signals ranging from 0V to 2.4V to control the high-voltage power supplies MNSX1100S and MNSX150S, respectively, to linearly output 0V to -1200V and 0V to 150V. In this embodiment, high-voltage module A11 outputs a high voltage of -1000V, while high-voltage module B12 outputs a high voltage of 100V.

[0062] The PMT detection unit 2 in this embodiment consists of a PMT detector 21 and a voltage divider circuit module 22. The PMT detector 21 is R9880U-01 from HAMAMATSU, which has 10 photomultiplier levels, a response wavelength range of 230nm to 870nm, and an operating bias voltage of -1100V to -800V. Figure 2The voltage divider circuit module 22 shown in the figure consists of a three-stage RC circuit and an eight-stage voltage divider circuit. The voltage divider resistors between stage K and DY1, DY7 and DY8, DY8 and DY9, DY9 and DY10, and DY10 and GND are 330K, and the voltage divider resistors between DY1 and DY3, DY3 and DY5, and DY5 and DY7 are 660K. The gated high-voltage pulse is input through the three-stage RC network to the voltages between DY1 and DY2, DY3 and DY4, and DY5 and DY6, respectively. The charge and discharge characteristics of the RC circuits are used to control the interstage voltages between DY1 and DY2, DY3 and DY4, and DY5 and DY6, achieving gate control of the PMT detector. Different R and C parameters can change the rise time, settling time, and fall time of the gated high-voltage pulse, thereby stabilizing the PMT detector's response within the gate. In addition, capacitors 226 are connected in parallel between DY8 and DY9, DY9 and DY10, and DY10 and GND, respectively, with the capacitance increasing in a tapered pattern to ensure the linearity and continuous current capability of the PMT detector's output signal. The capacitors set between DY8 and DY9 are 0.2 μF / 300 V, the capacitors set between DY9 and DY10 are 0.5 μF / 300 V, and the capacitors set between DY10 and GND are 1 μF / 300 V. The gated pulse unit 3 in this embodiment consists of an FPGA module 31, a level conversion module 32, and a MOS transistor switch module 33. FPGA module 31 utilizes an antifuse FPGA A54SX72A-CQ208B, which effectively reduces the effects of space radiation and single-event upsets. When working, the FPGA generates a 3.3V negative pulse gating signal with a pulse width of 200us and a frequency of 20Hz under external synchronous triggering; the level conversion module 32 uses the level conversion chip SNJ54ACT245FK to achieve the level conversion from 3.3V to 5V; Figure 2 The MOS transistor switch module 33 shown is composed of four N-channel MOS transistors IRHNJ6S7230 of the same model connected in series and parallel. The D-level input has a high voltage of 100V, and the G-level input has a low voltage gate control signal, which realizes the conversion of 5V negative pulse signal to 100V positive pulse signal.

[0063] Example 3

[0064] like Figure 3 As shown, a gating control method for a spaceborne PMT detector 21 includes the following steps:

[0065] S1. Low-voltage gate pulse signal generation: The FPGA module 31 generates a low-voltage gate pulse signal under synchronous triggering and outputs it to the level conversion module 32; the low-voltage gate pulse signal has a pulse width of 200 μs and a frequency of 20 Hz, and is a negative pulse signal;

[0066] S2, high-voltage gate pulse signal generation: the level conversion module 32 performs level conversion on the low-voltage gate pulse signal and then controls the MOS transistor switch module 33 to output the high-voltage gate pulse signal to the voltage divider circuit module 22;

[0067] The level conversion module 32 converts the low-voltage gate pulse signal from 3.3V to 5V, the high-voltage gate pulse signal is a 100V positive pulse signal, and the MOS tube switch module 33 is set to redundancy;

[0068] S3, PMT detector gate control operation: After receiving the high-voltage gate pulse signal, the voltage divider circuit module 22 changes the inter-stage voltage of the PMT detector 21 through the parallel multi-stage RC circuit, DY connection and voltage divider resistor. The voltage divider circuit module 22 enhances the freewheeling capability of the PMT detector 21 working under the gate timing through the capacitors arranged in sequence;

[0069] The high-voltage gate pulse signal is input between DY1 and DY2, DY3 and DY4, and DY5 and DY6 respectively through the first RC circuit 221, the second RC circuit 222, and the third RC circuit 223 connected in parallel. The inter-stage voltages of DY1 and DY2, DY3 and DY4, and DY5 and DY6 are controlled by the charging and discharging characteristics of the first RC circuit 221, the second RC circuit 222, and the third RC circuit 223 to perform gate control on the PMT detector 21. At the same time, the capacitance of the capacitor 226 connected in parallel between DY8 and DY9, DY9 and DY10, and DY10 and GND increases in a tapered manner to enhance the freewheeling capability of the output signal of the PMT detector 21.

[0070] The above description is only a preferred specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any technician familiar with the technical field, within the technical scope disclosed by the present invention, who makes equivalent replacements or changes based on the technical solution and inventive concept of the present invention, should be covered by the scope of protection of the present invention.

Claims

1. A gating circuit for a spaceborne PMT detector, characterized in that: It comprises a high voltage generating unit (1), a PMT detecting unit (2) and a gated pulse unit (3) both electrically connected to the high voltage generating unit (1), wherein the PMT detecting unit (2) is electrically connected to the gated pulse unit (3); The PMT detection unit (2) comprises a PMT detector (21) and a voltage divider circuit module (22) electrically connected to the PMT detector (21); the voltage divider circuit module (22) is electrically connected to both the high voltage generating unit (1) and the gated pulse unit (3); the PMT detector (21) is used to receive an echo light signal from a laser radar and perform photoelectric conversion to output an echo electrical signal; The high-voltage generating unit (1) is used to output high voltage electricity to the voltage-dividing circuit module (22) and the gate-controlled pulse unit (3); the gate-controlled pulse unit (3) is used to generate a low-voltage gate-controlled pulse signal under synchronous triggering and convert it into a high-voltage gate-controlled pulse signal and then output it to the voltage-dividing circuit module (22); the voltage-dividing circuit module (22) is used to change the inter-stage voltage of the multiplication stage of the PMT detector (21) after receiving the high-voltage gate-controlled pulse signal; and the voltage-dividing circuit module (22) is used to enable the PMT detector (21) to operate under the gate-controlled timing of the high-voltage gate-controlled pulse signal.

2. The onboard PMT detector gating circuit according to claim 1, wherein: The high-voltage generating unit (1) comprises a high-voltage module A (11) electrically connected to the voltage-dividing circuit module (22) and a high-voltage module B (12) electrically connected to the gate-controlled pulse unit (3), wherein the high-voltage module A (11) is used to provide a high-voltage power supply to the voltage-dividing circuit module (22), and the high-voltage module B (12) is used to provide a high-voltage power supply to the MOS tube switch module (33), and the output voltage value of the high-voltage module B (12) is the amplitude of the high-voltage gate-controlled pulse signal; The gated pulse unit (3) comprises an FPGA module (31), a level conversion module (32), and a MOS transistor switch module (33) electrically connected in sequence, and the MOS transistor switch module (33) is electrically connected to the voltage divider circuit module (22); The FPGA module (31) is used to generate the low-voltage gate pulse signal under synchronous triggering, and the low-voltage gate pulse signal is a pulse signal with a time sequence. The level conversion module (32) is used to perform level conversion on the low-voltage gate pulse signal and output the MOS tube control signal to the MOS tube switch module (33). The MOS tube switch module (33) is used to receive the MOS tube control signal and convert it into the high-voltage gate pulse signal to output to the voltage divider circuit module (22).

3. The onboard PMT detector gating circuit according to claim 1, wherein: The PMT detector (21) is a photomultiplier tube, and the multiplication level of the PMT detector (21) is 10 levels, the working bias voltage is -800V to -1100V, and the response wavelength is 230nm to 870nm.

4. The onboard PMT detector gating circuit according to claim 2, wherein: The voltage divider circuit module (22) comprises a first RC circuit (221), a second RC circuit (222), and a third RC circuit (223) connected in parallel to the output end of the MOS transistor switch module (33); a DY connection (224) connected to the output ends of the first RC circuit (221), the second RC circuit (222), and the third RC circuit (223); a voltage divider resistor (225) electrically connected to the DY connection; and a capacitor (226) electrically connected to the DY connection (224). The DY connection (224) includes a K level, DY1, DY2, DY3, DY4, DY5, DY6, DY7, DY8, DY9, DY10 and GND arranged in parallel, DY1 is connected to the resistance output end of the first RC circuit (221), DY2 is connected to the capacitance output end of the first RC circuit (221), DY3 is connected to the resistance output end of the second RC circuit (222), and DY4 is connected to the capacitance output end of the second RC circuit (222). DY5 is connected to the resistance output end of the third RC circuit (223), DY6 is connected to the capacitance output end of the third RC circuit (223), voltage dividing resistors are respectively set between the K level and DY1, DY7 and DY8, DY8 and DY9, DY9 and DY10, and DY10 and GND, voltage dividing resistors are respectively set between DY1 and DY3, DY3 and DY5, and DY5 and DY7, and capacitors are respectively connected in parallel between DY8 and DY9, DY9 and DY10, and DY10 and GND.

5. The onboard PMT detector gating circuit according to claim 4, characterized in that: The voltage divider resistor (225) between the K level and DY1, DY7 and DY8, DY8 and DY9, DY9 and DY10, and DY10 and GND is 330K, the voltage divider resistor (225) between DY1 and DY3, DY3 and DY5, and DY5 and DY7 is 660K, the capacitor (226) set between DY8 and DY9 is 0.2μF / 300V, the capacitor (226) set between DY9 and DY10 is 0.5μF / 300V, and the capacitor (226) set between DY10 and GND is 1μF / 300V.

6. The onboard PMT detector gating circuit according to claim 2, characterized in that: The high-voltage module A (11) is a continuously and linearly adjustable high-voltage module. The input voltage of the high-voltage module A (11) is 10V to 16V, the control voltage is 0 to 2.4V, the output voltage of the high-voltage module A (11) is 0V to -1200V, the output current is 4mA, and the power ripple is ≤200mVpp.

7. The onboard PMT detector gating circuit according to claim 2, characterized in that: The high-voltage module B (12) is a continuously and linearly adjustable high-voltage module. The input voltage of the high-voltage module B (12) is 10V to 16V, the control voltage is 0 to 2.4V, the output voltage of the high-voltage module B (12) is 0V to 150V, the output current is 30mA, and the power ripple is ≤50mVpp.

8. The onboard PMT detector gating circuit according to claim 2, characterized in that: The FPGA module (31) is an anti-fuse FPGA, and is used to reduce the influence of space radiation and single-event upset. The low-voltage gate pulse signal is a negative pulse signal with a pulse width of 200 μs and a frequency of 20 Hz and 5 V. The MOS tube control signal is 5 V. The MOS transistor switch module (33) comprises four N-channel MOS transistors of the same model, two of which are connected in parallel and then connected in series with the other two parallel MOS transistors. The D-level input voltage of the MOS transistor switch module (33) is 100V, and the high-voltage gate pulse signal is a 100V positive pulse signal.

9. A method for controlling a gating circuit of a spaceborne PMT detector, characterized in that: The following steps are involved: S1, low voltage gate pulse signal generation: the FPGA module (31) generates a low voltage gate pulse signal under synchronous triggering and outputs it to the level conversion module (32); S2, generating a high-voltage gate pulse signal: the level conversion module (32) performs level conversion on the low-voltage gate pulse signal and then controls the MOS tube switch module (33) to output a high-voltage gate pulse signal to the voltage divider circuit module (22); S3, PMT detector gated operation: after receiving the high-voltage gated pulse signal, the voltage divider circuit module (22) changes the inter-stage voltage of the multiplication stage of the PMT detector (21) through a parallel multi-stage RC circuit, a DY connection and a voltage divider resistor, and the voltage divider circuit module (22) enhances the freewheeling capability of the PMT detector (21) working under the gated timing by sequentially arranged capacitors.

10. The method for controlling a gating circuit of a space-borne PMT detector according to claim 9, wherein: In step S1, the pulse width of the low-voltage gated pulse signal is 200 μs and the frequency is 20 Hz, and the low-voltage gated pulse signal is a negative pulse signal; In step S2, the level conversion module (32) converts the low-voltage gate pulse signal from 3.3V to 5V, the high-voltage gate pulse signal is a 100V positive pulse signal, and the MOS tube switch module (33) is set to be redundant; In step S3, the high-voltage gate pulse signal is inputted between DY1 and DY2, DY3 and DY4, DY5 and DY6 respectively through a first RC circuit (221), a second RC circuit (222), and a third RC circuit (223) connected in parallel. The inter-stage voltages of DY1 and DY2, DY3 and DY4, DY5 and DY6 are controlled by the charge and discharge characteristics of the first RC circuit (221), the second RC circuit (222), and the third RC circuit (223), so as to perform gate control on the PMT detector (21). At the same time, the capacitance values ​​of the capacitors (226) respectively connected in parallel between DY8 and DY9, DY9 and DY10, and DY10 and GND are increased in a tapered manner, so as to enhance the freewheeling capability of the output signal of the PMT detector (21).

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