Memory circuit and method of performing programming operations

Abstract

A memory circuit includes a first set of non-volatile memory (NVM) devices, a first plurality of decoders, a first plurality of high voltage (HV) drivers corresponding to the first plurality of decoders, and a first plurality of HV power switches. The first HV power switches are coupled to each HV driver of the first plurality of HV drivers, and each decoder is configured to generate an enable signal corresponding to a column of the first set of NVM devices. Each HV driver is configured to output an HV activation signal to a corresponding column of the first set of NVM devices in response to a power signal of the first HV power switch and the enable signal of the corresponding decoder. Embodiments of the invention also provide a method of performing a program operation.

Description

Technical Field

[0001] Embodiments of the present invention relate to a memory circuit and a method for performing programming operations. Background Technology

[0002] Integrated circuits (ICs) sometimes include non-volatile memory (NVM), where data is not lost when the IC is powered off. In some NVM applications, one-time programmable (OTP) memory elements are designed to have an initial logic state that can be irreversibly switched during programming operations. One type of OTP memory includes an antifuse bit integrated into the IC using a dielectric material (oxide, etc.) layer connected to other circuit elements. To program the antifuse bit, a programming electric field is applied to the dielectric material layer to continuously alter (e.g., break down) the dielectric material, thereby reducing the resistance of the dielectric material layer. Typically, to determine the state of the antifuse bit, a read voltage lower than the programming voltage is applied across the dielectric material layer, and the resulting current is read. Summary of the Invention

[0003] According to one aspect of the present invention, a memory circuit is provided, comprising: a first group of non-volatile memory (NVM) devices; a first plurality of decoders, wherein each of the first plurality of decoders is configured to generate an enable signal corresponding to a column of the first group of NVM devices; a first plurality of high voltage (HV) drivers corresponding to the first plurality of decoders; and a first plurality of HV power switches, wherein a first HV power switch of the first plurality of HV power switches is coupled to each of the first plurality of HV drivers, wherein each of the first plurality of HV drivers is configured to output an HV activation signal to a corresponding column of the first group of NVM devices in response to a power signal of the first HV power switch of the first plurality of HV power switches and an enable signal of the corresponding decoder of the first plurality of decoders.

[0004] According to another aspect of the present invention, a memory circuit is provided, comprising: first and second once-programmable (OTP) devices, each OTP device including a read transistor and a programmable transistor. The memory circuit further includes a driver circuit comprising: a first HV power switch configured to generate a first power signal; a second HV power switch configured to generate a second power signal; a first high-voltage (HV) driver configured to output a first HV activation signal to the programmable transistor of the first OTP device in response to the first power signal; and a second HV driver configured to output a second HV activation signal to the programmable transistor of the second OTP device in response to the second power signal, wherein the driver circuit is configured to output the first activation signal to the read transistor of the first OTP device and the second activation signal to the read transistor of the second OTP device, the first activation signal and the first HV activation signal being based on a first enable signal, and the second activation signal and the second HV activation signal being based on the second enable signal.

[0005] According to another aspect of the present invention, a method for performing a programming operation is provided, the method comprising: in response to an address signal having a configuration corresponding to an NVM device in a first group of nonvolatile memory (NVM) devices; generating a first high voltage (HV) power supply signal having a first voltage amplitude; and generating a second HV power supply signal having a second voltage amplitude less than the first voltage amplitude; receiving the first HV power supply signal, the second HV power supply signal, and the address signal at a driver circuit adjacent to the first group of NVM devices and the second group of NVM devices; in response to the address signal having the configuration; outputting a first HV activation signal from the driver circuit to the NVM device, the first HV activation signal having a first voltage amplitude; and outputting a second HV activation signal from the driver circuit to the second group of NVM devices, the second HV activation signal having a third voltage amplitude equal to or less than the second voltage amplitude. Attached Figure Description

[0006] The various aspects of the invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components can be arbitrarily increased or decreased.

[0007] Figure 1A and Figure 1B This is a diagram of a memory circuit according to some embodiments.

[0008] Figure 2 These are illustrations of storage devices according to some embodiments.

[0009] Figure 3A and Figure 3B This is a diagram of a decoding circuit according to some embodiments.

[0010] Figure 4 This is a diagram of a high-voltage (HV) driver according to some embodiments.

[0011] Figure 5A This is a diagram of a driver circuit according to some embodiments.

[0012] Figure 5B This is a diagram showing the driver circuit parameters according to some embodiments.

[0013] Figure 6A This is a diagram of a driver circuit according to some embodiments.

[0014] Figure 6B This is a diagram showing the driver circuit parameters according to some embodiments.

[0015] Figure 7A This is a diagram of a memory circuit according to some embodiments.

[0016] Figure 7B This is a diagram showing the memory circuit parameters according to some embodiments.

[0017] Figure 7C This is a diagram of a memory circuit according to some embodiments.

[0018] Figure 8 This is a flowchart of a method for performing programming operations according to some embodiments. Detailed Implementation

[0019] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components, values, operations, materials, arrangements, etc., are described below to simplify this disclosure. These are merely examples and are not intended to be limiting. Other components, values, operations, materials, arrangements, etc., are contemplated. For example, in the following description, forming a first component on or above a second component can include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components such that the first and second components may not be in direct contact. Furthermore, reference numerals and / or letters may be repeated throughout the various embodiments of the invention. Such repetition is for brevity and clarity only and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0020] Furthermore, for ease of description, spatial relation terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or component and another, as shown in the figures. In addition to the orientations shown in the figures, spatial relation terms are intended to include different orientations of the device during use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spatial relation descriptors used herein can be interpreted accordingly.

[0021] In various embodiments, the memory circuitry includes a dual-path hierarchical arrangement for distributing high voltage (HV) levels during programming and read operations, such that unselected NVM devices in a group adjacent to the device driver circuitry receive a corresponding HV activation signal with a low voltage (LV) or ground voltage level. Compared to a method where NVM devices in an adjacent unselected group receive programming and read voltage levels during programming and read operations in an adjacent selected group, the NVM device current leakage level is reduced, thereby reducing power consumption, and HV stress is reduced, thereby improving NVM device reliability.

[0022] In some embodiments, the dual-path hierarchical arrangement includes an HV power switch and an HV driver, configured to generate an HV activation signal by switching a ground signal from a ground voltage level to an intermediate voltage (MV) level, or by detecting the HV level or based on a delay circuit. Compared to methods that do not include switching the ground signal from a ground voltage level to an MV level, the HV driver can include fewer cascode transistors, thereby reducing area requirements.

[0023] In some embodiments, the dual-path hierarchical arrangement in which the HV power switch is configured to detect the HV level includes a feedback arrangement, thereby controlling the discharge time during NVM device programming operation. Compared to methods that do not include detecting the HV level to control the discharge time, such embodiments can reduce power requirements and avoid residual voltage damage in subsequent operations.

[0024] Figure 1A and Figure 1B This is a diagram of a memory circuit 100 according to some embodiments. Figure 1A This is a block diagram of a non-limiting example of the layout of memory circuitry 100 in the xy-plane, represented by the x-axis and y-axis. Figure 1B This is a schematic diagram of memory circuit 100.

[0025] For the purpose of explanation, simplification has been adopted. Figure 1A and Figure 1B In various embodiments, the memory circuitry 100 includes, in addition to Figure 1A and Figure 1BVarious elements other than those described herein, or arranged in other ways to perform the operations discussed below.

[0026] like Figure 1A As shown, memory circuit 100 is an IC including memory partitions 100A-100D, bit line (BL) driver 100BL, global HV switch circuit 100HV, and functional circuit 100F. Each memory partition 100A-100D includes memory groups 110U and 110D adjacent to driver circuit 110AC (also referred to as activation circuit 110AC in some embodiments). Each memory group 110U and 110D includes array 110AR and BL selection circuit 110BS, and each driver circuit 110AC includes group decoder 110DC.

[0027] Memory partitions (e.g., memory partitions 100A-100D) are part of memory circuitry 100, which includes NVM devices ( Figure 1A (Not shown in the diagram) A subset of adjacent circuitry and a subset of NVM devices configured to selectively access the device during programming and read operations. Figure 1A In the illustrated embodiment, the memory circuit 100 comprises a total of four partitions. In various embodiments, the memory circuit 100 may comprise a total of more or less than four partitions.

[0028] The BL driver 100BL is an electronic circuit configured to control access to one or more electrical paths (e.g., bit lines) for each NVM device in a corresponding memory group 100U or 100D of each memory partition 100A-100D, for example by generating one or more control signals. In some embodiments, the BL driver 100BL includes detection circuitry (not shown), such as a sense amplifier, configured to determine the absolute and / or relative voltage and / or current levels of one or more signals received from the selected NVM device.

[0029] The global HV switching circuit 100HV is an electronic circuit configured to output HV power signals, each with a voltage level VPP corresponding to a programmed operation on the NVM device. Figure 1A (Not shown in the diagram) and the voltage level VRD corresponding to the read operation on the NVM device, where the amplitude of voltage level VPP is greater than the amplitude of voltage level VRD. See below for more information. Figure 1B Further discussion reveals that the global HV switching circuit 100HV includes first and second global HV power switches (…). Figure 1A (not shown in the image), each is configured to output an HV power supply signal with voltage levels VPP and VRD to the corresponding memory group 110U or 110D of each memory partition 100A-100D.

[0030] Functional circuit 100F is an electronic circuit configured to control some or all programming and read operations on each memory partition 100A-100D, for example, by generating and / or outputting one or more control and / or enable signals. In some embodiments, functional circuit 100F includes control circuitry (not shown). In various embodiments, functional circuit 100F includes one or more analog circuits configured to be connected to memory partitions 100A-100D to program data in one or more NVM devices and / or use data received from one or more NVM devices in one or more circuit operations. In some embodiments, functional circuit 100F includes one or more global address decoding or pre-decoding circuits (…). Figure 1A (Not shown in the image), configured to output one or more address signals to the activation circuit 110AC of each memory partition 100A-100D, for example... Figure 1B The address signal 100AD is depicted in the diagram.

[0031] Each driver circuit 110AC is an electronic circuit including a corresponding group decoding circuit 110DC, configured to receive one or more address signals and generate an enable signal corresponding to a neighboring subset of the NVM device identified by the one or more address signals. In some embodiments, the neighboring subset of the NVM device corresponds to a column of the NVM device. In some embodiments, each group decoding circuit 110DC is configured to generate each enable signal as a complementary pair of enable signals. (See below for more details.) Figures 1A-1B and Figures 3A-3B Further discussion reveals that, in various embodiments, each group decoding circuit 110DC is configured to generate each enable signal corresponding to one or both of the adjacent memory groups 110U or 110D of the corresponding memory partitions 100A-100D.

[0032] Each driver circuit 110AC includes a corresponding signal generation circuit. Figure 1A (Not shown in the diagram), configured to generate an activation signal in response to a corresponding enable signal, and output the activation signal to adjacent memory groups 110U and 110D of the corresponding memory partitions 100A-100D. See below for details. Figure 1B Further discussion reveals that each driver circuit 110AC includes an HV power switch and multiple HV drivers corresponding to an adjacent memory group 110U, and an HV power switch and multiple HV drivers corresponding to an adjacent memory group 110D. Thus, each driver circuit 110AC is configured to output a first plurality of HV activation signals to the adjacent memory group 110U in response to a corresponding enable signal and a first power signal received from the corresponding HV power switch, and to output a second plurality of HV activation signals to the adjacent memory group 110D in response to a corresponding enable signal and a second power signal received from the corresponding HV power switch.

[0033] Each memory bank 110U and 110D includes a corresponding BL selection circuit 110BS, configured, for example, based on one or more BL control signals, in response to the BL driver 100BL, to selectively access one or more bit lines (not shown) of a neighboring subset of the NVM devices coupled to the corresponding array 110AR. In some embodiments, the neighboring subset of the NVM devices corresponds to a row of the NVM devices.

[0034] Each memory group 110U and 110D includes a corresponding array 110AR, including an NVM device 112, which is described below. Figure 1B Further discussion reveals that the adjacent BL selection circuit 110BS and adjacent driver circuit 110AC are configured to be accessed during programming and reading operations as described above.

[0035] NVM device 112 is an electrical, electromechanical, electromagnetic, or other device configured to store bit data represented by logic states. At least one logic state of NVM device 112 can be programmed in a write operation and detected in a read operation. In some embodiments, the logic state corresponds to the voltage level of a charge stored in a given NVM device 112. In some embodiments, the logic state corresponds to a physical characteristic of a component of a given NVM device 112, such as resistance or magnetic orientation.

[0036] In various embodiments, the NVM device 112 includes one or more OTP memory devices, such as electronic fuse or antifuse devices, flash memory devices, random access memory (RAM) devices, resistive RAM devices, ferroelectric RAM devices, magnetoresistive RAM devices, erasable programmable read-only memory (EPROM) devices, electrically erasable programmable read-only memory (EEPROM) devices, etc. In some embodiments, the NVM device 112 is an OTP memory device, including the following regarding... Figure 2 One or more OTP devices 200 are discussed.

[0037] exist Figure 1B In the schematic diagram of memory circuitry 100, representative features of a single memory partition 100A are included, as well as representative features of a portion of each corresponding instance of memory groups 110U and 110D and driver circuitry 110AC within memory partition 100A. Each instance of memory groups 110U and 110D includes a corresponding instance of array 110AR, comprising multiple adjacent subsets of memory devices 112, each adjacent subset being in... Figure 1BThe image represents a single instance of memory device 112. In some embodiments, each adjacent subset of memory device 112 corresponds to a column of memory device 112 in a given array 110AR. For clarity, the BL driver 100BL, bit line selection circuitry 110BS, and bit lines are not shown in the image. Figure 1B As shown in the image.

[0038] Functional circuit 100F includes a global decoder (not shown) coupled to each instance of driver circuit 110AC corresponding to memory partitions 100A-100D. Global HV switch circuit 100HV includes global HV power switches HVSU and HVSD, each of which is coupled to each instance of driver circuit 110AC.

[0039] Two or more circuit elements are considered to be coupled based on one or more direct signal connections and / or one or more indirect signal connections (including one or more logic devices, such as inverters or logic gates) between the two or more circuit elements. In some embodiments, the signal communication between the two or more coupled circuit elements can be modified by one or more logic devices, for example, by inverting or making it conditional.

[0040] Each instance of the driver circuit 110AC includes an HV power switch HVPSU coupled to a global HV power switch HVSU and an HV power switch HVPSD coupled to a global HV power switch HVSD. Thus, each instance of the HV power switch HVPSU is configured to receive an HV power signal HVU from the global HV power switch HVSU, and each instance of the HV power switch HVPSD is configured to receive an HV power signal HVD from the global HV power switch HVSD.

[0041] Each portion of each driver circuit 110AC includes a corresponding portion of the group decoding circuit 110DC, which is coupled to a corresponding adjacent subset of the memory devices 112 of each of the global decoder and memory groups 110U and 110D. Each portion of each driver circuit 110AC also includes two instances of the HV driver HVDR. One instance of the HV driver HVDR is coupled to the HV power switch HVPSU, a portion of the group decoding circuit 110DC, and an adjacent subset of the memory devices 112 of the memory group 110U. The other instance of the HV driver HVDR is coupled to the HV power switch HVPSD, a portion of the group decoding circuit 110DC, and an adjacent subset of the memory devices 112 of the memory group 110D.

[0042] Each portion of the group decoding circuit 110DC is thus configured to receive one or more address signals 100AD from the global decoder. Each instance of the HV driver HVDR corresponding to the memory group 110U is thus configured to receive a power signal PSU and a ground signal AGU from the HV power switch HVPSU, and an enable signal ENU from a portion of the group decoding circuit 110DC. Each instance of the HV driver HVDR corresponding to the memory group 110D is thus configured to receive a power signal PSD and a ground signal AGD from the HV power switch HVPSD, and an enable signal END from a portion of the group decoding circuit 110DC.

[0043] Thus, each subset of the memory devices 112 of the memory group 110U is configured to receive an activation signal WLRU from a corresponding portion of the group decoding circuit 110DC and an HV activation signal WLPU from a corresponding HV driver HVDR, and thus each subset of the memory devices 112 of the memory group 110D is configured to receive an activation signal WLRD from a corresponding portion of the group decoding circuit 110DC and an HV activation signal WLPD from a corresponding HV driver HVDR.

[0044] Each global HV power switch, HVSU and HVSD, is an electronic circuit that includes at least one switching device. Figure 1B (Not shown) and configured to generate corresponding HV power signals HVU or HVD, which have voltage levels VPP and VRD corresponding to the respective programming and read operations on the NVM device 112. In various embodiments, each global HV power switch HVSU and HVSD is configured to output a corresponding HV power signal HVU or HVD, which has a positive or negative polarity relative to the ground voltage level.

[0045] In operation, the global HV power switch HVSU is configured to generate an HV power signal HVU with voltage level VPP in response to a first enable signal (not shown) indicating that programming operation is being performed on an NVM device in one of the memory groups 110U, otherwise with voltage level VRD. The global HV power switch HVSD is configured to generate an HV power signal HVD with voltage level VPP in response to a second enable signal (not shown) indicating that programming operation is being performed on an NVM device in one of the memory groups 110D, otherwise with voltage level VRD. In some embodiments, the first and second enable signals are received from functional circuitry 100F.

[0046] In some embodiments, global HV power switches HVSU and HVSD are the same global HV power switches configured to generate HV power signals HVU and HVD as the same HV power signal, which has a voltage level VPP in response to a single enable signal (e.g., received from functional circuitry 100F indicating that a programming operation is being performed on an NVM device in one of memory groups 110U or 110D), or a voltage level VRD otherwise.

[0047] In some embodiments, each global HV power switch HVSU and HVSD is configured to generate a corresponding HV power signal HVU or HVD with a voltage level VPP ranging from 3 volts (V) to 8 V. In some embodiments, each global HV power switch HVSU and HVSD is configured to generate a corresponding HV power signal HVU or HVD with a voltage level VPP ranging from 4 V to 6 V. In some embodiments, each global HV power switch HVSU and HVSD is configured to generate a corresponding HV power signal HVU or HVD with a voltage level VPP approximately equal to 4.8 V.

[0048] In some embodiments, each global HV power switch HVSU and HVSD is configured to generate a corresponding HV power signal HVU or HVD with a voltage level VRD ranging from 0.8V to 3V. In some embodiments, each global HV power switch HVSU and HVSD is configured to generate a corresponding HV power signal HVU or HVD with a voltage level VRD ranging from 1V to 1.8V. In some embodiments, each global HV power switch HVSU and HVSD is configured to generate a corresponding HV power signal HVU or HVD with a voltage level VRD approximately equal to 1.35V.

[0049] In some embodiments, the global HV power switches HVSU and / or HVSD include a global HV power switch 750, as described below. Figures 7A-7C The subject of discussion.

[0050] Each instance of the HV power switch HVPSU and HVPSD is an electronic circuit that includes at least one switching device. Figure 1B (not shown in the image) and configured to receive the corresponding HV power signal HVU or HVD, MV power signal, LV power signal and HV enable signal ( Figure 1B (not shown in the image), and in response to the HV enable signal, generates a corresponding power supply / ground signal PSU / AGU or PSD / AGD with one of the first or second pair of voltage levels.

[0051] The MV power signal is a power signal having a predetermined MV level between the voltage level VPP and the ground voltage level. In some embodiments, the predetermined MV level is between the voltage level VPP and VRD. In some embodiments, the difference between the voltage level VPP and the predetermined MV level is configured to avoid the transistor in the HV driver HVDR (e.g., hereinafter referred to as...). Figure 4 The overload of transistors P1, P2, N4, and N5 of the HV driver 400 is discussed.

[0052] In some embodiments, the predetermined MV level has a value ranging from 2.5V to 3V. In some embodiments, the predetermined MV level is approximately equal to 2.7V.

[0053] The LV power signal is a power signal having a predetermined LV level between the voltage level VRD and the ground voltage level. In some embodiments, the LV power signal is the power supply voltage of the memory circuit 100. In some embodiments, the predetermined LV level corresponds to a high logic state of various signals (e.g., enable signals) of the memory circuit 100, and the ground voltage level corresponds to a low logic state of various signals.

[0054] In some embodiments, the predetermined LV level has a value ranging from 0.8V to 1.8V. In some embodiments, the predetermined LV level is approximately equal to 1.2V.

[0055] The HV enable signal is configured to have a first logic state corresponding to no access to any of the NVM devices 112 in the corresponding memory groups 110U or 110D during a programming or read operation, and a second logic state corresponding to access to the NVM devices 112 in the corresponding memory groups 110U or 110D during a programming or read operation. In some embodiments, the HV enable signal is received from the functional circuitry 100F.

[0056] In operation, in response to an HV enable signal having a first logic state, each instance of the HV power switches HVPSU and HVPSD is configured to generate a corresponding power signal PSU or PSD with a voltage level of the LV power signal and a corresponding ground signal AGU or AGD with a ground voltage level. In response to an HV enable signal having a second logic state, each instance of the HV power switches HVPSU and HVPSD is configured to generate a corresponding power signal PSU or PSD with a voltage level VPP or VRD corresponding to the HV power signal HVU or HVD.

[0057] In response to an HV enable signal having a second logic state, each instance of the HV power switches HVPSU and HVPSD is configured to further generate a corresponding ground signal AGU or AGD with a ground voltage level or a voltage level of the MV power signal based on the voltage level of the corresponding HV power signal HVU or HVD. Each instance of the HV power switches HVPSU and HVPSD is configured to generate a corresponding ground signal AGU or AGD with a voltage level of the MV power signal when the corresponding HV power signal HVU or HVD has a voltage level VPP, and to generate a ground signal AGU or AGD with a ground voltage level when the corresponding HV power signal HVU or HVD has a voltage level VRD.

[0058] In some embodiments, the HV power switches HVPSU and / or HVPSD include a detection circuit configured to control the generation of a corresponding ground signal AGU or AGD based on the detected voltage level of the corresponding HV power signal HVU or HVD. In some embodiments, the HV power switches HVPSU and / or HVPSD include the following... Figure 5A and Figure 5B Discussion of HV power switches 500 or below Figures 7A-7C The HV power switch 700 is under discussion.

[0059] In some embodiments, the HV power switches HVPSU and / or HVPSD include delay and level shifter circuitry configured to control the generation of a corresponding ground signal AGU or AGD based on an HV enable signal and one or more additional signals. In some embodiments, the HV power switches HVPSU and / or HVPSD include the following regarding... Figure 6A and Figure 6B The HV power switch 600 is under discussion.

[0060] The group decoding circuit 110DC is an electronic circuit in which each part includes one or more logic gates (not shown) configured to generate corresponding enable signals ENU and END in response to the address signal 100AD. Each part of the group decoding circuit 110DC is configured to generate corresponding enable signals ENU and END having logic states (configured such that a corresponding subset of the NVM device 112 identified by the address signal 100AD is activated during programming and read operations). In some embodiments, each part of the group decoding circuit 110DC is configured to generate corresponding enable signals ENU and END as complementary pairs, each pair in Figure 1B The value is represented as either the enable signal ENU or END.

[0061] exist Figure 1BIn the illustrated embodiment, each portion of the group decoding circuit 110DC is configured to generate and output activation signals WLRU to a corresponding subset of NVM devices 112 in memory group 110U and to generate and output activation signals WLRD to a corresponding subset of NVM devices 112 in memory group 110D. Each portion of the group decoding circuit 110DC is configured to output each activation signal WLRU and WLRD having a logic state (configured to activate a corresponding subset of NVM devices 112 in programming and read operations based on the logic states of the corresponding enable signals ENU and END). In some embodiments, each portion of the group decoding circuit 110DC is configured to generate and output activation signal WLRU as a signal identical to some or all of the enable signals ENU, and to generate and output activation signal WLRD as a signal identical to some or all of the enable signals END.

[0062] In some embodiments, each driver circuit 110AC includes a portion of a group decoding circuit 110DC, configured such that a corresponding subset of the NVM device 112 identified by the address signal 100AD is activated during programming and reading operations, for example by including a buffer and / or inverter (not shown) coupled between each portion of the group decoding circuit 110DC and the corresponding subset of the NVM device 112, the buffer and / or inverter being configured to generate a corresponding activation signal WLRU or WLRD in response to a corresponding enable signal ENU or END.

[0063] In some embodiments, each portion of the group decoding circuit 110DC includes a single decoder configured to generate enable signals ENU and END as identical enable signals and generate activation signals WLRU and WLRD as identical activation signals based on address signals 100AD that identify any adjacent subset of the NVM device 112 as activated in programming and read operations. In some embodiments, each portion of the group decoding circuit 110DC includes the following regarding... Figure 3A The decoding circuit discussed is 300A.

[0064] In some embodiments, each portion of the group decoding circuit 110DC includes: a first decoder configured to generate an enable signal ENU and an activation signal WLRU based on an address signal 100AD that identifies a subset of NVM devices 112 of adjacent memory groups 110U as activated during programming and read operations; and a second decoder configured to generate an enable signal END and an activation signal WLRD based on the address signal 100AD that identifies a subset of NVM devices 112 of adjacent memory groups 110U as activated during programming and read operations. In some embodiments, each portion of the group decoding circuit 110DC includes the following regarding... Figure 3B The decoding circuit 300B is discussed.

[0065] Each instance of an HV driver (HVDR) is an electronic circuit comprising multiple transistors ( Figure 1B (not shown in the image), is configured to generate and output an HV activation signal WLPU or WLPD in response to the corresponding enable signal ENU and power / ground signal PSU / AGU or enable signal END and power / ground signal PSD / AGD.

[0066] Each instance of the HV driver is configured to generate a corresponding HV activation signal WLPU or WLPD with a voltage level of the corresponding power supply signal PSU or PSD in response to a corresponding enable signal ENU or END having a logic state (configured to activate the corresponding subset of NVM device 112 in a programming or read operation), otherwise generating a corresponding HV activation signal WLPU or WLPD with a ground voltage level.

[0067] In some embodiments, the HV driver HVDR includes the following about Figure 4 The HV drive 400 is under discussion.

[0068] As described above, each instance of the HV power switches HVPSU and HVPSD is configured to output a corresponding power signal PSU or PSD with voltage level VPP in response to performing a programming operation on the NVM device 112 in the corresponding memory group 110U or 110D, and to output a corresponding power signal PSU or PSD with voltage level VRD in response to performing a read operation on the NVM device 112 in the corresponding memory group 110U or 110D, otherwise having the voltage level of the LV power signal.

[0069] In an embodiment where each part of the group decoding circuit 110DC is configured to generate enable signals ENU and END as the same enable signal, each instance of the HV driver is thus configured to output a corresponding HV activation signal WLPU or WLPD with a voltage level VPP or VRD corresponding to the power supply signal PSU or PSD in response to performing a programming or read operation on a subset of the NVM devices in one of the memory groups 110U and 110D adjacent to the driver circuit 110AC, and to output a corresponding HV activation signal WLPU or WLPD with a voltage level LV power supply signal in response to performing a programming or read operation on a subset of the NVM devices in the other of the memory groups 110U and 110D adjacent to the driver circuit 110AC.

[0070] In an embodiment where each part of the group decoding circuit 110DC is configured to generate enable signals ENU and END as separate enable signals, each instance of the HV driver is thereby configured to output a corresponding HV activation signal WLPU or WLPD with a voltage level VPP or VRD corresponding to the power supply signal PSU or PSD in response to performing a programming or read operation on a subset of the NVM devices in one of the memory groups 110U and 110D adjacent to the driver circuit 110AC, and to output a corresponding HV activation signal WLPU or WLPD with a ground voltage level in response to performing a programming or read operation on a subset of the NVM devices in the other of the memory groups 110U and 110D adjacent to the driver circuit 110AC.

[0071] Therefore, during programming and reading operations, a subset of NVM devices in the unselected group of adjacent groups 110U and 110D are configured to receive the corresponding HV activation signal WLPU or WLPD with an LV or ground voltage level. Compared to the method where NVM devices in the unselected adjacent group receive programming and reading voltage levels during programming and reading operations on the selected adjacent group (sometimes referred to as interference events), the NVM device current leakage level is reduced, thereby reducing power consumption and reducing HV stress, thus improving NVM device reliability.

[0072] In some embodiments, each HV power switch HVPSU and HVPSD is configured to cause the corresponding HV driver HVDR to generate an HV activation signal WLPU or WLPD by switching the ground signal AGU or AGD from a ground voltage level to an MV level. Compared to methods that do not include switching the ground signal from a ground voltage level to an MV level, the HV driver HVDR can thus include fewer cascode transistors, thereby reducing area requirements.

[0073] Figure 2 This is a schematic diagram of an OTP device 200 according to some embodiments. The OTP device 200 (also referred to as an antifuse device 200 in some embodiments) can be used as described above regarding... Figure 1A and Figure 1B Some or all of the NVM devices discussed 112.

[0074] OTP device 200 includes a programming transistor 210 and a read transistor 220. The programming transistor 210 includes a gate 212 and a source / drain (S / D) terminal 214, the read transistor 220 includes a gate 222 and an S / D terminal 224, and the programming transistor 210 and the read transistor 220 share an S / D terminal 230.

[0075] exist Figure 2In the illustrated embodiment, each of the programming transistor 210 and the read transistor 220 is an NMOS transistor. In some embodiments, one or both of the programming transistor 210 or the read transistor 220 are PMOS transistors.

[0076] Gate 212 is coupled to an instance of the HV driver HVDR and is thus configured to receive an HV activation signal WLP corresponding to one of the HV activation signals WLPU or WLPD as described above. S / D terminal 214 is electrically isolated from circuit elements external to transistor 210 and is therefore considered to have a floating voltage level.

[0077] Gate 222 is coupled to a portion of the group decoding circuit 110DC and is thus configured to receive an HV activation signal WLR corresponding to one of the activation signals WLRU or WLRD as described above. S / D terminal 224 is coupled to a bit line and is thus configured to receive the bit line signal BL as described above.

[0078] S / D terminal 230 is electrically isolated from components outside transistors 210 and 220 and is thus configured as a conductive path between transistors 210 and 220.

[0079] Each of gates 212 and 222 shares an electrical connection with a corresponding gate of another instance (not shown) of OTP device 200, such that a corresponding subset (e.g., column) of OTP device 200 is configured to receive the same instance of activation signal WLRU or WLRD and HV activation signal WLPU or WLPD. S / D terminal 224 shares an electrical connection with a corresponding S / D terminal of another instance (not shown) of OTP device 200, such that a corresponding subset (e.g., row) of OTP device 200 is configured to receive the same instance of bit line signal BL. Each instance of OTP device 200 is thus configured to receive a unique combination of activation signal WLR, HV activation signal WLP, and bit line signal BL.

[0080] During programming and reading operations on the OTP device 200, a signal WLP is applied to the gate 212, and the transistor 220 is turned on in response to the signal WLR applied to the gate 222 and the bit line signal BL having a ground voltage level.

[0081] Prior to programming, the dielectric layer of gate 212 is configured as an insulator with high resistance, representing a logic high level in some embodiments. During programming, the signal WLP has the voltage level VPP discussed above, whereby the difference between the first voltage level and the ground voltage level generates a sufficiently large electric field on the dielectric layer of gate 212 to sustainably alter the dielectric material such that, in some embodiments, the resulting reduced resistance represents a logic low level.

[0082] During the read operation, the signal WLP has the voltage level VRD discussed above, whereby the difference between the second voltage level and the ground voltage level generates an electric field small enough to avoid continuously altering the dielectric material of the gate 212 and large enough to generate a current flowing through the S / D terminals 230 and 224 with an amplitude that can be sensed by a sensing amplifier (not shown), thereby determining the programming state of the OTP device 200.

[0083] Based on the configurations discussed above, and according to the above regarding... Figure 1A and Figure 1B The discussion of the memory circuit 100 shows that the OTP device 200 can be programmed and read in response to activation signals WLRU and WLRD and HV activation signals WLPU and WLPD, enabling the memory circuit 100 including the OTP device 200 to achieve the aforementioned benefits.

[0084] Figure 3A and Figure 3B This is a diagram illustrating decoding circuits 300A and 300B according to some embodiments. Each of decoding circuits 300A and 300B can be used as described above regarding... Figure 1A and Figure 1B A portion of the group decoding circuit 110DC under discussion. Decoding circuit 300A corresponds to an embodiment in which a portion of the group decoding circuit 110DC is configured to output enable / activation signals ENU / WLRU and END / WLRD as the same enable / activation signal, and decoding circuit 300B corresponds to an embodiment in which a portion of the group decoding circuit 110DC is configured to output enable / activation signals ENU / WLRU and END / WLRD as separate enable / activation signals.

[0085] The decoding circuit 300A includes a decoder 310A coupled to drivers DU and DD. The decoder 310A is configured to receive address signal 100AD and output a single enable signal ENU / END.

[0086] A decoder (e.g., decoder 310A) is a logic circuit configured to generate enable signals, such as enable signals ENU and / or END, having a first logic state based on a received signal (e.g., address signal 100AD), having a predetermined combination of logic states, such as addresses corresponding to a subset of NVM device 112, or otherwise having a second logic state. In some embodiments, the decoder is configured to generate enable signals as complementary pairs. In some embodiments, the decoder includes combinations of logic gates, such as inverters and / or NAND, NOR, and / or other suitable gates.

[0087] A driver (e.g., driver DU or DD) is an electronic circuit configured to generate an activation signal, such as an activation signal WLRU or WLRD, having a logic state based on a received signal (e.g., an enable signal ENU or END) and a maximum voltage level based on a received power supply signal. In various embodiments, the maximum voltage level of the activation signal is equal to or greater than the maximum voltage level of the received signal. In various embodiments, the driver includes one or more inverters and / or buffers. In some embodiments, the driver includes an output inverter or buffer configured to generate an activation signal including a drive current configured to charge a combined capacitor of a subset (e.g., a column) of NVM devices.

[0088] exist Figure 3A In the illustrated embodiments, each driver DU and DD is configured to receive a single enable signal ENU / END from the decoder 310A and generate corresponding activation signals WLRU and WLRD as the same activation signal. In some embodiments, drivers DU and DD are configured to generate corresponding activation signals WLRU and WLRD as a complementary pair based on the enable signal ENU / END received from the decoder 310A. In some embodiments, each driver DU and DD is configured to receive a single enable signal ENU / END from the decoder 310A and generate complementary signals, whereby the enable signal ENU / END is output from the decoding circuit 300A as a complementary pair. In some embodiments, the decoding circuit 300A does not include drivers DU and DD and is configured to output the enable signal ENU / END as the activation signal WLRU / WLRD.

[0089] Thus, the decoding circuit 300A is configured to generate an enable signal ENU / END and an activation signal WLRU / WLRD (if applicable) in response to the memory signal 100AD being configured to indicate the performance of programming or reading operations on NVM devices 112 in either a subset of NVM devices 112 in adjacent memory group 110U or a subset of NVM devices 112 in adjacent memory group 110D.

[0090] Decoding circuit 300B includes decoder 310B coupled to driver DU and decoder 310B coupled to driver DD. Each instance of decoder 310B is configured to receive address signal 100AD. A first instance of decoder 310B is configured to output enable signal ENU, and a second instance of decoder 310B is configured to output enable signal END. Drivers DU and DD are configured to receive separate enable signals ENU and END from instances of decoder 310B and generate corresponding separate activation signals WLRU and WLRD. In some embodiments, drivers DU and DD are configured to generate corresponding activation signals WLRU and WLRD as a complementary pair based on receiving enable signals ENU and END from decoder 310B. In some embodiments, each driver DU and DD is configured to receive a single enable signal ENU or END from the corresponding decoder 310B and generate complementary signals, whereby the enable signals ENU or END are output from decoding circuit 300B as a complementary pair. In some embodiments, the decoding circuit 300B does not include drivers DU and DD, and is configured to output enable signals ENU and END as activation signals WLRU and WLRD.

[0091] The decoding circuit 300B is thus configured to generate an enable signal ENU and an activation signal WLRU (if applicable) in response to the memory signal 100AD being configured to indicate the performance of programming or reading operations on NVM devices 112 in a subset of NVM devices 112 in adjacent memory groups 110U, and to generate an enable signal END and an activation signal WLRD (if applicable) in response to the memory signal 100AD being configured to indicate the performance of programming or reading operations on NVM devices 112 in a subset of NVM devices 112 in adjacent memory groups 110D.

[0092] With the configuration discussed above, each of the decoding circuits 300A and 300B can, according to the above description of the group decoding circuit 110DC, and Figure 1A and Figure 1B The discussion generates enable signals ENU and END, as well as activation signals WLRU and WLRD, enabling the memory circuit 100, including decoding circuits 300A or 300B, to achieve the aforementioned benefits.

[0093] Figure 4 This is a diagram of an HV driver 400 according to some embodiments. The HV driver 400 (also referred to in some embodiments as a hybrid latch 400 or a two-phase hybrid latch 400) can be used as described above regarding... Figure 1A and Figure 1B Some or all of the HV drives in the HVDR are discussed.

[0094] The HV driver 400 includes a power signal node PSN configured to receive a power signal PS corresponding to one of power signals PSU or PSD, a ground node AGN configured to receive a ground signal AG corresponding to one of ground signals AGU or AGD, and an output node WLPN configured to output an HV activation signal WLP corresponding to one of HV activation signals WLPU or WLPD, each described above. Figure 1A and Figure 1B A discussion was held.

[0095] PMOS transistor P1 and NMOS transistor N4 are coupled in series between the power signal node PSN and the ground node AGN. PMOS transistor P2 and NMOS transistor N5 are also coupled in series between the power signal node PSN and the ground node AGN. The gates of transistors P1 and N4 are coupled to each other and to the source terminals of transistors P2 and N5, and the gates of transistors P2 and N5 are coupled to each other and to the source terminals of transistors P1 and N4. PMOS transistors P1 and P2 and NMOS transistors N4 and N5 are thus arranged as a latch circuit, configured to latch one pair of coupled gates of transistors P1 and N4 or P2 and N5 to the voltage level of the power signal PS, and to latch the other pair of coupled gates of transistors P1 and N4 or P2 and N5 to the voltage level of the ground signal AG.

[0096] NMOS transistors N1 and N6 are coupled in series, and this series connection is arranged in parallel with NMOS transistor N4. NMOS transistors N2 and N7 are coupled in series, and this series connection is arranged in parallel with NMOS transistor N5. PMOS transistors P3 and P4 are coupled in series between the power signal node PSN and the output node WLRN. NMOS transistors N3 and N8 are coupled in series between the output node WLRN and a ground reference node configured to have a ground voltage level. The gate of PMOS transistor P3 is coupled to the coupled gate pair of transistors P2 and N5.

[0097] PMOS transistor P4 is configured to receive a cascode bias voltage VPCB, and each of NMOS transistors N1-N3 is configured to receive a cascode bias voltage VNCB. NMOS transistor N6 is configured to receive a bias voltage corresponding to the voltage described above. Figure 1A , Figure 1B , Figure 3A and Figure 3B The enable signal discussed is either ENU or END, and transistors N7 and N8 are configured to receive an enable signal ENB that is complementary to the enable signal EN.

[0098] The common-source cascode bias voltage VPCB has a voltage level relative to the power supply signal PS (configured to maintain the voltage drop across the element of PMOS transistor P3 at or below a predetermined PMOS overstress level), and the common-source cascode bias voltage VNCB has a voltage level relative to the ground signal AG (configured to maintain the voltage drop across the element of each of NMOS transistors N1-N3 at or below a predetermined NMOS overstress level).

[0099] The enable signal EN / ENB is configured to have a high / low logic state combination when selecting an NVM device coupled to the output node WLPN during programming or read operations, and a low / high logic state combination otherwise.

[0100] The HV driver 400 is thus configured to respond to an enable signal EN / ENB with a low / high logic state combination by turning off NMOS transistor N6 and turning on NMOS transistors N7 and N8 during operation. This causes the coupled gates of transistors P1 and N4 to have a voltage level of the ground signal AG, and the coupled gates of transistors P2, P3, and N5 to have a voltage level of the power supply signal PS. This voltage level causes PMOS transistor P3 to turn off and NMOS transistor N8 to turn on, thereby decoupling the output node WLPN from the power supply signal node PSN and coupling the output node WLPN to a ground reference node, causing the HV activation signal WLP to have a ground voltage level.

[0101] In response to an enable signal EN / ENB with a combination of high / low logic states, the HV driver 400 is thus configured to turn on NMOS transistor N6 and turn off NMOS transistors N7 and N8, thereby causing the coupled gates of transistors P1 and N4 to have a power supply signal PS voltage level, and the coupled gates of transistors P2, P3, and N5 to have a ground signal AG voltage level. This voltage level causes PMOS transistor P3 to turn on and NMOS transistor N8 to turn off, thereby decoupling the output node WLPN from the ground reference node and coupling the output node WLPN to the power supply signal node PSN, causing the HV activation signal WLP to have a power supply signal PS voltage level.

[0102] As described above, each HV power switch HVPSU and HVPSD is configured to output a corresponding power / ground signal PSU / AGU or PSD / AGD with a voltage level VPP or VRD / MV power signal voltage level in response to selecting the NVM device in the corresponding memory group 110U or 110D during a programming or read operation, otherwise with an LV power / ground voltage level. Therefore, the enable signal EN / ENB with a combination of high / low logic states occurs when the power / ground signal PS / AG has a voltage level VPP or VRD / MV power signal voltage level, causing the HV activation signal WLP to be output at the output node WLPN with a voltage level VPP during programming operations and with a voltage level VRD during read operations.

[0103] When the enable signal EN / ENB has a low / high logic state combination, the activation signal WLP is output on the output node WLPN, with a ground voltage level independent of the voltage level of the corresponding power / ground signal PSU / AGU or PSD / AGD received as power / ground signal PS / AG.

[0104] The programming operations for the HV drive 400 are described below. Figures 5A-7C Further discussion. Figure 5A , Figure 6A , Figure 7A and Figure 7C Each of these is a simplified circuit diagram of a portion of the memory circuit 100 for illustrative purposes. Figure 5B , Figure 6B and Figure 7B Each of these is a diagram of the corresponding memory circuit parameters. Figure 5B , Figure 6B and Figure 7B The parameters depicted are non-limiting examples presented for illustrative purposes. In various embodiments, the memory circuitry 100 includes, in addition to Figure 5B , Figure 6B and Figure 7B Operational parameters other than those described in the text, thereby performing programming operations as discussed in this article.

[0105] Figure 5A This is a diagram of the driver circuit 110AC. Figure 5B This is a diagram illustrating the corresponding driver circuit parameters according to some embodiments. Figure 5A In the non-limiting example depicted, the driver circuit 110AC includes the components described above. Figure 4 The HV driver 400 discussed above and can be used as mentioned above. Figure 1B The HV power switch discussed is the HV power switch 500 of the HVPSU or HVPSD type. For illustrative purposes, Figure 5AIncludes a simplified version of the HV drive 400.

[0106] The HV power switch 500 includes a level shifter / power switch S1 coupled to the power signal node PSN of the HV driver 400. A PMOS transistor P5, an NMOS transistor N9, and a current source IS1 are coupled in series between the power signal node PSN and the ground reference node, and NMOS transistors N10 and N11 are coupled in series between the power signal node / signal MV and the ground reference node. The junction between transistors P5 and N9 is coupled to the gate of NMOS transistor N10. The inverter IN1 includes an input terminal coupled to the junction between NMOS transistor N9 and current source IS1 and an output terminal coupled to the gate of NMOS transistor N11. The junction between NMOS transistors N10 and N11 is coupled to the ground node AGN of the HV driver 400.

[0107] Level converter / power switch S1 is an electronic circuit configured to receive an HV enable signal ENHV, an LV power signal LV, and an HV power signal HV corresponding to either the HV power signal HVU or HVD, each described above. Figure 1B The discussion focused on the level shifting section, which is configured to control the gates of multiple transistors (unlabeled) in response to an enable signal ENHV converted according to the voltage level VPP or VRD of the HV power signal HV. The level shifter / power switch S1 is thus configured to output a power signal PS at the power signal node PSN during operation, having one of the voltage levels of the HV power signal HV (VPP or VRD) or the LV power signal LV.

[0108] The gate of PMOS transistor P5 is configured to receive a reference voltage VDET, the gate of NMOS transistor N9 is configured to receive a common-source gate bias voltage VNCB, and when each of transistors P5 and N9 is turned on during programming operation as described below, current source IS1 is configured to limit the current conducted through transistors P5 and N9.

[0109] Transistors P5 and N9, along with current source IS1, are thus arranged as HV level detectors, configured to generate signal HVF1 at the gate of NMOS transistor N10 and HVF2 at the gate of NMOS transistor N10 in response to the voltage level of the power supply signal PS relative to the voltage levels of the reference voltage VDET and the cascode bias voltage VNCB. NMOS transistors N10 and N11 are thus arranged as ground signal switches, configured to output a ground signal AG at ground node AGN in response to the voltage levels of signals HVF1 and HVF2 relative to the voltage levels of the MV power supply signal MV and the ground voltage level.

[0110] refer to Figure 5B Further discussion on the operation of the HV power switch 500. Figure 5B This includes a power signal PS, a ground signal AG, a signal HVF1, and an HV enable signal ENHV plotted over time (unlabeled). The power signal PS is plotted relative to a reference voltage VDT1 corresponding to a reference voltage VDET plus the threshold voltage of the PMOS transistor P5. In some embodiments, the HV power switch 500 and the reference voltage VDET are configured such that the reference voltage VDT1 has a voltage level approximately equal to half of the voltage level VPP. The programming operation is divided into a first stage PH1, followed by a second stage PH2.

[0111] At the start of the programming operation phase PHL, the enable signals EN / ENB have a combination of high / low logic states, thereby causing the HV activation signal WLP to have the state as described above. Figure 4 The voltage level of the power supply signal PS is discussed. Based on the HV enable signal ENHV having a ground voltage level, the power supply signal PS has a voltage level LV, causing the PMOS transistor to be off. Signal HVF1 has a low logic state, causing the NMOS transistor N10 to be off. Signal HVF2 has a high logic state, causing the NMOS transistor N11 to be on. The ground signal node AGN is decoupled from the voltage node / level MV and coupled to the ground reference node, and the ground signal AG has a ground voltage level. (The rest of the text appears to be unrelated and possibly machine-generated.) Figure 5A and Figure 5B As shown, the HV power switch 500 is thus controlled to output a power signal PS with a voltage level LV, and the HV driver 400 is thus configured to output an HV activation signal WLP with a voltage level LV.

[0112] At the end of phase PH1 and the beginning of phase PH2, the HV enable signal ENHV switches from the ground voltage level to the voltage level LV, thereby causing the level converter / power switch S1 to ramp up the output power signal PS from the voltage level LV to the voltage level VPP of the HV power signal HV (corresponding to the programming operation), described as transformation T1.

[0113] The power supply signal PS increases to a level higher than the reference voltage VDT1, causing PMOS transistor P5 to conduct, resulting in signal HVF1 having a voltage level VPP equal to the power supply signal HV (and signal HVF2 having a ground voltage level), described as transformation T2. ​​Signal HVF1 having a voltage level VPP equal to the power supply signal HV causes NMOS transistor P11 to conduct (and signal HVF2 having a ground voltage level causes NMOS transistor P11 to turn off), causing the ground signal node AGN to couple to the voltage node / level MV and decouple from the ground reference node. Signal AG is output as the voltage level MV, described as transformation T3.

[0114] At the end of stage PH2, the power supply signal PS has a voltage level VPP equal to the power supply signal HV. For example... Figure 5A and Figure 5B As shown, the HV power switch 500 is thus controlled to output a power signal PS having a voltage level VPP of the HV power signal HV, and the HV driver 400 thereby latches the output HV activation signal WLP to the voltage level VPP of the HV power signal HV while receiving a ground signal AG having a voltage level MV.

[0115] Figure 6A This is a diagram of the driver circuit 110AC. Figure 6B This is a diagram illustrating the corresponding driver circuit parameters according to some embodiments. Figure 6A In the non-limiting example depicted, the driver circuit 110AC includes the components described above. Figure 4 The HV driver 400 discussed above and can be used as mentioned above. Figure 1B The HV power switch discussed is the HVPSU or HVPSD HV power switch 600. For illustrative purposes, Figure 6A Includes a simplified version of the HV drive 400.

[0116] The HV power switch 600 includes, as mentioned above, the HV power switch 500 and... Figure 5A The configuration discussed includes a level shifter / power switch S1, transistors N10 and N11, and an inverter IN1. Instead of transistors P5 and N9 and current source CS1, the HV power switch 600 includes a delay and HV level shifter circuit D1, also referred to as a delay circuit D1 in some embodiments.

[0117] The delay circuit D1 is an electronic circuit configured to receive the HV enable signal ENHV and, in response to the rising edge of the HV enable signal ENHV, output to the rising edge of each of the control signal (unmarked) to the inverter IN1 and the signal HVF1 (as a switching level) after a predetermined delay time.

[0118] like Figure 6B As shown, signals ENHV, HVF1, AG, and PS have the same characteristics as the HV power switch 500 mentioned above during phases PH1 and PH2. Figure 5A and Figure 5B The corresponding waveforms discussed. Instead of transforming T1-T3, Figure 6B Describe transformations T4-T6.

[0119] At the start of phase PH1, the HV enable signal with a ground voltage level causes the delay circuit D1 to output a signal HVF1 with a ground voltage level and controls the inverter IN1 to be in a high logic state, thereby giving the ground signal AG a ground voltage level as described above.

[0120] Transformation T4 corresponds to transformation T1 discussed above, where the rising edge of the HV enable signal ENHV causes the level shifter / power switch S1 to ramp up the output power signal PS from voltage level LV to the voltage level VPP of the HV power signal HV at the end of stage PH1 and the beginning of stage PH2. The rising edge of the HV enable signal ENHV also causes the delay circuit D1 to output a signal HVF1 with the voltage level VPP of the HV power signal HV after a predetermined delay time (and causes the inverter IN1 to output a signal HVF2 with the ground voltage level), described as transformation T5.

[0121] Transformation T6 corresponds to transformation T3 above, after which the HV power switch 600 outputs a ground signal AG with a voltage level MV.

[0122] With the configuration discussed above, the memory circuit 100, including the HV driver 400 and the HV power switch HVPSU or HVPSD, which includes one of the HV power switches 500 or 600, can output an HV activation signal WLP having the characteristics discussed above regarding the memory circuit 100, so that the memory circuit 100, including the HV driver 400 and the HV power switch HVPSU or HVPSD, which includes one of the HV power switches 500 or 600, can achieve the aforementioned benefits.

[0123] Figure 7A and Figure 7C Each of these is a diagram illustrating an example of memory circuit 100. Figure 7B This is a diagram illustrating the corresponding memory circuit parameters according to some embodiments. Figure 7A In the non-limiting example depicted, the memory circuit 100 includes the components described above. Figure 4 The HV driver 400 discussed, the HV power switch 700 which can be used as an HV power switch HVPSU or HVPSD, and the global HV power switch 750 which can be used as a global HV power switch HVSU or HVSD, are each mentioned above. Figure 1B A discussion was held. For illustrative purposes, Figure 7A Includes a simplified version of the HV drive 400.

[0124] For illustrative purposes, Figures 7A-7C In the illustrated embodiment, memory circuitry 100 includes an OTP device 200, represented by a single instance of OTP device 200, wherein a received activation signal WLR has a logic state corresponding to an on transistor 220, thereby providing a current path to bit line BL. In some embodiments, memory circuitry 100 includes an NVM device 112 in addition to OTP device 200, and is otherwise configured to provide one or more current paths to one or more bit lines BL.

[0125] The HV power switch 700 includes, as mentioned above, the HV power switch 500 and... Figure 5A The discussed configuration includes a level shifter / power switch S1, transistors N9-N11, a current source IS1, and an inverter. Instead of PMOS transistor P5, the HV power switch 700 includes PMOS transistors P6 and P7 coupled between the power signal node PSN and NMOS transistor N9, and the HV power switch 700 also includes an inverter IN2 with an input terminal coupled to the output terminal of inverter IN1.

[0126] The gate of transistor P6 is configured to receive the cascode bias voltage VPCB, and the gate of PMOS transistor P7 is configured to receive the voltage level VRD, each discussed above, such that the HV power switch 700 is configured to operate according to the above description of the HV power switch 500 and... Figure 5A and Figure 5B The discussion is that, in response to detecting the voltage level of the power signal PS on the power signal node PSN, a ground signal AG is output on the ground signal node AGN.

[0127] exist Figure 7A In the illustrated embodiment, as the power signal PS ramps up from voltage level LV to voltage level VPP, the HV power switch 700 is thus configured as described above regarding... Figure 5B The discussion focuses on detecting the voltage level of the power supply signal PS relative to the reference voltage VDT1 based on the common-source gate bias voltage VPCB, the voltage level VRD, and the threshold voltages of PMOS transistors P6 and P7. In some embodiments, the HV power switch 700 is thus configured to detect the voltage level of the power supply signal PS relative to the reference voltage VDT1, which has a voltage level approximately equal to half of the voltage level VPP.

[0128] By including inverter IN2, HV power switch 700 is also configured to generate signal HVF3 in response to the voltage level of power signal PS on power signal node PSN, such that signal HVF3 can be used by global HV power switch 750 during discharge operation, as described below.

[0129] The global HV power switch 750 includes a level shifter / power switch S2 coupled to node HVN, a discharge control circuit DC, and a PMOS transistor P8 and NMOS transistors N12 and N13 series coupled between node HVN and ground reference node.

[0130] Level shifter / power switch S2 is configured to output an HV power signal HV at node HVN, receiving either a voltage level VPP or VRD. Discharge control circuit DC is configured to receive signal HVF3 from HV power switch 700 and output a discharge enable signal ENHVD. The gate of transistor P8 is configured to receive voltage level VRD, the gate of NMOS transistor N12 is configured to receive the cascode bias voltage VNCB, and the gate of NMOS transistor N13 is configured to receive the enable signal ENHVD.

[0131] The memory circuit 100, including the global HV power switch 750 and the HV power switch 700, is thus configured to control programming operations, including discharge operations, as referenced below. Figure 7B and Figure 7C The subject of discussion.

[0132] Figure 7B This includes, for example, control signals PGM, discharge enable signals ENHVD, signal HVF3, power supply signal HV, BL signal BL, and activation signal WLR received from functional circuit 100F, plotted over time (unlabeled). The power supply signal HV is plotted relative to a reference voltage VDT2 corresponding to voltage level VRD plus the threshold voltage of PMOS transistor P7.

[0133] The HV power switch 700 and the voltage level VRD are configured such that the voltage level of the reference voltage VDT2 is lower than the voltage level of the aforementioned reference voltage VDT1. In some embodiments, the HV power switch 700 and the voltage level VRD are configured such that the reference voltage VDT2 has a voltage level between 1.5V and 2.0V. In some embodiments, the HV power switch 700 and the voltage level VRD are configured such that the reference voltage VDT2 has a voltage level approximately equal to 1.8V.

[0134] exist Figure 7B At the start of the period shown, the control signal PGM has a low logic state corresponding to the programming operation, followed by a rising edge corresponding to the start of the discharge operation. The rising edge of the control signal PGM causes the discharge control circuit DC output a discharge enable signal ENHVD with a high logic state, described as transition T7.

[0135] The rising edge of the discharge enable signal ENHVD causes the level shifter / power switch S2 to ramp up the HV power signal HV from voltage level VPP to voltage level VRD, described as transformation T8.

[0136] The HV power supply signal drops below the reference voltage VDT2, causing the PMOS transistor P6 to turn off, resulting in signal HVF2 having a high logic state and signal HVF3 having a ground voltage level, described as a transition T9.

[0137] The falling edge of signal HVF3 causes the discharge control circuit DC output to have a discharge enable signal ENHVD with a low logic state, described as transformation T10. The falling edge of discharge enable signal ENHVD causes the BL signal BL to have a high logic state and causes the activation signal WLR to have a ground voltage level, collectively referred to as transformation T11.

[0138] like Figure 7A As indicated by the middle arrow, during the period from transition T7 to transition T10, memory circuit 100 provides dual current discharge paths. A first discharge path to the ground reference node is provided through transistors P8, N12, and N13, and a second discharge path is provided through bit line BL and transistors 210 and 220 of OTP device 200, which are programmed to a low-resistance state during programming operations.

[0139] At transition T10, the falling edge of the discharge enable signal ENHVD turns off transistor N13, thereby disconnecting the first discharge path, and the subsequent falling edge of the activation signal WLR turns off transistor 220, thereby disconnecting the second discharge path.

[0140] Because converter T10 is based on detecting the power supply signal HV, which drops below the reference voltage VDT2 at converter T9, memory circuit 100 is configured as follows: Figure 7A As described, the discharge operation ends after the HV power signal HV reaches a voltage level lower than the reference voltage VDT2. This is because a subset of the NVM device 112, for example... Figure 7A The OTP device 200 described herein is collectively biased during programming operations to ensure that the HV power supply signal HV has a voltage level lower than the reference voltage VDT2, thus avoiding leaving potentially damaging residual voltages on a subset of the NVM devices.

[0141] Programming operations in Figure 7C This is further illustrated in the text. Figure 7C Three programming states are described: initial state ST1, programming state ST2, and termination state ST3. Each state includes... Figure 7A A simplified description of the embodiments described herein.

[0142] In each state ST1, ST2, and ST3, the global HV power switch 750 is described as a level shifter / power switch S2, a discharge control circuit DC, and transistors P8, N12, and N13 represented by current source IS2. The HV power switch 700 is described as a level shifter / power switch S1, transistors P6, P6, N9, inverters IN1 and IN2 represented by voltage detector VD, and transistors N10 and N11 represented by ground switch AGS. The HV driver 400 is described as including an output node WLPN (unlabeled) coupled to a power signal node PSN (unlabeled) corresponding to a subset of the NVM device 112 selected in the programming operation. The subset of NVM devices is represented by a non-limiting example of the OTP device 200, including the programming transistor 210 and the read transistor 220 (unlabeled) being turned on, thereby providing a current path to the bit line BL with a ground voltage level.

[0143] In state ST1, the HV power supply signal HV with voltage level VRD propagates from level shifter / power switch S2 through level shifter / power switch S1 and HV driver 400 to the gate of transistor 210. The discharge control circuit outputs a DC discharge enable signal ENHVD, causing current source IS2 to turn off. Based on the detection of the HV power supply signal HV with voltage level VRD lower than the reference voltage VDT1 by voltage detector VD, ground switch AGS is coupled to the ground reference node, causing the ground signal AG to have a ground voltage level.

[0144] In state ST2, the HV power supply signal HV with a programming voltage level VPP propagates from level shifter / power switch S2 through level shifter / power switch S1 and HV driver 400 to the gate of transistor 210, thereby programming the selected NVM device 112 to a low-resistance state, for example, by forming a conduction path in the gate of transistor 210. Based on the detection of the HV power supply signal HV with a voltage level VPP greater than VDT1 by voltage detector VD, the discharge control circuit DC outputs a discharge enable signal ENHVD, keeping current source IS2 off, and ground switch AGS is coupled to voltage node / level MV, such that ground signal AG has a voltage level MV.

[0145] In state ST3, the HV power supply signal HV, reduced to voltage level VRD, propagates from level shifter / power switch S2 through level shifter / power switch S1 and HV driver 400 to the gate of transistor 210. Based on the voltage detector VD detecting the HV power supply signal HV with a voltage level lower than the reference voltage VDT2, the discharge control circuit DC outputs a discharge enable signal ENHVD, turning on current source IS2. The ground switch AGS is coupled to the voltage reference node, giving the ground signal AG a voltage level. (The above is about...) Figure 7B The resulting dual-current discharge path discussed in Figure 7C The middle part is indicated by an arrow.

[0146] Based on the above... Figures 7A-7C The configuration discussed, including the HV driver 400, the HV power switch VPSU or HVPSD including the HV power switch 700, and the global HV power switch HVSU or HVSD including the global HV power switch 750, is capable of outputting an HV activation signal WLP having the characteristics discussed above regarding the memory circuit 100, so that the memory circuit 100 including the HV driver 400, the HV power switch HVPSU or HVPSD including the HV power switch 700, and the global HV power switch HVSU or HVSD including the global HV power switch 750 can achieve the benefits discussed above.

[0147] The memory circuit 100, including an HV driver 400, an HV power switch HVPSU or HVPSD including an HV power switch 700, and a global HV power switch HVSU or HVSD including a global HV power switch 750, can also use the detected HV level via a feedback arrangement to control the discharge time during NVM device programming operations. Compared to methods that do not include detecting the HV level to control the discharge time, such an embodiment can reduce power requirements and avoid residual voltage damage in subsequent operations.

[0148] Figure 8 This is a flowchart of a method 800 for performing programming operations according to one or more embodiments. Method 800 can be used in memory circuits, such as those described above. Figures 1A-7C The memory circuit 100 is discussed.

[0149] exist Figure 8 The order of operations described in method 800 is for illustrative purposes only; the operations of method 800 can be performed in conjunction with... Figure 8 The order shown may differ from the order of execution. In some embodiments, besides Figure 8 Operations other than those described in the text Figure 8 The operations shown are performed before, between, during, and / or after. In some embodiments, the operations of method 800 are a subset of the operations of methods that operate memory circuitry.

[0150] At operation 810, in some embodiments, an address signal having a configuration corresponding to the NVM devices in the first group of NVM devices is received at a driver circuit adjacent to the first group of NVM devices and the second group of NVM devices. In some embodiments, receiving the address signal at the driver circuit includes receiving an address signal 100AD at a driver circuit 110AC adjacent to the memory groups 110U and 110D, as described above regarding... Figure 1Aand Figure 1B The subject of discussion.

[0151] At operation 820, in response to an address signal having a configuration corresponding to an NVM device in the first group of NVM devices, first and second HV power signals are generated by first and second global HV power switches. The first HV power signal has a first voltage amplitude and the second HV power signal has a second voltage amplitude less than the first voltage amplitude.

[0152] In some embodiments, generating the first and second HV power signals includes using a global HV power switch HVSU to generate an HV power signal HVU with a voltage level VPP and using a global HV power switch HVSD to generate an HV power signal HVD with a voltage level VRD, as described above. Figures 1A-7C The subject of discussion.

[0153] At operation 830, first and second power signals are received at the driver circuitry adjacent to the first and second sets of NVM devices. In some embodiments, receiving the first and second power signals includes receiving an HV power signal HVU at an HV power switch HVPSU and an HV power signal HVD at an HV power switch HVPSD, as described above. Figures 1A-7C The subject of discussion.

[0154] At operation 840, in response to an address signal having this configuration, a first HV activation signal is output from the driver circuit to the NVM device, the first HV activation signal having a first voltage amplitude. In some embodiments, outputting the first HV activation signal to the NVM device includes using the HV driver HVDR to output an HV activation signal WLPU having a voltage level VPP to a subset of the NVM device 112, as described above regarding... Figures 1A-7C As discussed above. In some embodiments, using the HV driver HVDR to output the HV activation signal WLPU includes using the methods described above. Figures 4-7C The HV drive 400 is under discussion.

[0155] In some embodiments, outputting a first HV activation signal having a first voltage amplitude includes using an HV switch in the driver circuit to generate a ground signal having a fourth voltage amplitude between the first voltage amplitude and a ground voltage level. In some embodiments, using an HV switch in the driver circuit to generate a ground signal having a fourth voltage amplitude includes using the above-mentioned... Figures 5A-7C One of the HV power switches discussed is the 500-700 series.

[0156] In some embodiments, the NVM device includes an OTP device, and outputting a first HV activation signal from the driver circuit to the NVM device includes outputting a first HV activation signal and another activation signal to the OTP device. In some embodiments, outputting the first HV activation signal and another activation signal to the OTP device includes outputting an HV activation signal WLP and an activation signal WLR to the OTP device 200, as described above. Figure 2 The subject of discussion.

[0157] At operation 850, in response to an address signal having this configuration, a second HV activation signal is output from the driver circuit to the second group of NVM devices. The second HV activation signal has a third voltage amplitude equal to or less than the second voltage amplitude. In some embodiments, outputting the second HV activation signal to the second group of NVM devices includes using an HV driver HVDR to output an HV activation signal WLPD having a voltage level VRD or a voltage level LV to a subset of the NVM devices 112, as described above. Figures 1A-7C As discussed above. In some embodiments, using an HV driver HVDR to output an HV activation signal WLPD includes using the methods described above. Figures 4-7C The HV drive 400 is under discussion.

[0158] In some embodiments, each of the first HV activation signal and the second activation signal output in operation 840 is in response to the same enable signal generated by the driver circuit, and the output of the second HV activation signal from the driver circuit to the second group of NVM devices includes a second HV activation signal having a third voltage amplitude equal to the second voltage amplitude. In some embodiments, generating the same enable signal by the driver circuit includes using the decoding circuit 300A to generate enable signals ENU and END, as described above. Figure 3A The subject of discussion.

[0159] In some embodiments, during operation 840, a first HV activation signal is output in response to a first enable signal generated by the driver circuit, a second activation signal is output in response to a second enable signal generated separately from the first enable signal by the driver circuit, and the second HV activation signal output from the driver circuit to the second group of NVM devices includes a second HV activation signal having a third voltage amplitude equal to the ground voltage level. In some embodiments, generating the first and second enable signals by the driver circuit includes using decoding circuit 300B to generate enable signals ENU and END, as described above. Figure 3B The subject of discussion.

[0160] At operation 860, in some embodiments, the driver circuitry is used to perform a discharge operation on the NVM device, which includes detecting the voltage level of a first HV power signal. In some embodiments, performing the discharge operation includes using a global HV power switch 750, an HV power switch 700, and an HV driver 400 to detect the voltage level of the HV power signal HV, as described above regarding... Figures 7A-7C The subject of discussion.

[0161] By performing the operation of method 800, a programming operation is performed on the memory circuit, wherein a dual-path hierarchical arrangement is used to distribute the HV level, such that an unselected NVM device in the group adjacent to the device driver circuit receives a corresponding HV activation signal with an LV or ground voltage level, thereby achieving the benefits discussed above regarding memory circuit 100.

[0162] In some embodiments, the memory circuitry includes: a first group of NVM devices; a first plurality of decoders, wherein each of the first plurality of decoders is configured to generate an enable signal corresponding to a column of the first group of NVM devices; a first plurality of HV drivers corresponding to the first plurality of decoders; and a first plurality of HV power switches, wherein a first HV power switch of the first plurality of HV power switches is coupled to each of the first plurality of HV drivers, wherein each of the first plurality of HV drivers is configured to output an HV activation signal to a corresponding column of the first group of NVM devices in response to a power signal of the first HV power switch of the first plurality of HV power switches and an enable signal of the corresponding decoder of the first plurality of decoders. In some embodiments, the memory circuitry includes: a second set of NVM devices; a second plurality of HV drivers corresponding to a first plurality of decoders; and a second plurality of HV power switches, wherein a first HV power switch of the second plurality of HV power switches is coupled to each HV driver of the second plurality of HV drivers, wherein each decoder of the first plurality of decoders is configured to generate an enable signal further corresponding to a column of the second set of NVM devices, and each HV driver of the second plurality of HV drivers is configured to output an HV activation signal to the corresponding column of the second set of NVM devices in response to a power signal from the first HV power switch of the second plurality of HV power switches and an enable signal from the corresponding decoder of the second plurality of decoders. In some embodiments, the memory circuitry includes: a second set of NVM devices; a second plurality of decoders, wherein each decoder of the second plurality of decoders is configured to generate an enable signal corresponding to a column of the second set of NVM devices; a second plurality of HV drivers, corresponding to the second plurality of decoders; and a second plurality of HV power switches, wherein a first HV power switch of the second plurality of HV power switches is coupled to each HV driver of the second plurality of HV drivers, wherein each HV driver of the second plurality of HV drivers is configured to output an HV activation signal to a corresponding column of the second set of NVM devices in response to a power signal from the first HV power switch of the second plurality of HV power switches and an enable signal from a corresponding decoder of the second plurality of decoders. In some embodiments, the first plurality of HV drivers is one of a plurality of HV drivers, and each HV power switch of the first plurality of HV power switches is coupled to each HV driver of a corresponding plurality of HV drivers in the plurality of plurality of HV drivers. In some embodiments, the memory circuitry includes a global HV power switch configured to generate an HV power signal, wherein each HV power switch of the first plurality of HV power switches is configured to generate a power signal and a ground signal based on the HV power signal. In some embodiments, each of the first plurality of HV power switches includes a level detector configured to switch a ground signal from a ground voltage level to an intermediate voltage level in response to a voltage level of the HV power signal.In some embodiments, each of the first plurality of HV power switches includes a delay circuit configured to switch a ground signal from a ground voltage level to an intermediate voltage level in response to an HV enable signal. In some embodiments, each of the first group of NVM devices includes an OTP bit, each OTP bit including a programming transistor configured to receive an HV activation signal from a corresponding HV driver among the first plurality of HV drivers and a readout transistor configured to receive the activation signal based on an enable signal of a corresponding decoder among the first plurality of decoders.

[0163] In some embodiments, the memory circuitry includes: first and second OTP devices, each OTP device including a read transistor and a programming transistor; and driver circuitry including a first HV power switch configured to generate a first power signal, a second HV power switch configured to generate a second power signal, a first HV driver configured to output a first HV activation signal to the programming transistor of the first OTP device in response to the first power signal, and a second HV driver configured to output a second HV activation signal to the programming transistor of the second OTP device in response to the second power signal, wherein the driver circuitry is configured to output the first activation signal to the read transistor of the first OTP device and to output the second activation signal to the read transistor of the second OTP device, the first activation signal and the first HV activation signal being based on a first enable signal, and the second activation signal and the second HV activation signal being based on the second enable signal. In some embodiments, the driver circuitry includes a decoder configured to generate the first and second enable signals as the same enable signal, and each of the first and second activation signals and the first and second HV activation signals being based on the same enable signal. In some embodiments, the driver circuitry includes a first decoder configured to generate the first enable signal and a second decoder configured to generate a second enable signal separate from the first enable signal. In some embodiments, a first HV driver is one of a plurality of first HV drivers, a second HV driver is one of a plurality of second HV drivers, each of the plurality of first HV drivers is coupled to a first HV power switch, and each of the plurality of second HV drivers is coupled to a second HV power switch. In some embodiments, a first HV power switch is one of a plurality of first HV power switches, a second HV power switch is one of a plurality of second HV power switches, each of the plurality of first HV power switches is coupled to a first global HV power switch, and each of the plurality of second HV power switches is coupled to a second global HV power switch. In some embodiments, a first HV power switch is configured to generate a first power signal and a first ground signal based on a first HV power signal, a first LV power signal, and a first HV enable signal, and a second HV power switch is configured to generate a second power signal and a second ground signal based on a second HV power signal, a second LV power signal, and a second HV enable signal.

[0164] In some embodiments, a method of performing a programming operation includes: generating a first HV power signal having a first voltage amplitude and generating a second HV power signal having a second voltage amplitude less than the first voltage amplitude in response to an address signal having a configuration corresponding to an NVM device in a first group of NVM devices; receiving the first and second HV power signals and the address signal at a driver circuit adjacent to the first group of NVM devices and the second group of NVM devices; and outputting a first HV activation signal having a first voltage amplitude from the driver circuit to the NVM device in response to the address signal having the configuration, and outputting a second HV activation signal having a third voltage amplitude equal to or less than the second voltage amplitude from the driver circuit to the second group of NVM devices. In some embodiments, each of the output of the first HV activation signal and the output of the second activation signal is in response to the same enable signal generated by the driver circuit, and the output of the second HV activation signal from the driver circuit to the second group of NVM devices includes the second HV activation signal having a third voltage amplitude equal to the second voltage amplitude. In some embodiments, outputting a first HV activation signal in response to a first enable signal generated by a driver circuit, outputting a second activation signal in response to a second enable signal generated separately by the driver circuit from the first enable signal, and outputting the second HV activation signal from the driver circuit to the second group of NVM devices includes a second HV activation signal having a third voltage amplitude equal to the ground voltage level. In some embodiments, outputting the first HV activation signal having a first voltage amplitude includes using an HV switch in the driver circuit to generate a ground signal having a fourth voltage amplitude between the first voltage amplitude and the ground voltage level. In some embodiments, the NVM device includes an OTP device, and outputting the first HV activation signal from the driver circuit to the NVM device includes outputting the first HV activation signal and another activation signal to the OTP device. In some embodiments, the method includes performing a discharge operation on the NVM device, the discharge operation including detecting the voltage level of the first HV power supply signal.

[0165] The foregoing has described components of several embodiments, enabling those skilled in the art to better understand the various embodiments of the present invention. Those skilled in the art should understand that other processes and structures can be readily designed or modified based on the present invention to achieve the same objectives and / or realize the same advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent structures do not depart from the spirit and scope of the present invention, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of the present invention.

Claims

1. A memory circuit, comprising: The first group of non-volatile memory devices; The first plurality of decoders, wherein each of the first plurality of decoders is configured to generate an enable signal corresponding to a column of the first group of nonvolatile memory devices; The first plurality of high-voltage drivers, corresponding to the first plurality of decoders; and A plurality of high-voltage power switches, wherein a first high-voltage power switch in the plurality of high-voltage power switches is coupled to each of the plurality of high-voltage drivers in the plurality of high-voltage drivers. The second group of non-volatile memory devices; The second plurality of high-voltage drivers correspond to the first plurality of decoders; and A second plurality of high-voltage power switches, wherein a first high-voltage power switch in the second plurality of high-voltage power switches is coupled to each of the second plurality of high-voltage drivers. Each of the first plurality of decoders is configured to generate an enable signal that further corresponds to a column of the second group of non-volatile memory devices. Each of the first plurality of high-voltage drivers is configured to output a first high-voltage activation signal to the corresponding column of the first group of non-volatile memory devices in response to a power signal from the first high-voltage power switch in the first plurality of high-voltage power switches and an enable signal from the corresponding decoder in the first plurality of decoders. Each of the second plurality of high-voltage drivers is configured to output a second high-voltage activation signal to the corresponding column of the second group of non-volatile memory devices in response to a power signal from the first high-voltage power switch in the second plurality of high-voltage power switches and the enable signal from the corresponding decoder in the first plurality of decoders.

2. The memory circuit according to claim 1, wherein: The first plurality of decoders includes inverters and / or NAND, NOR.

3. A memory circuit, comprising: The first group of non-volatile memory devices; The first plurality of decoders, wherein each of the first plurality of decoders is configured to generate an enable signal corresponding to a column of the first group of nonvolatile memory devices; The first plurality of high-voltage drivers correspond to the first plurality of decoders; A first plurality of high-voltage power switches, wherein a first high-voltage power switch in the first plurality of high-voltage power switches is coupled to each of the first plurality of high-voltage drivers; a second set of non-volatile memory devices; The second plurality of decoders, wherein each of the second plurality of decoders is configured to generate an enable signal corresponding to a column of the second set of nonvolatile memory devices; The second plurality of high-voltage drivers, corresponding to the second plurality of decoders; and A second plurality of high-voltage power switches, wherein a first high-voltage power switch in the second plurality of high-voltage power switches is coupled to each of the second plurality of high-voltage drivers. Each of the first plurality of high-voltage drivers is configured to output a first high-voltage activation signal to the corresponding column of the first group of non-volatile memory devices in response to the power signal of the first high-voltage power switch in the first plurality of high-voltage power switches and the enable signal of the corresponding decoder in the first plurality of decoders. Each of the second plurality of high-voltage drivers is configured to output a high-voltage activation signal to the corresponding column of the second group of non-volatile memory devices in response to the power signal of the first high-voltage power switch in the second plurality of high-voltage power switches and the enable signal of the corresponding decoder in the second plurality of decoders.

4. The memory circuit according to claim 1, wherein: The first plurality of high-voltage drivers is one of a plurality of high-voltage drivers, and Each of the first plurality of high-voltage power switches is coupled to each of the corresponding plurality of high-voltage drivers in the plurality of high-voltage drivers.

5. The memory circuit according to claim 1, further comprising: A global high-voltage power switch is configured to generate a high-voltage power signal. Each of the first plurality of high-voltage power switches is configured to generate the power signal and the ground signal based on the high-voltage power signal.

6. The memory circuit according to claim 5, wherein: Each of the first plurality of high-voltage power switches includes a level detector configured to switch the ground signal from a ground voltage level to an intermediate voltage level in response to the voltage level of the high-voltage power signal.

7. The memory circuit according to claim 5, wherein: Each of the first plurality of high-voltage power switches includes a delay circuit configured to switch the ground signal from a ground voltage level to an intermediate voltage level in response to a high-voltage enable signal.

8. The memory circuit according to claim 1, wherein, Each of the first group of non-volatile memory devices includes a one-time programmable bit, and each one-time programmable bit includes: A programmable transistor is configured to receive the high-voltage activation signal from a corresponding high-voltage driver among the first plurality of high-voltage drivers; and The read transistor is configured to receive an activation signal based on the enable signal of the corresponding decoder among the first plurality of decoders.

9. A memory circuit, comprising: The first primary programmable device and the second primary programmable device, each primary programmable device including a read transistor and a programmable transistor; as well as The driver circuit includes: The first high-voltage power switch is configured to generate a first power signal; The second high-voltage power switch is configured to generate a second power signal; A first high-voltage driver is configured to output a first high-voltage activation signal to the programming transistor of the first programmable device in response to the first power supply signal; and The second high-voltage driver is configured to output a second high-voltage activation signal to the programming transistor of the second primary programmable device in response to the second power supply signal. in The driver circuit is configured to output a first activation signal to the read transistor of the first primary programmable device and a second activation signal to the read transistor of the second primary programmable device. The first activation signal and the first high-voltage activation signal are based on the first enable signal, and The second activation signal and the second high-voltage activation signal are based on the second enable signal.

10. The memory circuit according to claim 9, wherein: The driver circuit includes a decoder configured to generate the first enable signal and the second enable signal into the same enable signal, and Each of the first activation signal and the second activation signal, as well as the first high-voltage activation signal and the second high-voltage activation signal, is based on the same enable signal.

11. The memory circuit according to claim 9, wherein, The driver circuit includes: A first decoder is configured to generate the first enable signal; The second decoder is configured to generate a second enable signal that is separate from the first enable signal.

12. The memory circuit according to claim 9, wherein: The first high-voltage driver is one of a plurality of first high-voltage drivers. The second high-voltage driver is one of a plurality of second high-voltage drivers. Each of the plurality of first high-voltage drivers is coupled to the first high-voltage power switch, and Each of the plurality of second high-voltage drivers is coupled to the second high-voltage power switch.

13. The memory circuit according to claim 9, wherein: The first high-voltage power switch is one of a plurality of first high-voltage power switches. The second high-voltage power switch is one of a plurality of second high-voltage power switches. Each of the plurality of first high-voltage power switches is coupled to a first global high-voltage power switch, and Each of the plurality of second high-voltage power switches is coupled to a second global high-voltage power switch.

14. The memory circuit according to claim 9, wherein: The first high-voltage power switch is configured to generate the first power signal and the first ground signal based on the first high-voltage power signal, the first low-voltage power signal, and the first high-voltage enable signal, and The second high-voltage power switch is configured to generate the second power signal and the second ground signal based on the second high-voltage power signal, the second low-voltage power signal and the second high-voltage enable signal.

15. A method for performing programming operations, the method comprising: In response to an address signal having a configuration corresponding to a non-volatile memory device in the first group of non-volatile memory devices: a first high-voltage power supply signal having a first voltage amplitude is generated; And generate a second high-voltage power supply signal with a second voltage amplitude that is smaller than the first voltage amplitude; The first high-voltage power supply signal, the second high-voltage power supply signal, and the address signal are received at the driver circuit adjacent to the first group of non-volatile memory devices and the second group of non-volatile memory devices. as well as In response to the address signal having the configuration described above: a first high-voltage activation signal is output from the driver circuit to the non-volatile memory device, the first high-voltage activation signal having the first voltage amplitude; and a second high-voltage activation signal is output from the driver circuit to the second group of non-volatile memory devices, the second high-voltage activation signal having a third voltage amplitude equal to or less than the second voltage amplitude.

16. The method of claim 15, wherein Each of the first high-voltage activation signal and the second activation signal output responds to the same enable signal generated by the driver circuit, and The output of the second high-voltage activation signal from the driver circuit to the second group of non-volatile memory devices includes a second high-voltage activation signal having a third voltage amplitude equal to the second voltage amplitude.

17. The method of claim 15, wherein The output of the first high-voltage activation signal is in response to the first enable signal generated by the driver circuit. The output of the second activation signal is in response to a second enable signal generated by the driver circuit that is separate from the first enable signal, and The output of the second high-voltage activation signal from the driver circuit to the second group of non-volatile memory devices includes a second high-voltage activation signal having a third voltage amplitude equal to the ground voltage level.

18. The method according to claim 15, wherein, Outputting the first high-voltage activation signal having the first voltage amplitude includes using a high-voltage switch in the driver circuit to generate a ground signal having a fourth voltage amplitude between the first voltage amplitude and the ground voltage level.

19. The method of claim 15, wherein The non-volatile memory device includes a one-time programmable device, and Outputting the first high-voltage activation signal from the driver circuit to the non-volatile memory device includes outputting the first high-voltage activation signal and another activation signal to the one-time programmable device.

20. The method of claim 15, further comprising performing a discharge operation on the non-volatile memory device, the discharge operation including detecting the voltage level of the first high-voltage power supply signal.

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