Method for manufacturing embedded package substrate and embedded package substrate

Abstract

The application discloses a kind of embedded packaging substrate manufacturing method and embedded packaging substrate, it is related to semiconductor packaging technical field.The manufacturing method includes the following steps: providing support frame;Wherein, support frame is provided with through support frame and cavity of through copper column;Chip to be packaged is placed in cavity, and is fixed by first dielectric layer;Wherein, first dielectric layer covers the double surface of support frame, and fills cavity;First circuit layer is formed on the surface of first dielectric layer, and first circuit layer is respectively communicated with through copper column, the pin of the front surface of chip and the back surface of chip;Second dielectric layer is arranged on the surface of first dielectric layer;Second circuit layer is arranged on the surface of second dielectric layer, and embedded packaging substrate is formed.According to the manufacturing method of embedded packaging substrate of the embodiment of the application, the stability and reliability of operation can be avoided when chip works in harsh operating environment such as high temperature and high humidity due to the influence of water vapor penetration.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, and in particular to a method for manufacturing an embedded packaging substrate and the embedded packaging substrate. Background Technology

[0002] With the rapid development of electronic technology, the performance requirements of electronic products are becoming increasingly demanding, leading to more complex electronic components and circuit board substrates. Simultaneously, the size requirements for electronic products are shrinking and thinning, making the integration, miniaturization, and multifunctionality of electronic components and circuit board substrates an inevitable trend. To achieve the integration, miniaturization, and multifunctionality of electronic products, embedding and packaging active and passive components such as chips within the substrate is currently an important research topic in the industry.

[0003] Existing board-level chip packaging fan-out primarily utilizes a frame as a support structure, mounts chips and other components, packages them, and then fans out. There are two main methods for mounting chips: chip front-side down and chip back-side down.

[0004] like Figure 1 As shown, when the front of the chip 10 is facing down during packaging, the pins on the front of the chip 10 are located at the junction of the packaging material 20 and the bottom circuit 30. However, in a high-temperature and high-humidity working environment, moisture can easily seep in from the interface between different materials, thereby affecting the stability and reliability of the normal operation of the chip 10.

[0005] like Figure 2 As shown, when the back side of chip 10 is facing down during packaging, windows are created in the packaging material 20 using ion etching and laser engraving to expose the circuit pins on the front side of chip 10. Typically, the frame 40 needs to be approximately 50 μm thicker than the chip 10, or even more, to ensure the quality of the chip 10 packaging; that is, the depth of the blind via 50 is approximately 50 μm, or even deeper. The depth of the blind via 50 increases the distance between chip 10 and the upper-layer circuitry 60, which to some extent increases signal transmission delay and signal loss. Simultaneously, due to the increasingly high density requirements of the pins on the front side of chip 10, the aperture of the blind via 50 needs to be smaller and smaller. Small-aperture, deep blind vias 50 pose a significant challenge to the process capabilities of laser equipment. Summary of the Invention

[0006] The present invention aims to at least solve one of the technical problems existing in the prior art. To this end, the present invention proposes a method for manufacturing an embedded packaging substrate and an embedded packaging substrate, which can prevent the stability and reliability of chip operation from being affected by moisture infiltration when the chip is operating in harsh environments such as high temperature and high humidity.

[0007] On one hand, the method for manufacturing an embedded packaging substrate according to an embodiment of the present invention includes the following steps:

[0008] A support frame is provided; wherein the support frame is provided with a conductive copper pillar and a cavity penetrating the support frame;

[0009] The chip to be packaged is placed in the cavity and fixed by a first dielectric layer; wherein the first dielectric layer covers both sides of the support frame and fills the cavity;

[0010] A first circuit layer is formed on the surface of the first dielectric layer, and the first circuit layer is connected to the conductive copper pillar, the pins on the front side of the chip, and the back side of the chip.

[0011] A second dielectric layer is disposed on the surface of the first dielectric layer;

[0012] A second circuit layer is formed on the surface of the second dielectric layer to form the embedded packaging substrate; wherein the second circuit layer is conductive to the first circuit layer.

[0013] According to some embodiments of the present invention, placing the chip to be packaged within the cavity and fixing it with a first dielectric layer specifically includes:

[0014] A first adhesive material is placed at the bottom of the support frame, and the first adhesive material is filled into a preset position inside the cavity;

[0015] The chip to be packaged is placed inside the cavity and fixed with the first adhesive material;

[0016] A second adhesive material is disposed on the top of the support frame, and the second adhesive material fills the remaining portion of the cavity; wherein the first adhesive material and the second adhesive material form the first medium layer.

[0017] According to some embodiments of the present invention, forming a first circuit layer on the surface of the first dielectric layer, wherein the first circuit layer is respectively connected to the conductive copper pillar, the pins on the front side of the chip, and the back side of the chip, specifically includes:

[0018] A window is made in the first dielectric layer, and the window is electroplated to form a first conductive block that is connected to the conductive copper pillar, a second conductive block that is connected to the pins on the front side of the chip, and a third conductive block that is connected to the back side of the chip.

[0019] The first circuit layer is formed on the surface of the first dielectric layer, and the first circuit layer is connected to the first conductive block, the second conductive block and the third conductive block respectively.

[0020] According to some embodiments of the present invention, opening a window in the first dielectric layer includes at least one of the following:

[0021] A window is created in the first dielectric layer by laser drilling;

[0022] or,

[0023] A window is created in the first dielectric layer by exposing and developing it.

[0024] or,

[0025] A window is created on the first dielectric layer by exposing and developing it, followed by plasma treatment.

[0026] According to some embodiments of the present invention, the provision of a second dielectric layer on the surface of the first dielectric layer specifically includes:

[0027] A second electroplating is performed at the position corresponding to the third conductive block to form a fourth conductive block that is connected to the third conductive block;

[0028] A second dielectric layer is disposed on the surface of the first dielectric layer, and the second dielectric layer is windowed and electroplated to form a fifth conductive block that is connected to the first circuit layer and a blind via metal block that is connected to the fourth conductive block.

[0029] According to some embodiments of the present invention, the provision of a second dielectric layer on the surface of the first dielectric layer specifically includes:

[0030] A second dielectric layer is disposed on the surface of the first dielectric layer, and a window is made and electroplated on the second dielectric layer at the position corresponding to the third conductive block to form a fourth conductive block that is in communication with the third conductive block;

[0031] The second dielectric layer is filled at the location of the window on the second dielectric layer, and the second dielectric layer is opened and electroplated to form a fifth conductive block that is connected to the first circuit layer and a blind via metal block that is connected to the fourth conductive block.

[0032] On the other hand, the packaging substrate according to the embodiments of the present invention is prepared by the method for fabricating an embedded packaging substrate described in the above embodiments of the present invention.

[0033] On the other hand, the packaging substrate according to an embodiment of the present invention includes:

[0034] A support frame, wherein the support frame is provided with a conductive copper pillar and a cavity penetrating the support frame;

[0035] A first dielectric layer covers the upper and lower surfaces of the support frame, and the first dielectric layer fills the cavity;

[0036] The chip is disposed inside the cavity and fixed by the first dielectric layer;

[0037] A first circuit layer is disposed on the surface of the first dielectric layer, and the first circuit layer is connected to the conductive copper pillar, the pins on the front side of the chip, and the back side of the chip.

[0038] The second dielectric layer is disposed on the surface of the first dielectric layer;

[0039] The second circuit layer is disposed on the surface of the second dielectric layer, and the second circuit layer is connected to the first circuit layer.

[0040] According to some embodiments of the present invention, the first circuit layer is connected to the conductive copper pillar through a first conductive block disposed in the first dielectric layer; the first circuit layer is connected to the pins on the front side of the chip through a second conductive block disposed in the first dielectric layer; and the first circuit layer is connected to the back side of the chip through a third conductive block disposed in the first dielectric layer.

[0041] According to some embodiments of the present invention, the second circuit layer is connected to the third conductive block through a blind via metal block and a fourth conductive block disposed in the second dielectric layer; the second circuit layer is connected to the first circuit layer through a fifth conductive block disposed in the second dielectric layer.

[0042] The method for manufacturing the embedded packaging substrate and the embedded packaging substrate of the present invention have at least the following beneficial effects: by placing the chip in the cavity and fixing it with the first dielectric layer, the chip pins are not located at the junction of the packaging material and the bottom circuit as in the prior art, so that moisture is not easily penetrated, and the chip can maintain the stability and reliability of operation in harsh operating environments such as high temperature and high humidity.

[0043] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0044] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0045] Figure 1 This is a schematic diagram of a chip packaging structure in related technologies;

[0046] Figure 2 This is a schematic diagram of another chip packaging structure in related technologies;

[0047] Figure 3This is a flowchart illustrating the steps of a method for fabricating an embedded packaging substrate according to an embodiment of the present invention.

[0048] Figure 4 This is a schematic diagram of the support frame structure according to an embodiment of the present invention;

[0049] Figure 5 A schematic diagram of the structure after the first adhesive material is applied to the bottom of the support frame;

[0050] Figure 6 This is a schematic diagram of a structure in which a chip to be packaged is placed inside a cavity.

[0051] Figure 7 This is a schematic diagram of another structure for placing a chip to be packaged inside a cavity;

[0052] Figure 8 A schematic diagram of the structure after a second adhesive material is applied to the top of the support frame;

[0053] Figure 9 A schematic diagram of the structure after opening a window in the first dielectric layer;

[0054] Figure 10 A schematic diagram of the structure after electroplating on the first dielectric layer;

[0055] Figure 11 This is a schematic diagram of the structure after electroplating the fourth conductive block onto the third conductive block;

[0056] Figure 12 A schematic diagram of the structure after a second dielectric layer is applied to the surface of the first dielectric layer;

[0057] Figure 13 A schematic diagram of the structure after opening a window in the second dielectric layer;

[0058] Figure 14 This is a schematic diagram of the complete structure of the embedded packaging substrate;

[0059] Figure 15 A schematic diagram of another structure after a second dielectric layer is disposed on the surface of the first dielectric layer;

[0060] Figure 16 A schematic diagram of the structure after opening a window at the position corresponding to the third conductive block in the second dielectric layer;

[0061] Figure 17 A schematic diagram of the structure after electroplating the fourth conductive block on the second dielectric layer;

[0062] Figure 18 A schematic diagram of the structure after opening a window in the second dielectric layer;

[0063] Figure 19 This is a schematic diagram of the complete structure of the embedded packaging substrate;

[0064] Figure label:

[0065] Support frame 100, conductive copper pillar 110, cavity 120, first dielectric layer 200, first adhesive material 210, second adhesive material 220, chip 300, first conductive block 410, second conductive block 420, third conductive block 430, fourth conductive block 440, fifth conductive block 450, first circuit layer 500, second dielectric layer 600, blind via metal block 700, second circuit layer 800. Detailed Implementation

[0066] This section will describe in detail specific embodiments of the present invention. Preferred embodiments of the present invention are shown in the accompanying drawings. The purpose of the drawings is to supplement the textual description with graphics, so that people can intuitively and vividly understand each technical feature and overall technical solution of the present invention, but they should not be construed as limiting the scope of protection of the present invention.

[0067] In the description of this invention, it should be understood that the orientation descriptions, such as up, down, front, back, left, right, etc., are based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0068] In the description of this invention, "several" means one or more, "more than" means two or more, "greater than," "less than," and "exceeding" are understood to exclude the stated number, while "above," "below," and "within" are understood to include the stated number. The use of "first" and "second" in the description is merely for distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.

[0069] In the description of this invention, unless otherwise explicitly defined, terms such as "set up," "install," and "connect" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this invention in conjunction with the specific content of the technical solution.

[0070] On the one hand, such as Figure 3 As shown, the method for fabricating an embedded packaging substrate according to an embodiment of the present invention includes the following steps:

[0071] Step S100: Provide a support frame 100; wherein the support frame 100 is provided with a conductive copper post 110 and a cavity 120 passing through the support frame 100.

[0072] Specifically, such as Figure 4As shown, the support frame 100 may be provided with one or more cavities 120, which penetrate the support frame 100 in the vertical direction. It should be noted that, for the convenience of describing the manufacturing method of the embodiments of the present invention, a single cavity 120 will be used as an example in the following description. Meanwhile, the support frame 100 is also provided with a plurality of conductive copper pillars 110 (the specific number is not limited); similarly, the conductive copper pillars 110 also penetrate the support frame 100 in the vertical direction, used to realize the conduction of lines on the upper and lower surfaces of the support frame 100.

[0073] Step S200: As Figure 8 As shown, the chip 300 to be packaged is placed in the cavity 120 and fixed by the first dielectric layer 200; wherein, the first dielectric layer 200 covers both sides of the support frame 100 and fills the cavity 120.

[0074] Specifically, in this embodiment of the invention, step S200 includes the following three sub-steps:

[0075] like Figure 5 As shown, a first adhesive material 210 is provided at the bottom of the support frame 100, and the first adhesive material 210 is filled into a preset position inside the cavity 120.

[0076] like Figure 6 or Figure 7 As shown, the chip 300 to be packaged is placed in the cavity 120 and fixed by the first adhesive material 210;

[0077] like Figure 8 As shown, a second adhesive material 220 is provided on the top of the support frame 100, and the second adhesive material 220 fills the remaining part of the cavity 120; wherein, the first adhesive material 210 and the second adhesive material 220 form a first medium layer 200.

[0078] Specifically, in this embodiment of the invention, the first adhesive material 210 and the second adhesive material 220 can be adhesive media such as PID material (Photo-Imageable Dielectric). The first adhesive material 210 can be hot-pressed to cover the bottom of the support frame 100 and fill a preset position inside the cavity 120. The specific position can be controlled by adjusting the pressure and temperature. After the first adhesive material 210 is set, the chip 300 is placed face up or face down in the cavity 120; in this embodiment of the invention, the face-down placement of the chip 300 is mainly described; it can be understood that the face-up placement is similar. Also, in this embodiment of the invention, the chip 300 refers to an unpackaged bare chip (die). After the chip 300 is placed in the cavity 120, it is fixed by the adhesiveness of the first adhesive material 210. Subsequently, the second adhesive material 220 can be hot-pressed to cover the upper surface of the support frame 100 and completely fill the cavity 120. The first adhesive material 210 and the second adhesive material 220 constitute the first dielectric layer 200 of the embedded packaging substrate.

[0079] Step S300: As Figure 10 As shown, a first circuit layer 500 is formed on the surface of the first dielectric layer 200. The first circuit layer 500 is connected to the conductive copper pillar 110, the pins on the front side of the chip 300, and the back side of the chip 300.

[0080] Specifically, in this embodiment of the invention, in order to enable the first circuit layer 500 to be connected to the conductive copper pillar 110, the pins on the front side of the chip 300, and the back side of the chip 300, the above-mentioned step S300 specifically includes the following two sub-steps:

[0081] like Figure 9 and Figure 10 As shown, a window is made in the first dielectric layer 200, and the window is electroplated to form a first conductive block 410 that is connected to the conductive copper pillar 110, a second conductive block 420 that is connected to the pins on the front side of the chip 300, and a third conductive block 430 that is connected to the back side of the chip 300.

[0082] like Figure 10 As shown, a first circuit layer 500 is formed on the surface of the first dielectric layer 200, and the first circuit layer 500 is connected to the first conductive block 410, the second conductive block 420 and the third conductive block 430 respectively.

[0083] Specifically, such as Figure 9 As shown, the window can be created on the first dielectric layer 200 in at least one of the following ways:

[0084] ① By laser drilling, windows are made on the first dielectric layer 200 at the positions corresponding to the conductive copper pillars 110, the positions corresponding to the pins on the front side of the chip 300, and the positions corresponding to the back side of the chip 300.

[0085] ② Alternatively, by exposing and developing the first dielectric layer 200, windows can be made on the first dielectric layer 200 at the positions corresponding to the conductive copper pillars 110, the positions corresponding to the pins on the front side of the chip 300, and the positions corresponding to the back side of the chip 300.

[0086] ③ Alternatively, by exposing and developing the first dielectric layer 200, and performing plasma treatment (i.e., plasma treatment, which can effectively remove impurities at the bottom of the window opening location), windows can be opened on the first dielectric layer 200 at the locations corresponding to the conductive copper pillars 110, the locations corresponding to the pins on the front side of the chip 300, and the locations corresponding to the back side of the chip 300. It should be noted that since the PID material used in the first dielectric layer 200 is a curable photoimageable dielectric material, it can be directly exposed and developed to open windows on the first dielectric layer 200.

[0087] After opening a window on the first dielectric layer 200, as Figure 10 As shown, the window opening is filled by electroplating, thereby forming a first conductive block 410 at the upper and lower ends of the conductive copper pillar 110, a second conductive block 420 at the pins on the front side of the chip 300, and a third conductive block 430 on the back side of the chip 300 (since the window opening on the back side of the chip 300 is relatively large, only the inner wall of the window needs to be electroplated with a metal layer). Simultaneously, a first circuit layer 500 is electroplated on the surface of the first dielectric layer 200, enabling the first circuit layer 500 to conduct with the first conductive block 410, the second conductive block 420, and the third conductive block 430, thereby allowing the chip 300 to transmit signals with the first circuit layer 500.

[0088] Step S400: A second dielectric layer 600 is disposed on the surface of the first dielectric layer 200.

[0089] Specifically, to provide a second dielectric layer 600 on the surface of the first dielectric layer 200, this solution provides two specific embodiments. The first embodiment includes the following two steps:

[0090] like Figure 11 As shown, a second electroplating is performed at the position corresponding to the third conductive block 430 to form a fourth conductive block 440 that is connected to the third conductive block 430.

[0091] like Figures 12 to 14As shown, a second dielectric layer 600 is disposed on the surface of the first dielectric layer 200, and the second dielectric layer 600 is opened and electroplated to form a fifth conductive block 450 that is connected to the first circuit layer 500 and a blind hole metal block 700 that is connected to the fourth conductive block 440.

[0092] Specifically, firstly, such as Figure 11 As shown, a second electroplating is performed separately at the position corresponding to the third conductive block 430 to form a fourth conductive block 440, and the fourth conductive block 440 is conductive to the third conductive block 430. Then, as... Figure 12 As shown, a second dielectric layer 600 is laminated on both sides of the first dielectric layer 200. The second dielectric layer 600 can be made of the same material as the first dielectric layer 200; subsequently, as... Figure 13 As shown, windows are made on the second dielectric layer 600 at positions corresponding to the first circuit layer 500 and the fourth conductive block 440; finally, as... Figure 14 As shown, electroplating is performed on the window opening to form a fifth conductive block 450 that is connected to the first circuit layer 500, and a blind via metal block 700 that is connected to the fourth conductive block 440. Because the fourth conductive block 440 is provided on the third conductive block 430, the distance between the upper surface of the second dielectric layer 600 and the fourth conductive block 440 can be reduced, decreasing the depth of the blind via and thus reducing the difficulty of laser drilling.

[0093] The second embodiment includes the following two steps:

[0094] like Figures 15 to 17 As shown, a second dielectric layer 600 is disposed on the surface of the first dielectric layer 200, and a window is made and electroplated on the second dielectric layer 600 at the position corresponding to the third conductive block 430 to form a fourth conductive block 440 that is in communication with the third conductive block 430.

[0095] like Figure 18 and Figure 19 As shown, the second dielectric layer 600 is filled at the location of the window on the second dielectric layer 600, and the second dielectric layer 600 is opened and electroplated to form a fifth conductive block 450 that is connected to the first circuit layer 500 and a blind hole metal block 700 that is connected to the fourth conductive block 440.

[0096] Specifically, the difference between this embodiment and the previous embodiment is that in this embodiment, a second dielectric layer 600 is first laminated onto the surface of the first dielectric layer 200, then a window is opened on the second dielectric layer 600 at the position corresponding to the third conductive block 430, and a fourth conductive block 440 is formed by electroplating; whereas in the previous embodiment, the fourth conductive block 440 was formed by electroplating first, and then the second dielectric layer 600 was set. In this embodiment, as... Figure 18As shown, after forming the fourth conductive block 440, the second dielectric layer 600 is laminated again at the location where a window is created on the second dielectric layer 600, thereby completely filling the second dielectric layer 600. Then, a window is created at the desired location on the second dielectric layer 600. Figure 19 As shown, after opening the window, electroplating continues to form a fifth conductive block 450 that is connected to the first circuit layer 500 and a blind hole metal block 700 that is connected to the fourth conductive block 440.

[0097] Step S500: A second circuit layer 800 is formed on the surface of the second dielectric layer 600 to form an embedded packaging substrate; wherein the second circuit layer 800 is connected to the first circuit layer 600.

[0098] Specifically, such as Figure 14 or Figure 19 As shown, a second circuit layer 800 is formed on the surface of the second dielectric layer 600 by electroplating. The second circuit layer 800 is connected to the fifth conductive block 450 and the blind via metal block 700, thereby enabling signal transmission between the second circuit layer 800, the first circuit layer 500, and the chip 300. Simultaneously, the third conductive block 430, the fourth conductive block 440, the blind via metal block 700, and the second circuit layer 800 form a heat dissipation structure on the back of the chip 300, which is beneficial for heat dissipation of the chip 300.

[0099] According to the method for fabricating an embedded packaging substrate according to an embodiment of the present invention, the chip 300 is placed in the cavity 120 and fixed by the first dielectric layer 200. Unlike the prior art, the pins of the chip 300 are not located at the junction of the packaging material and the bottom surface circuitry, thus preventing moisture penetration and enabling the chip 300 to maintain operational stability and reliability in harsh operating environments such as high temperature and high humidity. Furthermore, a heat dissipation structure is formed on the back of the chip 300, which facilitates heat dissipation and reduces the depth of the blind via metal block 700, thereby reducing the difficulty of laser drilling. Simultaneously, the method for fabricating an embedded packaging substrate according to an embodiment of the present invention can effectively avoid problems such as substrate warpage and chip cracking, and reduce the difficulty of densely packed openings.

[0100] On the other hand, embodiments of the present invention also propose an embedded packaging substrate, which is prepared by one of the two manufacturing methods described above, and has good stability and reliability, as well as good heat dissipation performance.

[0101] On the other hand, such as Figure 19As shown, this embodiment of the invention also proposes an embedded packaging substrate, including a support frame 100, a first dielectric layer 200, a chip 300, a first circuit layer 500, a second dielectric layer 600, and a second circuit layer 800; wherein, the support frame 100 is provided with a conductive copper pillar 110 penetrating the support frame 100 and a cavity 120; the first dielectric layer 200 covers the upper and lower surfaces of the support frame 100 and fills the cavity 120; the chip 300 is disposed inside the cavity 120 and fixed by the first dielectric layer 200; the first circuit layer 500 is disposed on the surface of the first dielectric layer 200 and is conductive to the conductive copper pillar 110, the pins on the front side of the chip 300, and the back side of the chip 300; the second dielectric layer 600 is disposed on the surface of the first dielectric layer 200; the second circuit layer 800 is disposed on the surface of the second dielectric layer 200 and is conductive to the first circuit layer 500.

[0102] According to the embedded packaging substrate of the present invention, by placing the chip 300 in the cavity 120 of the support frame 100 and fixing it by the first dielectric layer 200, the pins of the chip 300 are not located at the junction of the packaging material and the bottom circuit, so that moisture is not easy to penetrate, and the chip 300 can maintain the stability and reliability of operation in harsh operating environments such as high temperature and high humidity.

[0103] like Figure 19 As shown, in some embodiments of the present invention, the first circuit layer 500 is connected to the conductive copper pillar 110 through the first conductive block 410 disposed in the first dielectric layer 200; the first circuit layer 500 is connected to the pins on the front side of the chip 300 through the second conductive block 420 disposed in the first dielectric layer 200; and the first circuit layer 500 is connected to the back side of the chip 300 through the third conductive block 430 disposed in the first dielectric layer 200.

[0104] The first line layer 500 is connected to the first conducting block 410, the second conducting block 420 and the third conducting block 430 respectively, so that the chip 300 can transmit signals with the first line layer 500.

[0105] In some embodiments of the present invention, the second circuit layer 800 is connected to the third conductive block 430 through a blind via metal block 700 and a fourth conductive block 440 disposed in the second dielectric layer 600; the second circuit layer 800 is connected to the first circuit layer 440 through a fifth conductive block 450 disposed in the second dielectric layer 600.

[0106] A second circuit layer 800 is formed on the surface of the second dielectric layer 600, and the second circuit layer 800 is connected to the fifth conductive block 450 and the blind via metal block 700, thereby realizing signal transmission between the second circuit layer 800, the first circuit layer 500, and the chip 300. Simultaneously, the third conductive block 430, the fourth conductive block 440, the blind via metal block 700, and the second circuit layer 800 form a heat dissipation structure, which is beneficial for heat dissipation of the chip 300.

[0107] According to the embedded packaging substrate of the present invention, a heat dissipation structure is formed on the back side of the chip 300, which is beneficial to the heat dissipation of the chip 300 and reduces the depth of the blind hole metal block 700, thereby reducing the difficulty of laser drilling and reducing the difficulty of dense opening.

[0108] The embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the above embodiments. Within the scope of knowledge possessed by those skilled in the art, various changes can be made without departing from the spirit of the present invention.

Claims

1. A method for fabricating an embedded encapsulation substrate, characterized in that, Includes the following steps: A support frame is provided; wherein the support frame is provided with a conductive copper pillar and a cavity penetrating the support frame; The chip to be packaged is placed in the cavity and fixed by a first dielectric layer; wherein the first dielectric layer covers both sides of the support frame and fills the cavity; A first circuit layer is formed on the surface of the first dielectric layer, and the first circuit layer is connected to the conductive copper pillar, the pins on the front side of the chip, and the back side of the chip. A second dielectric layer is disposed on the surface of the first dielectric layer; A second circuit layer is formed on the surface of the second dielectric layer to create the embedded packaging substrate; wherein the second circuit layer is electrically connected to the first circuit layer. The step of placing the chip to be packaged inside the cavity and fixing it with the first dielectric layer specifically includes: A first adhesive material is placed at the bottom of the support frame, and the first adhesive material is filled into a preset position inside the cavity; The chip to be packaged is placed inside the cavity and fixed with the first adhesive material; A second adhesive material is disposed on the top of the support frame, and the second adhesive material fills the remaining portion of the cavity; wherein the first adhesive material and the second adhesive material form the first medium layer; The step of forming a first circuit layer on the surface of the first dielectric layer, wherein the first circuit layer is connected to the conductive copper pillars, the pins on the front side of the chip, and the back side of the chip, specifically includes: A window is made in the first dielectric layer, and the window is electroplated to form a first conductive block that is connected to the conductive copper pillar, a second conductive block that is connected to the pins on the front side of the chip, and a third conductive block that is connected to the back side of the chip. A first circuit layer is formed on the surface of the first dielectric layer, and the first circuit layer is connected to the first conductive block, the second conductive block and the third conductive block respectively. The provision of a second dielectric layer on the surface of the first dielectric layer specifically includes: A second electroplating is performed at the position corresponding to the third conductive block to form a fourth conductive block that is connected to the third conductive block; A second dielectric layer is disposed on the surface of the first dielectric layer, and the second dielectric layer is windowed and electroplated to form a fifth conductive block that is connected to the first circuit layer and a blind via metal block that is connected to the fourth conductive block.

2. The method for fabricating an embedded packaging substrate according to claim 1, characterized in that, The step of creating a window in the first dielectric layer includes at least one of the following: A window is created in the first dielectric layer by laser drilling; or, A window is created in the first dielectric layer by exposing and developing it. or, A window is created on the first dielectric layer by exposing and developing it, followed by plasma treatment.

3. The method for fabricating an embedded packaging substrate according to claim 1, characterized in that, The provision of a second dielectric layer on the surface of the first dielectric layer specifically includes: A second dielectric layer is disposed on the surface of the first dielectric layer, and a window is made and electroplated on the second dielectric layer at the position corresponding to the third conductive block to form a fourth conductive block that is in communication with the third conductive block; The second dielectric layer is filled at the location of the window on the second dielectric layer, and the second dielectric layer is opened and electroplated to form a fifth conductive block that is connected to the first circuit layer and a blind via metal block that is connected to the fourth conductive block.

4. An embedded packaging substrate, characterized in that, It is prepared by the method of embedding encapsulation substrate according to any one of claims 1-3.

5. A packaging substrate, characterized in that, include: A support frame, wherein the support frame is provided with a conductive copper pillar and a cavity penetrating the support frame; A first dielectric layer covers the upper and lower surfaces of the support frame, and the first dielectric layer fills the cavity; The chip is disposed inside the cavity and fixed by the first dielectric layer; A first circuit layer is disposed on the surface of the first dielectric layer, and the first circuit layer is connected to the conductive copper pillar, the pins on the front side of the chip, and the back side of the chip. The second dielectric layer is disposed on the surface of the first dielectric layer; The second circuit layer is disposed on the surface of the second dielectric layer, and the second circuit layer is conductive to the first circuit layer; The first circuit layer is connected to the conductive copper pillar through a first conductive block disposed in the first dielectric layer; the first circuit layer is connected to the pins on the front side of the chip through a second conductive block disposed in the first dielectric layer; the first circuit layer is connected to the back side of the chip through a third conductive block disposed in the first dielectric layer. The second circuit layer is connected to the third conductive block through a blind via metal block and a fourth conductive block disposed in the second dielectric layer; the second circuit layer is connected to the first circuit layer through a fifth conductive block disposed in the second dielectric layer.

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