Display substrate, display panel and display device

Abstract

A display substrate, a display panel (110) and a display device (1000) are provided. The display substrate comprises: a substrate (10); a first semiconductor layer (20) disposed on the substrate (10); and a second semiconductor layer (50) disposed on the side of the first semiconductor layer (20) away from the substrate (10), wherein the display substrate further comprises a plurality of thin film transistors (T1, T2, T3, T4, T5, T6, T7) disposed on the substrate (10), the plurality of thin film transistors (T1, T2, T3, T4, T5, T6, T7) at least comprising a first transistor (T1), a second transistor (T2) and a third transistor (T3), each of the plurality of thin film transistors (T1, T2, T3, T4, T5, T6, T7) comprising an active layer, the active layer (20a, 20b) of at least one of the first transistor (T1) and the second transistor (T2) comprising an oxide semiconductor material, the active layer (20c) of the third transistor (T3) comprising a polysilicon semiconductor material, the active layer (20c) of the third transistor (T3) being located in the first semiconductor layer (20), the active layer (20a, 20b) of at least one of the first transistor (T1) and the second transistor (T2) being located in the second semiconductor layer (50); and at least one of the first transistor (T1) and the second transistor (T2) having a double-gate structure.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular, to a display substrate, a display panel and a display device. BACKGROUND

[0002] An organic light emitting diode (abbreviated as OLED) display device is a kind of display device using an OLED to display image information and the like. The OLED display device has characteristics such as low power consumption, high brightness and high response speed. The Low Temperature Poly-Oxide TFT (hereinafter referred to as LTPO TFT) technology is a new thin film transistor technology in recent years. In theory, compared with the traditional Low Temperature Poly-Silicon TFT (hereinafter referred to as LTPS TFT) technology, the LTPO TFT can save 5-15% of power, and make the power consumption of the whole display screen lower.

[0003] The above information disclosed in this section is only for understanding the background of the technical concept of the present disclosure, and therefore, the above information can contain information which does not constitute prior art. SUMMARY

[0004] In one aspect, a display substrate is provided, wherein the display substrate comprises:

[0005] a substrate substrate;

[0006] a first semiconductor layer disposed on the substrate substrate; and

[0007] a second semiconductor layer disposed on a side of the first semiconductor layer away from the substrate substrate,

[0008] wherein the display substrate further comprises a plurality of thin film transistors disposed on the substrate substrate, the plurality of thin film transistors comprising at least a first transistor and a third transistor,

[0009] each of the plurality of thin film transistors comprises an active layer, the active layer of the first transistor comprises an oxide semiconductor material, the active layer of the third transistor comprises a polysilicon semiconductor material, the active layer of the third transistor is located in the first semiconductor layer, and the active layer of the first transistor is located in the second semiconductor layer;

[0010] The first transistor includes a first bottom gate located between the substrate and an active layer of the first transistor and a first top gate located on a side of the active layer of the first transistor away from the substrate, and a projection on the substrate of any two of the active layer of the first transistor, the first bottom gate, and the first top gate at least partially overlap with each other.

[0011] The display substrate includes a first conductive layer and a second conductive layer disposed on the substrate, the first conductive layer is located on a side of the first semiconductor layer away from the substrate, and the second conductive layer is located between the first conductive layer and the second semiconductor layer.

[0012] The third transistor includes a gate, a source, and a drain, the gate of the third transistor is located on the first conductive layer, and the source of the third transistor and the drain of the third transistor are located on the second conductive layer.

[0013] The first bottom gate is located on the second conductive layer.

[0014] According to some exemplary embodiments, the display substrate further includes a second transistor, the second transistor includes a second bottom gate located between the substrate and an active layer of the second transistor and a second top gate located on a side of the active layer of the second transistor away from the substrate, and a projection on the substrate of any two of the active layer of the second transistor, the second bottom gate, and the second top gate at least partially overlap with each other. The active layer in the second transistor includes an oxide semiconductor material, the active layer in the second transistor is located on the second semiconductor layer, and the second bottom gate is located on the second conductive layer.

[0015] According to some exemplary embodiments, the display substrate includes a storage capacitor, the storage capacitor includes a first capacitor electrode and a second capacitor electrode disposed on the substrate, a projection on the substrate of the first capacitor electrode at least partially overlaps with a projection on the substrate of the second capacitor electrode, and the second capacitor electrode is located on the second conductive layer and the first capacitor electrode is located on the first conductive layer.

[0016] According to some exemplary embodiments, the display substrate includes a first bottom gate structure in the second conductive layer, the first bottom gate structure includes a first bottom gate body portion and a first bottom gate extension portion, a footprint of the first bottom gate body portion on the substrate is at least partially overlapped with a footprint of the active layer of the first transistor on the substrate, the first bottom gate includes a portion of the first bottom gate body portion that overlaps with the active layer of the first transistor; and / or, the display substrate includes a second bottom gate structure in the second conductive layer, the second bottom gate structure includes a second bottom gate body portion and a second bottom gate extension portion, a footprint of the second bottom gate body portion on the substrate is at least partially overlapped with a footprint of the active layer of the second transistor on the substrate, the second bottom gate includes a portion of the second bottom gate body portion that overlaps with the active layer of the second transistor.

[0017] According to some exemplary embodiments, the display substrate further includes a data line for transmitting a data signal, the data line extends along a first direction on the substrate, at least one of the first bottom gate extension portion and the second bottom gate extension portion extends along the first direction; at least one of the active layer of the first transistor and the active layer of the second transistor extends along the first direction.

[0018] According to some exemplary embodiments, the display substrate includes a third conductive layer, the third conductive layer is located on a side of the second semiconductor layer away from the substrate,

[0019] The display substrate includes a first top gate structure in the third conductive layer, the first top gate structure extends along a second direction, the second direction intersects the first direction;

[0020] The first top gate structure includes a first widened portion, a dimension of the first widened portion along the first direction is greater than a dimension of a remaining portion of the first top gate structure along the first direction; and

[0021] A footprint of the first widened portion on the substrate is at least partially overlapped with a footprint of the active layer of the first transistor on the substrate, the first top gate includes a portion of the first widened portion that overlaps with the active layer of the first transistor.

[0022] According to some exemplary embodiments, the display substrate includes a second top gate structure in the third conductive layer, the second top gate structure extends along the second direction;

[0023] The second top gate structure includes a second widened portion, a dimension of the second widened portion along the first direction is greater than a dimension of a remaining portion of the second top gate structure along the first direction; and

[0024] A normal projection of the second widened portion on the substrate substrate at least partially overlaps with a normal projection of the active layer of the second transistor on the substrate substrate.

[0025] According to some exemplary embodiments, the first widened portion protrudes to both sides of the rest of the first top gate structure along the first direction respectively; and / or, the second widened portion protrudes to both sides of the rest of the second top gate structure along the first direction respectively.

[0026] According to some exemplary embodiments, the display substrate comprises a fourth conductive layer located on a side of the third conductive layer away from the substrate substrate; the first transistor comprises a first source and a first drain, and the second transistor comprises a second source and a second drain, and the first source, the first drain, the second source and the second drain are all located on the fourth conductive layer.

[0027] According to some exemplary embodiments, the display substrate comprises an initialization voltage line located on the third conductive layer, the initialization voltage line being used for transmitting an initialization voltage signal; and the display substrate further comprises a first conductive component located on the fourth conductive layer, one end of the first conductive component being electrically connected to the active layer of the first transistor through a first via, and a part of the first conductive component being further electrically connected to the initialization voltage line through a second via.

[0028] According to some exemplary embodiments, the display substrate further comprises a second conductive component and a third conductive component located on the fourth conductive layer, one end of the second conductive component being electrically connected to the active layer of the second transistor through a third via, the other end of the second conductive component being electrically connected to the active layer of the first transistor and one end of the third conductive component through a fourth via; and the other end of the third conductive component being electrically connected to the gate of the third transistor and the first capacitor electrode through a fifth via.

[0029] According to some exemplary embodiments, the display substrate further comprises a light emitting device disposed on the substrate substrate, the light emitting device at least comprising a first electrode, the first electrode being located on a side of the fourth conductive layer away from the substrate substrate; and a normal projection of the first electrode on the substrate substrate at least partially overlaps with a normal projection of the active layer of the first transistor on the substrate substrate.

[0030] According to some exemplary embodiments, the normal projection of the first electrode on the substrate substrate is spaced apart from a normal projection of the active layer of the second transistor on the substrate substrate.

[0031] According to some exemplary embodiments, the display substrate further includes a pixel defining layer disposed on the substrate, the pixel defining layer including an opening exposing at least a portion of the first electrode, and a spacer disposed on a side of the pixel defining layer distal to the substrate, a projection of the spacer on the substrate at least partially overlapping a projection of the active layer of the second transistor on the substrate.

[0032] According to some exemplary embodiments, the display substrate further includes a first buffer layer disposed between the substrate and the first semiconductor layer, the first buffer layer including silicon oxide or silicon nitride; and / or,

[0033] the display substrate further includes a first gate insulating layer disposed between the first semiconductor layer and the first conductive layer, the first gate insulating layer including silicon oxide; and / or,

[0034] the display substrate further includes a second buffer layer disposed between the second conductive layer and the second semiconductor layer, the second buffer layer including silicon oxide; and / or,

[0035] the display substrate further includes a second gate insulating layer disposed between the second semiconductor layer and the third conductive layer, the second gate insulating layer including silicon oxide.

[0036] According to some exemplary embodiments, the display substrate is a flexible display substrate, the flexible display substrate including a display area and a bending area; and the display substrate further includes a groove disposed in the bending area, the groove exposing at least a portion of the substrate in the bending area.

[0037] According to some exemplary embodiments, the display substrate further includes a trace disposed in the bending area, the trace being disposed on the fourth conductive layer, and the trace being disposed on a bottom of the groove.

[0038] According to some exemplary embodiments, the display substrate further includes a passivation layer disposed on a side of the fourth conductive layer distal to the substrate, a portion of the passivation layer covering at least the trace; and the display substrate further includes a planarization layer disposed on a side of the passivation layer distal to the substrate, the planarization layer filling the groove.

[0039] In another aspect, a display panel is provided, including the display substrate as described above.

[0040] In yet another aspect, a display device is provided, including the display substrate as described above or the display panel as described above. BRIEF DESCRIPTION OF DRAWINGS

[0041] The features and advantages of the present disclosure will become more apparent from the detailed description of example embodiments of the present disclosure with reference made to the accompanying drawings.

[0042] Figure 1 is a plan view of a display device according to some embodiments of the present disclosure;

[0043] Figure 2 is a plan view of a display substrate included in a display device according to some embodiments of the present disclosure;

[0044] Figure 3 is a partial enlarged view of the display substrate according to some embodiments of the present disclosure at portion I in Figure 2

[0045] Figure 4 is an equivalent circuit diagram of one pixel driving circuit of a display substrate according to some example embodiments of the present disclosure;

[0046] Figure 5 is a schematic diagram showing a planar structure of a pixel driving circuit of one sub-pixel of a display substrate according to some example embodiments of the present disclosure;

[0047] Figure 6 is a schematic diagram showing a planar structure of a first semiconductor layer of the pixel driving circuit shown in Figure 5

[0048] Figure 7 is a schematic diagram showing a combination of the first semiconductor layer and a first conductive layer of the pixel driving circuit shown in Figure 5

[0049] Figure 8 is a schematic diagram showing a combination of the first semiconductor layer, the first conductive layer and a second conductive layer of the pixel driving circuit shown in Figure 5

[0050] Figure 9 is a schematic diagram showing a combination of the first semiconductor layer, the first conductive layer, the second conductive layer and a second semiconductor layer of the pixel driving circuit shown in Figure 5

[0051] Figure 10 is a schematic diagram showing a combination of the first semiconductor layer, the first conductive layer, the second conductive layer, the second semiconductor layer and a third conductive layer of the pixel driving circuit shown in Figure 5

[0052] Figure 11 is a schematic diagram showing a combination of the first semiconductor layer, the first conductive layer, the second conductive layer, the second semiconductor layer and a third conductive layer of the pixel driving circuit shown in Figure 5 ​​​​​​A schematic view of a cross-sectional structure taken along the line AA' and the line BB' in FIG. 1A is shown in FIG. 1B. For ease of description, the cross-sectional structure taken along the line AA' and the line BB' in FIG. 1A is shown in the same schematic view in FIG. 1B.

[0053] Figure 12 is a schematic view showing a planar structure of a display substrate according to some example embodiments of the present disclosure, in which a planar structure of a first electrode of a light emitting device is schematically shown. Figure 5 Figure 5

[0054] Figure 13 is a schematic view showing a planar structure of a display substrate according to some example embodiments of the present disclosure, in which a planar structure of a first electrode of a light emitting device is schematically shown.

[0055] Figure 14 is a schematic view showing a planar structure of a display substrate according to some example embodiments of the present disclosure, in which an opening of a pixel defining layer is schematically shown.

[0056] Figure 15 is a schematic view showing a planar structure of a display substrate according to some example embodiments of the present disclosure, in which a planar structure of a spacer is schematically shown.

[0057] Figure 16 is a schematic view showing a cross-sectional structure of a display substrate according to some example embodiments of the present disclosure.

[0058] Figure 17 is a schematic view of a flexible display substrate according to example embodiments of the present disclosure in a folded state.

[0059] Figure 18 shows a cross-sectional view of the flexible display substrate in FIG. 1A along the X direction. Figure 17

[0060] is a flowchart of a manufacturing method of a display substrate according to some example embodiments of the present disclosure; and Figure 19

[0061] is a schematic view of a cross-sectional structure of a display substrate formed after some steps in the manufacturing method shown in FIG. 2A are performed. Figures 20 to 23 DETAILED DESCRIPTION Figure 19

[0062] ​​​​In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings. Obviously, the described embodiments are some but not all of the embodiments of the present disclosure. Based on the described embodiments of the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without creative effort belong to the protection scope of the present disclosure.

[0063] It should be noted that in the drawings, the size and relative size of the elements can be exaggerated for clarity and / or descriptive purposes. Thus, the size and relative sizes of the elements in the drawings are not necessarily drawn to scale. In the description and drawings, identical or similar reference numerals indicate identical or similar components.

[0064] When an element is described as being "on" another element, "connected to" another element, or "coupled to" another element, it can be directly on, directly connected to, or directly coupled to the other element, or intervening elements can be present. However, when an element is described as being "directly on," "directly connected to," or "directly coupled to" another element, there are no intervening elements present. Other terms and / or expressions used herein to describe relationships between elements should be interpreted in a like manner, such as "between" versus "directly between," "adjacent" versus "directly adjacent" or "on" versus "directly on" and the like. In addition, the term "connected" can refer to physical or electrical connectivity, communicative connectivity, and / or fluidic connectivity. Furthermore, the X-axis, Y-axis, and Z-axis are not limited to the three axes of a rectangular coordinate system, and can be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. For the purposes of the present disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted to mean only X, only Y, only Z, or any combination of two or more of X, Y, and Z such as XYZ, XYY, YZ, and ZZ. As used herein, the term "and / or" includes any and all combinations of one or more of the associated items.

[0065] It should be noted that, although the terms "first," "second," etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. Rather, these terms are used only to distinguish one element, component, region, layer and / or section from another element, component, region, layer and / or section. Thus, a first element, component, region, layer and / or section discussed below could be termed a second element, component, region, layer and / or section without departing from the teachings of the present disclosure.

[0066] Spatially relative terms, such as "upper," "lower," "left," "right," and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. For example, if a device described is turned over in the figure, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features.

[0067] In this document, the terms "substantially," "approximately," "about," "generally," and other similar terms are used as terms of approximation and not as terms of degree, and they are intended to account for the inherent deviations in measured or calculated values that would be recognized by those of ordinary skill in the art. "About" or "approximately," as used herein when used in relation to a particular value, includes the stated value, plus or minus 30%, 20%, 10%, 5%, or within one or more standard deviations, as determined by one of ordinary skill in the art. For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0068] It should be noted that, in this document, the term "same layer" refers to a layer structure formed by using the same film formation process to form a film layer for forming a specific pattern, and then patterning the film layer by a one-time patterning process using the same mask plate. Depending on the specific pattern, the one-time patterning process can include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure can be continuous or discontinuous. That is, the plurality of elements, components, structures and / or parts located in the "same layer" are composed of the same material and are formed by the same one-time patterning process, and generally, the plurality of elements, components, structures and / or parts located in the "same layer" have substantially the same thickness.

[0069] Those skilled in the art should understand that, herein, unless otherwise specified, the expression "height" or "thickness" refers to the dimension along the surface of each film layer arranged perpendicularly to the display substrate, i.e. the dimension along the light-out direction of the display substrate, or the dimension along the normal direction of the display device.

[0070] Embodiments of the present disclosure provide at least a display substrate. The display substrate comprises: a substrate substrate; a first semiconductor layer disposed on the substrate substrate; and a second semiconductor layer disposed on a side of the first semiconductor layer away from the substrate substrate, wherein the display substrate further comprises a plurality of thin film transistors disposed on the substrate substrate, the plurality of thin film transistors at least comprising a first transistor, a second transistor and a third transistor, wherein each of the plurality of thin film transistors comprises an active layer, the active layer of at least one of the first transistor and the second transistor comprises an oxide semiconductor material, the active layer of the third transistor comprises a polysilicon semiconductor material, the active layer of the third transistor is located in the first semiconductor layer, the active layer of at least one of the first transistor and the second transistor is located in the second semiconductor layer; and at least one of the first transistor and the second transistor has a double-gate structure. In embodiments of the present disclosure, the active layer of at least one of the first transistor and the second transistor is formed by using an oxide semiconductor material such as LTPO, and a double-gate structure is adopted, so that the display performance of the display panel can be improved.

[0071] Figure 1 is a plan view of a display device according to some embodiments of the present disclosure. For example, the display device can be an OLED display device. Referring to Figure 1 , the display device 1000 can include a display panel 110, a gate driver 120, a data driver 130, a controller 140, and a voltage generator 150. For example, the display device 1000 can be an OLED display device. The display panel 110 can include an array substrate 100 and a plurality of pixels PX, the array substrate 100 can include a display area AA and a non-display area NA, and the plurality of pixels PX are arranged in an array in the display area AA. The signal generated by the gate driver 120 can be applied to the pixel PX through a signal line such as a scan signal line GL, and the signal generated by the data driver 130 can be applied to the pixel PX through a signal line such as a data line DL. A first voltage such as VDD and a second voltage such as VSS can be applied to the pixel PX. The first voltage such as VDD can be higher than the second voltage such as VSS. Alternatively, the first voltage such as VDD can be applied to the anode of a light-emitting device (e.g. an OLED), and the second voltage such as VSS can be applied to the cathode of the light-emitting device, so that the light-emitting device can emit light.

[0072] For example, each pixel PX can include multiple sub-pixels, such as a red sub-pixel, a green sub-pixel, and a blue sub-pixel, or can include a white sub-pixel, a red sub-pixel, a green sub-pixel, and a blue sub-pixel.

[0073] Figure 2 is a plan view of a display substrate included in a display device according to some embodiments of the present disclosure. For example, the display substrate can be an array substrate for an OLED display panel.

[0074] Referring to Figure 2 , the display substrate can include a display area AA and a non-display area NA. For example, the display area AA and the non-display area NA can include multiple boundaries, such as AAS1, AAS2, AAS3, and AAS4 as shown in Figure 2 . The display substrate can also include a driver located within the non-display area NA. For example, the driver can be located at least one side of the display area AA. In the embodiment shown in Figure 2 , the driving circuit is located at the left and right sides of the display area AA, respectively. It should be noted that the left and right sides herein can be the left and right sides of the display substrate (screen) as viewed by the human eye during display. The driver can be used to drive each pixel in the display substrate to display. For example, the driver can include the above-mentioned gate driver 120 and data driver 130. The data driver 130 is used to sequentially latch the input data according to the timing of the clock signal and convert the latched data into an analog signal and then input to each data line of the display substrate. The gate driver 120 is usually implemented by a shift register, which converts the clock signal into an on / off voltage and outputs to each scan signal line of the display substrate, respectively.

[0075] It should be noted that although the driver is shown to be located at the left and right sides of the display area AA in Figure 2 , embodiments of the present disclosure are not limited thereto, and the driving circuit can be located at any suitable position in the non-display area NA.

[0076] For example, the driver can adopt GOA technology, i.e., Gate Driver on Array. In GOA technology, the gate driving circuit is directly arranged on the array substrate to replace the external driving chip. Each GOA unit serves as a level of shift register, each level of shift register is connected with a gate line, and the opening voltage is sequentially and alternately output by each level of shift register to realize the row-by-row scanning of the pixels. In some embodiments, each level of shift register can also be connected with multiple gate lines. In this way, the development trend of high resolution and narrow frame of the display substrate can be adapted.

[0077] Referring to Figure 2On the display substrate, a left GOA circuit DA1, a plurality of pixels P in a display area AA, and a right GOA circuit DA2 are provided. The left GOA circuit DA1 and the right GOA circuit DA2 are electrically connected to a display IC through signal lines, respectively, and the supply of GOA signals is controlled by the display IC, which is provided, for example, on the lower side of the display substrate (in the direction of the human eye). The left GOA circuit DA1 and the right GOA circuit DA2 are also electrically connected to each pixel through a signal line (for example, a scan signal line GL), respectively, to supply a driving signal to each pixel.

[0078] Figure 3 is a partial enlarged view of part I in Figure 2 of a display substrate according to some embodiments of the present disclosure. It should be noted that the shape of the orthographic projection of the sub-pixel on the substrate is a rounded rectangle in the example shown in the figure, but embodiments of the present disclosure are not limited thereto, for example, the shape of the orthographic projection of the sub-pixel on the substrate can be rectangular, hexagonal, pentagonal, square, circular, or other shapes. Moreover, the arrangement of the 3 sub-pixels in one pixel unit is not limited to the manner shown in Figure 3 .

[0079] In combination with reference to Figure 1 , Figure 2 and Figure 3 , each pixel unit PX can include a plurality of sub-pixels, for example, a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. For the convenience of understanding, the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can be described as red sub-pixels, green sub-pixels, and blue sub-pixels, respectively, but embodiments of the present disclosure are not limited thereto.

[0080] The plurality of sub-pixels are arranged in an array on the substrate 1 along the row direction X and the column direction Y. It should be noted that although in the illustrated embodiment, the row direction X and the column direction Y are perpendicular to each other, embodiments of the present disclosure are not limited thereto.

[0081] It should be understood that in embodiments of the present disclosure, each sub-pixel includes a pixel driving circuit and a light emitting device. For example, the light emitting device can be an OLED light emitting device, including an anode, an organic light emitting layer, and a cathode arranged in layers. The pixel driving circuit can include a plurality of thin film transistors and at least one storage capacitor.

[0082] In the following, taking a 7T1C pixel driving circuit as an example, the structure of the pixel driving circuit is described in detail, but embodiments of the present disclosure are not limited to the 7T1C pixel driving circuit, and other known pixel driving circuit structures can be applied to embodiments of the present disclosure without conflict.

[0083] Figure 4 is an equivalent circuit diagram of one pixel driving circuit of a display substrate according to some exemplary embodiments of the present disclosure. As shown in Figure 4 , the pixel driving circuit can include a plurality of thin film transistors and one storage capacitor Cst. The pixel driving circuit is used to drive an organic light emitting diode (i.e., OLED). The plurality of thin film transistors includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7. Each transistor includes a gate, a source, and a drain.

[0084] The display substrate can further include a plurality of signal lines, for example, the plurality of signal lines include a scan signal line 61 for transmitting a scan signal Sn, a reset signal line 62 for transmitting a reset control signal RESET (i.e., the scan signal of the previous row), a light emitting control line 63 for transmitting a light emitting control signal En, a data line 64 for transmitting a data signal Dm, a driving voltage line 65 for transmitting a driving voltage VDD, an initialization voltage line 66 for transmitting an initialization voltage Vint, and a power supply line 67 for transmitting a VSS voltage.

[0085] The gate G1 of the first transistor T1 is electrically connected to the reset signal line 62, and the source S1 of the first transistor T1 is electrically connected to the initialization voltage line 66. And the drain D1 of the first transistor T1 is electrically connected to one end Cst1 of the storage capacitor Cst, the drain D2 of the second transistor T2, and the gate G3 of the third transistor T3, as shown in Figure 4 , the drain D1 of the first transistor T1, the one end Cst1 of the storage capacitor Cst, the drain D2 of the second transistor T2, and the gate G3 of the third transistor T3 are electrically connected at a node N1. The first transistor T1 is turned on according to the reset control signal RESET transmitted by the reset signal line 62 to transmit the initialization voltage Vint to the gate G1 of the third transistor T3, so as to perform an initialization operation to initialize the voltage of the gate G3 of the third transistor T3. That is, the first transistor T1 is also called an initialization transistor.

[0086] The gate G2 of the second transistor T2 is electrically connected to the scan signal line 61, the source S2 of the second transistor T2 is electrically connected to a node N3, and the drain D2 of the second transistor T2 is electrically connected to the node N1. The second transistor T2 is turned on according to the scan signal Sn transmitted by the scan signal line 61 to electrically connect the gate G3 and the drain D3 of the third transistor T3 to each other, so as to perform a diode connection of the third transistor T3.

[0087] The gate G3 of the third transistor T3 is electrically connected to the node N1, the source S3 of the third transistor T3 is electrically connected to the node N2, and the drain D3 of the third transistor T3 is electrically connected to the node N3. The third transistor T3 receives the data signal Dm according to the switching operation of the fourth transistor T4 to supply the driving current Id to the OLED. That is, the third transistor T3 is also called a driving transistor.

[0088] The gate G4 of the fourth transistor T4 is electrically connected to the scan signal line 61, the source S4 of the fourth transistor T4 is electrically connected to the data line 64, and the drain D4 of the fourth transistor T4 is electrically connected to the node N2, i.e., the source S3 of the third transistor T3. The fourth transistor T4 is turned on according to the scan signal Sn transmitted through the scan signal line 61 to perform the switching operation to transmit the data signal Dm to the source S3 of the third transistor T3.

[0089] The gate G5 of the fifth transistor T5 is electrically connected to the light-emitting control line 63, the source S5 of the fifth transistor T5 is electrically connected to the driving voltage line 65, and the drain D5 of the fifth transistor T5 is electrically connected to the node N2.

[0090] The gate G6 of the sixth transistor T6 is electrically connected to the light-emitting control line 63, the source S6 of the sixth transistor T6 is electrically connected to the node N3, and the drain D6 of the sixth transistor T6 is electrically connected to the node N4, i.e., the anode of the OLED. The fifth transistor T5 and the sixth transistor T6 are concurrently (e.g., simultaneously) turned on according to the light-emitting control signal En transmitted through the light-emitting control line 63 to transmit the driving voltage VDD to the OLED, thereby allowing the driving current Id to flow into the OLED.

[0091] The gate G7 of the seventh transistor T7 is electrically connected to the reset signal line 62, the source S7 of the seventh transistor T7 is electrically connected to the node N4, and the drain D7 of the seventh transistor T7 is electrically connected to the initialization voltage line 66.

[0092] One end (hereinafter referred to as a first capacitor electrode) Cst1 of the storage capacitor Cst is electrically connected to the node N1, and the other end (hereinafter referred to as a second capacitor electrode) Cst2 is electrically connected to the driving voltage line 65.

[0093] The anode of the OLED is electrically connected to the node N4, and the cathode is electrically connected to the power supply line 67 to receive the common voltage VSS. Accordingly, the OLED receives the driving current Id from the third transistor T3 to emit light, thereby displaying an image.

[0094] It should be noted that, in the above embodiment, the driving voltage line 65 is electrically connected to the source S5 of the fifth transistor T5 and the second capacitor electrode Cst2 of the storage capacitor Cst. Alternatively, the driving voltage line 65 can be electrically connected to the source S5 of the fifth transistor T5 and the first capacitor electrode Cst1 of the storage capacitor Cst. Figure 4In the present embodiment, each of the thin film transistors T1, T2, T3, T4, T5, T6, and T7 is a p-channel field effect transistor, but the embodiment of the present disclosure is not limited thereto, and at least some of the thin film transistors T1, T2, T3, T4, T5, T6, and T7 can be n-channel field effect transistors.

[0095] In operation, in an initialization phase, a reset control signal RESET having a low level is supplied through the reset signal line 62. Subsequently, the first transistor T1 turns on based on the low level of the reset control signal RESET, and an initialization voltage Vint from the initialization voltage line 66 is transmitted to the gate G1 of the third transistor T3 through the first transistor T1. Thus, the third transistor T3 is initialized due to the initialization voltage Vint.

[0096] In a data programming phase, a scan signal Sn having a low level is supplied through the scan signal line 61. Subsequently, the fourth transistor T4 and the second transistor T2 turn on based on the low level of the scan signal Sn. Thus, the third transistor T3 is placed in a diode connection state and biased in a positive direction through the turned-on second transistor T2.

[0097] Subsequently, a compensation voltage Dm+Vth (e.g., Vth is a negative value) obtained by subtracting a threshold voltage Vth of the third transistor T3 from a data signal Dm supplied through the data line 64 is applied to the gate G3 of the third transistor T3. Subsequently, the drive voltage VDD and the compensation voltage Dm+Vth are applied to both terminals of the storage capacitor Cst, so that a charge corresponding to a voltage difference between the respective terminals is stored in the storage capacitor Cst.

[0098] In a light emission phase, a light emission control signal En from the light emission control line 63 changes from a high level to a low level. Subsequently, in the light emission phase, the fifth transistor T5 and the sixth transistor T6 turn on based on the low level of the light emission control signal En.

[0099] Subsequently, a drive current is generated based on a difference between the voltage of the gate G3 of the third transistor T3 and the drive voltage VDD. A drive current Id corresponding to a difference between the drive current and the bypass current is supplied to the OLED through the sixth transistor T6.

[0100] In the light emission phase, based on a current-voltage relationship of the third transistor T3, a gate-source voltage of the third transistor T3 is maintained at (Dm+Vth)-VDD due to the storage capacitor Cst. The drive current Id is proportional to (Dm-VDD)2. Thus, the drive current Id can not be affected by a threshold voltage Vth variation of the third transistor T3.

[0101] Figure 5is a schematic diagram illustrating a planar structure of a pixel driving circuit of one sub-pixel of a display substrate according to some example embodiments of the present disclosure. Figure 6 is a schematic diagram illustrating a planar structure of a first semiconductor layer of the pixel driving circuit shown in Figure 5 . Figure 7 is a schematic diagram illustrating a planar structure of a first semiconductor layer and a first conductive layer of the pixel driving circuit shown in Figure 5 . Figure 8 is a schematic diagram illustrating a planar structure of a first semiconductor layer, a first conductive layer and a second conductive layer of the pixel driving circuit shown in Figure 5 . Figure 9 is a schematic diagram illustrating a planar structure of a first semiconductor layer, a first conductive layer, a second conductive layer and a second semiconductor layer of the pixel driving circuit shown in Figure 5 . Figure 10 is a schematic diagram illustrating a planar structure of a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer and a third conductive layer of the pixel driving circuit shown in Figure 5 . Figure 11 is a schematic diagram illustrating a planar structure of a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer and a fourth conductive layer of the pixel driving circuit shown in Figure 5 . Figure 12 is a schematic diagram illustrating a cross-sectional structure taken along a line AA' and a line BB' in Figure 5 according to some example embodiments of the present disclosure, for ease of description, the cross-sectional structures taken along the line AA' and the line BB' in Figure 5 are shown in the same schematic diagram.

[0102] With reference to Figures 5 to 12 , the display substrate includes a substrate 10 and a plurality of film layers disposed on the substrate 10. In some embodiments, the plurality of film layers includes at least a first semiconductor layer 20, a first conductive layer 30, a second conductive layer 40, a second semiconductor layer 50, a third conductive layer 60 and a fourth conductive layer 70. The first semiconductor layer 20, the first conductive layer 30, the second conductive layer 40, the second semiconductor layer 50, the third conductive layer 60 and the fourth conductive layer 70 are disposed away from the substrate 10 in sequence.

[0103] For example, the first semiconductor layer 20 can be formed of a semiconductor material such as low-temperature polysilicon, and can have a film thickness in a range of 400 to 800 angstroms, for example, 500 angstroms. The second semiconductor layer 50 can be formed of an oxide semiconductor material such as IGZO, and can have a film thickness in a range of 300 to 600 angstroms, for example, 400 angstroms. The first conductive layer 30 can be formed of a conductive material forming a gate of a thin film transistor, and can have a film thickness in a range of 2000 to 3000 angstroms, for example, 2500 angstroms. The second conductive layer 40 can be formed of a conductive material forming a source and a drain of a thin film transistor, and can have a film thickness in a range of 7000 to 9000 angstroms. For example, in a case where the second conductive layer 40 has a stacked structure formed of Ti / Al / Ti, the thickness of each layer of Ti / Al / Ti can be about 500 angstroms, 5500 angstroms, and 500 angstroms, respectively. The third conductive layer 60 can be formed of a conductive material forming a gate of a thin film transistor, and can have a film thickness in a range of 2000 to 3000 angstroms, for example, 2500 angstroms. The fourth conductive layer 70 can be formed of a conductive material forming a source and a drain of a thin film transistor, and can have a film thickness in a range of 7000 to 9000 angstroms. For example, in a case where the fourth conductive layer 70 has a stacked structure formed of Ti / Al / Ti, the thickness of each layer of Ti / Al / Ti can be about 500 angstroms, 5500 angstroms, and 300 angstroms, respectively.

[0104] The display substrate includes scan signal lines 61, reset signal lines 62, light emission control lines 63, and initialization voltage lines 66 arranged along a row direction to apply a scan signal Sn, a reset control signal RESET, a light emission control signal En, and an initialization voltage Vint to the sub-pixels, respectively. The display substrate can further include data lines 64 and a driving voltage line 65 crossing the scan signal lines 61, the reset signal lines 62, the light emission control lines 63, and the initialization voltage lines 66 to apply a data signal Dm and a driving voltage VDD to the sub-pixels, respectively.

[0105] In connection with the above description of Figure 4 In connection with the above description of

[0106] The first transistor T1 and the second transistor T2 can be arranged along a row direction asFigure 9 The second semiconductor layer is formed as illustrated in FIG. 2B. The third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be formed along the first semiconductor layer 20 as illustrated in FIG. 2B. Figure 6 The first semiconductor layer 20 is formed as illustrated in FIG. 2A.

[0107] As illustrated in FIG. 2A, the first semiconductor layer 20 can have a curved or bent shape, and can include a third active layer 20c corresponding to the third transistor T3, a fourth active layer 20d corresponding to the fourth transistor T4, a fifth active layer 20e corresponding to the fifth transistor T5, a sixth active layer 20f corresponding to the sixth transistor T6, and a seventh active layer 20g corresponding to the seventh transistor T7. Figure 6 As illustrated in FIG. 2A, the first semiconductor layer 20 can have a curved or bent shape, and can include a third active layer 20c corresponding to the third transistor T3, a fourth active layer 20d corresponding to the fourth transistor T4, a fifth active layer 20e corresponding to the fifth transistor T5, a sixth active layer 20f corresponding to the sixth transistor T6, and a seventh active layer 20g corresponding to the seventh transistor T7.

[0108] For example, the first semiconductor layer 20 can include polysilicon, such as a low-temperature polysilicon material. The active layer of each transistor can include a channel region, a source region, and a drain region. The channel region can not be doped or doped differently from the source region and the drain region, and thus have semiconductor properties. The source region and the drain region are located on both sides of the channel region, respectively, and are doped with impurities, and thus have electrical conductivity. The impurities can vary depending on whether the TFT is an N-type or a P-type transistor.

[0109] The third transistor T3 includes the third active layer 20c and a third gate G3. The third active layer 20c includes a third source region 203c, a third drain region 205c, and a third channel region 201c connecting the third source region 203c and the third drain region 205c. The third source region 203c and the third drain region 205c extend in opposite directions with respect to the third channel region 201c.

[0110] The fourth transistor T4 includes the fourth active layer 20d and a fourth gate G4. The fourth active layer 20d includes a fourth source region 203d, a fourth drain region 205d, and a fourth channel region 201d connecting the fourth source region 203d and the fourth drain region 205d. The fourth source region 203d and the fourth drain region 205d extend in opposite directions with respect to the fourth channel region 201d.

[0111] The fifth transistor T5 includes the fifth active layer 20e and a fifth gate G5. The fifth active layer 20e includes a fifth source region 203e, a fifth drain region 205e, and a fifth channel region 201e connecting the fifth source region 203e and the fifth drain region 205e. The fifth source region 203e and the fifth drain region 205e extend in opposite directions with respect to the fifth channel region 201e.

[0112] The sixth transistor T6 includes a sixth active layer 20f and a sixth gate G6. The sixth active layer 20f includes a sixth source region 203f, a sixth drain region 205f, and a sixth channel region 201f connecting the sixth source region 203f and the sixth drain region 205f. The sixth source region 203f and the sixth drain region 205f extend in opposite directions relative to the sixth channel region 201f.

[0113] The seventh transistor T7 includes a seventh active layer 20g and a seventh gate G7. The seventh active layer 20g includes a seventh source region 203g, a seventh drain region 205g, and a seventh channel region 201g connecting the seventh source region 203g and the seventh drain region 205g. The seventh source region 203g and the seventh drain region 205g extend in opposite directions relative to the seventh channel region 201g.

[0114] like Figure 7 As shown, scan signal line 61, reset signal line 62, and light emission control line 63 are all located in the first conductive layer 30. Gate structure CG1 is also located in the first conductive layer 30. The portion of gate structure CG1 overlapping with the first semiconductor layer 20 forms the third gate G3 of the third transistor T3. The portion of scan signal line 61 overlapping with the first semiconductor layer 20 forms the fourth gate G4 of the fourth transistor T4. A portion of light emission control line 63 overlapping with the first semiconductor layer 20 forms the fifth gate G5 of the fifth transistor T5. Another portion of light emission control line 63 overlapping with the first semiconductor layer 20 forms the sixth gate G6 of the sixth transistor T6. The portion of reset signal line 62 overlapping with the first semiconductor layer 20 forms the seventh gate G7 of the seventh transistor T7. Gate structure CG1 also forms a terminal of storage capacitor Cst, such as the first capacitor electrode Cst1. That is, gate structure CG1 serves simultaneously as the gate of the third transistor T3 and an electrode of storage capacitor Cst.

[0115] like Figure 8 As shown, both data line 64 and drive voltage line 65 are located in the second conductive layer 40. The first bottom gate structure BG1 and the second bottom gate structure BG2 are also located in the second conductive layer 40. Data line 64 is electrically connected to the source region 203d of the fourth transistor T4 through via VAH1 to apply the data signal Dm to the source of the fourth transistor T4. That is, the portion where data line 64 overlaps with the source region 203d of the fourth transistor T4 constitutes the source of the fourth transistor T4. The portion where the second conductive layer 40 overlaps with the gate structure CG1 forms another electrode of the storage capacitor Cst, such as the second capacitor electrode Cst2. The second capacitor electrode Cst2 is electrically connected to the drive voltage line 65, for example, in… Figure 8In the embodiment, the second capacitor electrode Cst2 is connected to the driving voltage line 65 integrally. The driving voltage line 65 is electrically connected to the source region 203e of the fifth transistor T5 through the via hole VAH12. The portion of the driving voltage line 65 overlapping the source region 203e of the fifth transistor T5 constitutes the source of the fifth transistor T5.

[0116] Through such a design, the first capacitor electrode Cst1 and the second capacitor electrode Cst2 have a large overlapping area, which can increase the capacitance value of the storage capacitor Cst, thereby improving the performance of the display panel and reducing the power consumption of the display panel.

[0117] Continuing to refer to Figure 8 , the second conductive layer 40 includes a via hole 40H that exposes a portion of the gate structure CG1 to facilitate electrical connection of the third gate G3 of the third transistor T3 to other components.

[0118] The second conductive layer 40 further includes a first conductive member 401, a second conductive member 402, and a third conductive member 403. The first conductive member 401 is electrically connected to the drain region 205g of the seventh transistor T7 through the via hole VAH5. The second conductive member 402 is electrically connected to the drain region 205c of the third transistor T3 through the via hole VAH11. The third conductive member 403 is electrically connected to the drain region 205f of the sixth transistor T6 and the source region 203g of the seventh transistor T7 through the via hole VAH13.

[0119] As shown in Figure 9 , the second semiconductor layer 50 includes a first active layer 20a corresponding to the first transistor T1 and a second active layer 20b corresponding to the second transistor T2. For example, the first active layer 20a of the first transistor T1 and the second active layer 20b of the second transistor T2 extend in the same direction as the extension direction of the data line, i.e., both extend in the up-down direction in the figure.

[0120] For example, the second semiconductor layer 50 can include an oxide semiconductor material, such as a low-temperature polysilicon oxide semiconductor material (abbreviated as LTPO). The active layer of each transistor can include a channel region, a source region, and a drain region. The channel region can not be doped or have a different doping type from the source region and the drain region, and thus has semiconductor properties. The source region and the drain region are respectively located on both sides of the channel region, and are doped with impurities, and thus have electrical conductivity. The impurities can vary depending on whether the TFT is an N-type or a P-type transistor.

[0121] The first active layer 20a of the first transistor T1 includes a first source region 203a, a first drain region 205a, and a first channel region 201a connecting the first source region 203a and the first drain region 205a. The first source region 203a and the first drain region 205a extend in opposite directions with respect to the first channel region 201a.

[0122] The second active layer 20b of the second transistor T2 includes a second source region 203b, a second drain region 205b, and a second channel region 201b connecting the second source region 203b and the second drain region 205b. The second source region 203b and the second drain region 205b extend in opposite directions with respect to the second channel region 201b.

[0123] A projection of the first active layer 20a on the substrate 10 at least partially overlaps a projection of the first bottom gate structure BG1 on the substrate 10, and the first bottom gate G11 of the first transistor T1 is constituted by a portion of the first bottom gate structure BG1 that overlaps the first active layer 20a.

[0124] A projection of the second active layer 20b on the substrate 10 at least partially overlaps a projection of the second bottom gate structure BG2 on the substrate 10, and the second bottom gate G21 of the second transistor T2 is constituted by a portion of the second bottom gate structure BG2 that overlaps the second active layer 20b.

[0125] For example, continuing to refer to Figure 8 and Figure 9 , the first bottom gate structure BG1 includes a first bottom gate main portion BG11 and a first bottom gate extension portion BG12. A projection of the first bottom gate main portion BG11 on the substrate 10 has a rectangular shape. A projection of the first bottom gate main portion BG11 on the substrate 10 at least partially overlaps a projection of the active layer of the first transistor T1 on the substrate 10, and the first bottom gate G11 includes a portion of the first bottom gate main portion BG11 that overlaps the active layer of the first transistor T1.

[0126] The second bottom gate structure BG2 includes a second bottom gate main portion BG21 and a second bottom gate extension portion BG22. A projection of the second bottom gate main portion BG21 on the substrate 10 has a rectangular shape. A projection of the second bottom gate main portion BG21 on the substrate 10 at least partially overlaps a projection of the active layer of the second transistor T2 on the substrate 10, and the second bottom gate G21 includes a portion of the second bottom gate main portion BG21 that overlaps the active layer of the second transistor T2.

[0127] In the embodiment illustrated in the figure, at least one of the first bottom gate extension BG12 and the second bottom gate extension BG22 is in the same extension direction as the data line, i.e. both extend in the up-down direction in the figure.

[0128] As Figure 10 illustrated, the third conductive layer 60 includes a first top gate structure TG1 and a second top gate structure TG2. An initialization voltage line 66 is also located in the third conductive layer 60.

[0129] The orthographic projection of each of the first active layer 20a and the first bottom gate structure BG1 on the substrate 10 at least partially overlaps the orthographic projection of the first top gate structure TG1 on the substrate 10. The portion of the first top gate structure TG1 that overlaps the first active layer 20a constitutes a first top gate G12 of the first transistor. In combination with reference to Figure 12 , in the direction perpendicular to the upper surface of the substrate 10 (i.e. along the vertical direction illustrated in Figure 12 , the first active layer 20a is located between the first bottom gate G11 and the first top gate G12. In this way, the first transistor T1 has a dual-gate structure.

[0130] Continuing to refer to Figure 10 , the first top gate structure TG1 extends along the horizontal direction in Figure 10 . The first top gate structure TG1 can include a first widened portion TG11, the dimension of the first widened portion TG11 along the vertical direction being greater than the dimension of the rest of the first top gate structure TG1 along the vertical direction. The orthographic projection of the first widened portion TG11 on the substrate 10 at least partially overlaps the orthographic projection of the active layer 20a of the first transistor T1 on the substrate 10, the first top gate G12 including the portion of the first widened portion TG11 that overlaps the active layer 20a of the first transistor T1.

[0131] In the embodiment illustrated in Figure 10 , the first widened portion TG11 protrudes to both sides relative to the rest of the first top gate structure TG1 along the first direction (i.e. the vertical direction illustrated in Figure 10 . Alternatively, the first widened portion TG11 can protrude to only one side relative to the rest of the first top gate structure TG1 along the first direction (i.e. the vertical direction illustrated in Figure 10 . For example, the first widened portion TG11 can protrude only upwards or only downwards.

[0132] The orthographic projection of each of the second active layer 20b and the second bottom gate structure BG2 on the substrate 10 at least partially overlaps the orthographic projection of the second top gate structure TG2 on the substrate 10. The portion of the second top gate structure TG2 that overlaps the second active layer 20b constitutes a second top gate G22 of the second transistor. In combination with reference toFigure 12 In the direction perpendicular to the upper surface of the substrate 10 (i.e. along) Figure 12 (As shown in the vertical direction), the second active layer 20b is located between the second bottom gate G21 and the second top gate G22. Thus, the second transistor T2 has a dual-gate structure.

[0133] Continue to refer to Figure 10 The second top grid structure TG2 along Figure 10 The second top gate structure TG2 extends horizontally. The second top gate structure TG2 may include a second widened portion TG21, the vertical dimension of which is larger than the vertical dimension of the remaining portion of the second top gate structure TG2. The orthographic projection of the second widened portion TG21 onto the substrate 10 at least partially overlaps with the orthographic projection of the active layer 20b of the second transistor T2 onto the substrate 10. The second top gate G22 includes the portion where the second widened portion TG21 overlaps with the active layer 20b of the second transistor T2.

[0134] exist Figure 10 In the embodiment shown, the second widened portion TG21 is along the first direction (i.e. Figure 10 The second widened portion TG21 protrudes to both sides relative to the remainder of the second top grid structure TG2 (in the vertical direction shown). Optionally, the second widened portion TG21 extends along the first direction (i.e., the vertical direction shown). Figure 10 The vertical direction shown may protrude only to one side relative to the rest of the second top grid structure TG2, for example, only upward or only downward.

[0135] like Figure 11 As shown, the fourth conductive layer 70 includes a first conductive component 701, a second conductive component 702, a third conductive component 703, and a fourth conductive component 704. One end of the first conductive component 701 is electrically connected to the source region 203a of the first transistor T1 through a via VAH2. A portion of the first conductive component 701 is also electrically connected to the initialization voltage line 66 through a via VAH3. The other end of the first conductive component 701 is electrically connected to the first conductive member 401 through a via VAH4. In this way, the source of the first transistor T1 is electrically connected to the drain of the seventh transistor T7, and both are electrically connected to the initialization voltage line 66. Thus, the initialization voltage Vint can be applied to the source of the first transistor T1 and the drain of the seventh transistor T7.

[0136] One end of the second conductive member 702 is electrically connected to the drain region 205b of the second transistor T2 through the via hole VAH7, and the other end of the second conductive member 702 is electrically connected to the drain region 205a of the first transistor T1 and the third conductive member 703 through the via hole VAH6. One end of the third conductive member 703 is electrically connected to the second conductive member 702 through the via hole VAH6, and the other end of the third conductive member 703 is electrically connected to the gate G1 of the third transistor T3 and the first capacitor electrode Cst1 through the via hole VAH8. In this way, the electrical connection between the drain of the first transistor T1, the drain of the second transistor T2, the gate of the third transistor T3, and the first capacitor electrode Cst1 can be achieved. For details, refer to Figure 4 , which are all electrically connected to the node N1.

[0137] One end of the fourth conductive member 704 is electrically connected to the source region 203b of the second transistor T2 through the via hole VAH9, and the other end of the fourth conductive member 704 is electrically connected to the second conductive member 402 through the via hole VAH10. In this way, the electrical connection between the source of the second transistor T2 and the source of the sixth transistor T6 can be achieved.

[0138] In the embodiments of the present disclosure, the active layers of the first transistor T1 and the second transistor T2 are both formed by using an oxide semiconductor material such as LTPO, which can improve the voltage stability at the node N1 (as shown in Figure 4 ) in the pixel driving circuit, thereby improving the display performance of the display panel. Moreover, the first transistor T1 and the second transistor T2 both have a double-gate structure, so that the stability and the uniformity of the threshold voltage (Vth) of the first transistor T1 and the second transistor T2 are both improved, thereby further improving the performance of the display panel.

[0139] It should be further noted that, in the embodiments of the present disclosure, the bottom gates G11, G21 of the transistors T1, T2 not only function as bottom gates, but also function as light shielding layers, which can avoid the interference of external light on the active layers 20a, 20b of the transistors T1, T2, and is conducive to further improving the performance of the transistors. The bottom gates G11, G21 of the transistors T1, T2 and the sources and drains of the transistors T3, T4, T5, T6, T7 are located in the same layer, i.e., all located in the second conductive layer 40, so that the bottom gates G11, G21 of the transistors T1, T2 and the sources and drains of the transistors T3, T4, T5, T6, T7 can be formed by the same patterning process, which is conducive to saving the number of times of the patterning process and reducing the number of mask plates.

[0140] Figure 13 is a schematic diagram showing a planar structure of a display substrate according to some example embodiments of the present disclosure, in which the planar structure of a first electrode of a light emitting device is schematically shown. Figure 14is a schematic diagram showing a planar structure of a display substrate according to some example embodiments of the present disclosure, in which an opening of a pixel definition layer is schematically shown. Figure 15 is a schematic diagram showing a planar structure of a display substrate according to some example embodiments of the present disclosure, in which a planar structure of a spacer is schematically shown. Figure 16 is a schematic diagram showing a cross-sectional structure of a display substrate according to some example embodiments of the present disclosure.

[0141] For example, the light emitting device can be an organic light emitting diode, which can include a first electrode, an organic light emitting layer, and a second electrode disposed on a substrate 10, wherein the first electrode can be one of an anode and a cathode, and the second electrode can be the other of the anode and the cathode. The first electrode, the organic light emitting layer, and the second electrode can be disposed in sequence away from the substrate 10.

[0142] As shown in Figure 13 , the first electrode 80 can include an electrode body portion 801 and an electrode connection portion 802. In Figure 13 the embodiment shown, the electrode body portion 801 can have a substantially rectangular shape, i.e., a normal projection of the electrode body portion 801 on the substrate 10 is substantially rectangular. However, embodiments of the present disclosure are not limited thereto, and the electrode body portion 801 can have any suitable shape, e.g., a hexagonal shape, an octagonal shape, etc.

[0143] The electrode body portion 801 and the electrode connection portion 802 can be connected into one body. The electrode connection portion 802 is electrically connected with one end of the third conductive member 403 through the via hole VAH14. As described above, the other end of the third conductive member 403 is electrically connected with the drain of the sixth transistor T6 and the source of the seventh transistor T7 through the via hole VAH13. In this way, the first electrode 80 is electrically connected with the drain of the sixth transistor T6 and the source of the seventh transistor T7.

[0144] For example, a normal projection of the first electrode 80 on the substrate 10 covers at least a normal projection of the active layer 20a of the first transistor T1 on the substrate 10. The normal projection of the first electrode 80 on the substrate 10 is spaced apart from a normal projection of the active layer 20b of the second transistor T2 on the substrate 10.

[0145] In combination with reference to Figure 14 and Figure 16 , the display substrate further includes a pixel definition layer PDL disposed on a side of the first electrode 80 away from the substrate 10, the pixel definition layer PDL including an opening 803 exposing at least a portion of the first electrode 80. For example, in Figure 14In the illustrated embodiment, the opening 803 has a hexagonal shape, that is, the orthographic projection of the opening 803 onto the substrate 10 is hexagonal. However, the embodiments of this disclosure are not limited thereto, and the opening 803 may have any suitable shape, such as rectangular, octagonal, etc.

[0146] Combined with reference Figure 15 and Figure 16 The display substrate further includes spacers PS disposed on the side of the pixel defining layer PDL away from the substrate 10. For example, in Figure 15 In the illustrated embodiment, the spacer PS has a rectangular shape, that is, the orthographic projection of the spacer PS onto the substrate 10 is rectangular. However, the embodiments of this disclosure are not limited thereto, and the spacer PS can have any suitable shape, such as circular.

[0147] For example, the orthographic projection of the spacer PS on the substrate 10 at least partially overlaps with the orthographic projection of the active layer 20b of the second transistor T2 on the substrate 10.

[0148] In some embodiments of this disclosure, the display substrate may be a flexible display substrate.

[0149] Figure 17 This is a schematic diagram of a flexible display substrate in a folded state according to an exemplary embodiment of the present disclosure. Figure 18 It shows Figure 17 A cross-sectional view along the X direction of the flexible display substrate. Please refer to the attached document. Figure 17 and Figure 18 The flexible display substrate includes a display area (AA), a pad area 130, and a bending area 140 located between the display area and the pad area 130. Both the pad area 130 and the bending area 140 are located in a non-display area (NA) outside the display area.

[0150] For example, when the display substrate is a flexible display substrate, the substrate 10 can be an organic flexible substrate formed of, for example, polyimide (PI), polyethylene terephthalate (PET), polycarbonate, polyethylene, polyacrylate, polyetherimide, polyethersulfone, etc.

[0151] For example, the substrate 10 may include a first substrate, a first barrier layer, and a second substrate, with the first barrier layer disposed between the first and second substrates. The first substrate may be formed of polyimide (PI) and have a thickness of about 10 micrometers. The first barrier layer may be formed of silicon oxide and have a thickness of about 6,000 angstroms; or, the first barrier layer may be formed of amorphous silicon and have a thickness of about 40 angstroms. The second substrate may be formed of polyimide (PI) and have a thickness of about 6 micrometers.

[0152] Figure 17 The bending region 140 in the flexible display substrate can be bent around a bending axis (BX). It should be noted that, in this document, the expression "bending axis" is a virtual axis around which the bending region 140 can be bent, rather than referring to an actual bending axis provided in the flexible display substrate.

[0153] For example, in order to facilitate wiring, the bending region 140 is provided on the side of the non-display region of the flexible display substrate along the X direction. In this way, the gate driving circuit can be bound on the side of the non-display region of the flexible display substrate along the Y direction, or the GOA circuit (Gate Driver On Array) can be directly formed on the flexible substrate. The trace 105 is provided in the bending region 140, and is used to electrically connect the GOA circuit to the pixel driving circuit. In the embodiments of the present disclosure, the trace 105 can be various conductive traces used to transmit electrical signals, such as data lines, VSS power lines, VDD power lines, etc., which extend from the display region AA to the non-display region NA.

[0154] In the embodiments of the present disclosure, by providing the bending region, the pad region 130 can be bent to overlap with the display region from the back of the display region, so as to realize a narrow-frame or even a frameless display device.

[0155] For reference Figures 16 to 18 The display substrate includes the trace 105 provided in the bending region 140, and the trace 105 can be located in the fourth conductive layer 70.

[0156] In the following, other film layers (such as insulating layers) of the display substrate according to the embodiments of the present disclosure will be described in combination with Figure 12 and Figure 16

[0157] For example, the second barrier layer 161 can be formed of silicon oxide and has a thickness of about 5500 angstroms. The first buffer layer 162 can be formed of silicon nitride and has a thickness of about 1000 angstroms, or the first buffer layer 162 can be formed of silicon oxide and has a thickness of about 3000 angstroms.

[0158] For example, the second barrier layer 161 can be formed of silicon oxide and has a thickness of about 5500 angstroms. The first buffer layer 162 can be formed of silicon nitride and has a thickness of about 1000 angstroms, or the first buffer layer 162 can be formed of silicon oxide and has a thickness of about 3000 angstroms.

[0159] The display substrate can include a first gate insulating layer GI1 provided between the first semiconductor layer 20 and the first conductive layer 30. For example, the first gate insulating layer GI1 can be formed of silicon oxide and has a thickness of about 1000-2000 angstroms.

[0160] ​The display substrate may include a first interlayer insulating layer ILD1 disposed between the first conductive layer 30 and the second conductive layer 40. For example, the first interlayer insulating layer ILD1 may be formed of silicon nitride and have a thickness of about 1000 to 2000 angstroms.

[0161] The display substrate may include a second buffer layer 163 disposed between the second conductive layer 40 and the second semiconductor layer 50. For example, the second buffer layer 163 may be formed of silicon oxide and have a thickness of about 3,000 to 6,000 angstroms.

[0162] The display substrate may include a second gate insulating layer GI2 disposed between the second semiconductor layer 50 and the third conductive layer 60. For example, the second gate insulating layer GI2 may be formed of silicon oxide and have a thickness of about 1300 angstroms.

[0163] The display substrate may include a second interlayer insulating layer (ILD2) disposed between the third conductive layer 60 and the fourth conductive layer 70. For example, the second interlayer insulating layer (ILD2) may be formed of silicon oxide and have a thickness of about 3000 to 6000 angstroms.

[0164] The display substrate may include a passivation layer PVX disposed on the side of the fourth conductive layer 70 away from the substrate 10, and a planarization layer PLN disposed on the side of the passivation layer PVX away from the substrate 10. For example, the passivation layer PVX may be formed of silicon oxide and have a thickness of about 2000 to 3500 angstroms. The planarization layer PLN may be formed of polyimide (PI) and have a thickness of about 1.5 micrometers.

[0165] like Figure 16 As shown, the display substrate includes a groove 165 located in the bending region 140. The groove 165 is a stepped groove, that is, it includes a first groove portion 1651 and a second groove portion 1652. The orthographic projection of the second groove portion 1652 on the substrate 10 covers the orthographic projection of the first groove portion 1651 on the substrate 10, and the area of ​​the orthographic projection of the second groove portion 1652 on the substrate 10 is greater than the area of ​​the orthographic projection of the first groove portion 1651 on the substrate 10.

[0166] The first recess 1651 penetrates at least the first interlayer insulating layer ILD1, the first gate insulating layer GI1, and the first buffer layer 162 to expose a portion of the substrate 10 in the bending region 140. The second recess 1652 penetrates at least the second buffer layer 163, the second gate insulating layer GI2, the second interlayer insulating layer ILD2, and the passivation layer PVX.

[0167] A portion of the planarization layer PLN is filled in the groove 165. In this way, the substrate 10 and the planarization layer PLN are mainly formed at the bending region 140, which helps to improve the bending performance of the display substrate at this bending region.

[0168] Referring to Figure 16 , the trace 105 is located at the bottom of the groove 165. In embodiments of the present disclosure, a portion of the passivation layer PVX covers the trace 105 to protect the trace 105.

[0169] Figure 19 is a flowchart of a manufacturing method of a display substrate according to some exemplary embodiments of the present disclosure. Figures 20 to 23 and Figure 16 are Figure 19 are schematic diagrams of cross-sectional structures of display substrates formed after some steps of the manufacturing methods shown in Figure 16 and Figures 19 to 23 The manufacturing method of the display substrate can be performed according to the following steps.

[0170] Referring to Figure 20 In step S191, a substrate substrate 10 is prepared. For example, the substrate substrate 10 can be an organic flexible substrate formed of, for example, polyimide (PI), polyethylene terephthalate (PET), polycarbonate, polyethylene, polyacrylate, polyetherimide, polyethersulfone, etc. The substrate substrate 10 can be a single-layer structure or a double-layer structure. For example, the substrate substrate 10 can include a first substrate, a first barrier layer, and a second substrate, the first barrier layer being disposed between the first substrate and the second substrate. The thickness of the substrate substrate 10 is approximately in the range of 5-20 microns. A second barrier layer 161 and a first buffer layer 162 are sequentially prepared on the substrate substrate 10.

[0171] Then, a polysilicon semiconductor silicon island layer, i.e., a first semiconductor layer 20, is prepared on the first buffer layer 162 by using a patterning process.

[0172] A first gate insulating layer GI1 is formed above the first semiconductor layer 20, and a first conductive material layer is deposited, and a gate electrode of the third transistor T3 to the seventh transistor T7 and a first capacitor electrode of the storage capacitor Cst, i.e., the first conductive layer 30, are formed in the first conductive material layer by using a patterning process.

[0173] A first interlayer insulating layer ILD1 is formed above the first conductive layer 30, and a plurality of vias exposing the source region and the drain region of the active layer of the third transistor T3 to the seventh transistor T7 are etched in the first interlayer insulating layer ILD1 by using an etching process.

[0174] Then, a second conductive material layer is deposited over the first interlayer insulating layer ILD1, and a patterning process is used to form the source and drain of the third transistor T3 to the seventh transistor T7, the second capacitor electrode of the storage capacitor Cst, and the bottom gate of the first transistor T1 and the second transistor T2, i.e., the second conductive layer 40 is formed. Thus, the source and drain of the third transistor T3 to the seventh transistor T7, the second capacitor electrode of the storage capacitor Cst, and the bottom gate of the first transistor T1 and the second transistor T2 are formed by one patterning process, which is advantageous to reduce the number of patterning processes and the number of masks.

[0175] Referring to Figure 21 In step S192, a second buffer layer 163 is formed over the second conductive layer 40.

[0176] An oxide semiconductor silicon island layer, i.e., the second semiconductor layer 50, is prepared on the second buffer layer 163 by a patterning process. A second gate insulating layer GI2 is formed over the second semiconductor layer 50, and a third conductive material layer is deposited, and a patterning process is used to form the top gate of the first transistor T1 and the second transistor T2 in the third conductive material layer, i.e., the third conductive layer 60 is formed.

[0177] A second interlayer insulating layer ILD2 is formed over the third conductive layer 60, and a plurality of vias are formed in the second interlayer insulating layer ILD2 by a patterning process, the plurality of vias expose the source and drain of the third transistor T3 to the seventh transistor T7, and expose the source region and the drain region of the active layer of the first transistor T1 and the second transistor T2; and the patterning process can also form a first groove portion 1651 in the second interlayer insulating layer ILD2. The first groove portion 1651 is located in the bending region 140, and the first groove portion 1651 at least penetrates the first interlayer insulating layer ILD1, the first gate insulating layer GI1 and the first buffer layer 162 to expose a portion of the substrate 10 in the bending region 140.

[0178] Referring to Figure 22 In step S193, a second groove portion 1652 is formed in the bending region 140 by an etching process. The second groove portion 1652 at least penetrates the second buffer layer 163 and the second interlayer insulating layer ILD2. The orthographic projection of the second groove portion 1652 on the substrate 10 covers the orthographic projection of the first groove portion 1651 on the substrate 10, and the area of the orthographic projection of the second groove portion 1652 on the substrate 10 is greater than the area of the orthographic projection of the first groove portion 1651 on the substrate 10. In this way, a stepped groove 165 is formed in the bending region 140.

[0179] Referring to Figure 23In step S194, a fourth conductive material layer is formed over the second interlayer insulating layer ILD2 and at the bottom of the recess 165, and a patterning process is performed on the fourth conductive material layer to form the fourth conductive layer 70, which includes the first conductive part 701, the second conductive part 702, the third conductive part 703, and the fourth conductive part 704, and further includes the trace 105 at the bottom of the recess 165.

[0180] Then, a passivation layer PVX is deposited, which covers the fourth conductive layer 70. A planarization layer PLN is coated over the passivation layer PVX.

[0181] Referring to Figure 16 In step S195, a first electrode 80, a pixel defining layer PDL, and a spacer PS are sequentially prepared over the planarization layer PLN.

[0182] At least some embodiments of the present disclosure further provide a display panel including the display substrate as described above. For example, the display panel can be an OLED display panel.

[0183] Referring to Figure 1 At least some embodiments of the present disclosure further provide a display device. The display device can include the display substrate as described above.

[0184] The display device can include any device or product having a display function. For example, the display device can be a smart phone, a mobile phone, an e-book reader, a desktop PC (personal computer), a laptop PC, a netbook PC, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital audio player, a mobile medical device, a camera, a wearable device (e.g., a head-mounted device, electronic clothing, an electronic bracelet, an electronic necklace, electronic accessories, an electronic tattoo, or a smart watch), a television, etc.

[0185] It should be understood that the display panel and the display device according to embodiments of the present disclosure have all the features and advantages of the display substrate described above, and specific descriptions thereof can be found in the foregoing description, which will not be repeated here.

[0186] Although some embodiments of the general inventive concept have been shown and described, it will be understood by those having ordinary skill in the art that changes can be made in these embodiments without departing from the principles and spirit of the general inventive concept, the scope of which is defined by the claims and their equivalents.

Claims

1. A display substrate, wherein, The display substrate comprises: a substrate substrate; a first semiconductor layer disposed on the substrate substrate; and a second semiconductor layer disposed on a side of the first semiconductor layer away from the substrate substrate, wherein the display substrate further comprises a plurality of thin film transistors disposed on the substrate substrate, the plurality of thin film transistors comprising at least a first transistor and a third transistor, each of the plurality of thin film transistors comprises an active layer, the active layer of the first transistor comprises an oxide semiconductor material, the active layer of the third transistor comprises a polysilicon semiconductor material, the active layer of the third transistor is located in the first semiconductor layer, and the active layer of the first transistor is located in the second semiconductor layer; the first transistor comprises a first bottom gate and a first top gate, the first bottom gate is located between the substrate substrate and the active layer of the first transistor, the first top gate is located on a side of the active layer of the first transistor away from the substrate substrate, and the projections of any two of the active layer of the first transistor, the first bottom gate and the first top gate on the substrate substrate at least partially overlap with each other; the display substrate comprises a first conductive layer and a second conductive layer disposed on the substrate substrate, the first conductive layer is located on a side of the first semiconductor layer away from the substrate substrate, and the second conductive layer is located between the first conductive layer and the second semiconductor layer; the third transistor comprises a gate, a source and a drain, the gate of the third transistor is located in the first conductive layer, and the source and the drain of the third transistor are located in the second conductive layer; and the first bottom gate is located in the second conductive layer; the display substrate comprises a first bottom gate structure located in the second conductive layer, the first bottom gate structure comprises a first bottom gate main body portion and a first bottom gate extension portion, the projection of the first bottom gate main body portion on the substrate substrate at least partially overlaps with the projection of the active layer of the first transistor on the substrate substrate, and the first bottom gate comprises a portion overlapping with the active layer of the first transistor; the display substrate further comprises a data line for transmitting a data signal, the data line extends in a first direction on the substrate substrate, and the first bottom gate extension portion extends in the first direction.

2. The display substrate of claim 1, wherein the display substrate further comprises a second transistor, the second transistor comprises a second bottom gate and a second top gate, the second bottom gate is located between the substrate substrate and the active layer of the second transistor, the second top gate is located on a side of the active layer of the second transistor away from the substrate substrate, and the projections of any two of the active layer of the second transistor, the second bottom gate and the second top gate on the substrate substrate at least partially overlap with each other, the active layer in the second transistor comprises an oxide semiconductor material, and the active layer in the second transistor is located in the second semiconductor layer, and the second bottom gate is located in the second conductive layer. 3.The display substrate of claim 1, wherein, The display substrate includes a storage capacitor including a first capacitor electrode and a second capacitor electrode provided to the substrate substrate, a projection of the first capacitor electrode on the substrate substrate at least partially overlaps with a projection of the second capacitor electrode on the substrate substrate; and The second capacitor electrode is located in the second conductive layer, and the first capacitor electrode is located in the first conductive layer.

4. The display substrate of claim 2, wherein The display substrate includes a second bottom gate structure located in the second conductive layer, the second bottom gate structure includes a second bottom gate main body portion and a second bottom gate extension portion, a projection of the second bottom gate main body portion on the substrate substrate at least partially overlaps with a projection of the active layer of the second transistor on the substrate substrate, and the second bottom gate includes a portion in which the second bottom gate main body portion overlaps with the active layer of the second transistor. 5.The display substrate of claim 4, wherein, The second bottom gate extension portion extends along the first direction; and at least one of the active layer of the first transistor and the active layer of the second transistor extends along the first direction. 6.The display substrate of any one of claims 2, 4 or 5, wherein, The display substrate includes a third conductive layer located on a side of the second semiconductor layer away from the substrate substrate, The display substrate includes a first top gate structure located in the third conductive layer, the first top gate structure extends along a second direction, and the second direction intersects the first direction; The first top gate structure includes a first widened portion, a dimension of the first widened portion along the first direction is greater than a dimension of a remaining portion of the first top gate structure along the first direction; and A projection of the first widened portion on the substrate substrate at least partially overlaps with a projection of the active layer of the first transistor on the substrate substrate, and the first top gate includes a portion in which the first widened portion overlaps with the active layer of the first transistor. 7.The display substrate of claim 6, wherein, The display substrate includes a second top gate structure located in the third conductive layer, the second top gate structure extends along the second direction; The second top gate structure includes a second widened portion, a dimension of the second widened portion along the first direction is greater than a dimension of a remaining portion of the second top gate structure along the first direction; and A projection of the second widened portion on the substrate substrate at least partially overlaps with a projection of the active layer of the second transistor on the substrate substrate, and the second top gate includes a portion in which the second widened portion overlaps with the active layer of the second transistor. 8.The display substrate of claim 7, wherein, The first widened portion protrudes to both sides relative to the remaining portion of the first top gate structure along the first direction; and / or The second widened portion protrudes to both sides relative to the remaining portion of the second top gate structure along the first direction. 9.The display substrate of claim 6, wherein, The display substrate includes a fourth conductive layer located on a side of the third conductive layer away from the substrate substrate; The first transistor includes a first source and a first drain, and the second transistor includes a second source and a second drain, and the first source, the first drain, the second source, and the second drain are all located in the fourth conductive layer. 10.The display substrate of claim 9, wherein, The display substrate comprises an initialization voltage line on the third conductive layer, the initialization voltage line being configured to transmit an initialization voltage signal; and The display substrate further comprises a first conductive component on the fourth conductive layer, one end of the first conductive component being electrically connected to the active layer of the first transistor through a first via, and a part of the first conductive component being further electrically connected to the initialization voltage line through a second via. 11.The display substrate of claim 10, wherein, The display substrate further comprises a second conductive component and a third conductive component on the fourth conductive layer, one end of the second conductive component being electrically connected to the active layer of the second transistor through a third via, the other end of the second conductive component being electrically connected to the active layer of the first transistor and one end of the third conductive component through a fourth via; and The display substrate comprises a storage capacitor, the storage capacitor comprising a first capacitor electrode and a second capacitor electrode disposed on the substrate, a projection of the first capacitor electrode on the substrate and a projection of the second capacitor electrode on the substrate at least partially overlap, the first capacitor electrode is located on the first conductive layer, the other end of the third conductive component is electrically connected to the gate of the third transistor and the first capacitor electrode through a fifth via. 12.The display substrate of claim 11, wherein, The display substrate further comprises a light emitting device disposed on the substrate, the light emitting device comprising at least a first electrode, the first electrode being located on the fourth conductive layer away from the substrate; And A projection of the first electrode on the substrate and a projection of the active layer of the first transistor on the substrate at least partially overlap. 13.The display substrate of claim 12, wherein, A projection of the first electrode on the substrate and a projection of the active layer of the second transistor on the substrate are arranged at intervals. 14.The display substrate of claim 13, wherein, The display substrate further comprises a pixel definition layer and a spacer disposed on the substrate, the pixel definition layer comprising an opening, the opening exposing at least a part of the first electrode, the spacer being located on the pixel definition layer away from the substrate; And A projection of the spacer on the substrate and a projection of the active layer of the second transistor on the substrate at least partially overlap. 15.The display substrate of claim 14, wherein, The display substrate comprises a first buffer layer between the substrate and the first semiconductor layer, the first buffer layer comprising silicon oxide or silicon nitride; and / or, The display substrate comprises a first gate insulating layer between the first semiconductor layer and the first conductive layer, the first gate insulating layer comprising silicon oxide; and / or, The display substrate comprises a second buffer layer between the second conductive layer and the second semiconductor layer, the second buffer layer comprising silicon oxide; and / or, The display substrate comprises a second gate insulating layer between the second semiconductor layer and the third conductive layer, the second gate insulating layer comprising silicon oxide. 16.The display substrate of claim 15, wherein, The display substrate is a flexible display substrate that can be bent, the flexible display substrate comprising a display area and a bending area; and The display substrate further comprises a groove in the bending area, the groove exposing at least a portion of the substrate in the bending area. 17.The display substrate of claim 16, wherein, The display substrate further comprises a trace in the bending area, the trace being on the fourth conductive layer, and the trace being on the bottom of the groove. 18.The display substrate of claim 17, wherein, The display substrate further comprises a passivation layer on a side of the fourth conductive layer away from the substrate, at least a portion of the passivation layer covering the trace; and The display substrate further comprises a planarization layer on a side of the passivation layer away from the substrate, the planarization layer filling in the groove.

19. A display panel comprising the display substrate according to any one of claims 1-18.

20. A display device comprising the display substrate according to any one of claims 1-18 or the display panel according to claim 19.

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