Level shift circuit, control method thereof, and drive circuit

Abstract

The application provides a level shifting circuit and a control method thereof, and a driving circuit, and relates to the technical field of level shifting. The level shifting circuit comprises a first input end, a first output end, an alternating current (AC) coupling sub-circuit and a positive feedback sub-circuit. The AC coupling sub-circuit comprises a first coupling input end and a first coupling output end. The first coupling input end is connected with the first input end, and the first coupling output end is connected with a first node. The AC coupling sub-circuit is used for AC coupling a signal at the first coupling input end to the first coupling output end. The positive feedback sub-circuit comprises a first feedback input end and a first feedback output end. The first feedback input end and the first feedback output end are both connected with the first node. The first node is connected with the first output end. The level shifting circuit can be applied to level shifting of a full frequency band or a wide frequency band.

Description

Technical Field

[0001] This application relates to the field of level shifting technology, and in particular to a level shifting circuit and its control method and driving circuit. Background Technology

[0002] The driver circuit (DC), also known as the IC driver circuit, is an important module that determines the performance of the transmitting circuit. It is widely used in various signal transmission systems such as display, monitoring, and audio. With the increase in high-speed data transmission services, the requirements for IC driver circuits are also getting higher and higher.

[0003] Existing IC driver circuits include internal circuits, level shifting circuits, and output circuits. The internal circuits typically use faster, lower-parasitic-capacitance core transistors (core MOSFETs) for internal data processing. Since core MOSFETs are not resistant to high voltage, the internal circuits operate in a low-voltage domain. However, the output circuits, to achieve large output amplitudes or adjustable common-mode voltage (supporting multiple protocols), need to operate in a high-voltage domain. Therefore, level shifting circuits are required to shift the low-voltage signal output from the internal circuits to a suitable voltage domain before inputting it to the output circuit. This ensures that the core MOSFETs in the output circuit do not overvoltage, or that the input / output transistors (IO MOSFETs) operate in an appropriate voltage domain.

[0004] However, existing level shifting circuits focus on level shifting of low-frequency or high-frequency signals and cannot perform level shifting of full-band or wide-band signals, which limits the application of IC driver circuits. Summary of the Invention

[0005] This application provides a level shifting circuit and its control method and driving circuit, which can be applied to level shifting in the full frequency band or wide frequency band.

[0006] This application provides a level shifting circuit, including a first input terminal, a first output terminal, an AC coupling sub-circuit, and a positive feedback sub-circuit. The AC coupling sub-circuit includes a first coupling input terminal and a first coupling output terminal. The first coupling input terminal is connected to the first input terminal, and the first coupling output terminal is connected to a first node. The AC coupling sub-circuit is used to AC couple the signal from the first coupling input terminal to the first coupling output terminal. The positive feedback sub-circuit includes a first feedback input terminal and a first feedback output terminal. Both the first feedback input terminal and the first feedback output terminal are connected to the first node. The first node is connected to the first output terminal.

[0007] The level shifting circuit of this application uses an AC coupling sub-circuit to AC couple the signal input at the first input terminal to the first node. The positive feedback sub-circuit, through positive feedback from the first feedback input terminal to the first feedback output terminal, provides common-mode and differential-mode voltages to the first node. This allows the transmission of AC signals (high-frequency signals) via the AC coupling sub-circuit and the stabilization of DC signals (low-frequency signals) via the positive feedback sub-circuit. In other words, level shifting can be achieved regardless of whether the signal input at the first input terminal is AC or DC. Furthermore, the combination of the AC coupling sub-circuit and the positive feedback sub-circuit in this application enables the level shifting circuit to support higher frequencies while reducing circuit complexity.

[0008] In some possible implementations, the level shifting circuit further includes a second input terminal and a second output terminal; the AC coupling sub-circuit further includes a second coupling input terminal and a second coupling output terminal; the second coupling input terminal is connected to the second input terminal, and the second coupling output terminal is connected to a second node; the AC coupling sub-circuit is also used to AC couple the signal from the second coupling input terminal to the second coupling output terminal; the positive feedback sub-circuit further includes a second feedback input terminal and a second feedback output terminal; wherein both the second feedback input terminal and the second feedback output terminal are connected to the second node; the second node is connected to the second output terminal. In this case, the level shifting circuit can simultaneously perform level shifting on a set of signals input from the first input terminal and the second input terminal; for example, level shifting of a set of differential signals.

[0009] In some possible implementations, the AC coupling sub-circuit includes a first capacitor; the first terminal of the first capacitor is connected to the first coupling input terminal, and the second terminal of the first capacitor is connected to the first coupling output terminal.

[0010] This AC coupling sub-circuit utilizes the characteristic of the first capacitor to pass AC while blocking DC, AC coupling the input signal at the first coupling input terminal to the first coupling output terminal, and also blocking the DC signal input at the first input terminal.

[0011] In some possible implementations, the positive feedback sub-circuit includes a first resistor, a second resistor, a first transistor, a second transistor, and a current source; one end of the first resistor is connected to a first voltage terminal, and the other end of the first resistor is connected to a control node; the gate of the first transistor is connected to the first feedback input terminal, the first electrode of the first transistor is connected to the control node, and the second electrode of the first transistor is connected to the second voltage terminal through the current source; one end of the second resistor is connected to the first voltage terminal, and the other end of the second resistor is connected to the first feedback output terminal; the gate of the second transistor is connected to the control node, the first electrode of the second transistor is connected to the first feedback output terminal, and the second electrode of the second transistor is connected to the second voltage terminal through the current source.

[0012] In this scenario, when a high level is input to the first feedback input terminal, the first transistor is turned on, the control node is at a low level, and the second transistor is turned off. At this time, the voltage at the first feedback output terminal is equal to the voltage at the first voltage terminal. When a low level is input to the first feedback input terminal, the first transistor is turned off, the control node is at a high level, the second transistor is turned on, and the voltage at the first feedback output terminal is equal to the voltage at the first voltage terminal minus the voltage division of the second resistor. In this way, during the DC phase, the positive feedback from the first feedback output terminal to the first feedback input terminal can lock the first node at a fixed level.

[0013] In some possible implementations, the first resistor and the second resistor have the same resistance value. This ensures that the rate at which the first node transitions from low to high and from high to low is equal, thereby optimizing the eye diagram of the output signal at the first signal output terminal.

[0014] In some possible implementations, the AC coupling sub-circuit includes a second capacitor; the first terminal of the second capacitor is connected to the second coupling input terminal, and the second terminal of the second capacitor is connected to the second coupling output terminal.

[0015] This AC coupling sub-circuit utilizes the characteristic of the second capacitor to pass AC while blocking DC, AC coupling the input signal at the second coupling input terminal to the second coupling output terminal, and also blocking the DC signal input at the second input terminal.

[0016] In some possible implementations, the positive feedback sub-circuit includes a first resistor, a second resistor, a first transistor, a second transistor, and a current source; one end of the first resistor is connected to a first voltage terminal, and the other end of the first resistor is connected to the second feedback output terminal; the gate of the first transistor is connected to the first feedback input terminal, the first electrode of the first transistor is connected to the second feedback output terminal, and the second electrode of the first transistor is connected to the second voltage terminal through the current source; one end of the second resistor is connected to the first voltage terminal, and the other end of the second resistor is connected to the first feedback output terminal; the gate of the second transistor is connected to the second feedback input terminal, the first electrode of the second transistor is connected to the first feedback output terminal, and the second electrode of the second transistor is connected to the second voltage terminal through the current source.

[0017] In this scenario, when the first feedback input is high, the second feedback input is low, the first transistor is turned on, the second transistor is turned off, and the voltage at the first feedback output equals the voltage at the first voltage terminal, while the voltage at the second feedback output equals the voltage at the first voltage terminal minus the voltage division of the second resistor. Conversely, when the first feedback input is low, the second feedback input is high, the first transistor is turned off, the second transistor is turned on, and the voltage at the first feedback output equals the voltage at the first voltage terminal minus the voltage division of the first resistor, while the voltage at the second feedback output equals the voltage at the first voltage terminal. Thus, during the DC phase, the positive feedback from the first feedback output to the first feedback input locks the first node and the second node at a fixed level.

[0018] In some possible implementations, both the first transistor and the second transistor are N-type transistors; the voltage at the first voltage terminal is greater than the voltage at the second voltage terminal; or, both the first transistor and the second transistor are P-type transistors; the voltage at the second voltage terminal is greater than the voltage at the first voltage terminal.

[0019] In some possible implementations, the signals input to the first input terminal and the second input terminal are a set of differential signals.

[0020] In some possible implementations, the first capacitor and the second capacitor have the same capacitance. This ensures that the signals input to the first and second input terminals have the same AC differential amplitude after level shifting.

[0021] In some possible implementations, the first resistor and the second resistor have the same resistance value. This ensures that, on the one hand, the rates at which the first node transitions from low to high and from high to low are equal, and the rates at which the second node transitions from low to high and from high to low are equal, thereby optimizing the eye diagrams of the output signals at the first and second signal output terminals. On the other hand, it also ensures that the signals input to the first and second input terminals (e.g., a set of differential signals) have the same DC differential amplitude after level shifting.

[0022] This application embodiment also provides a control method for any of the aforementioned level shifting circuits, comprising: inputting a first input data signal to a first input terminal to output a first output data signal through the first output terminal; wherein the first data signal is in a first voltage domain, the first output data signal is in a second voltage domain, and the second voltage domain is different from the first voltage domain.

[0023] In some possible implementations, the control method further includes: while inputting the first input data signal to the first input terminal and outputting the first output data signal through the first output terminal, inputting the second input data signal to the second input terminal, so as to output the second output data signal through the second output terminal respectively; wherein the second input data signal is in a third voltage domain and the second output data signal is in a fourth voltage domain; the fourth voltage domain is different from the third voltage domain.

[0024] In some possible implementations, the third voltage domain and the first voltage domain are the same voltage domain; the fourth voltage domain and the second voltage domain are the same voltage domain.

[0025] This application embodiment also provides a driving circuit, including an internal circuit, an output circuit, and any of the aforementioned level shifting circuits; the first input terminal of the level shifting circuit is connected to the first output terminal of the internal circuit, and the first output terminal of the level shifting circuit is connected to the first input terminal of the output circuit.

[0026] In some possible implementations, the second input terminal of the level shifting circuit is connected to the second output terminal of the internal circuit, and the second output terminal of the level shifting circuit is connected to the second input terminal of the output circuit.

[0027] This application also provides an electronic device, including any of the aforementioned driving circuits. Attached Figure Description

[0028] Figure 1 This is a schematic diagram of a level shifting circuit provided in an embodiment of this application;

[0029] Figure 2 This is a schematic diagram of a positive feedback sub-circuit provided in an embodiment of this application;

[0030] Figure 3 This is a schematic diagram of a level shifting circuit provided in an embodiment of this application;

[0031] Figure 4 This is a schematic diagram of a positive feedback sub-circuit provided in an embodiment of this application;

[0032] Figure 5 This is a schematic diagram of a level shifting circuit provided in an embodiment of this application;

[0033] Figure 6 This is a schematic diagram of a positive feedback sub-circuit provided in an embodiment of this application;

[0034] Figure 7 This application provides a schematic diagram of a level shifting signal.

[0035] Figure 8 This is a schematic diagram of a driving circuit provided in an embodiment of this application;

[0036] Figure 9 This is a schematic diagram of a driving circuit provided in an embodiment of this application;

[0037] Figure 10 A schematic diagram of an internal circuit provided in an embodiment of this application;

[0038] Figure 11 for Figure 10 The timing control diagram of the internal circuitry;

[0039] Figure 12 This is a schematic diagram of an output circuit provided in an embodiment of this application. Detailed Implementation

[0040] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0041] The terms "first," "second," etc., used in the specification, embodiments, claims, and drawings of this application are for distinguishing purposes only and should not be construed as indicating or implying relative importance or order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, such as including a series of steps or units. Methods and circuits are not necessarily limited to those steps or circuits explicitly listed, but may include other steps or circuits not explicitly listed or inherent to these processes, methods, or circuits.

[0042] This application provides a level shifting circuit, such as... Figure 1 As shown, the level shifting circuit 2 includes a first input terminal IN1, a first output terminal OUT1, an AC coupling sub-circuit 10, and a positive feedback sub-circuit 20.

[0043] like Figure 1 As shown, the AC coupling sub-circuit 10 includes a first coupling input terminal a1 and a first coupling output terminal b1. The first coupling input terminal a1 is connected to the first input terminal IN1, and the first coupling output terminal b1 is connected to the first node N1. This AC coupling sub-circuit 10 is used to AC couple the signal input to the first coupling input terminal a1 (i.e., the first input terminal IN1) to the first coupling output terminal b1 (also known as the first node N1).

[0044] like Figure 1 As shown, the positive feedback sub-circuit 20 includes a first feedback input terminal c1 and a first feedback output terminal d1. Both the first feedback input terminal c1 and the first feedback output terminal d1 are connected to the first node N1; the first node N1 is connected to the first output terminal OUT1. This positive feedback sub-circuit 20 sends the output signal (i.e., the feedback signal) from the first feedback output terminal d1 back to the first feedback input terminal c1. Through the combined action of this feedback signal and the original input signal from the first feedback input terminal c1, it provides a first common-mode voltage and a first differential-mode voltage to the first node N1.

[0045] Regarding the first feedback input terminal c1, the first feedback output terminal d1, and the first output terminal OUT1, all connected to the first node N1, it can be understood that they have the same potential. It can also be understood that a node in the circuit is the intersection of three or more branches, and multiple nodes directly connected by wires can be equivalently considered as one node. In this case, the first node N1 is an equivalent node in the circuit, and is not necessarily a single node; it can also be multiple nodes. For example, ... Figure 1 As shown, the first feedback input terminal c1 and the first feedback output terminal d1 are connected to the same node, and are connected to the first output terminal OUT1 through another node; for example, as Figure 3 As shown, the first feedback input terminal c1 and the first feedback output terminal d1 are connected to different nodes, and both of these nodes are connected to the first output terminal OUT1; for example, the first feedback input terminal c1, the first feedback output terminal d1, and the first output terminal OUT1 are directly connected to the same node; the aforementioned connection methods can all be considered equivalent connection methods. In actual process design, settings can be made according to requirements, similarly to the second node N2 in the following text (reference). Figure 3 (This will not be elaborated upon here.)

[0046] In summary, the level shifting circuit of this application uses an AC coupling sub-circuit to AC couple the signal input at the first input terminal to the first node. The positive feedback sub-circuit, through positive feedback from the first feedback input terminal to the first feedback output terminal, provides common-mode and differential-mode voltages to the first node. This allows the transmission of AC signals (high-frequency signals) via the AC coupling sub-circuit and the stabilization of DC signals (low-frequency signals) via the positive feedback sub-circuit. In other words, regardless of whether the signal input at the first input terminal is AC or DC, level shifting can be achieved. Furthermore, the combination of the AC coupling sub-circuit and the positive feedback sub-circuit in this application enables the level shifting circuit to support higher frequencies while reducing circuit complexity.

[0047] As illustrated, when a DC signal is input to the first input terminal, the AC coupling sub-circuit blocks the DC signal. The positive feedback sub-circuit provides the first node with DC common-mode voltage and DC differential-mode voltage for level shifting. The first output terminal maintains the DC voltage, which corresponds to maintaining a long 0 or long 1 signal level in non-DC equalized signal transmission. When an AC signal is input to the first input terminal, the AC signal is output to the first node through the AC coupling sub-circuit. The positive feedback sub-circuit provides the first node with AC common-mode voltage for level shifting and outputs the signal through the first output terminal.

[0048] The following is a schematic diagram of a level shifting circuit that uses a single-ended input and a single-ended output; that is, the level shifting circuit includes an input terminal (IN1) and an output terminal (OUT1).

[0049] In some possible implementations, such as Figure 1 As shown, the AC coupling sub-circuit 10 may include a first capacitor C1. The first terminal of the first capacitor C1 is connected to the first coupling input terminal a1, and the second terminal of the first capacitor C1 is connected to the first coupling output terminal b1. Indicatively, the first capacitor C1 may be a single capacitor, or it may be composed of multiple capacitors connected in series or parallel; this application does not impose specific limitations in this regard.

[0050] It is understandable that the first capacitor C1 has the characteristic of passing AC and blocking DC. Therefore, under the action of the first capacitor C1, the signal input to the first input terminal N1 can be AC ​​coupled. That is to say, the first capacitor C1 can couple the AC signal input to the first input terminal N1 to the first node N1, while blocking the DC signal input to the first input terminal N1.

[0051] In some possible implementations, the AC coupling sub-circuit 10 can be an electromagnetic induction coupling circuit, which AC couples the signal input at the first coupling input terminal a1 to the first coupling output terminal b1. This application does not limit the specific configuration of the electromagnetic induction coupling circuit, and the configuration can be selected as needed in practice.

[0052] In some possible implementations, combining Figure 1 and Figure 2As shown, the positive feedback sub-circuit 20 may include a first resistor R1, a second resistor R2, a first transistor T1, a second transistor T2, and a current source S (e.g., a constant current source). One end of the first resistor R1 is connected to the first voltage terminal AVHH, and the other end is connected to the control node O. The gate of the first transistor T1 is connected to the first feedback input terminal c1, the first electrode of the first transistor T1 is connected to the control node O, and the second electrode of the first transistor T1 is connected to the second voltage terminal AVSS through the current source S. One end of the second resistor R2 is connected to the first voltage terminal AVHH, and the other end is connected to the first feedback output terminal d1. The gate of the second transistor T2 is connected to the control node O, the first electrode of the second transistor T2 is connected to the first feedback output terminal d1, and the second electrode of the second transistor T2 is connected to the second voltage terminal AVSS through the current source S; that is, the first transistor T1 and the second transistor T2 share a common-mode current source S. Indicatively, the first transistor T1 and the second transistor T2 can both be P-type transistors, or both can be N-type transistors; the choice can be made according to actual needs.

[0053] When both the first transistor T1 and the second transistor T2 are N-type transistors (e.g., NMOS transistors), the first terminal of the first transistor T1 and the second terminal of the second transistor T2 are the source and the second terminal is the drain; the voltage at the first voltage terminal AVHH can be a high-level voltage, and the voltage at the second voltage terminal AVSS is a low-level voltage; that is, the voltage at the second voltage terminal AVSS is less than the voltage at the first voltage terminal AVHH. Illustrated, the first voltage terminal AVHH is connected to a high-level voltage terminal, and the second voltage terminal AVSS is connected to ground (i.e., the voltage at the second voltage terminal AVSS is the ground voltage).

[0054] When both the first transistor T1 and the second transistor T2 are P-type transistors (e.g., PMOS transistors), the first terminal of the first transistor T1 and the second terminal of the second transistor T2 are the drain and the second terminal is the source; the voltage at the second voltage terminal can be a high-level voltage, and the voltage at the first voltage terminal is a low-level voltage; that is, the voltage at the second voltage terminal is greater than the voltage at the first voltage terminal. Illustrated, the second voltage terminal is connected to the high-level voltage terminal, and the first voltage terminal is connected to the ground terminal (i.e., the voltage at the first voltage terminal is the ground voltage).

[0055] In some possible implementations, it is possible to set Figure 2The first resistor R1 and the second resistor R2 in the circuit have the same resistance value, which makes the rate at which the first node N1 flips from low level to high level and from high level to low level equal, thereby optimizing the eye diagram of the output signal at the first signal output terminal. It can be understood that an eye diagram is a graph displayed on an oscilloscope showing the accumulated output data signal of the transmitting circuit. The eye diagram can reflect the magnitude of inter-symbol interference and noise, and reflects the overall characteristics of the signal; the quality of the eye diagram is also an important indicator of the performance of the transmitting circuit.

[0056] As an illustration, the following is about Figure 2 The operation of the positive feedback sub-circuit 20 shown in the diagram is illustrated below. Figure 2 Taking the example where the first transistor T1 and the second transistor T2 are both N-type transistors, the current supplied by the current source S is I; R1 = R2 = R.

[0057] When the first feedback input terminal c1 is high, the first transistor T1 is turned on, control node O is at a low level, and the second transistor T2 is turned off. At this time, the voltage at the first feedback output terminal d1 is equal to the voltage V at the first voltage terminal AVHH. AVHH When the first feedback input terminal c1 is low, the first transistor T1 is turned off, control node O is at a high level, the second transistor T2 is turned on, and the voltage at the first feedback output terminal d1 is equal to V. AVHH -IR; where V AVHH This is the voltage at the first voltage terminal AVHH. In this case, during the DC phase, the positive feedback from the first feedback output terminal d1 to the first feedback input terminal c1 can lock the first node N1 at a fixed level (V). AVHH or V AVHH -IR). For information on the potential control of the first node N1 during the AC phase, please refer to subsequent embodiments.

[0058] In some embodiments, in order to simultaneously shift the voltage domains of two signals (e.g., a set of differential signals), such as Figure 3 As shown, the level shifting circuit 2, in addition to including the first input terminal IN1 and the first output terminal OUT1, may also include the second input terminal IN2 and the second output terminal OUT2.

[0059] In this case, such as Figure 3As shown, the AC coupling sub-circuit 10, in addition to the aforementioned first coupling input terminal a1 and first coupling output terminal b1, also includes a second coupling input terminal a2 and a second coupling output terminal b2. The second coupling input terminal a2 is connected to the second input terminal IN2, and the second coupling output terminal b2 is connected to the second node N2. This AC coupling sub-circuit 10 is also used to AC couple the signal input to the second coupling input terminal a2 (i.e., the second input terminal IN2) to the second coupling output terminal b2.

[0060] The positive feedback sub-circuit 20, in addition to the aforementioned first feedback input terminal c1 and first feedback output terminal d1, also includes a second feedback input terminal c2 and a second feedback output terminal d2. Both the second feedback input terminal c2 and the second feedback output terminal d2 are connected to the second node N2; the second node N2 is connected to the second output terminal OUT2. This positive feedback sub-circuit 20 sends the output signal (i.e., the feedback signal) from the second feedback output terminal d2 back to the second feedback input terminal c2. Through the interaction of this feedback signal and the original input signal at the second feedback input terminal c2, a second common-mode voltage and a second differential-mode voltage are provided to the second node N2.

[0061] Of course, in actual manufacturing, the level shifting circuit itself, such as Figure 5 As shown, parasitic capacitances Cp1 and Cp2 will inevitably form at the first node N1 and the second node N2; for example, capacitor plates and wires connected to the first node N1 and the second node N2 will generate parasitic capacitances. Illustrated, in some possible implementations, the capacitances of the two parasitic capacitances Cp1 and Cp2 can be equal, which can be expressed as Cp1 = Cp2.

[0062] The following is a schematic diagram of a level shifting circuit that uses dual-input and dual-output, that is, the level shifting circuit includes two input terminals (IN1, IN2) and two output terminals (OUT1, OUT2).

[0063] For AC-coupled sub-circuit 10:

[0064] In some possible implementations, such as Figure 3 As shown, the AC coupling sub-circuit 10 may include a first capacitor C1 and a second capacitor C2.

[0065] The first terminal of the first capacitor C1 is connected to the first coupling input terminal a1, and the second terminal of the first capacitor C1 is connected to the first coupling output terminal b1. The first terminal of the second capacitor C2 is connected to the second coupling input terminal a2, and the second terminal of the second capacitor C2 is connected to the second coupling output terminal b2. Illustrated, the first capacitor C1 can be a single capacitor, or it can be composed of multiple capacitors connected in series or parallel; the same applies to the second capacitor C2; this application does not impose specific limitations in this regard.

[0066] In some possible implementations, the AC coupling sub-circuit 10 can be an electromagnetic induction coupling circuit; the signal input at the first coupling input terminal a1 is AC coupled and output to the first coupling output terminal b1 through the electromagnetic induction coupling circuit, and the signal input at the second coupling input terminal a2 is AC coupled and output to the second coupling output terminal b2. In this application, the specific configuration structure of the electromagnetic induction coupling circuit is not limited, and the configuration can be selected as needed in practice.

[0067] In some possible implementations, to ensure that the signals input to the first input terminal IN1 and the second input terminal IN2 have the same AC differential amplitude after level shifting, the following settings can be configured: Figure 3 The capacitance of the second capacitor C2 is the same as that of the first capacitor C1, which can be expressed as C1 = C2.

[0068] For the positive feedback sub-circuit 20:

[0069] In some possible implementations, the positive feedback sub-circuit 20 can employ two independently configured feedback circuits (a first feedback circuit and a second feedback circuit); the first feedback circuit (e.g. Figure 2 The first common-mode voltage and the first differential-mode voltage are provided to the first node N1 through the first feedback input terminal C1 and the first feedback output terminal D1, and the second feedback circuit (such as...) Figure 4 The second common-mode voltage and the second differential-mode voltage are provided to the second node N2 through the second feedback input terminal c2 and the second feedback output terminal d2. Among these, regarding... Figure 4 The connection relationships and related working processes of the feedback circuit shown in the diagram can be found in the aforementioned diagram. Figure 2 The description of the feedback circuit will not be repeated here.

[0070] It should be noted that the circuit structures of the two feedback circuits mentioned above can be the same (see reference). Figure 2 and Figure 4 The first common-mode voltage provided by the first feedback circuit to the first node N1 and the second common-mode voltage provided by the second feedback circuit to the second node N2 can be the same or different; similarly, the first differential-mode voltage and the second differential-mode voltage can be the same or different.

[0071] As illustrated, positive feedback sub-circuit 20 respectively adopts Figure 2 and Figure 4Taking the two feedback circuits shown as examples, in actual circuit design, the resistance values ​​of the first resistor R1 and the second resistor R2, the voltage values ​​of the first voltage terminal AVHH and the second voltage terminal AVSS, and the current values ​​of the current source S in the first and second feedback circuits can be set to be the same or different; in practice, the settings can be selected according to the needs.

[0072] In some possible implementations, such as Figure 5 As shown, the positive feedback sub-circuit 20 can be a DC positive feedback differential operational amplifier circuit; the first feedback input terminal c1 is connected to the positive input terminal of the operational amplifier circuit, and the first feedback output terminal d1 is connected to the positive output terminal of the operational amplifier circuit; the second feedback input terminal c2 is connected to the inverting input terminal of the operational amplifier circuit, and the second feedback output terminal d2 is connected to the inverting output terminal of the operational amplifier circuit. It can be understood that the current in the DC positive feedback differential operational amplifier circuit typically originates from a mirror image of a reference current, which is generated by a fixed voltage and resistor.

[0073] As illustrated, in some embodiments, the differential operational amplifier circuit described above can employ current-mode logic (CML) circuitry, i.e., a CML differential operational amplifier circuit. For example... Figure 6 As shown, the CML differential operational amplifier circuit may include a first resistor R1, a second resistor R2, a first transistor T1, a second transistor T2, and a current source S (e.g., a constant current source). One end of the first resistor R1 is connected to the first voltage terminal AVHH, and the other end is connected to the second feedback output terminal d2. The gate of the first transistor T1 is connected to the first feedback input terminal c1, the first electrode of the first transistor T1 is connected to the second feedback output terminal d2, and the second electrode of the first transistor T1 is connected to the second voltage terminal AVSS through the current source S. One end of the second resistor R2 is connected to the first voltage terminal AVHH, and the other end is connected to the first feedback output terminal d1. The gate of the second transistor T2 is connected to the second feedback input terminal c2, the first electrode of the second transistor T2 is connected to the first feedback output terminal d1, and the second electrode of the second transistor T2 is connected to the second voltage terminal AVSS through the current source S; that is, the first transistor T1 and the second transistor T2 share a common-mode current source S.

[0074] As illustrated, the first transistor T1 and the second transistor T2 can both be P-type transistors, or the first transistor T1 and the second transistor can both be N-type transistors. In practice, the choice can be made according to the needs.

[0075] In the case where both the first transistor T1 and the second transistor T2 can be N-type transistors, the first terminal of the first transistor T1 and the second terminal of the second transistor T2 are the source and the second terminal is the drain; the voltage at the first voltage terminal AVHH can be a high-level voltage, and the voltage at the second voltage terminal AVSS can be a low-level voltage (e.g., ground voltage).

[0076] When both the first transistor T1 and the second transistor T2 are P-type transistors (e.g., PMOS transistors), the first terminal of the first transistor T1 and the second transistor T2 are drains and the second terminal is the source; the voltage at the second voltage terminal can be a high-level voltage, and the voltage at the first voltage terminal can be a low-level voltage (e.g., ground voltage).

[0077] In some possible implementations, it is possible to set Figure 6 The resistance values ​​of the first resistor R1 and the second resistor R2 can be the same, or it can be expressed as R1 = R2. In this way, on the one hand, the rate at which the first node N1 flips from low level to high level and from high level to low level are equal, and the rate at which the second node N2 flips from low level to high level and from high level to low level are equal, thereby optimizing the eye diagram of the output signals of the first signal output terminal and the second signal output terminal; on the other hand, it also ensures that the signals (e.g., a set of differential signals) input to the first input terminal IN1 and the second input terminal IN2 have the same DC differential amplitude after level shifting.

[0078] In some possible implementations, it is possible to set Figure 6 The first capacitor C1 and the second capacitor C2 have the same capacitance, which can also be expressed as C1 = C2. In this way, the signals (e.g., a set of differential signals) input to the first input terminal IN1 and the second input terminal IN2 have the same AC differential amplitude after level shifting.

[0079] As an illustration, the following is about Figure 6 The operation of the positive feedback sub-circuit 20 shown in the diagram is illustrated below. Figure 6 Taking the example where the first transistor T1 and the second transistor T2 are both N-type transistors, the current supplied by the current source S is I; R1 = R2 = R. The level shifting circuit receives a set of differential signals (such as...) at its first input terminal N1 and second input terminal N2. Figure 7 (Data_p and Data_n in the original text). In this case, the signals input to the first feedback input terminal c1 and the second feedback input terminal c2 are also a set of differential signals.

[0080] When the first feedback input terminal C1 is high, the second feedback input terminal C2 is low, the first transistor T1 is turned on, the second transistor T2 is turned off, and the voltage at the first feedback output terminal D1 is equal to the voltage V at the first voltage terminal AVHH.AVHH The voltage at the second feedback output terminal d2 is equal to V. AVHH -IR; where V AVHH This is the voltage at the first voltage terminal AVHH. When the first feedback input terminal c1 is low, the second feedback input terminal c2 is high, the first transistor T1 is off, the second transistor T2 is on, and the voltage at the first feedback output terminal d1 is equal to V. AVHH -IR, the voltage at the second feedback output terminal d2 is equal to V. AVHH .

[0081] In this case, during the DC phase, the first node N1 is locked at a fixed level V through the positive feedback from the first feedback output terminal d1 to the first feedback input terminal c1. AVHH -IR (or V) AVHH By using the positive feedback from the second feedback output terminal d2 to the second feedback input terminal c2, the second node N2 is locked at a fixed level V. AVHH (or V) AVHH -IR). The potential control of the first node N1 and the second node N2 during the AC phase is detailed in subsequent embodiments.

[0082] Understandable Figure 6 The differential mode of the CML differential op-amp circuit shown is typically determined by the AC differential mode. The common-mode voltage of the first node N1 and the second node N2 can be adjusted by regulating the power supply voltage of the CML differential op-amp circuit (i.e., the voltage at the first voltage terminal AVHH). Furthermore, using this CML differential op-amp circuit can achieve the goal of narrow bandwidth and low power consumption.

[0083] It should be noted that the above Figure 6 The CML differential operational amplifier circuit with dual-ended inputs (c1, c2) and dual-ended outputs (d1, d2) shown can also be applied to the aforementioned level shifting circuit with single-ended inputs and single-ended outputs. In this case, it is only necessary to connect the first feedback input terminal c1 and the first feedback output terminal d1 to the first node N1, input a fixed level to the second feedback input terminal c2, and the level value can be the common-mode voltage of the CML differential operational amplifier circuit. The second feedback output terminal d2 can be left floating.

[0084] refer to Figure 5 The level shifting circuit includes two input terminals (first input terminal IN1 and second input terminal IN2) and two output terminals (first output terminal OUT1 and second output terminal OUT2). The positive feedback sub-circuit 20 adopts... Figure 6 Taking the CML differential operational amplifier circuit as an example, let C1 = C2 = C AC R1 = R2 = R; the current supplied by current source S is I; the parasitic capacitances of the first node N1 and the second node N2 are Cp1 = Cp2 = CPAR The following is a schematic explanation of the level shifting process of the level shifting circuit, using specific numerical calculations.

[0085] refer to Figure 5 and Figure 7 Let the set of differential signals input to the first input terminal IN1 and the second input terminal IN2 be Data_n and Data_p, and the set of differential signals output to the first output terminal OUT1 and the second output terminal OUT2 be Pre_n and Pre_p; where Data_n and Data_p include the AC stage HF and the DC stage LF.

[0086] refer to Figure 7 The high and low levels of Data_n and Data_p are V respectively. avddl And 0; in this case, the amplitude between the high and low levels of Data_n and Data_p after passing through the first capacitor C1 and the second capacitor C2.

[0087] refer to Figure 7 The positive feedback sub-circuit 20 provides the DC common-mode voltage V to the first node N1 and the second node N2. CM and DC differential voltage V DM They are the same; among them, the DC common-mode voltage V CM =V AVHH -IR / 2: DC differential voltage V DM =IR.

[0088] During the AC phase HF, a set of differential signals (Data_n and Data_p) input from the first input terminal IN1 and the second input terminal IN2 are AC coupled through the AC coupling sub-circuit 10, and then coupled to the DC common-mode voltage V of the positive feedback sub-circuit 20. CM Under the control of the first output terminal OUT1 and the second output terminal OUT2, the signals (Pre_n and Pre_p) are shifted to the AC high level V. ac_vhh and AC low level V ac_vll Among them, the AC high level V ac_vhh =V CM +V AC / 2, AC low level V ac_vll =V CM -V AC / 2.

[0089] In the DC phase LF, the DC common-mode voltage V of the positive feedback sub-circuit 20 is... CM and DC differential voltage V DM Under the combined action of the two output terminals, the signals (Pre_n and Pre_p) controlling the output of the first output terminal OUT1 and the second output terminal OUT2 are shifted to the DC high level V.dc_vhh and DC low level V dc_vll Among them, the DC high level V dc_vhh =V AVHH DC low level V dc_vll =V AVHH -IR.

[0090] In practice, this can be achieved by setting relevant parameters ( Figure 5 The capacitance values ​​of capacitors C1 and C2 Figure 6 The values ​​of resistors R1 and R2, and the voltage at the first voltage terminal AVHH, are used to ensure that the DC differential mode amplitude and the AC differential mode amplitude are similar (i.e., V...). ac_vhh and V dc_vhh Similar, V ac_vll and V dc_vll (Similar), thus ensuring the best effect of data signal level shifting.

[0091] Furthermore, it is understood that the signals (Data_n and Data_p) input to the input terminals (IN1, IN2) of the level shifting circuit of this application, during the DC stage LF, utilize the positive feedback sub-circuit 20 to control the high and low levels of the first node N1 and the second node N2 to reach the high and low levels of the CML differential operational amplifier circuit. This not only solves the transmission of non-DC equalized code stream signals, but also allows for the processing of ultra-low frequency signals.

[0092] In addition, when the level shifting circuit includes two input terminals (first input terminal IN1 and second input terminal IN2) and two output terminals (first output terminal OUT1 and second output terminal OUT2), the first input terminal IN1 and the second input terminal IN2 can input a set of differential signals.

[0093] In this case, in some possible implementations, a level shifting circuit can be used to shift the group of differential signals to different level ranges; for example, one signal in a group of differential signals located between 0 and 1.1V can be shifted to 0 to 1.5V, and the other signal can be shifted to 0 to 1.8V. In some possible implementations, a level shifting circuit can be used to shift the group of differential signals to the same level range (that is, the first output terminal OUT1 and the second output terminal OUT2 also output a group of differential signals); for example, both signals in a group of differential signals located between 0 and 1.1V can be shifted to 0 to 1.5V.

[0094] This application embodiment also provides a control method for any of the aforementioned level shifting circuits, the control method comprising:

[0095] The first input data signal is input to the first input terminal IN1, and the first output data signal is output through the first output terminal OUT1.

[0096] The first data signal is located in the first voltage domain, and the first output data signal is located in the second voltage domain, which is different from the first voltage domain.

[0097] In other words, the first input data signal in the first voltage domain is shifted to the first output data signal in the second voltage domain after passing through the level shifting circuit. For example, the first input data signal in the 0–1.1V range can be shifted to the first output data signal in the 0–1.5V range after passing through the level shifting circuit.

[0098] For a level shifting circuit including a first input terminal IN1, a second input terminal IN2, a first output terminal OUT1, and a second output terminal OUT2, the above control method further includes:

[0099] While inputting the first input data signal to the first input terminal IN1 and outputting the first output data signal through the first output terminal OUT1, the second input data signal can be input to the second input terminal IN2 and output through the second output terminal OUT2; wherein, the second input data signal is in the third voltage domain and the second output data signal is in the fourth voltage domain.

[0100] In other words, the first input data signal in the first voltage domain is shifted to the first output data signal in the second voltage domain after passing through the level shifting circuit, and the second input data signal in the third voltage domain is shifted to the second output data signal in the fourth voltage domain after passing through the level shifting circuit.

[0101] In some possible implementations, the first and third voltage domains can be the same voltage domain, and the second and fourth voltage domains can be the same voltage domain. For example, a set of differential signals (i.e., the first input data signal and the second input data signal) in the same voltage domain (0-1.1V) can be shifted to a set of differential signals (i.e., the first output data signal and the second output data signal) in another voltage domain (0-1.5V) after passing through a level shifting circuit.

[0102] This application also provides a driving circuit, such as... Figure 8 As shown, the driving circuit includes an internal circuit 1, any of the aforementioned level shifting circuits 2, and an output circuit 3. The first input terminal IN1 of the level shifting circuit 2 is connected to the first output terminal of the internal circuit 1, and the first output terminal OUT1 of the level shifting circuit 2 is connected to the first input terminal of the output circuit 3.

[0103] In the case where the level shifting circuit includes two input terminals (first input terminal IN1 and second input terminal IN2) and two output terminals (first output terminal OUT1 and second output terminal OUT2), such as Figure 9As shown, internal circuit 1 includes two output terminals, and output circuit 3 includes two input terminals. The two input terminals (IN1, IN2) of level shifting circuit 2 are respectively connected to the two output terminals of internal circuit, and the two output terminals (OUT1, OUT2) of level shifting circuit are respectively connected to the two input terminals of output circuit 3.

[0104] In the case where the level shifting circuit mentioned above includes two input terminals (IN1, IN2) and two output terminals (OUT1, OUT2), the following schematically provides a specific internal circuit 1 and output circuit 3 (but the internal circuit 1 and output circuit 3 are not limited to this), and the driving process of the driving circuit is illustrated in conjunction with the level shifting circuit 2.

[0105] like Figure 10 The internal circuit 1 shown is a common internal signal processing circuit in serializers (SERDEs), including a core module 11, a frequency divider 12, and a flip-flop 13 (D flip-flop). The core module 11 includes two D flip-flops and a selector; the inputs D of the two D flip-flops are respectively input to two parallel data signals Data (D0, D1), and the outputs Q of the two D flip-flops are connected to the two inputs of the selector; the output of the selector is connected to the input D of the flip-flop 13, and the two outputs Q and QB of the flip-flop 13 are respectively connected to the two inputs (first input IN1 and second input IN2) of the level shifting circuit 2. The high-frequency clock signal CLK is connected to the clock control terminal CK of the flip-flop 13 and the input of the frequency divider 12, and the output of the frequency divider 12 is connected to the clock control terminal CK of the two D flip-flops and the selector in the core module 11.

[0106] like Figure 11 As shown, the clock signal (CLK) at the high-frequency clock signal terminal is divided by a divider 12 to obtain a clock signal (CLK / 2) at half the original frequency. For clarity, the clock signal terminal and its signal are represented by the same symbol in the accompanying diagram and the following text; this should not be interpreted as unclear. In this case, the two D flip-flops in the core module 11 sample the two parallel data signals Data(D0, D1) under the control of the clock signal (CLK / 2), and the two sampled signals are mixed into a single high-frequency data signal by a selector. This high-frequency data signal is then sampled again by flip-flop 13 under the control of the clock signal CLK, and a set of differential signals Data_p and Data_n are output to the first input IN1 and the second input IN2 respectively through the two output terminals Q and QB.

[0107] like Figure 12The output circuit 3 shown is an output stage drive circuit with common-mode feedback, including a first switching transistor S1, a second switching transistor S2, a first matching resistor Ra, a second matching resistor Rb, and a control transistor S3. One end of the first matching resistor Ra is connected to the power supply terminal AVDDRX, and the other end is connected to the first output terminal outp. One end of the second matching resistor Rb is connected to the power supply terminal AVDDRX, and the other end is connected to the second output terminal outn. The gate of the first switching transistor S1 is connected to the first output terminal OUT1 of the level shifting circuit, the source of the first switching transistor S1 is connected to the first output terminal outp, and the drain of the first switching transistor S1 is connected to the source of the control transistor S3. The gate of the second switching transistor S2 is connected to the second output terminal OUT2 of the level shifting circuit, the source of the second switching transistor S2 is connected to the second output terminal outn, and the drain of the second switching transistor S2 is connected to the source of the control transistor S3. The gate of the control transistor S3 is connected to the control terminal V_nbias, and the drain of the control transistor S3 is connected to the ground terminal. A load Rterm can be connected between the first output terminal outp and the second output terminal outn.

[0108] The first switching transistor S1 and the second switching transistor S2 are a switching pair, using N-type input / output transistors (i.e., IO nmos), and the control transistor S3 is an NMOS transistor; the voltage of the power supply terminal AVDDRX exceeds the high voltage withstand voltage of the core MOS.

[0109] use Figure 12 The output circuit 3 with common-mode feedback, although the switching transistors (first switching transistor S1 and second switching transistor S2) of the output stage are IO MOSFETs, can shift the potential of the differential signals Data_p and Data_n output by the internal circuit 1 through the level shifting circuit 2. This not only protects the IO MOSFET from overvoltage, but also ensures that the IO MOSFETs work in a suitable voltage domain to adapt to different output common modes.

[0110] The application of the level shifting circuit in the embodiments of this application includes, but is not limited to, driving circuits. Other circuits that require level shifting can also use the above-mentioned level shifting circuit.

[0111] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A level shifting circuit, characterized in that, It includes a first input terminal, a first output terminal, an AC coupling sub-circuit, and a positive feedback sub-circuit; The AC coupling sub-circuit includes a first coupling input terminal and a first coupling output terminal; wherein, the first coupling input terminal is connected to the first input terminal, and the first coupling output terminal is connected to the first node; The AC coupling sub-circuit is used to AC couple the signal at the first coupling input terminal to the first coupling output terminal; The positive feedback sub-circuit includes a first feedback input terminal and a first feedback output terminal; wherein, both the first feedback input terminal and the first feedback output terminal are connected to the first node; The positive feedback sub-circuit is used to provide the first common-mode voltage and the first differential-mode voltage to the first node; The first node is connected to the first output terminal.

2. The level shifting circuit according to claim 1, characterized in that, The level shifting circuit further includes a second input terminal and a second output terminal; the AC coupling sub-circuit further includes a second coupling input terminal and a second coupling output terminal. The second coupling input terminal is connected to the second input terminal, and the second coupling output terminal is connected to the second node; The AC coupling sub-circuit is also used to AC couple the signal at the second coupling input terminal to the second coupling output terminal; The positive feedback sub-circuit further includes a second feedback input terminal and a second feedback output terminal; wherein, both the second feedback input terminal and the second feedback output terminal are connected to the second node; The second node is connected to the second output terminal.

3. The level shifting circuit according to claim 1 or 2, characterized in that, The AC coupling sub-circuit includes a first capacitor; the first terminal of the first capacitor is connected to the first coupling input terminal, and the second terminal of the first capacitor is connected to the first coupling output terminal.

4. The level shifting circuit according to claim 1 or 2, characterized in that, The positive feedback sub-circuit includes a first resistor, a second resistor, a first transistor, a second transistor, and a current source; One end of the first resistor is connected to the first voltage terminal, and the other end of the first resistor is connected to the control node; The gate of the first transistor is connected to the first feedback input terminal, the first electrode of the first transistor is connected to the control node, and the second electrode of the first transistor is connected to the second voltage terminal through the current source. One end of the second resistor is connected to the first voltage terminal, and the other end of the second resistor is connected to the first feedback output terminal; The gate of the second transistor is connected to the control node, the first terminal of the second transistor is connected to the first feedback output terminal, and the second terminal of the second transistor is connected to the second voltage terminal through the current source.

5. The level shifting circuit according to claim 3, characterized in that, The AC coupling sub-circuit includes a second capacitor; the first terminal of the second capacitor is connected to the second coupling input terminal, and the second terminal of the second capacitor is connected to the second coupling output terminal.

6. The level shifting circuit according to claim 2 or 5, characterized in that, The positive feedback sub-circuit includes a first resistor, a second resistor, a first transistor, a second transistor, and a current source; One end of the first resistor is connected to the first voltage terminal, and the other end of the first resistor is connected to the second feedback output terminal; The gate of the first transistor is connected to the first feedback input terminal, the first electrode of the first transistor is connected to the second feedback output terminal, and the second electrode of the first transistor is connected to the second voltage terminal through the current source. One end of the second resistor is connected to the first voltage terminal, and the other end of the second resistor is connected to the first feedback output terminal; The gate of the second transistor is connected to the second feedback input terminal, the first terminal of the second transistor is connected to the first feedback output terminal, and the second terminal of the second transistor is connected to the second voltage terminal through the current source.

7. The level shifting circuit according to claim 4, characterized in that, Both the first transistor and the second transistor are N-type transistors; the voltage at the first voltage terminal is greater than the voltage at the second voltage terminal; Alternatively, both the first transistor and the second transistor are P-type transistors; the voltage at the second voltage terminal is greater than the voltage at the first voltage terminal.

8. The level shifting circuit according to any one of claims 2, 5, and 7, characterized in that, The signals input to the first input terminal and the second input terminal are a set of differential signals.

9. The level shifting circuit according to claim 5, characterized in that, The first capacitor and the second capacitor have the same capacitance.

10. The level shifting circuit according to claim 4, characterized in that, The first resistor and the second resistor have the same resistance value.

11. A control method for a level shifting circuit as described in any one of claims 1-10, characterized in that, include: The first input data signal is input to the first input terminal, so that the first output data signal is output through the first output terminal; Wherein, the first input data signal is in a first voltage domain, and the first output data signal is in a second voltage domain, which is different from the first voltage domain.

12. The control method for the level shifting circuit according to claim 11, characterized in that, include: While inputting the first input data signal to the first input terminal and outputting the first output data signal through the first output terminal, the second input data signal is input to the second input terminal so that the second output data signal is output through the second output terminal. Wherein, the second input data signal is in the third voltage domain, and the second output data signal is in the fourth voltage domain; the fourth voltage domain is different from the third voltage domain.

13. A driving circuit, characterized in that, Includes internal circuitry, output circuitry, and the level shifting circuitry as described in any one of claims 1-10; The first input terminal of the level shifting circuit is connected to the first output terminal of the internal circuit, and the first output terminal of the level shifting circuit is connected to the first input terminal of the output circuit.

14. The driving circuit according to claim 13, characterized in that, The second input terminal of the level shifting circuit is connected to the second output terminal of the internal circuit, and the second output terminal of the level shifting circuit is connected to the second input terminal of the output circuit.

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