Operational amplifier circuit, analog-to-digital converter and internet of things chip

Abstract

The application discloses an operational amplifier circuit, an analog-to-digital converter and an Internet of Things chip, wherein the operational amplifier circuit comprises an amplifier module and a level shift module; the level shift module comprises a level shift capacitor and a clock controller; the level shift capacitor is connected in series between the differential output end of the amplifier module in the first amplification time of the first amplification of the amplifier module to sample the output voltage of the amplifier module, and is connected in series between the output end of the amplifier module and a load capacitor in the second amplification time of the second amplification to perform secondary amplification after level shifting; and the first amplification of the amplifier module is disconnected before the amplifier module is completely amplified and established, so that the first amplification time is less than the time required for the amplifier module to be completely amplified and established. The circuit of the application can ensure high gain, improve speed and reduce power consumption.

Description

Operational amplifier circuits, analog-to-digital converters, and Internet of Things (IoT) chips Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to an operational amplifier circuit, an analog-to-digital converter, and an Internet of Things (IoT) chip. Background Technology

[0002] Analog-to-digital converters (ADCs) serve as the bridge connecting external physical information and internal digital processing units, acting as the front-end interface for all sensors and IoT systems. Low-power, high-precision ADC circuits are fundamental to improving the integration and miniaturization of IoT circuits. ADCs have three main structures: successive approximation (SAR), Delta-Sigma (DSM), and pipelined. Among these, pipelined ADCs offer high accuracy and speed, making them the mainstream structure for ADCs today. However, the energy efficiency of pipelined ADCs is primarily limited by the gain and bandwidth of the interstage margin amplifiers. Furthermore, with continuous advancements in process technology and the reduction in transistor intrinsic gain, the design difficulty of amplifiers is increasing.

[0003] In existing technologies, correlated level shifting (CLS) is commonly used to improve amplifier gain. Figures 1a-1b show schematic diagrams of amplifier circuits using correlated level shifting, and Figure 1c shows the output voltage of the amplifier in Figure 1a-1b. As shown in Figures 1a-1c, correlated level shifting consists of two stages: a first amplification stage and a second amplification stage (level shifting stage). In the first amplification stage, the amplifier coarsely amplifies the input signal, and the output voltage is sampled and stored by a level shifting capacitor connected in parallel with the load capacitor. In the second amplification stage, the level shifting capacitor is connected in series between the amplifier's output and the feedback loop, and the amplifier performs secondary amplification to obtain an output closer to the ideal value, thus enhancing the amplifier's equivalent gain. However, the equivalent gain of this CLS amplifier is positively correlated with the capacitance value of the level shifting capacitor. Increasing the level shifting capacitor reduces the amplifier's bandwidth, increases the amplifier's response time, and also results in relatively higher power consumption. Summary of the Invention

[0004] This invention provides an operational amplifier circuit, an analog-to-digital converter, and an Internet of Things (IoT) chip, which can overcome the above-mentioned technical problems, enabling the circuit to maintain high gain while improving speed and reducing power consumption.

[0005] This invention provides an operational amplifier circuit, comprising: an amplifier module and a level shifting module. The level shifting module includes a level shifting capacitor and a clock controller. The clock controller controls the level shifting capacitor to be connected across the differential output terminal of the amplifier module during the first amplification time of the first amplification, so as to sample the output voltage of the amplifier module. During the second amplification time of the second amplification, the capacitor is connected in series between the output terminal of the amplifier module and the load capacitor to perform level shifting and secondary amplification. Furthermore, the first amplification of the amplifier module is disconnected before the amplifier module is fully amplified, so that the first amplification time is less than the time required for the amplifier module to be fully amplified.

[0006] The present invention also provides an analog-to-digital converter, comprising: a first-stage ADC, a second-stage ADC, and an interstage margin amplifier, wherein the margin amplifier employs the operational amplifier circuit described above.

[0007] The present invention also provides an Internet of Things (IoT) chip, including the analog-to-digital converter described above.

[0008] This invention shortens the amplifier's amplification time by making the first amplification time shorter than the time required for the amplifier module to fully amplify and establish itself, thereby increasing the speed and reducing the amplifier's power consumption without reducing the gain. At the same time, the calibration loop adaptively and accurately determines the time required for the first amplification, reducing power consumption and achieving infinite equivalent open-loop gain. It also avoids manual adjustment and can automatically adjust and maintain sufficient stability under different temperatures, voltages, and processes. Attached Figure Description

[0009] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 is a simplified schematic diagram of an existing analog-to-digital converter sampling circuit;

[0011] Figure 2 is a schematic diagram of an operational amplifier circuit provided in an embodiment of the present invention;

[0012] Figure 3 is the control timing diagram of the amplifier and shift capacitor in Figure 2;

[0013] Figure 4 is a schematic diagram of the output voltage of the amplifier in Figure 2;

[0014] Figure 5 is a schematic diagram of another operational amplifier circuit provided in an embodiment of the present invention;

[0015] Figure 6 is a schematic diagram of the delay unit in Figure 5;

[0016] Figure 7 is a schematic diagram of an analog-to-digital converter provided in an embodiment of the present invention;

[0017] Figure 8 shows the average noise data test results and spectrum of the capacitor-to-digital converter provided in the embodiment of the present invention.

[0018] Figure 9 is a comparison diagram of the noise efficiency of the capacitor-to-digital converter provided in the embodiment of the present invention with that of the prior art. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0020] As mentioned earlier, in the prior art, a trade-off between the amplifier's gain and bandwidth is required to obtain a suitable amplifier. In order to overcome the trade-off between gain and bandwidth and improve the stability of process, voltage, and temperature (PVT), this invention proposes an incomplete-Settling-based CLS (ISCLS) closed-loop amplifier, which shortens the time of the coarse amplification phase (first amplification) by about ten times, reduces amplifier power consumption while increasing speed, and raises the equivalent gain to over 100dB. Furthermore, by adaptively adjusting the time of the coarse amplification phase through the calibration loop, the stability of the PVT and accurate closed-loop amplification are achieved.

[0021] To make the technical solution of the present invention clearer, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0022] Figure 2 is a schematic diagram of an operational amplifier circuit provided in an embodiment of the present invention, and Figure 3 is a control timing diagram of the amplifier and shift capacitor in Figure 2. As shown in Figures 2 and 3, the red control switch K1 is controlled by φ1, and the blue control switch K2 is controlled by φ2. The operational amplifier circuit in this embodiment includes an amplifier module and a level shifting module. The level shifting module includes a level shifting capacitor C. LSThe clock controller (CLK GEN) controls the level shifting capacitor to be connected across the differential output terminal of the amplifier module during the first amplification time φ1 (Phase 1) of the first amplification, so as to sample the output voltage of the amplifier module. During the second amplification time φ2 (Phase 2) of the second amplification, it is connected in series between the output terminal of the amplifier module and the load capacitor to perform level shifting and secondary amplification. The first amplification of the amplifier module is disconnected before the amplifier module is fully amplified, so that the first amplification time is less than the time required for the amplifier module to be fully amplified.

[0023] In practical applications, to maximize the shared charge during the second amplification time, a cross-connection method is generally used. Other connection methods can also be employed. With the cross-connection method, the level shifting capacitors include identical first and second shifting capacitors. During the first amplification time, both the first and second shifting capacitors are connected across the differential output of the amplifier module. During the second amplification time, the first and second shifting capacitors are connected in series between the output of the amplifier module and the load capacitor, respectively. Specifically, the first shifting capacitor is connected in series between the differential positive output of the amplifier module and the load capacitor, and the second shifting capacitor is connected in series between the differential negative output of the amplifier module and the load capacitor. With this configuration, the sampling charge on the level shifting capacitors is doubled during the first amplification, resulting in a greater increase in the amplifier's output voltage during the second amplification, thereby increasing the amplifier's equivalent gain.

[0024] Figure 4 shows a schematic diagram of the output voltage of the amplifier in Figure 2. As shown in Figure 4, as mentioned above, by using a cross-capacitor connection, the charge of the level shift capacitor can be doubled during the first amplification. Therefore, the amplifier can disconnect the first amplification before the full amplification settling time t2 is reached at the first amplification time t1. The charge on the level shift capacitor is also sufficient to make the amplifier's output voltage reach the ideal output voltage V. ideal However, if the first amplification time reaches the amplifier's full amplification settling time t2, the charge on the shift level will cause the output voltage after the second amplification to be greater than the ideal output voltage (V). idealThis means that overcharging occurs, wasting the amplifier's power consumption during the first amplification. Therefore, to save amplifier power consumption, in this embodiment of the invention, the first amplification of the amplifier module is disconnected before the amplifier module is fully amplified, so that the first amplification time is less than the time t2 required for the amplifier module to be fully amplified. The time required for the amplifier module to be fully amplified is the time corresponding to when the amplifier output voltage increases very slowly as time increases during the first amplification. This time can be determined by a preset output voltage, which can be a percentage of the ideal output voltage. In specific applications, the preset output voltage can be determined according to the requirements. Before the amplifier module is fully amplified, the amplifier output voltage increases relatively quickly as time increases, and the output voltage is much lower than the ideal output voltage. After the amplifier module is fully amplified, the amplifier output voltage reaches the preset output voltage, and the increase in amplifier output voltage will be slower as time increases. Timely disconnection of the amplifier's amplification operation before the time required for the amplifier module to be fully amplified not only improves the amplifier's operating speed but also avoids wasting extra charge, effectively improving the circuit's energy efficiency.

[0025] In this embodiment of the invention, the output voltage of the amplifier is exactly equal to the ideal output voltage after the charge charged on the level shift capacitor during the first amplification time is shared during the second amplification time. This not only ensures the gain of the amplifier, but also makes the power consumption of the amplifier equal to the power consumption consumed during the first amplification time. Therefore, the power consumption of the amplifier is reduced due to the reduction of the first amplification time. At the same time, the operating speed of the amplifier is increased due to the reduction of the first amplification time. Thus, the circuit structure in this embodiment of the invention can simultaneously ensure the energy efficiency and speed of the amplifier module.

[0026] In the above embodiments, if the amplifier module maintains an equivalent open-loop gain of 80dB, there is a 30% time margin for t1 or φ1. Therefore, the first amplification time φ1 generated by the clock controller (CLK GEN) in Figure 2 can be formed by a delay unit composed of a low-cost inverter chain, by controlling the bias voltage (delay voltage) V. delay The working time of the delay unit can be controlled, thereby adjusting t1, as shown in Figure 6.

[0027] To accurately determine the first amplification time φ1 (Phase 1), that is, to find a suitable t1 so that the output voltage after the second amplification is exactly equal to the ideal output voltage, in this embodiment of the invention, a calibration loop is configured to accurately and adaptively adjust the first amplification time φ1 of the amplifier module.

[0028] Figure 5 is a schematic diagram of another operational amplifier circuit provided by an embodiment of the present invention. As shown in Figure 5, this embodiment includes an amplifier module, a level shifting module, and a calibration loop. The amplifier module and the level shifting module can be the corresponding modules in the embodiment of Figure 2 above. When the output voltage of the amplifier module is the ideal output voltage, the voltages at both ends of its differential output are equal but opposite in sign. Therefore, the magnitude of the voltages at the two differential output terminals (output polarity) can be detected to determine whether the amplifier module in the closed loop has reached the ideal output voltage. In specific applications, the polarity of the amplifier module input terminal can also be detected to determine whether the amplifier module has reached the ideal output voltage. Since the amplifier input terminal is relatively sensitive to parasitic effects and the input voltage is in the microvolt range, it is not easy to detect. Therefore, in practical applications, the polarity of the amplifier module output voltage is usually detected. The amplifier output voltage can reach the millivolt range after amplification by the amplifier, so it is easier to detect. To determine the adjustment direction of the first amplification time, the calibration loop can control and adjust the first amplification time φ1 according to the polarity of the differential output of the amplifier module and the polarity of the output voltage of the level shifting module. When the polarity of the differential output of the amplifier module is opposite to the polarity of the output voltage of the level shift module (the polarity of the output voltage input to the next stage after level shifting of the differential output of the amplifier module), it indicates that the first amplification time φ1 is too large. Too much charge is accumulated on the shifted level during the first amplification time, requiring a reduction in the first amplification time. Conversely, when the polarity of the differential output of the amplifier module is the same as the polarity of the output voltage of the level shift module, it indicates that the first amplification time φ1 is too small. The charge stored on the shifted level during the first amplification time is insufficient to reach the ideal output voltage after sharing in the second amplification time, requiring an extension of the first amplification time. When a suitable first amplification time φ1 is reached, the output voltages at the two differential terminals of the amplifier module are equal, and the output voltage of the level shift module reaches the ideal output voltage. Thus, the output voltage input to the next stage of the operational amplifier circuit is the ideal output voltage, ensuring that the operational amplifier achieves a high gain while maintaining a small first amplification time, thereby increasing the speed of the operational amplifier and reducing power consumption. While maintaining an equivalent open-loop gain of over 80dB, the operational amplifier speed can be effectively increased and power consumption effectively reduced within the time margin of the first amplification time φ1.

[0029] In practical applications, the calibration loop may include a direction detector and a delay unit. The direction detector determines whether to output a trigger signal to control the delay unit based on the voltage output direction of the amplifier module and the voltage output direction of the level shift module (the voltage output input to the next stage). The delay unit adjusts the first amplification time of the clock controller according to the trigger signal. The direction detector includes a comparator and a pulse direction detection unit. The comparator compares whether the voltage output direction of the amplifier module and the voltage output direction of the level shift module are the same or opposite, and dynamically adjusts φ1 accordingly. Through the calibration loop, precise adaptive adjustment of the first amplification time is achieved.

[0030] To avoid erroneous outputs caused by interference or noise, the pulse direction detection unit determines whether to output a trigger signal based on a preset number of consecutive pulses in the same direction. By adding the pulse direction detection unit, only the comparator results from multiple consecutive pulses in the same direction will affect the bias voltage control of the delay chain. This allows for low-pass filtering of the amplifier's feedback results, avoiding the influence of randomness and noise, and enabling the loop to converge faster.

[0031] Figure 6 is a schematic diagram of the delay unit in Figure 5. In another embodiment, the calibration loop also includes a charge pump unit, as shown in Figure 6. The delay unit is an inverter chain, and each inverter in the inverter chain is powered by a delay voltage V generated by the charge pump unit according to the trigger signal. delay Control. When the direction detector outputs a trigger signal, it triggers the charge pump unit, which adjusts the delay voltage V by outputting the amount of charge. delay， The on-time of the delay unit can be adjusted, thereby controlling the operating time of the inverter chain to adjust the first amplification time.

[0032] The specific working process of this embodiment is as follows:

[0033] 1. When the first magnification begins, C LS A capacitor is connected across the differential terminals and in parallel with the load capacitor at the output for normal amplification. When time φ1 is reached, the first amplification is cut off.

[0034] 2. At the start of the second magnification, C LS A capacitor is connected in series between the amplifier output and the load capacitor to provide level shifting.

[0035] 3. The calibration loop opens the direction detector to detect the output polarity, determine whether the output voltage reaches the ideal voltage, and adjust the value of φ1 accordingly. If, within this amplification cycle, the polarity of the differential output of the amplifier module is opposite to the polarity of the output voltage of the operational amplifier circuit, then the first amplification time φ1 of the current cycle is too large, the circuit gain is too high, and overcharging occurs in the first amplification. The first amplification time φ1 needs to be reduced in the next cycle. If, within this amplification cycle, the polarity of the differential output of the amplifier module is the same as the polarity of the output voltage of the operational amplifier circuit, then the first amplification time φ1 of the current cycle is too small, the circuit gain is insufficient, and φ1 needs to be increased in the next cycle to improve the gain.

[0036] 4. Proceed to the next amplification cycle.

[0037] After multiple amplification cycles, by repeatedly adjusting the first amplification time φ1, the amplifier module can adaptively obtain the same positive and negative output voltages at the output terminal of the amplifier module, that is, the operational amplifier circuit output reaches the ideal output voltage, thereby achieving precise closed-loop amplification.

[0038] For the same amplifier module, the above method can be used to find a precise first amplification time φ1. This first amplification time is much shorter than the time required for the amplifier module to fully amplify and build up. Furthermore, the charging charge on the capacitor during this first amplification time can ensure the shared charge required for the amplifier to output the ideal output voltage during the second amplification time. Moreover, through this calibration loop adjustment method, the circuit can adaptively and precisely adjust to match the first amplification time under different process, voltage, and temperature conditions. This achieves high gain in the amplifier circuit, shortens the amplification time, and reduces power consumption. This adaptive adjustment process requires no manual calibration intervention; instead, the circuit adjusts adaptively according to the circuit's operating environment, greatly reducing the difficulty of amplifier calibration and improving the product's stability in different operating environments.

[0039] In the above embodiments, a calibration loop is used to accurately determine the first amplification time. In practical applications, other methods can also be used, such as manual adjustment or continuous adjustment of other circuit structures to obtain an accurate first amplification time, as long as it can be adjusted so that the output voltage of the amplifier module is the ideal output voltage after two amplification stages.

[0040] This invention shortens the amplifier's amplification time by making the first amplification time shorter than the time required for the amplifier module to fully amplify and establish itself, thereby increasing the speed and reducing the amplifier's power consumption without reducing the gain. At the same time, the calibration loop adaptively and accurately determines the time required for the first amplification, reducing power consumption and achieving infinite equivalent open-loop gain. It also avoids manual adjustment and can automatically adjust and maintain sufficient stability under different temperatures, voltages, and processes.

[0041] In the above embodiments, to further reduce power consumption, the operational amplifier circuit may further include: a sampling thermal noise cancellation module for eliminating sampling thermal noise, such as the noise cancellation capacitor Cnc shown in FIG2. By setting Cnc and controlling the switch, the amplifier A1 is made to work only in the noise sampling stage and the margin amplification stage, so as to further reduce the power consumption of the circuit.

[0042] Figure 7 is a schematic diagram of an analog-to-digital converter (ADC) according to an embodiment of the present invention. As shown in Figure 7, the ADC in this embodiment has a pipelined structure, mainly including a first-stage ADC, a second-stage ADC, and an interstage margin amplifier. The input physical signal is sampled by a front-end sampling capacitor to obtain the input signal Vin. During the operation of the sampling capacitor, the sampling thermal noise Vn-ktc is also stored. The first-stage ADC of the ADC performs digital conversion and quantization on the input signal. This process is coarse quantization. After quantization, there is still a margin signal that needs to be further refined. Before the second-stage ADC performs fine quantization, the margin amplifier needs to amplify the margin signal. The final digital result Dout output by the converter is the superposition of the coarse quantization result of the first-stage ADC and the fine quantization result of the second-stage ADC. Since margin amplification is performed before fine quantization, the fine quantization result needs to be divided by the amplification factor of the margin amplifier before superposition. That is, through the digital signal output circuit, the conversion and quantization result of the second-stage ADC is reduced by the amplification factor of the margin amplifier and then superimposed with the conversion and quantization result of the first-stage ADC before output, thus obtaining the complete analog-to-digital conversion result.

[0043] In this embodiment, the margin amplifier adopts the operational amplifier circuit shown in the embodiments of Figure 2 or Figure 5. As described in the above embodiments, the operational amplifier circuit limits the first amplification time, ensuring high gain while timely disconnection during the first amplification, thereby reducing power consumption and increasing speed, thus improving the speed of the analog-to-digital converter and reducing power consumption. The margin amplifier employs a calibration loop (CALIBRE) to adaptively adjust the first amplification time to precisely control the timely disconnection of the amplifier module from amplification operation.

[0044] This invention also provides an Internet of Things (IoT) chip, including the analog-to-digital converter shown in FIG7 above.

[0045] The operational amplifier in this embodiment can also be applied to a capacitor-to-digital converter. Figure 8 shows the average noise data test results and spectrum of the capacitor-to-digital converter provided in this embodiment. Figure 9 shows a comparison of the noise efficiency of the capacitor-to-digital converter provided in this embodiment with that of the prior art. As shown in Figures 8 and 9, this embodiment was fabricated and verified in an analog-to-digital converter structure using TSMC's 22nm process. At a power supply voltage of 1.1V and an operating frequency of 200kHz, the converter power consumption is approximately 4.71uW, with an efficiency index of 7.9fJ / conv.-step and a conversion accuracy of 37.12aF. This interstage amplifier structure uses an open-loop amplifier of approximately 50dB to achieve an equivalent amplification accuracy of over 90dB. Furthermore, the amplification time is continuously adjusted by background calibration, exhibiting excellent temperature, voltage, and process stability. No additional factory calibration is required, and the first amplification cycle is successfully shortened by approximately 10 times using incomplete amplification, significantly improving efficiency. Compared to the current higher efficiency level (16fJ / conv.-step) within a conversion accuracy of 1fF, the analog-to-digital converter using this invention improves efficiency by a factor of two. Overall performance is outstanding among capacitive sensors, with fast conversion speed and higher accuracy. The average noise data and corresponding spectrum obtained from the test are shown in Figure 8. By adopting thermal noise cancellation technology, the conversion accuracy at a 384fF input is 37.12aF, which exceeds the theoretical accuracy of 51.8aF, thereby reducing the system noise requirements.

[0046] Figure 9 shows a comparison between this invention and other existing solutions. Figure 9 illustrates the noise and energy efficiency performance of various high-performance capacitive sensors in recent years. The pentagrams in the figure represent the technical effects of this invention, which achieves outstanding accuracy while also exhibiting very high energy efficiency.

[0047] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. An operational amplifier circuit, characterized in that, include: An amplifier module and a level shifting module are provided. The level shifting module includes a level shifting capacitor and a clock controller. The clock controller controls the level shifting capacitor to be connected across the differential output terminal of the amplifier module during the first amplification time of the first amplification to sample the output voltage of the amplifier module. During the second amplification time of the second amplification, it is connected in series between the output terminal of the amplifier module and the load capacitor for level shifting and secondary amplification. The first amplification of the amplifier module is disconnected before the amplifier module is fully amplified, so that the first amplification time is less than the time required for the amplifier module to be fully amplified. The level shifting capacitor includes an identical first shifting capacitor and a second shifting capacitor. During the first amplification time, both the first shifting capacitor and the second shifting capacitor are connected across the differential output terminal of the amplifier module. During the second amplification time, the first shifting capacitor is connected in series between the positive differential output terminal of the amplifier module and the load capacitor, and the second shifting capacitor is connected in series between the negative differential output terminal of the amplifier module and the load capacitor.

2. The circuit according to claim 1, characterized in that, Also includes: A calibration loop is provided to control the first amplification time based on the voltage output direction of the amplifier module and the voltage output direction of the level shifting module.

3. The circuit according to claim 2, characterized in that, The calibration loop includes a direction detector and a delay unit. The direction detector determines whether to output a trigger signal to control the delay unit by comparing the voltage output direction of the amplifier module with the voltage output direction of the level shift module. The delay unit adjusts the first amplification time of the clock controller according to the trigger signal.

4. The circuit according to claim 3, characterized in that, The calibration loop also includes a charge pump unit, and the delay unit is an inverter chain, wherein each inverter in the inverter chain is controlled by the charge pump unit according to the delay voltage generated by the trigger signal.

5. The circuit according to any one of claims 1-4, characterized in that, Also includes: A sampling thermal noise cancellation module for eliminating sampling thermal noise.

6. An analog-to-digital converter, characterized in that, include: The first-stage ADC, the second-stage ADC, and the interstage margin amplifier, wherein the margin amplifier adopts the operational amplifier circuit as described in any one of claims 1-5.

7. An Internet of Things (IoT) chip, characterized in that, Includes the analog-to-digital converter as described in claim 6.

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