A packaging method for a packaging structure of a vertical MOSFET chip

Abstract

The present invention discloses a method for manufacturing a packaging structure for a vertical MOSFET chip, belonging to the field of semiconductor packaging technology. The method employs a method for mounting the vertical MOSFET chip with its back side facing downward onto an etched surface of a three-dimensional metal frame. By folding the three-dimensional metal frame, the drain, source, and gate of the vertical MOSFET chip are distributed on the same plane, shortening the interconnection distance between the vertical MOSFET chip and the outside world, enhancing the chip's conductive effect, and streamlining the packaging structure. Simultaneously, a metal conductive heat sink is employed to contact the back drain region of the vertical MOSFET chip over a large area, resulting in excellent heat dissipation performance and improved product quality. Alternatively, the drain metal pins of the three-dimensional metal frame are concavely curved columns, or a glue-locking through-hole is provided at the bottom of the drain metal pins of the three-dimensional metal frame, both of which enhance the bonding strength between the metal column and the plastic encapsulation material, thereby achieving the purpose of increasing product reliability.

Description

Technical Field

[0001] The invention relates to a packaging method for a packaging structure of a vertical MOSFET chip, belonging to the technical field of semiconductor packaging. Background Art

[0002] MOSFET stands for Metal Oxide Semiconductor Field Effect Transistor. Vertical MOSFETs are common voltage-controlled devices with a range of advantages, including fast switching speed, high-frequency performance, high input impedance, low noise, low drive power, large dynamic range, and a wide safe operating area (SOA). Therefore, they are widely used in various industries, including switching power supplies, motor control, and power tools.

[0003] With the development of the 5G industry, consumer electronics and new energy vehicle industries, for example, the power consumption of 5G base stations has increased, and the power consumption of 5G base stations is twice that of 4G. In order to reduce power consumption requirements, it is necessary to increase the low loss and high thermal stability requirements of vertical MOSFETs. This also places higher requirements on the package type with low on-resistance, low heat generation and fast heat dissipation.

[0004] On-resistance (RDS), or the resistance between the drain and source, is one of the main characteristic parameters of power vertical MOSFETs. Vertical MOSFET devices achieve low RDS(on) by placing the drain region on the surface opposite to the source contact. By placing the drain region on the surface opposite to the source contact, the current conduction path is shortened, which reduces RDS(on).

[0005] In traditional wire-bonded packages, the on-resistance is equal to the sum of the chip’s on-resistance and the package’s parasitic resistance, i.e., RDS(on) = R L +R D +R W +Rds(on), where R L is the lead frame resistance, R D is the resistance between the chip drain and the frame, R W is the bonding wire resistance, Rds(on) is the internal resistance of the chip. Traditional wire bonding packages all use wire bonding packaging. The bonding wire resistance R w The larger the on-resistance of the entire package, the higher the on-resistance will be, which will eventually affect the current carrying capacity of the product. In addition, the traditional vertical MOSFET packaging method completely wraps the chip in the plastic package, which causes the heat generated by the chip during operation to not be dissipated in time, thus restricting the performance improvement of the product. Summary of the Invention

[0006] In order to overcome the shortcomings of the traditional vertical MOSFET wire-bonding packaging structure implementation method, the present invention provides a packaging method for a vertical MOSFET packaging structure, so that the vertical MOSFET chip using this packaging method can achieve low on-resistance, carry large current, have excellent heat dissipation performance, and have a simple packaging structure.

[0007] The technical solution of the present invention:

[0008] The present invention provides a packaging method for a vertical MOSFET chip packaging structure, and the process method is as follows:

[0009] Step 1: Prepare the incoming wafer. The wafer has neatly arranged horizontal and vertical dicing lanes I. The dicing lanes I pre-divide the wafer into a plurality of vertical MOSFET chips. Each vertical MOSFET chip has a source and gate region on the front side and a drain region on the back side.

[0010] Step 2: forming a source conductive pad in the source region of the vertical MOSFET chip and a gate conductive pad in the gate region thereof by sputtering, etching, chemical deposition, printing or spraying liquid metal in sequence;

[0011] Step 3: Using low-temperature sintering silver connection technology to form a high-conductivity silver particle sintered body as a conductive circuit layer in the drain region of the vertical MOSFET chip;

[0012] Step 4: Using a cutting process to form a plurality of independent chip units along the cutting path I;

[0013] Step 5: Prepare a three-dimensional metal frame strip, with the etched surface on the back facing upward as the working surface. Arrange a plurality of hollow patterns, transverse cutting lanes III, longitudinal cutting lanes III, and alignment points on the three-dimensional metal frame strip. The transverse cutting lanes III are set on the upper and lower sides of the three-dimensional metal frame strip. Each hollow pattern is a discontinuous pattern and is distributed along the transverse cutting lanes III on both sides of the three-dimensional metal frame strip. The upper and lower transverse cutting lanes III pass through the upper and lower edges of each hollow pattern respectively. The transverse cutting lanes III and the longitudinal cutting lanes III pre-divide the three-dimensional metal frame strip into a plurality of three-dimensional metal frames. The hollow pattern is pre-cut by the transverse cutting lanes III to form a guide hole. Each three-dimensional metal frame includes a metal frame body and a drain metal pin. The drain metal pin and the inner side of the three-dimensional metal frame together constitute a cavity.

[0014] Step 6: Place the chip monomers with their backs facing downwards into the cavity of the three-dimensional metal frame strip by aligning the points, so that the conductive circuit layer in the drain region is electrically connected to the etched surface of the metal frame body through the welding layer I;

[0015] Step 7: Using a film-assisted plastic encapsulation single-sided molding process, the three-dimensional metal frame bar and the vertical MOSFET chip are covered with a plastic encapsulation material above the three-dimensional metal frame bar, and the hollow pattern is filled;

[0016] Step 8: Exposing the upper surface of the drain metal pin of the three-dimensional metal frame bar, as well as the upper surface of the source conductive pad and the upper surface of the gate conductive pad of the vertical MOSFET chip through a grinding process, so that the upper surface of the source conductive pad and the upper surface of the gate conductive pad are flush with the upper surface of the drain metal pin;

[0017] Step 9: forming a conductive metal layer I, a conductive metal layer II, and a conductive metal layer III on the upper surface of the source conductive pad, the upper surface of the gate conductive pad, and the upper surface of the drain metal pin respectively by sputtering, etching, chemical deposition, printing, or spraying liquid metal;

[0018] Step 10: Divide the package into a plurality of vertical MOSFET chip package structure units along the horizontal cutting line III and the vertical cutting line III, and lead the drain of the vertical MOSFET chip upward through the three-dimensional metal frame to the same plane as the source and gate of the vertical MOSFET chip.

[0019] Furthermore, in step five, the forming process of the drain metal pin is as follows: a plurality of metal pillars of the same height are prepared, and the metal pillars are arranged on the periphery of the hollow pattern of the etched surface of the metal frame body through welding layer II to form the drain metal pin.

[0020] Furthermore, the metal column forming process includes preparing a metal sheet and dividing it into rectangular metal columns by a blade or laser.

[0021] Furthermore, in step five, the forming process of the drain metal pin (25) is as follows: when the three-dimensional metal frame bar is formed, the raw material of the three-dimensional metal frame bar is subjected to multiple half-etching processes to remove excess metal material to form a three-dimensional metal frame bar with a drain metal pin, the drain metal pin is in a concave arc column shape, and the three-dimensional metal frame bar is cut into a plurality of three-dimensional metal frames.

[0022] Furthermore, in step five, a glue locking through hole is opened at the bottom of the drain metal pin, the longitudinal section of the glue locking through hole is arc-shaped, single-X-shaped or double-X-shaped, and the through hole direction is perpendicular to the short side of the vertical MOSFET chip.

[0023] Furthermore, in step 5, the forming process of the metal column with the glue-locking through hole provided at the bottom of the drain metal pin is as follows:

[0024] Prepare a metal sheet with pre-cutting lines on it, the pre-cutting lines dividing the metal sheet into metal pillars arranged in an array, and the metal pillars are rectangular;

[0025] The upper surface of the metal sheet is covered with a photoresist layer;

[0026] A photoresist pattern is formed by a photoresist forming process, wherein an opening of the photoresist pattern is circular, penetrates the photoresist layer and straddles a cutting path on one of the short sides of the metal pillar;

[0027] Then, the exposed metal in the opening of the photoresist pattern is removed by etching until a circular through hole is formed. The circular through hole straddles the cutting path and removes an arc-shaped portion of each adjacent rectangular metal column to form an arc-shaped glue locking through hole;

[0028] The remaining photoresist is then removed, and the metal sheet is divided along the photoetching lanes to form a plurality of independent metal pillars with arc-shaped photoresist locking holes.

[0029] Furthermore, in step 5, the forming process of the metal column of the glue-locking through hole with a single-X-shaped longitudinal section is as follows:

[0030] Prepare a metal sheet with pre-cutting lines on it, the pre-cutting lines dividing the metal sheet into metal pillars arranged in an array, and the metal pillars are rectangular;

[0031] The upper surface of the metal sheet is covered with a photoresist layer;

[0032] A photoresist pattern is formed by a photoresist forming process, wherein an opening of the photoresist pattern is a large rectangle, penetrates the photoresist layer and straddles a cutting path of one short side of the metal pillar;

[0033] Then, the exposed metal in the opening of the photoresist pattern is removed by etching until a large rectangular through hole is formed. The large rectangular through hole straddles the cutting path and removes a portion of each adjacent rectangular metal column to form a small rectangular glue-locking through hole.

[0034] The remaining photoresist is then removed, and the metal sheet is divided along the photoetching path to form a plurality of independent metal pillars with single-digit "X"-shaped glue locking through holes.

[0035] Furthermore, in step five, the welding layer II is a metal selected from titanium, copper, silver, nickel, gold, and tin, or a combination of several metals.

[0036] Furthermore, in step five, the hollow pattern is in the shape of a letter "2".

[0037] Furthermore, in step 2, the source conductive pad and the gate conductive pad are formed into a composite conductive metal layer of corresponding materials by repeating the process of step 2 multiple times.

[0038] Beneficial effects

[0039] The present invention provides a packaging method for a vertical MOSFET chip packaging structure, provides a low-temperature solder connection technology represented by sintered silver, realizes the connection between the metal heat sink and the drain area of the vertical MOSFET chip, avoids the use of traditional wire bonding, increases the current carrying capacity, and reduces the resistance R between the chip drain and the lead frame. D , reducing the bond wire resistance R W , thereby achieving the purpose of reducing the on-resistance RDS(on) of the packaged product. This packaging method can improve production efficiency and has the advantage of reducing production costs; the packaging structure of the vertical MOSFET chip formed thereby adopts the back side of the vertical MOSFET chip to be mounted downward on the etched surface of the three-dimensional metal frame, and the drain, source and gate of the vertical MOSFET chip are distributed in the same plane through the folding use of the three-dimensional metal frame, thereby shortening the interconnection distance between the vertical MOSFET chip and the outside world, enhancing the conductive effect of the chip, and streamlining the packaging structure; at the same time, a metal conductive heat sink is used to contact the back drain area of the vertical MOSFET chip over a large area, thereby achieving excellent heat dissipation performance and improving product quality; in addition, the drain metal pin of the three-dimensional metal frame is in a concave arc columnar shape, or a glue locking through-hole is provided at the bottom of the drain metal pin of the three-dimensional metal frame, both of which enhance the bonding force between the metal column and the plastic packaging material, thereby achieving the purpose of increasing product reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 This is a flow chart of a packaging method for a vertical MOSFET chip packaging structure according to the present invention;

[0041] Figure 2 Schematic diagram of the cross-sectional structure of a first embodiment of a packaging structure for a vertical MOSFET chip according to the present invention;

[0042] Figure 3 for Figure 2 Schematic diagram of the relative positions of the vertical MOSFET chip and the three-dimensional metal frame;

[0043] Figure 4 A schematic diagram of a deformed cross-sectional structure of a vertical MOSFET chip packaging structure according to the present invention;

[0044] 5A to 5O for Figure 2 A flowchart of a process of a packaging method for a vertical MOSFET chip packaging structure according to the present invention;

[0045] Figure 6 A schematic diagram of the cross-sectional structure of a second embodiment of a packaging structure for a vertical MOSFET chip according to the present invention;

[0046] Figure 7for Figure 6 Schematic diagram of the relative positions of the vertical MOSFET chip and the three-dimensional metal frame;

[0047] Figures 8 to 10 for Figure 6 Schematic diagram of the cross-sectional structure of the glue-locking through hole;

[0048] Figures 11A to 11N for Figure 6 A flowchart of a process of a packaging method for a vertical MOSFET chip packaging structure according to the present invention;

[0049] Including: vertical MOSFET chip 10

[0050] Source conductive pad 13

[0051] The upper surface 131 of the source conductive pad

[0052] Gate conductive pad 15

[0053] The upper surface 151 of the gate conductive pad is welded with the layer I18

[0054] Welding layer II19

[0055] Conductive circuit layer 30

[0056] Three-dimensional metal frame 20

[0057] Metal frame body 21

[0058] Horizontal cutting channel Ⅲ210

[0059] Longitudinal cutting channel Ⅲ230

[0060] Drain metal pin 25

[0061] Diversion hole 221

[0062] Glue lock hole 27

[0063] The upper surface 221 of the source metal pin and the upper surface 241 of the gate metal pin are molded into the cavity 26.

[0064] Conductive metal layer Ⅰ61

[0065] Conductive metal layer II 63

[0066] Conductive metal layer III65

[0067] Plastic packaging material 90;

[0068] Wafer 100

[0069] Cutting Road Ⅰ110

[0070] Three-dimensional metal frame bar 200 diversion hole 221

[0071] Horizontal cutting channel Ⅲ210

[0072] Longitudinal cutting channel Ⅲ230

[0073] Counterpoint 250

[0074] Metal sheet 270

[0075] Pre-cutting channel 271

[0076] Photoresist layer 274

[0077] Photoresist pattern 275

[0078] Circular through hole 276

[0079] Large rectangular through hole 278. DETAILED DESCRIPTION

[0080] The present application will be further described in detail below with reference to the accompanying drawings and examples. It will be understood that the specific embodiments described herein are intended only to explain the relevant inventions and are not intended to limit the inventions. It should also be noted that, for ease of description, only portions relevant to the relevant inventions are shown in the accompanying drawings. It should be noted that, unless there is a conflict, the embodiments and features in the embodiments of the present application may be combined with one another. The present application will be described in detail below with reference to the accompanying drawings and in conjunction with the examples.

[0081] The present invention is a flowchart of a packaging method for a vertical MOSFET chip packaging structure, as shown in FIG. Figure 1 As shown:

[0082] S1: prepare incoming wafers;

[0083] S2: forming a source conductive pad in the source region of the vertical MOSFET chip and a gate conductive pad in the gate region thereof by sputtering, etching, chemical deposition, printing or spraying liquid metal in sequence;

[0084] S3: forming a high-conductivity silver particle sintered body as a conductive circuit layer in the drain region of the vertical MOSFET chip through low-temperature sintering silver connection technology;

[0085] S4: using a cutting process to form a plurality of independent chip units;

[0086] S5: preparing a three-dimensional metal frame strip to form a three-dimensional metal frame, and forming a drain metal pin on the three-dimensional metal frame, wherein the inner side of the three-dimensional metal frame and the drain metal pin together constitute a mold cavity;

[0087] S6: Place the chip units with their backs facing downward into the cavity one by one;

[0088] S7: Plastic encapsulating the three-dimensional metal frame strip and the vertical MOSFET chip through a film-assisted plastic encapsulation single-sided molding process;

[0089] S8: exposing the upper surface of the drain metal pin of the three-dimensional metal frame bar, and the upper surface of the source conductive pad and the upper surface of the gate conductive pad of the vertical MOSFET chip through a grinding process;

[0090] S9: forming a conductive metal layer I, a conductive metal layer II, and a conductive metal layer III on the upper surface of the source conductive pad, the upper surface of the gate conductive pad, and the upper surface of the drain metal pin respectively by sputtering, chemical deposition, printing, or spraying;

[0091] S10: dividing the package into a plurality of vertical MOSFET chip package structure units.

[0092] Example 1

[0093] The present invention provides a packaging structure for a vertical MOSFET chip, wherein the front side of the vertical MOSFET chip 10 is provided with a source region and a gate region, and the back side is provided with a drain region. Figure 2 shown.

[0094] The source region of the vertical MOSFET chip 10 is provided with a source conductive pad 13, and the gate region is provided with a gate conductive pad 15. The cross-sections of the source conductive pad 13 and the gate conductive pad 15 are circular, rectangular, hexagonal or octagonal, and are made of a composite conductive metal layer, such as a Cu / Sn layer or a Ni / Au layer. The drain region of the vertical MOSFET chip 10 is provided with a conductive circuit layer 30. The conductive circuit layer 30 can form a high-conductivity silver particle sintered body in the drain region of the vertical MOSFET chip 10 through low-temperature sintering silver connection technology, or can be laid in the drain region of the vertical MOSFET chip 10 using finished welding materials, such as conductive glue, soft solder, solder paste, etc., or can be made of one or a combination of several materials selected from copper, silver, nickel, gold, tin, and tin-silver, such as a Cu / Sn layer or a Ni / Au layer.

[0095] Its three-dimensional metal frame 20 includes a metal frame body 21, a guide hole 221 and a plurality of drain metal pins 25. The metal frame body 21 is in the shape of an I-shaped body rotated 90 degrees, including a central I-shaped part and I-shaped parts on both sides. The guide hole 221 is arranged in the center of the upper and lower sides of the metal frame body 21 and passes through the metal frame body 21 from top to bottom, such as the guide hole 221 is in the shape of an I-shaped body. The drain metal pins 25 are arranged on the I-shaped parts on both sides of the etched surface of the metal frame body 21. The drain metal pins 25 are fixedly connected to the etched surface of the metal frame body 21 through the welding layer II19. The etched surface of the metal frame body 21 is a rough surface, which helps to strengthen the connection between the three-dimensional metal frame 20 and the drain metal pins 25 and the vertical MOSFET chip 10. The drain metal pins 25 and the three-dimensional metal frame 20 together form a cavity 26, which is used to carry the vertical MOSFET chip 10. In actual design, the number of drain metal pins 25 can be one, two, three, or more, depending on the needs. The drain metal pins 25 can be distributed on one side of the three-dimensional metal frame 20 or on both the left and right sides of the three-dimensional metal frame 20. The cross-section of the drain metal pins 25 is circular, rectangular, hexagonal, or octagonal. Figure 3 In the figure, two drain metal pins 25 with circular cross sections are respectively distributed on the left and right sides of the three-dimensional metal frame 20. The drain metal pins 25 are preferably copper pillars.

[0096] Within cavity 26, the conductive circuit layer 30 in the drain region of the backside of the vertical MOSFET chip 10 is electrically connected to the etched surface of the metal frame body 21 via solder layer I 18. The backside of the vertical MOSFET chip 10 is in contact with the three-dimensional metal frame 20 over a large area through the conductive circuit layer 30 and solder layer I 18, achieving excellent heat dissipation performance for the packaged product.

[0097] The upper surface 251 of the drain metal pin of the three-dimensional metal frame 20, the upper surface 131 of the source conductive pad, and the upper surface 151 of the gate conductive pad are flush, so that the source, gate, and drain of the vertical MOSFET chip 10 are distributed on the same plane, shortening the interconnection distance between the vertical MOSFET chip 10 and the outside world, enhancing the conductive effect of the chip, avoiding the use of traditional wire bonding methods, and reducing the resistance R between the chip drain and the lead frame. D , reducing the bond wire resistance R W , thereby achieving the purpose of reducing the on-resistance RDS(on) of the packaged product.

[0098] The plastic encapsulation material 90 completely fills and encapsulates the three-dimensional metal frame 20 and vertical MOSFET chip 10, leaving only the upper surface 251 of the drain metal pin, the upper surface 131 of the source conductive pad, and the upper surface 151 of the gate conductive pad exposed. The flow holes 221 allow the plastic encapsulation material 90 to flow more smoothly. The plastic encapsulation material 90 disposed between the source conductive pad 13 and the gate conductive pad 15 of the vertical MOSFET chip 10 and the three-dimensional metal frame 20 effectively prevents short circuits caused by voltage breakdown, thereby improving product reliability.

[0099] In an optional embodiment, the drain metal pin 25 is in a concave arc column shape, and its curvature R is generated due to the difference in etching rate during the half-etching process of the three-dimensional metal frame 20, such as Figure 4 As shown, by controlling the half-etching process to obtain the actually required arc R, the bonding force between the drain metal pin 25 and the plastic packaging material 90 can also be increased, thereby achieving the purpose of increasing product reliability.

[0100] In an optional embodiment, the molding material 90 may also be exposed on both sides of the metal frame body 21 .

[0101] In an optional embodiment, the packaging structure of a vertical MOSFET chip of the present invention further includes a conductive metal layer I 61, a conductive metal layer II 63 and a conductive metal layer III 65, wherein the conductive metal layer I 61 is disposed on the upper surface 251 of the drain metal pin, the conductive metal layer II 63 is disposed on the upper surface 131 of the source conductive pad, and the conductive metal layer III 65 is disposed on the upper surface 151 of the gate conductive pad, so as to facilitate electrical connection with other external devices, such as Figure 1 shown.

[0102] The present invention provides a packaging method for a vertical MOSFET chip packaging structure, and the process thereof is as follows:

[0103] Step 1: Figure 5A As shown, the incoming wafer 100 is prepared, and qualified wafers are selected through the incoming material inspection process, and a cleaning process is performed to remove dust, oil, etc. There are neatly arranged horizontal and vertical cross-cutting lanes I110 on the wafer 100. The cutting lanes I110 pre-divide the wafer 100 into a plurality of vertical MOSFET chips 10. The front side of each vertical MOSFET chip 10 is provided with a source region and a gate region, and the back side is provided with a drain region; "pre-dividing" means that a plan is planned for the following steps in this step.

[0104] Step 2: Figure 5BAs shown, a source conductive pad 13 is formed in the source region of the vertical MOSFET chip 10, and a gate conductive pad 15 is provided in the gate region thereof by sputtering etching, chemical deposition, printing or spraying liquid metal. When forming a composite conductive metal layer such as a Cu / Sn layer or a Ni / Au layer, the process of step 2 needs to be repeated multiple times to form a conductive metal layer of the corresponding material.

[0105] Step 3: Figure 5C As shown, a high-conductivity silver particle sintered body is formed as a conductive circuit layer 30 in the drain region of the vertical MOSFET chip 10 by low-temperature sintering silver connection technology;

[0106] Step 4: Figure 5D and Figure 5E As shown, a plurality of independent chip monomers 10 are formed along the cutting path I 110 by using a cutting process. Figure 5E In its front view, the source region of the vertical MOSFET chip 10 is provided with a source conductive pad 13 and the gate region thereof is provided with a gate conductive pad 15;

[0107] Step 5: Figure 5F and Figure 5G 、 Figure 5H As shown, a three-dimensional metal frame bar 200 is prepared, with the etched surface on the back facing upward as the working surface. A plurality of hollow patterns 220, transverse cutting paths III 210, longitudinal cutting paths III 230 and alignment points 250 are arranged on the three-dimensional metal frame bar 200. The transverse cutting paths III 210 are set on the upper and lower sides of the three-dimensional metal frame bar 200. Each hollow pattern 220 is a discontinuous pattern and is distributed on both sides of the three-dimensional metal frame bar 200 along the array of the transverse cutting paths III 210, such as the hollow pattern 220 is in the shape of a two-character. Upper and lower transverse cutting paths III 210 respectively pass through the top and bottom edges of each hollow pattern 220. Transverse cutting paths III 210 and longitudinal cutting paths III 230 pre-divide the three-dimensional metal frame strip 200 into a plurality of three-dimensional metal frames 20. Each three-dimensional metal frame 20 includes a metal frame body 21 and drain metal pins 25. The drain metal pins 25 are formed by separately prepared metal pillars of the same height. These rectangular metal pillars can be formed by cutting a metal sheet with a blade or laser, or by a metal casting process. These metal pillars are arranged around the periphery of the hollow pattern 220 on the etched surface of the metal frame body 21 via a welding layer II 19 to form the drain metal pins 25. This solder can be one or a combination of metals selected from titanium, copper, silver, nickel, gold, and tin. The hollow pattern 220 is pre-cut by transverse cutting paths III 210 to form the diversion holes 221. "Pre-cutting" means that the plan for the following steps has been planned in this step.

[0108] The drain metal pin 25 and the inner side of the three-dimensional metal frame 20 together form a cavity 26; Figure 5G As shown; the drain metal pin 25 is preferably a copper column.

[0109] Alternatively, when the three-dimensional metal frame strip 200 is formed, the raw material of the three-dimensional metal frame strip 200 is subjected to multiple half-etching processes to remove excess metal material, thereby forming a three-dimensional metal frame strip 200 with a drain metal pin 25. The drain metal pin 25 is in a concave arc column shape, and its curvature R is generated due to the difference in etching rate during the half-etching process of the three-dimensional metal frame 20; after the three-dimensional metal frame strip 200 is cut into the three-dimensional metal frame 20, the drain metal pin 25 and the three-dimensional metal frame 20 are an integrated structure, such as Figure 5H shown.

[0110] Step 6: Figure 5I and Figure 5J As shown, by aligning at the alignment point 250, the new chip unit 10 is placed with its back side facing downward into the cavity 26 of the three-dimensional metal frame bar 200, so that the conductive circuit layer 30 in its drain region is electrically connected to the etched surface of the metal frame body 21 via the solder layer I 18. The solder of the solder layer I 18 can be one of titanium, copper, silver, nickel, gold, tin, or tin-silver, or a combination thereof.

[0111] Step 7: Figure 5K As shown, through the film-assisted molding (FAM) process, the three-dimensional metal frame bar 200 and the vertical MOSFET chip 10 are covered with a molding material 90 above the three-dimensional metal frame bar 200, and the hollow pattern 220 is filled.

[0112] Step 8: Figure 5L As shown, the upper surface 251 of the drain metal pin 25 of the three-dimensional metal frame bar 200, as well as the upper surface 131 of the source conductive pad and the upper surface 151 of the gate conductive pad of the vertical MOSFET chip 10 are exposed through the grinding process. The upper surface 131 of the source conductive pad and the upper surface 151 of the gate conductive pad are flush with the upper surface 251 of the drain metal pin.

[0113] Step 9: Figure 5M As shown, a conductive metal layer I 61, a conductive metal layer II 63 and a conductive metal layer III 65 are respectively formed on the upper surface 131 of the source conductive pad, the upper surface 151 of the gate conductive pad and the upper surface 251 of the drain metal pin by sputtering etching, chemical deposition, printing or spraying. The conductive metal layer I 61, the conductive metal layer II 63 and the conductive metal layer III 65 are used for subsequent mounting of the packaged chip. Figure 5M shown.

[0114] Step 10: Figure 5N and Figure 5OAs shown, the above-mentioned package body is divided into a plurality of package structure units of vertical MOSFET chips along the horizontal cutting street III210 and the vertical cutting street III230, and the drain of the vertical MOSFET chip 10 is led upward to the same plane as the source and gate of the vertical MOSFET chip 10 through the three-dimensional metal frame 20.

[0115] Embodiment 2 The present invention provides a packaging structure for a vertical MOSFET chip, wherein the front surface of the vertical MOSFET chip 10 is provided with a source region and a gate region, and the back surface is provided with a drain region, such as Figure 6 shown.

[0116] The source region of the vertical MOSFET chip 10 is provided with a source conductive pad 13, and the gate region thereof is provided with a gate conductive pad 15. The cross-sections of the source conductive pad 13 and the gate conductive pad 15 are circular, rectangular, hexagonal or octagonal, and are made of a composite conductive metal layer, such as a Cu / Sn layer or a Ni / Au layer. The drain region of the vertical MOSFET chip 10 is provided with a conductive circuit layer 30. The conductive circuit layer 30 can be formed into a high-conductivity silver particle sintered body in the drain region of the vertical MOSFET chip 10 by low-temperature sintering silver connection technology, or can be laid in the drain region of the vertical MOSFET chip 10 using finished welding materials, such as conductive glue, soft solder, solder paste, etc., or can be made of one or a combination of several materials selected from copper, silver, nickel, gold, tin, and tin-silver, such as a Cu / Sn layer or a Ni / Au layer.

[0117] Its three-dimensional metal frame 20 includes a metal frame body 21, a guide hole 221, a plurality of drain metal pins 25 and a glue locking through hole 27. The metal frame body 21 is in the shape of an I-shaped body rotated 90 degrees, including a central I-shaped part and 1-shaped parts on both sides. The guide hole 221 is arranged in the center of the upper and lower sides of the metal frame body 21, such as the guide hole 221 is in the shape of an I-shaped character. The drain metal pin 25 is arranged on the periphery of the etched surface of the metal frame body 21, and a glue locking through hole 27 is arranged at the bottom thereof. The longitudinal section of the glue locking through hole 27 is in the shape of an arc, a single I-shaped character or a double I-shaped character, and the through hole direction is perpendicular to the short side of the vertical MOSFET chip 10, such as Figures 8 to 10 shown.

[0118] The drain metal pin 25 is fixedly connected to the etched surface of the metal frame body 21 via a welding layer II 19. The material of the metal frame body 21 is similar to that of the lead frame in the industry.

[0119] The drain metal pins 25 and the inner side of the three-dimensional metal frame 20 together form a cavity 26 for supporting the vertical MOSFET chip 10. In actual design, the number of drain metal pins 25 can be one, two, three, or more, depending on the needs. The drain metal pins 25 can be located on the left or right side of the three-dimensional metal frame 20, or on both sides. The cross-section of the drain metal pins 25 can be circular, rectangular, hexagonal, or octagonal. Figure 7 In the figure, two drain metal pins 25 with circular cross sections are respectively distributed on the left and right sides of the three-dimensional metal frame 20. The drain metal pins 25 are preferably copper pillars.

[0120] Within cavity 26, the conductive circuit layer 30 in the drain region of the backside of the vertical MOSFET chip 10 is electrically connected to the etched surface of the metal frame body 21 via solder layer I 18. The backside of the vertical MOSFET chip 10 is in contact with the three-dimensional metal frame 20 over a large area through the conductive circuit layer 30 and solder layer I 18, achieving excellent heat dissipation performance for the packaged product.

[0121] The upper surface 251 of the drain metal pin of the three-dimensional metal frame 20, the upper surface 131 of the source conductive pad, and the upper surface 151 of the gate conductive pad are flush, so that the source, gate, and drain of the vertical MOSFET chip 10 are distributed on the same plane, shortening the interconnection distance between the vertical MOSFET chip 10 and the outside world, enhancing the conductive effect of the chip, avoiding the use of traditional wire bonding methods, and reducing the resistance R between the chip drain and the lead frame. D , reducing the bond wire resistance R W , thereby achieving the purpose of reducing the on-resistance RDS(on) of the packaged product.

[0122] The plastic encapsulation material 90 completely fills and encapsulates the three-dimensional metal frame 20, vertical MOSFET chip 10, as well as the flow guide holes 221 and the glue locking holes 27, leaving only the upper surface 251 of the drain metal pin, the upper surface 131 of the source conductive pad, and the upper surface 151 of the gate conductive pad exposed. The flow guide holes 221 and the glue locking holes 27 allow the plastic encapsulation material 90 to flow more smoothly, while also enhancing the plastic encapsulation strength of the plastic encapsulation material 90. The plastic encapsulation material 90 disposed between the source conductive pad 13 and the gate conductive pad 15 of the vertical MOSFET chip 10 and the three-dimensional metal frame 20 can effectively prevent short circuits caused by voltage breakdown, thereby improving product reliability.

[0123] In an optional embodiment, the packaging structure of a vertical MOSFET chip of the present invention also includes a conductive metal layer I 61, a conductive metal layer II 63 and a conductive metal layer III 65, wherein the conductive metal layer I 61 is arranged on the upper surface 251 of the drain metal pin, the conductive metal layer II 63 is arranged on the upper surface 131 of the source conductive pad, and the conductive metal layer III 65 is arranged on the upper surface 151 of the gate conductive pad, so as to facilitate electrical connection with other external devices.

[0124] The present invention provides a packaging method for a vertical MOSFET chip packaging structure, and the process thereof is as follows:

[0125] Step 1: Figure 11A As shown, the incoming wafer 100 is prepared, and qualified wafers are selected through the incoming material inspection process, and a cleaning process is performed to remove dust, oil, etc. There are neatly arranged horizontal and vertical cross-cutting lanes I110 on the wafer 100. The cutting lanes I110 pre-divide the wafer 100 into a plurality of vertical MOSFET chips 10. The front side of each vertical MOSFET chip 10 is provided with a source region and a gate region, and the back side is set as a drain region.

[0126] Step 2: Figure 11B As shown, a source conductive pad 13 is made in the source region of the vertical MOSFET chip 10, and a gate conductive pad 15 is set in its gate region by sputtering corrosion, chemical deposition, printing or spraying liquid metal. When a composite conductive metal layer such as a Cu / Sn layer or a Ni / Au layer is made, the process of step 2 needs to be repeated multiple times to form a conductive metal layer of the corresponding material.

[0127] Step 3: Figure 11C As shown, a high-conductivity silver particle sintered body is formed as a conductive circuit layer 30 in the drain region of the vertical MOSFET chip 10 by low-temperature sintering silver connection technology.

[0128] Step 4: Figure 11D and Figure 11E As shown, a plurality of independent chip monomers 10 are formed along the cutting path I 110 by using a cutting process. Figure 11E As shown in the front view, a source conductive pad 13 is provided in the source region of the vertical MOSFET chip 10 , and a gate conductive pad 15 is provided in the gate region thereof.

[0129] Step 5: Figure 11F and Figure 11GAs shown, a three-dimensional metal frame strip 200 is prepared, with the etched back surface facing upward as the working surface. A plurality of hollow patterns 220, transverse cutting lanes III 210, longitudinal cutting lanes III 230, and alignment points 250 are arranged on the three-dimensional metal frame strip 200. The transverse cutting lanes III 210 are arranged on the upper and lower sides of the three-dimensional metal frame strip 200. Each hollow pattern 220 is a discontinuous pattern and is arranged in an array along the transverse cutting lanes III 210 on both sides of the three-dimensional metal frame strip 200, such as the hollow patterns 220 forming a "two" shape. The upper and lower transverse cutting lanes III 210 respectively pass through the upper and lower edges of each hollow pattern 220. The transverse cutting lanes III 210 and the longitudinal cutting lanes III 230 pre-divide the three-dimensional metal frame strip 200 into a plurality of three-dimensional metal frames 20. Each three-dimensional metal frame 20 includes a metal frame body 21 and a drain metal pin 25. The drain metal pin 25 passes through several separately prepared metal pillars of the same height. The bottom of the metal pillars is provided with a glue locking hole 27. The longitudinal section of the glue locking through hole 27 is in an arc shape, a single-line "X" shape or a double-line "X" shape, and the through hole direction is perpendicular to the short side of the vertical MOSFET chip 10, such as Figure 11G shown.

[0130] Specifically, the forming process of the metal column with the arc-shaped glue locking through hole 27 is as follows:

[0131] Prepare a metal sheet 270 with a pre-cut path 271 on the metal sheet 270, such as Figure 11Ga and Figure 11Gb As shown, Figure 11Gb for Figure 11Ga A partially enlarged front view shows that the pre-cutting road 271 divides the metal sheet 270 into metal pillars arranged in an array, and the metal pillars are rectangular parallelepipeds;

[0132] The upper surface of the metal sheet 270 is covered with a photoresist layer 274, such as Figure 11Gc As shown;

[0133] A photoresist pattern 275 is formed by a photoresist forming process. The opening of the photoresist pattern 275 is circular, penetrates the photoresist layer 274 and straddles the cutting street 271 on one of the short sides of the metal pillar.

[0134] Then, the exposed metal in the opening of the photoresist pattern 275 is removed by etching until a circular through hole 276 is formed. Figure 11Gd As shown, the circular through hole 276 straddles the cutting path 271 and removes an arc portion of each adjacent rectangular metal column to form an arc-shaped glue locking through hole 27, and then removes the remaining photoresist, as shown in FIG. Figure 11Ge As shown, the metal sheet 270 is divided along the cutting line 271 to form a plurality of independent metal columns with arc-shaped glue locking holes 27, as shown in FIG. Figure 11Gg shown.

[0135] Specifically, the forming process of the metal column with the single-letter-shaped glue locking through hole 27 is as follows:

[0136] Prepare a metal sheet 270 with a pre-cut path 271 on the metal sheet 270, such as Figure 11Ga and Figure 11Gb As shown, Figure 11Gb for Figure 11Ga A partially enlarged front view shows that the pre-cutting road 271 divides the metal sheet 270 into metal pillars arranged in an array, and the metal pillars are rectangular parallelepipeds;

[0137] The upper surface of the metal sheet 270 is covered with a photoresist layer 274, such as Figure 11Gc As shown;

[0138] A photoresist pattern 275 is formed by a photoresist forming process. The opening of the photoresist pattern 275 is a large rectangular shape, which penetrates the photoresist layer 274 and straddles the cutting road 271 on one of the short sides of the metal pillar. Then, the exposed metal in the opening of the photoresist pattern 275 is removed by an etching process until a large rectangular through hole 278 is formed. Figure 11Gf As shown, the large rectangular through hole 278 straddles the cutting path 271 and removes a portion of each of the adjacent rectangular metal pillars to form a small rectangular glue locking through hole 27.

[0139] Then remove the remaining photoresist, such as Figure 11Gh As shown, the metal sheet 270 is divided along the cutting line 271 to form a plurality of independent metal pillars with single-letter-shaped locking glue holes 27, as shown in FIG. Figure 11Gi shown.

[0140] Through the same process, a metal column with a double-X-shaped glue-locking through hole 27 can be formed.

[0141] These metal pillars are placed around the hollow pattern 220 on the etched surface of the metal frame body 21 through a solder layer II 19 to form drain metal pins 25. This solder can be titanium, copper, silver, nickel, gold, tin, or tin-silver, or a combination thereof. The hollow pattern 220 is pre-cut by transverse cutting lanes III 210 to form diversion holes 221.

[0142] The drain metal pin 25 and the inner side of the three-dimensional metal frame 20 together form a cavity 26; Figure 11G As shown; the drain metal pin 25 is preferably a copper column.

[0143] Step 6: Figure 11H and Figure 11IAs shown, by aligning the alignment point 250, the conductive circuit layer 30 of the drain region on the back side of the new chip monomer 10 is sequentially placed into the cavity 26 of the three-dimensional metal frame bar 200 through the welding layer I 18, thereby achieving electrical connection between the new chip monomer 10 and the etched surface of the metal frame body 21;

[0144] Step 7: Figure 11J As shown, through the film-assisted molding single-sided molding process (FAM), the three-dimensional metal frame bar 200 and the vertical MOSFET chip 10 are covered with a molding material 90 above the three-dimensional metal frame bar 200, and the hollow pattern 220 and the glue locking through hole 27 are filled.

[0145] Step 8: Figure 11K As shown, the upper surface 251 of the drain metal pin 25 of the three-dimensional metal frame bar 200, as well as the upper surface 131 of the source conductive pad and the upper surface 151 of the gate conductive pad of the vertical MOSFET chip 10 are exposed through the grinding process. The upper surface 131 of the source conductive pad and the upper surface 151 of the gate conductive pad are flush with the upper surface 251 of the drain metal pin.

[0146] Step 9: Figure 11L As shown, a conductive metal layer I 61, a conductive metal layer II 63 and a conductive metal layer III 65 are respectively formed on the upper surface 131 of the source conductive pad, the upper surface 151 of the gate conductive pad and the upper surface 251 of the drain metal pin by sputtering etching, chemical deposition, printing or spraying. The conductive metal layer I 61, the conductive metal layer II 63 and the conductive metal layer III 65 are used for subsequent mounting of the packaged chip. Figure 11L shown.

[0147] Step 10: Figure 11M and Figure 11N As shown, the above-mentioned package body is divided into a plurality of package structure units of vertical MOSFET chips along the horizontal cutting street III210 and the vertical cutting street III230, and the drain of the vertical MOSFET chip 10 is led upward to the same plane as the source and gate of the vertical MOSFET chip 10 through the three-dimensional metal frame 20.

[0148] The above description is merely a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the embodiments of the present invention should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A packaging method for a vertical MOSFET chip packaging structure, wherein the process is as follows: Step 1: preparing an incoming wafer (100), wherein the wafer (100) has neatly arranged horizontal and vertical intersecting cutting paths I (110), wherein the cutting paths I (110) pre-divide the wafer (100) into a plurality of vertical MOSFET chips (10), wherein each vertical MOSFET chip (10) has a source region and a gate region on the front side and a drain region on the back side; Step 2: forming a source conductive pad (13) in the source region of the vertical MOSFET chip (10) and setting a gate conductive pad (15) in the gate region thereof by sputtering, etching, chemical deposition, printing or spraying liquid metal in sequence; Step 3: forming a high-conductivity silver particle sintered body as a conductive circuit layer (30) in the drain region of the vertical MOSFET chip (10) by low-temperature sintering silver connection technology; Step 4: Using a cutting process to form a plurality of independent chip monomers (10) along the cutting path I (110); Step 5: Prepare a three-dimensional metal frame strip (200), with the etching surface on the back facing upward as the working surface. A plurality of two-shaped hollow patterns (220), a horizontal cutting path III (210), a vertical cutting path III (230) and a registration point (250) are arranged on the three-dimensional metal frame strip (200). The horizontal cutting path III (210) is set on the upper and lower sides of the three-dimensional metal frame strip (200). Each hollow pattern (220) is a discontinuous pattern, and is distributed along the array of the horizontal cutting path III (210) on the three-dimensional metal frame strip. On both sides of the frame bar (200), upper and lower transverse cutting paths III (210) pass through the upper edge and lower edge of each hollow pattern (220), respectively. The transverse cutting path III (210) and the longitudinal cutting path III (230) pre-divide the three-dimensional metal frame bar (200) into a plurality of three-dimensional metal frames (20). The hollow pattern (220) is pre-cut by the transverse cutting path III (210) to form a guide hole (221). Each three-dimensional metal frame (20) includes a metal frame body (21) and a drain metal pin (25). The drain metal pin (25) and the inner side of the three-dimensional metal frame (20) together form a cavity (26); a glue locking through hole (27) is provided at the bottom of the drain metal pin (25). The longitudinal section of the glue locking through hole (27) is arc-shaped, single-shaped or double-shaped, and the through hole direction is perpendicular to the short side of the vertical MOSFET chip (10); The forming process of the drain metal pin (25): when the three-dimensional metal frame bar (200) is formed, the raw material of the three-dimensional metal frame bar (200) is subjected to multiple half-etching processes to remove excess metal material, thereby forming a three-dimensional metal frame bar (200) with a drain metal pin (25), wherein the drain metal pin (25) is in a concave arc column shape, and the three-dimensional metal frame bar (200) is cut into a plurality of three-dimensional metal frames (20); Or the forming process of the drain metal pin (25): prepare a plurality of metal pillars of the same height, and arrange the metal pillars on the periphery of the hollow pattern (220) of the etched surface of the metal frame body (21) through the welding layer II (19) to form the drain metal pin (25), and the welding layer II (19) is a metal selected from titanium, copper, silver, nickel, gold, and tin, or a combination of several metals; the forming process of the metal pillar: prepare a metal sheet, and divide it into rectangular metal pillars by a blade or a laser; Step 6: Align the chip monomer (10) with its back side facing downwards into the cavity (26) of the three-dimensional metal frame bar (200) through the alignment point (250), so that the conductive circuit layer (30) in the drain region is electrically connected to the etched surface of the metal frame body (21) through the welding layer I (18); Step 7: Using a film-assisted plastic encapsulation single-sided molding process, the three-dimensional metal frame bar (200) and the vertical MOSFET chip (10) are covered with a plastic encapsulation material (90) above the three-dimensional metal frame bar (200), and the hollow pattern (220) is filled; Step 8: exposing the upper surface (251) of the drain metal pin (25) of the three-dimensional metal frame bar (200), and the upper surface (131) of the source conductive pad and the upper surface (151) of the gate conductive pad of the vertical MOSFET chip (10) through a grinding process, wherein the upper surface (131) of the source conductive pad and the upper surface (151) of the gate conductive pad are flush with the upper surface (251) of the drain metal pin; Step nine, forming a conductive metal layer I (61), a conductive metal layer II (63) and a conductive metal layer III (65) on the upper surface of the source conductive pad (131), the upper surface of the gate conductive pad (151) and the upper surface of the drain metal pin (251) respectively by sputtering, etching, chemical deposition, printing or spraying liquid metal; Step 10: Divide the package into a plurality of package structure units of vertical MOSFET chips along the horizontal cutting path III (210) and the vertical cutting path III (230), and lead the drain of the vertical MOSFET chip (10) upward through the three-dimensional metal frame (20) to the same plane as the source and gate of the vertical MOSFET chip (10).

2. The packaging method according to claim 1, wherein: In step 5, the forming process of the metal column with the glue locking through hole (27) provided at the bottom of the drain metal pin (25) is as follows: A metal sheet (270) is prepared, wherein a pre-cutting path (271) is provided on the metal sheet (270), and the pre-cutting path (271) divides the metal sheet (270) into metal columns arranged in an array, and the metal columns are in the form of rectangular parallelepipeds; The upper surface of the metal sheet (270) is covered with a photoresist layer (274); A photoresist pattern (275) is formed by a photoresist forming process, wherein the opening of the photoresist pattern (275) is circular, penetrates the photoresist layer (274) and straddles a cutting path (271) on one of the short sides of the metal column; Then, the exposed metal in the opening of the photoresist pattern (275) is removed by an etching process until a circular through hole (276) is formed. The circular through hole (276) straddles the cutting path (271) and removes an arc-shaped portion of each adjacent rectangular metal column to form an arc-shaped glue locking through hole (27); The remaining photoresist is then removed, and the metal sheet (270) is divided along the cutting path (271) to form a plurality of independent metal pillars with arc-shaped glue-locking through holes (27).

3. The packaging method according to claim 1, wherein: In step 5, the forming process of the metal column of the glue locking through hole (27) with a single-cross section is as follows: A metal sheet (270) is prepared, wherein a pre-cutting path (271) is provided on the metal sheet (270), and the pre-cutting path (271) divides the metal sheet (270) into metal columns arranged in an array, and the metal columns are in the form of rectangular parallelepipeds; The upper surface of the metal sheet (270) is covered with a photoresist layer (274); A photoresist pattern (275) is formed by a photoresist forming process, wherein the opening of the photoresist pattern (275) is a large rectangle, penetrates the photoresist layer (274) and straddles a cutting path (271) on one of the short sides of the metal column; Then, the exposed metal in the opening of the photoresist pattern (275) is removed by an etching process until a large rectangular through hole (278) is formed. The large rectangular through hole (278) straddles the cutting path (271) and removes a portion of each of the adjacent rectangular metal pillars to form a small rectangular glue locking through hole (27); The remaining photoresist is then removed, and the metal sheet (270) is divided along the cutting path (271) to form a plurality of independent metal pillars with single-digit "X"-shaped glue-locking through holes (27).

4. The packaging method according to claim 1, wherein: In step 2, the source conductive pad (13) and the gate conductive pad (15) are formed into a composite conductive metal layer of corresponding materials by repeating the process of step 2 multiple times.

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