Array substrate and display panel

Abstract

The array substrate and the display panel provided by the embodiment of the present application comprise: a substrate, a first gate layer, a first active layer, a second active layer, a second gate layer and a source-drain layer; the first gate layer is arranged on the substrate; the first active layer is arranged on the side of the first gate layer away from the substrate; the second active layer is arranged on the side of the first active layer away from the substrate; the second gate layer is arranged on the side of the second active layer away from the substrate, and the second gate layer, the second active layer, the first active layer and the first gate layer are insulatively arranged; the source-drain layer comprises a source electrode and a drain electrode, the source electrode is electrically connected with the first active layer and the second active layer, and the drain electrode is electrically connected with the first active layer and the second active layer. The array substrate can improve the stability of the thin film transistor device.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to an array substrate and a display panel. BACKGROUND

[0002] There are at least two types of display devices in the prior art, one is liquid crystal display device, and the other is organic light emitting display device. In the display device, the thin film transistor device is a key device for control, which can be used to control the pixel electrode, the touch electrode, the common electrode and the like. For the liquid crystal display device, the thin film transistor device is located not only in the display area but also in the non-display area outside the display area. Generally, the thin film transistor device located in the non-display area is an important component of the gate driving circuit, the source driving circuit, the anti-static circuit and the like. In the gate driving circuit, the source driving circuit or the anti-static circuit, a plurality of circuit units for controlling the conduction and turn-off of the signal are usually included, such as the inverter.

[0003] However, after working at high temperature for a long time, the stability of the thin film transistor device is poor, and the threshold voltage will drift, so that the thin film transistor device is not fully opened after the subsequent period is opened, which affects the display effect of the display panel. Therefore, how to improve the stability of the thin film transistor device is a problem to be solved at present. SUMMARY

[0004] The purpose of the embodiments of the present application is to provide an array substrate and a display panel, which can improve the stability of the thin film transistor device.

[0005] In one aspect, the embodiments of the present application provide an array substrate, comprising: a substrate, a first gate layer, a first active layer, a second active layer, a second gate layer and a source-drain layer; the first gate layer is arranged on the substrate; the first active layer is arranged on the side of the first gate layer away from the substrate; the second active layer is arranged on the side of the first active layer away from the substrate; the second gate layer is arranged on the side of the second active layer away from the substrate, and the second gate layer, the second active layer, the first active layer and the first gate layer are insulated; the source-drain layer includes a source and a drain, the source is electrically connected with the first active layer and the second active layer; and the drain is electrically connected with the first active layer and the second active layer.

[0006] Optionally, in some embodiments of the present application, the first active layer comprises a first source region, a first channel region and a first drain region, the first channel region is located between the first source region and the first drain region, the source is connected with the first source region, the drain is connected with the first drain region, and a vertical projection of the first gate layer on the first active layer overlaps the first channel region.

[0007] Optionally, in some embodiments of the present application, a vertical projection of the first active layer on the substrate substrate covers a vertical projection of the second active layer on the substrate substrate, the source is electrically connected with a left side of the second active layer, and the drain is electrically connected with a right side of the second active layer.

[0008] Optionally, in some embodiments of the present application, the source and the drain each comprise a first connecting portion, a second connecting portion and a third connecting portion, the first connecting portion is located between the first active layer and the second active layer, the second connecting portion is arranged in the same layer as the second active layer, and the third connecting portion is located on a side of the second connecting portion away from the first connecting portion.

[0009] Optionally, in some embodiments of the present application, a cross-sectional width of the third connecting portion is greater than a cross-sectional width of the second connecting portion, and the cross-sectional width of the second connecting portion is greater than a cross-sectional width of the first connecting portion.

[0010] Optionally, in some embodiments of the present application, a cross-sectional width of the third connecting portion is greater than a cross-sectional width of the first connecting portion, and the cross-sectional width of the first connecting portion is greater than a cross-sectional width of the second connecting portion.

[0011] Optionally, in some embodiments of the present application, the first gate layer comprises a first gate, the second gate layer comprises a second gate, and a vertical projection of the first gate on the substrate substrate covers a vertical projection of the second gate on the substrate substrate.

[0012] Optionally, in some embodiments of the present application, the second gate layer further comprises a third gate, the third gate is arranged in the same layer as the second gate and is insulated, and a vertical projection of the first gate on the substrate substrate covers vertical projections of the second gate and the third gate on the substrate substrate.

[0013] Optionally, in some embodiments of the present application, a material of one of the first active layer and the second active layer comprises indium gallium zinc oxide, and a material of the other of the first active layer and the second active layer comprises polysilicon.

[0014] In another aspect, the present application provides a display panel, comprising a color film substrate and the array substrate as described above, wherein the color film substrate is arranged opposite to the array substrate.

[0015] In the array substrate and the display panel provided by the embodiments of the present application, the array substrate comprises a substrate, a first gate layer, a first active layer, a second active layer, a second gate layer and a source-drain layer; the first gate layer is arranged on the substrate; the first active layer is arranged on a side of the first gate layer away from the substrate; the second active layer is arranged on a side of the first active layer away from the substrate; the second gate layer is arranged on a side of the second active layer away from the substrate, and the second gate layer, the second active layer, the first active layer and the first gate layer are insulatively arranged; the source-drain layer comprises a source and a drain, the source is electrically connected with the first active layer and the second active layer, and the drain is electrically connected with the first active layer and the second active layer. The array substrate can improve the stability of the thin film transistor device and prolong the service life thereof. BRIEF DESCRIPTION OF DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort.

[0017] Figure 1 A top view of the array substrate provided by the first embodiment of the present application;

[0018] Figure 2 A first equivalent circuit diagram of the array substrate in the first embodiment of the present application; Figure 1 A first cross-sectional schematic view of the array substrate along the direction of AA' in the first embodiment of the present application;

[0019] Figure 3 A second equivalent circuit diagram of the array substrate in the first embodiment of the present application; Figure 1 A first equivalent circuit diagram of the array substrate in the first embodiment of the present application;

[0020] Figure 4 A second equivalent circuit diagram of the array substrate in the first embodiment of the present application; Figure 1 A second equivalent circuit diagram of the array substrate in the first embodiment of the present application;

[0021] Figure 5 A second cross-sectional schematic view of the array substrate along the direction of AA' in the first embodiment of the present application; Figure 1 A second cross-sectional schematic view of the array substrate along the direction of AA' in the first embodiment of the present application;

[0022] Figure 6 A top view of the array substrate provided by the second embodiment of the present application;

[0023] Figure 7 A top view of the array substrate provided by the second embodiment of the present application; Figure 6A cross-sectional schematic diagram of the array substrate along the BB' direction;

[0024] Figure 8 This is a schematic diagram of the structure of the display panel provided in an embodiment of this application. Detailed Implementation

[0025] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0026] This application provides an array substrate and a display panel, which can improve the stability of thin-film transistors. Detailed descriptions are provided below. It should be noted that the order of description of the following embodiments is not intended to limit the preferred order of embodiments. Furthermore, in the description of this application, the term "comprising" means "including but not limited to". The terms "first", "second", "third", etc., are used merely as identifiers to distinguish different objects, and are not used to describe a specific order.

[0027] Please see Figures 1 to 4 , Figure 1 A top view of the array substrate provided in the first embodiment of this application; Figure 2 for Figure 1 A cross-sectional view of the array substrate along the ' direction; Figure 3 for Figure 1 The first equivalent circuit diagram of the array substrate in the diagram; Figure 4 for Figure 1 The second equivalent circuit diagram of the array substrate in the image. For example... Figures 1 to 4 As shown, this application provides an array substrate 100, which includes: a substrate 10, a first gate layer 20, a first active layer 30, a second active layer 40, a second gate layer 50, and a source-drain layer 60; the first gate layer 20 is disposed on the substrate; the first active layer 30 is disposed on the side of the first gate layer 20 away from the substrate; the second active layer 40 is disposed on the side of the first active layer 30 away from the substrate; the second gate layer 50 is disposed on the side of the second active layer 40 away from the substrate, and the second gate layer 50, the second active layer 40, the first active layer 30, and the first gate layer 20 are insulated from each other; the source-drain layer 60 includes a source 61 and a drain 62, the source 61 is electrically connected to the first active layer 30 and the second active layer 40, and the drain 62 is electrically connected to the first active layer 30 and the second active layer 40.

[0028] In this embodiment, the first gate layer 20 includes a first gate 21, the second gate layer 50 includes a second gate 51, and the orthogonal projection of the first gate 21 on the substrate covers the orthogonal projection of the second gate 51 on the substrate.

[0029] In this embodiment, the array substrate 100 includes a first gate 21, a first active layer 30, a source 61, and a drain 62 to form a first thin-film transistor. The array substrate 100 also includes a second gate 51, a second active layer 40, and shared source 61 and drain 62 to form a second thin-film transistor. This design helps reduce the number of data lines electrically connected to the source 61, thereby reducing the number of output pins of the driver chip and lowering product costs. More importantly, the first gate 21 and the second gate 51 can be controlled independently. This allows for the alternating use of the first and second thin-film transistors by controlling scan signals of different polarities applied to the first gate 21 and the second gate 51. This avoids the first thin-film transistor from operating for extended periods, which could cause a positive shift in its threshold voltage, reducing its stability and affecting the product's display performance.

[0030] In this embodiment, the first active layer 30 includes a first source region 31, a first channel region 32, and a first drain region 33. The first channel region 32 is located between the first source region 31 and the first drain region 33. The source 61 is connected to the first source region 31, and the drain 62 is connected to the first drain region 33. The vertical orthographic projection of the first gate 21 on the first active layer 30 coincides with the first channel region 32.

[0031] In this embodiment, the vertical orthographic projection of the first active layer 30 on the substrate covers the vertical orthographic projection of the second active layer 40 on the substrate. The source 61 is electrically connected to the left side of the second active layer 40, and the drain 62 is electrically connected to the right side of the second active layer 40.

[0032] In this embodiment, both the source 61 and the drain 62 include a first connection portion 601, a second connection portion 602, and a third connection portion 603. The first connection portion 601 is located between the first active layer 30 and the second active layer 40. The second connection portion 602 is disposed on the same layer as the second active layer 40. The third connection portion 603 is located on the side of the second connection portion 602 away from the first connection portion 601.

[0033] In this embodiment, the cross-sectional width of the third connection portion 603 is greater than the cross-sectional width of the second connection portion 602, and the cross-sectional width of the second connection portion 602 is greater than the cross-sectional width of the first connection portion 601. This design helps to reduce the parasitic capacitance between the source and drain terminals 61 and 62 and the first gate 21 and the second gate 51, thereby improving the stability and lifespan of the thin-film transistor.

[0034] In the embodiment of the present application, the array substrate further comprises an interlayer dielectric layer 70, which is arranged between the first active layer 30 and the second active layer 40, so as to avoid mutual interference of the first thin film transistor and the second thin film transistor during operation.

[0035] In the embodiment of the present application, the materials of the first active layer 30 and the second active layer 40 are different. When the materials of the first active layer 30 and the second active layer 40 are different, the on-voltages of the first active layer 30 and the second active layer 40 are also different. Preferably, the material of one of the first active layer 30 and the second active layer 40 comprises indium gallium zinc oxide, and the material of the other of the first active layer 30 and the second active layer 40 comprises polysilicon.

[0036] Specifically, the active layer made of polysilicon material has a high electron mobility and a fast electron moving speed, so that a large on-current is required for the thin film transistor device. The active layer made of indium gallium zinc oxide material has a low electron mobility and a slow electron moving speed, so that the thin film transistor is stable under light or high temperature environment, and can effectively suppress the leakage current even under special environment such as light or high temperature, so that the thin film transistor device has a small leakage current. For example, the first active layer 30 is made of indium gallium zinc oxide material, and the second active layer 40 is made of polysilicon material. Since the on-voltages of the first active layer 30 and the second active layer 40 are different, the mutual interference between the first thin film transistor and the second thin film transistor is avoided.

[0037] Such design can realize high mobility and low leakage current, and realize alternate conduction of the first thin film transistor and the second thin film transistor, so as to further improve the stability and prolong the service life of the thin film transistor, and improve the display effect of the product.

[0038] Further, the materials of the first active layer 30 and the second active layer 40 can also be the same. Specifically, the materials of the first active layer 30 and the second active layer 40 both comprise indium gallium zinc oxide, or both comprise polysilicon. The present application does not make any limitation in this regard.

[0039] In the embodiment of the present application, the array substrate further comprises a first insulating layer 80, a second insulating layer 81 and a third insulating layer 82. The first insulating layer 80 is arranged between the first gate 21 and the first active layer 30, and the second insulating layer 81 is arranged between the second gate 51 and the second active layer 40. Further, the array substrate further comprises a third insulating layer 82, which is arranged on the side of the second gate 51 away from the substrate 10.

[0040] In the embodiments of the present application, the materials of the first insulating layer 80, the second insulating layer 81 and the third insulating layer 82 all include at least one of silicon oxide, silicon nitride, organic silicon resin and acrylic resin. Such design can avoid mutual interference between the film layers and affect the display effect.

[0041] In the embodiments of the present application, as shown in Figure 3 the array substrate includes a display area, the first thin film transistor T1 and the second thin film transistor T2 are both located in the display area, the display area includes scan lines G(1, 2...n), data lines D(1, 2...n) and a plurality of pixel units arranged in an array, and the first thin film transistor T1 and the second thin film transistor T2 are located in one pixel unit, wherein the first gate of the first thin film transistor T1 is electrically connected with the first scan line G1, the second gate of the second thin film transistor T2 is electrically connected with the second scan line G2, and the first thin film transistor T1 and the second thin film transistor T2 are electrically connected with each other through the source and the drain, wherein the source is electrically connected with the data line D(1, 2...n), and the drain is electrically connected with the pixel electrode.

[0042] In the embodiments of the present application, as shown in Figure 4 the array substrate includes a non-display area, and the first thin film transistor T1 and the second thin film transistor T2 are both located in the non-display area. The first thin film transistor T1 and the second thin film transistor T2 in the present application are both used to alternately open under the control of the shunt control signal line DEMUX(1, 2...n) and the data line D(1, 2...n) in the DEMUX (Demultiplexer, demultiplexer) control signal generation circuit, so as to improve the stability and prolong the service life, while being beneficial to reducing the pin number of the driving chip, reducing the production cost of the display panel, realizing the narrow frame design. Specifically, the first gate of the first thin film transistor T1 is electrically connected with the first shunt control signal line DEMUX_1, the second gate of the second thin film transistor T2 is electrically connected with the second shunt control signal line DEMUX_2, and the first thin film transistor T1 and the second thin film transistor T2 are electrically connected with each other through the source and the drain, wherein the source is electrically connected with the data signal input port S(1, 2...n), and the drain is electrically connected with the corresponding data line D(1, 2...n).

[0043] The array substrate provided in the embodiments of the present application can improve the stability of the thin film transistor and prolong the service life by setting different gate voltages to control the first thin film transistor and the second thin film transistor to alternately conduct.

[0044] As a specific embodiment of the present application, please refer to Figure 5 , Figure 5 ​Figure 1 The second cross-sectional schematic view of the array substrate in the direction of AA' is shown in FIG. 2B. As shown in FIG. 2B, the present application provides an array substrate 200, which is different from the array substrate 100 in that the cross-sectional width of the third connecting part 603 of the source-drain layer 60 is greater than the cross-sectional width of the first connecting part 601, and the cross-sectional width of the first connecting part 601 is greater than the cross-sectional width of the second connecting part 602. Such a design can increase the contact area between the second active layer 40 and the source 61 and the drain 62, avoid short circuit or open circuit caused by insufficient contact area, and further improve the stability and service life of the thin film transistor. Figure 5 As a specific embodiment of the present application, please refer to FIG. 3A, which is a top view of the array substrate provided by the second embodiment of the present application.

[0045] Figures 6 to 7 As a specific embodiment of the present application, please refer to FIG. 3A, which is a top view of the array substrate provided by the second embodiment of the present application. Figure 6 Figure 7 As a specific embodiment of the present application, please refer to FIG. 3A, which is a top view of the array substrate provided by the second embodiment of the present application. Figure 6 The cross-sectional schematic view of the array substrate in the direction of BB' is shown in FIG. 3B. As shown in FIG. 3B, the present application provides an array substrate 300, which is different from the array substrate 100 in that the second gate layer 50 of the array substrate 300 further includes a third gate 52, the third gate 52 is in the same layer as the second gate 51 and is insulatively arranged, the vertical projection of the first gate 21 on the substrate 10 covers the vertical projection of the second gate 51 and the third gate 52 on the substrate 10, and specifically, the charging polarity of the third gate 52 is the same as that of the second gate 51. Figures 6 to 7 Such a design is conducive to reducing the overlapping area between the first gate 21 and the second gate 51 and the third gate 52, thereby reducing the parasitic capacitance and lowering the resistance, improving the stability of the thin film transistor, and improving the display effect and service life of the display panel. On the other hand, it is conducive to increasing the on-state current, further improving the display effect.

[0046] In the embodiment of the present application, the array substrate 300 includes a substrate 10, a first gate layer 20, a first active layer 30, a second active layer 40, a second gate layer 50, and a source-drain layer 60; the first gate layer 20 is arranged on the substrate; the first active layer 30 is arranged on the side of the first gate layer 20 away from the substrate; the second active layer 40 is arranged on the side of the first active layer 30 away from the substrate; the second gate layer 50 is arranged on the side of the second active layer 40 away from the substrate, and the second gate layer 50, the second active layer 40, the first active layer 30, and the first gate layer 20 are insulatively arranged; the source-drain layer 60 includes a source 61 and a drain 62, the source 61 is electrically connected with the first active layer 30 and the second active layer 40; and the drain 62 is electrically connected with the first active layer 30 and the second active layer 40.

[0047] In the embodiment of the present application, the array substrate 300 includes a substrate 10, a first gate layer 20, a first active layer 30, a second active layer 40, a second gate layer 50, and a source-drain layer 60; the first gate layer 20 is arranged on the substrate; the first active layer 30 is arranged on the side of the first gate layer 20 away from the substrate; the second active layer 40 is arranged on the side of the first active layer 30 away from the substrate; the second gate layer 50 is arranged on the side of the second active layer 40 away from the substrate, and the second gate layer 50, the second active layer 40, the first active layer 30, and the first gate layer 20 are insulatively arranged; the source-drain layer 60 includes a source 61 and a drain 62, the source 61 is electrically connected with the first active layer 30 and the second active layer 40; and the drain 62 is electrically connected with the first active layer 30 and the second active layer 40.​​

[0048] In the embodiment of the present application, the first gate layer 20 comprises the first gate 21, and the second gate layer 50 comprises the second gate 51. The orthogonal projection of the first gate 21 on the substrate covers the orthogonal projection of the second gate 51 on the substrate.

[0049] In the embodiment of the present application, the array substrate 300 comprises the first gate 21, the first active layer 30, the source 61 and the drain 62 to form the first thin film transistor; and the array substrate 300 further comprises the second gate 51, the second active layer 40, and the common source 61 and drain 62 to form the second thin film transistor. Such design is advantageous to reduce the number of data lines electrically connected to the source 61, thereby reducing the number of output pins of the driving chip and lowering the product cost. More importantly, the first gate 21 and the second gate 51 can be controlled separately, so as to realize the alternate use of the first thin film transistor and the second thin film transistor by controlling the different polarity of the scanning signals loaded on the first gate 21 and the second gate 51, thereby avoiding the long-term work of the first thin film transistor, which leads to the positive shift of the threshold voltage and reduces the stability of the first thin film transistor, thereby affecting the display effect of the product.

[0050] In the embodiment of the present application, the first active layer 30 comprises the first source region 31, the first channel region 32 and the first drain region 33. The first channel region 32 is located between the first source region 31 and the first drain region 33. The source 61 is connected to the first source region 31, and the drain 62 is connected to the first drain region 33. The vertical orthogonal projection of the first gate 21 on the first active layer 30 coincides with the first channel region 32.

[0051] In the embodiment of the present application, the vertical orthogonal projection of the first active layer 30 on the substrate covers the vertical orthogonal projection of the second active layer 40 on the substrate. The source 61 is electrically connected to the left side of the second active layer 40, and the drain 62 is electrically connected to the right side of the second active layer 40.

[0052] In the embodiment of the present application, the source 61 and the drain 62 each comprise the first connecting part 601, the second connecting part 602 and the third connecting part 603. The first connecting part 601 is located between the first active layer 30 and the second active layer 40. The second connecting part 602 is arranged in the same layer as the second active layer 40. The third connecting part 603 is located on the side of the second connecting part 602 away from the first connecting part 601.

[0053] In the embodiment of the present application, the cross-sectional width of the third connecting part 603 is greater than the cross-sectional width of the second connecting part 602, and the cross-sectional width of the second connecting part 602 is greater than the cross-sectional width of the first connecting part 601. Such design is advantageous to reduce the parasitic capacitance between the source 61, the drain 62, the first gate 21 and the second gate 51, thereby improving the stability and service life of the thin film transistor.

[0054] In the embodiment of the present application, the array substrate further comprises an interlayer dielectric layer 70, which is arranged between the first active layer 30 and the second active layer 40, so as to avoid mutual interference of the first thin film transistor and the second thin film transistor during operation.

[0055] In the embodiment of the present application, the materials of the first active layer 30 and the second active layer 40 are different. When the materials of the first active layer 30 and the second active layer 40 are different, the turn-on voltages of the first active layer 30 and the second active layer 40 are also different. Preferably, the material of one of the first active layer 30 and the second active layer 40 comprises indium gallium zinc oxide, and the material of the other of the first active layer 30 and the second active layer 40 comprises polysilicon.

[0056] Such design can realize high mobility and low leakage current, and realize alternate turn-on of the first thin film transistor and the second thin film transistor, thereby further improving the stability of the thin film transistor and prolonging the service life of the thin film transistor, and improving the display effect of the product.

[0057] Further, the materials of the first active layer 30 and the second active layer 40 can also be the same. Specifically, the materials of the first active layer 30 and the second active layer 40 both comprise indium gallium zinc oxide, or the materials of the first active layer 30 and the second active layer 40 both comprise polysilicon. The present application does not make any limitation in this regard.

[0058] In the embodiment of the present application, the array substrate further comprises a first insulating layer 80, a second insulating layer 81 and a third insulating layer 82. The first insulating layer 80 is arranged between the first gate 21 and the first active layer 30, and the second insulating layer 81 is arranged between the second gate 51, the third gate 52 and the second active layer 40. Further, the array substrate further comprises a third insulating layer 82, which is arranged on the side of the second gate 51 and the third gate 52 away from the substrate 10.

[0059] In the embodiment of the present application, the materials of the first insulating layer 80, the second insulating layer 81 and the third insulating layer 82 all comprise at least one of silicon oxide, silicon nitride, organic silicon resin and acrylic resin. Such design can avoid mutual interference between the film layers and affect the display effect.

[0060] The array substrate provided by the embodiment of the present application can control alternate turn-on between the first thin film transistor and the second thin film transistor by setting different gate voltages, avoid positive shift of threshold voltage caused by long-time operation of a single thin film transistor, and improve the stability of the thin film transistor and prolong the service life of the thin film transistor.

[0061] Please refer to Figure 8 , Figure 8 The structural schematic diagram of the display panel provided by the embodiment of the present application is shown in FIG. 1. Figure 8As shown, the display panel 400 provided by the present application comprises a color film substrate 410 and an array substrate 100 / 200 / 300, and the color film substrate 410 is arranged opposite to the array substrate 100 / 200 / 300.

[0062] The array substrate in the display panel provided by the present application controls the alternate conduction between the first thin film transistor and the second thin film transistor by setting different gate voltages, avoids the threshold voltage positive shift caused by the long-time work of a single thin film transistor, and can improve the stability of the thin film transistor, prolong the service life of the thin film transistor, and improve the display effect of the display panel.

[0063] The display panel can be used in any product or component with display function, such as mobile phones, tablet computers, televisions, displays, notebook computers, digital photo frames, navigation devices, etc. Other essential components of the display panel should be understood by those skilled in the art, and will not be described here, nor should it be considered as a limitation on the present application.

[0064] The above has introduced in detail the array substrate and the display panel provided by the embodiments of the present application, and the principles and implementation manners of the present application have been described by applying specific examples. The above description of the embodiments is only used to help understand the method of the present application and its core idea; meanwhile, for those skilled in the art, according to the idea of the present application, the specific implementation manner and application range will be changed, and the above description should not be understood as a limitation on the present application.

Claims

1. An array substrate, characterized by, The array substrate comprises: a substrate substrate; a first gate layer disposed on the substrate substrate; a first active layer disposed on a side of the first gate layer away from the substrate substrate; a second active layer disposed on a side of the first active layer away from the substrate substrate; a second gate layer disposed on a side of the second active layer away from the substrate substrate, the second gate layer, the second active layer, the first active layer and the first gate layer being insulatively arranged; a source-drain layer, the source-drain layer comprising a source and a drain, the source being electrically connected with the first active layer and the second active layer, and the drain being electrically connected with the first active layer and the second active layer; the source and the drain each comprising a first connecting portion, a second connecting portion and a third connecting portion, the first connecting portion being located between the first active layer and the second active layer, the second connecting portion being arranged in the same layer as the second active layer, and the third connecting portion being located on a side of the second connecting portion away from the first connecting portion; a cross-sectional width of the third connecting portion being greater than a cross-sectional width of the first connecting portion, and the cross-sectional width of the first connecting portion being greater than a cross-sectional width of the second connecting portion. the first active layer comprising a first source region, a first channel region and a first drain region, the first channel region being located between the first source region and the first drain region, the source being connected with the first source region, the drain being connected with the first drain region, and a vertical orthographic projection of the first gate layer on the first active layer overlapping the first channel region.

2. The array substrate of claim 1, wherein, a vertical orthographic projection of the first active layer on the substrate substrate covering a vertical orthographic projection of the second active layer on the substrate substrate, the source being electrically connected with a left side edge of the second active layer, and the drain being electrically connected with a right side edge of the second active layer.

3. The array substrate of claim 2, wherein, the cross-sectional width of the third connecting portion being greater than the cross-sectional width of the second connecting portion, and the cross-sectional width of the second connecting portion being greater than the cross-sectional width of the first connecting portion.

4. The array substrate of claim 1, wherein, the first gate layer comprising a first gate, and the second gate layer comprising a second gate, a vertical orthographic projection of the first gate on the substrate substrate covering a vertical orthographic projection of the second gate on the substrate substrate.

5. The array substrate of claim 1, wherein, the second gate layer further comprising a third gate, the third gate being arranged in the same layer as the second gate and being insulatively arranged, and a vertical orthographic projection of the first gate on the substrate substrate covering vertical orthographic projections of the second gate and the third gate on the substrate substrate.

6. The array substrate of claim 5, wherein, a material of one of the first active layer and the second active layer comprising indium gallium zinc oxide, and a material of the other of the first active layer and the second active layer comprising polysilicon.

7. The array substrate of claim 1, wherein, The array substrate is arranged opposite to a color filter substrate.

8. A display panel, characterized by, The array substrate is arranged opposite to a color filter substrate.

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