Clock synchronization method and device

Abstract

The present application provides a method for clock synchronization, including: a receiving device receives multiple data blocks through multiple physical layer modules PHY, the multiple data blocks include multiple first data blocks; the receiving device performs timestamp sampling on the multiple data blocks to generate multiple receiving timestamps; the receiving device aligns the multiple receiving timestamps based on the first receiving timestamp; the receiving device generates a clock synchronization message according to the multiple data blocks; the receiving device writes the value of the second receiving timestamp into the clock synchronization message, wherein the second receiving timestamp is the receiving timestamp of the second data block determined based on the aligned multiple receiving timestamps, and the second data block is a data block in the multiple data blocks used for sending timestamp sampling. The clock synchronization method provided in the present application can correct the skew between multiple data blocks of the same FlexE customer after they arrive at the receiving device.

Description

[0001] This application is a divisional application of an application filed with the State Intellectual Property Office of China with an application date of October 30, 2017, application number 201780094495.0, and invention name “Clock Synchronization Method and Device”. Technical Field

[0002] The present application relates to the field of communications, and in particular to a method and device for clock synchronization. Background Art

[0003] Flexible Ethernet (FlexE) is a type of Ethernet developed on the basis of traditional Ethernet. FlexE defines a variable rate interface between a router and an optical transport network (OTN), with the main purpose of simplifying the mapping and transmission of Ethernet interfaces on OTN as much as possible. Based on rate binding technology and the flexible mapping between Ethernet interfaces and OTN, FlexE can achieve higher transmission rates and transmission bandwidth.

[0004] During the transmission process, the message in FlexE is divided into multiple data packets and transmitted through different physical layer modules (PHY). After receiving multiple data packets, the receiving device needs to recover the Ethernet message from the multiple data packets according to the overhead frame. Multiple data blocks will undergo the mapping from FlexE client to PHY during the transmission process. Since FlexE has multiple PHYs, multiple data blocks from the same FlexE client may be mapped to any one or more PHYs. In addition, since the mapping relationship may change during the transmission process, the data blocks of the same FlexE client may appear on different PHYs at different times, which ultimately causes skew between multiple data blocks from the same FlexE client after they arrive at the receiving device, and the amount of skew cannot be estimated, causing the receiving device to be unable to accurately determine the reception time of the clock synchronization message. Summary of the invention

[0005] The present application provides a clock synchronization method and device, which generates multiple receiving timestamps by sampling the timestamps of received data blocks and aligning the multiple receiving timestamps. It is possible to correct the skew of multiple data blocks from the same FlexE customer after they arrive at a receiving device, thereby accurately determining the receiving time of the clock synchronization message.

[0006] In a first aspect, a clock synchronization method is provided, including: a receiving device receives multiple data blocks through multiple physical layer modules PHY, the multiple data blocks include multiple leading data blocks, the leading data block is the data block that first arrives at the receiving device among the data blocks transmitted in the PHY, and the multiple leading data blocks correspond one-to-one to multiple PHYs; the receiving device performs timestamp sampling on the multiple data blocks to generate multiple receiving timestamps; the receiving device aligns the multiple receiving timestamps based on the first receiving timestamp, the first receiving timestamp is the receiving timestamp corresponding to the first data block among the multiple receiving timestamps, the first data block is the data block transmitted through the first PHY, and the first PHY is the PHY corresponding to the leading data block that arrives at the receiving device latest among the multiple leading data blocks; the receiving device generates a clock synchronization message according to the multiple data blocks; the receiving device writes the value of the second receiving timestamp into the clock synchronization message, wherein the second receiving timestamp is the receiving timestamp of the second data block determined based on the aligned multiple receiving timestamps, the second data block is the data block used for sending timestamp sampling among the multiple data blocks, and the sending timestamp of the second data block is the sending timestamp of the clock synchronization message.

[0007] According to the technical solution provided in this embodiment, the receiving device continuously and periodically stamps (i.e., performs timestamp sampling) the data blocks received by each PHY, generates multiple receiving timestamps, and the multiple receiving timestamps include the timestamps corresponding to the data blocks (i.e., the second data blocks) used for sending timestamp sampling in the multiple data blocks, and aligns the timestamps, that is, waits for the last PHY (i.e., the first PHY) among the multiple PHYs to receive the overhead block (OH), and adjusts the timestamps of the data blocks received by other PHYs in the multiple PHYs based on the timestamp (i.e., the first timestamp) of the first data block received after the first PHY receives the overhead block, and regards the first timestamp as the common timestamp of the first data block received after all PHYs receive the overhead block, thereby aligning the time when the multiple data blocks arrive at the receiving device. The multiple data blocks include the data blocks corresponding to the clock synchronization message. When the clock synchronization message is restored, the receiving timestamp corresponding to the second data block can be determined, and the timestamp corrects the skew of the multiple data blocks from the same FlexE customer after they arrive at the receiving device.

[0008] Optionally, the receiving device aligns multiple receiving timestamps based on the first receiving timestamp, including: the receiving device adjusts the values ​​of the multiple receiving timestamps based on the duration of the receiving cycle and the first receiving timestamp.

[0009] Optionally, the duration of the receiving cycle is equal to the duration required for the receiving device to receive X bits of data, where X is the smaller value of the data bus width of the receiving device or the data buffer width of the serial-to-parallel conversion port of the receiving device.

[0010] The smaller the bit width, the shorter the receiving cycle, the higher the sampling frequency of the receiving timestamp, and the finer the time granularity of adjusting multiple timestamps at the same time, which is conducive to improving the accuracy of the receiving timestamp of the final clock synchronization message.

[0011] Optionally, before the receiving device generates a clock synchronization message according to the multiple data blocks, the method further includes: the receiving device deletes a receiving timestamp other than a receiving timestamp corresponding to the first PHY.

[0012] After the alignment process, the receiving timestamps of the various PHYs are the same, so only the receiving timestamp of one PHY may be retained, thereby reducing the occupation of storage space.

[0013] Optionally, the second data block is a data block corresponding to a start of frame delimiter (SFD) of the clock synchronization message.

[0014] SFD is the first field sent and received in the clock synchronization message. Traditional Ethernet uses SFD as the reference point for timestamp sampling. Therefore, using the first bit received in the receiving cycle as the timestamp sampling point can improve the compatibility of the FlexE clock synchronization method.

[0015] Optionally, the clock synchronization message is carried in a FlexE client payload.

[0016] The method provided in this embodiment receives the clock synchronization message through the client payload of FlexE, which is the same as the method of receiving the clock synchronization message of the traditional Ethernet, thereby improving the compatibility of the FlexE clock synchronization method. In addition, in the scenario of FlexE to FlexE direct connection, the sending timestamp is directly passed to the downstream. Compared with the method of sending timestamps through overhead frames in the prior art, this embodiment does not need to extract the sending timestamp from the client payload and put it into the overhead frame in the sending device, nor does it need to extract the sending timestamp from the overhead frame and put it into the client payload in the receiving device, thereby reducing the logic complexity.

[0017] In a second aspect, a clock synchronization device is provided, which can implement the function performed by the receiving device in the method involved in the first aspect, and the function can be implemented by hardware or by hardware executing corresponding software. The hardware or software includes one or more units or modules corresponding to the above functions.

[0018] In one possible design, the structure of the device includes a processor and a communication interface, and the processor is configured to support the device to perform the corresponding functions in the method involved in the first aspect. The communication interface is used to support communication within the device and communication between the device and other devices. The device may also include a memory, which is used to couple with the processor and store program instructions and data necessary for the device.

[0019] In a third aspect, a computer-readable storage medium is provided, in which a computer program code is stored. When the computer program code is executed by a processing unit or a processor, a receiving device executes the method described in the first aspect.

[0020] In a fourth aspect, a chip is provided, in which instructions are stored, and when the instructions are executed on a receiving device, the chip executes the method of the first aspect.

[0021] In a fifth aspect, a computer program product is provided, which includes: a computer program code, which, when executed by a communication unit or a communication interface of a receiving device, and a processing unit or a processor, enables the sending device to execute the method of the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is a schematic diagram of the general architecture of FlexE;

[0023] Figure 2 is a schematic diagram of a partial architecture of FlexE applicable to the present application;

[0024] Figure 3 It is a schematic diagram of the data packet format of an Ethernet message;

[0025] Figure 4 is a schematic diagram of a method for transmitting messages via dual PHYs;

[0026] Figure 5 is a schematic diagram of the result of mapping data packets of dual clients on dual PHYs;

[0027] Figure 6 is a schematic diagram of the skew relationship between multiple PHYs;

[0028] Figure 7 is a schematic diagram of a clock synchronization method provided by the present application;

[0029] Figure 8 is a schematic diagram of a method for aligning receiving timestamps provided by the present application;

[0030] Fig. 9 is a schematic diagram of a possible receiving device provided by the present application;

[0031] Fig.10 It is a schematic diagram of another possible receiving device provided by the present application. DETAILED DESCRIPTION

[0032] The technical solution in this application will be described below in conjunction with the accompanying drawings.

[0033] In traditional Ethernet, after the service flow comes out of the switching network board, it is generally processed by modules or devices such as the traffic management (TM) module, network processing units (NPUs), media access control (MAC) layer module, and physical layer module (hereinafter referred to as "PHY") in sequence.

[0034] The TM module performs quality of service (QoS) processing on service flows according to the available bandwidth of the network and the priority of the service flows. For example, if the available bandwidth of the network is not enough to transmit all service flows, the TM module can transmit high-priority service flows and perform packet loss processing on low-priority service flows.

[0035] NP is a chip for processing Ethernet services and is used to process Ethernet frames, including parsing and routing lookup.

[0036] The MAC layer module is mainly responsible for connecting and controlling the physical medium of the physical layer. Service messages in Ethernet can encapsulate and decapsulate physical layer information at this layer.

[0037] PHY can be defined as providing mechanical, electronic, functional and normative characteristics for establishing, maintaining and removing the physical link required for data transmission. The PHY mentioned in this article may include physical layer working devices at both ends of the transmitter and receiver, and optical fibers between the two ends of the transmitter and receiver. The physical layer working devices may include, for example, Ethernet physical layer interface devices.

[0038] See also Figure 1 Based on traditional Ethernet, FlexE introduces new concepts such as bundling group, flexible Ethernet client (FlexEclient, hereinafter referred to as "client"), time slot configuration table (calendar), flexible Ethernet time division multiplexing layer (FlexEshim, hereinafter referred to as "time division multiplexing layer"), etc.

[0039] Bundled group: A bundled group may be composed of multiple PHYs, for example, 1 to 256 PHYs supporting 100 Gigabit Ethernet (GE) rates.

[0040] Client: A client can be considered as an Ethernet stream based on a physical address. Clients sent through the same bundle group need to share the same clock, and these clients need to adapt according to the allocated time slot rate. The bandwidth overhead of each client can be adapted by inserting / deleting idle blocks.

[0041] Slot: The bandwidth resources of a PHY are usually divided into multiple slots (for example, 20 slots). When actually used, the service data will be encapsulated into the slot first, and then the slot should be mapped to the PHY in the bundled group. The mapping relationship between the slot and the PHY is recorded in the FlexE slot configuration table. FlexE generally supports 2 sets of slot configuration tables, one of which is the slot configuration table currently in use, and the other can be used as a backup, and the two sets of slot configuration tables can be switched between each other. The specific switching time can be negotiated by the upstream and downstream, and switched synchronously, so that when the service configuration of a customer changes, the services of other customers will not be affected.

[0042] Time division multiplexing layer: The main function of the time division multiplexing layer is to slice the service data according to the same clock, and encapsulate the sliced ​​service data into pre-divided time slots, and then map the divided time slots to the PHY in the bundled group for transmission according to the pre-configured time slot configuration table (which can be configured by the user), where each time slot is mapped to a PHY in the bundled group.

[0043] As a technology based on time division multiplexing (TDM), FlexE breaks all Ethernet messages into 64B / 66B ("B" is short for "bit") data blocks, and maps these data blocks to multiple different PHYs based on time slots. Taking 100GE PHY as an example, each 100GE PHY corresponds to 20 64B / 66B code blocks, and each code block corresponds to a payload rate of 5 gigabits per second (Gbps). Under this new network architecture, the time sequence of data blocks arriving at the receiving device will change, and the premise of applying the clock synchronization technology of traditional Ethernet is that the time sequence of data blocks arriving at the receiving device remains unchanged. Therefore, applying the clock synchronization technology of traditional Ethernet in FlexE faces huge difficulties. This article will analyze this difficulty in detail later.

[0044] In order to facilitate understanding of the technical solution of the present application, some technical features involved in the present application will be explained below.

[0045] Figure 2 A partial architecture diagram of a FlexE applicable to the present application is shown.

[0046] like Figure 2 As shown in the figure, part of the FlexE architecture includes the MAC sublayer, the time division multiplexing layer and the physical layer, wherein the MAC sublayer is a sublayer of the data link layer and is connected to the logical link control sublayer. The physical layer can be divided into the physical coding sublayer (PCS), the physical medium attachment (PMA) sublayer and the physical medium dependent (PMD) sublayer. The MAC sublayer and the time division multiplexing layer and the time division multiplexing layer and the physical layer are connected through the medium independent interface (MII), the physical layer is connected to the transmission medium, and the physical layer and the transmission medium are connected through the medium dependent interface (MDI). The functions of the above-mentioned layers and interfaces are implemented by corresponding chips or modules. For example, the functions corresponding to the PCS, PMA sublayer and PMD sublayer can be implemented by different PHYs respectively.

[0047] Since the MAC address of data passing through the same MAC module is the same, the MAC module is the FlexE client. In the process of sending signals, the PCS is used to encode, scramble, insert overhead headers (OH), and insert alignment markers (AM). In the process of receiving signals, the PCS will perform the reverse process of the above steps. Sending and receiving signals can be implemented by different functional modules of the PCS.

[0048] The main functions of the PMA sublayer are link monitoring, carrier monitoring, coding, transmit clock synthesis, and receive clock recovery. The main functions of the PMD sublayer are data stream scrambling / descrambling, coding, and DC restoration and adaptive equalization of the received signal.

[0049] It should be understood that the above architecture is only an example, and the FlexE architecture applicable to the present application is not limited to this. For example, there may be an adaptation sublayer (reconciliation sublayer, RS) between the MAC sublayer and the time division multiplexing layer to provide a signal mapping mechanism between the MII and the MAC sublayer; there may also be a forward error correction (forward error correction, FEC) sublayer between the PCS and PMA sublayers to enhance the reliability of the sent data.

[0050] Figure 3 The structure of an Ethernet message and the location of the start of frame delimiter (SFD) in an Ethernet message are shown. An Ethernet message consists of a 7-octet preamble, a 1-octet SFD, and a variable-length frame. The SFD and preamble are usually located in a 66-byte data block. The order in which Ethernet messages are sent is: Figure 3 The order from left to right shown in the figure, that is, the preamble is sent first, then the SFD is sent, and finally the frame is sent. Since the least significant bit (LSB) is sent first and then the most significant bit (MSB) is sent in the actual sending process, the SFD is the first part of the entire Ethernet message sent in the actual sending process.

[0051] In the clock synchronization process of traditional Ethernet, the sending device uses the time when the data block corresponding to SFD crosses the PMA sublayer and reaches MDI as the sending timestamp of the clock synchronization message. Since traditional Ethernet is a single PHY transmission and traditional Ethernet has no Figure 2 The time division multiplexing layer shown, therefore, the time order of the data blocks arriving at the receiving device does not change, and the MDI of the sending device can identify the data block corresponding to the clock synchronization message and timestamp the data block. The receiving device can identify the data block corresponding to the SFD of the clock synchronization message and record the SFD of the clock synchronization message.

[0052] like Figure 1 As shown in Figure 2, FlexE uses multiple PHYs to transmit data, and FlexE Figure 2 The time division multiplexing layer shown maps data blocks to different PHYs, thereby disrupting the order of the data blocks. If the traditional Ethernet clock synchronization method is used, the timestamp sampling modules of the sending device and the receiving device will not be able to determine the SFD of the clock synchronization message, resulting in the inability to perform clock synchronization.

[0053] The following describes in detail the difficulties faced by traditional Ethernet clock synchronization technology when applied to FlexE.

[0054] Figure 4 FIG. 1 is a schematic diagram showing a method for transmitting messages via dual PHY. Figure 4 As shown, PHY A and PHY B are two physical links, belonging to a 2×100GE FlexE bundle group. Based on the FlexE bundle group, there are two 100 Gbps clients, namely, Client 1 and Client 2.

[0055] The bandwidth of each PHY can correspond to 20 time slots. The FlexE bundle group corresponds to a total of 40 time slots, numbered 0 to 39. The time slot mapping method of the two customers is as follows: Figure 4 As shown, client 1 occupies time slots 0 to 9 and time slots 20 to 29, and client 2 occupies time slots 10 to 19 and time slots 30 to 39. The Ethernet message sent by client 1 includes a message, and the Ethernet message sent by client 2 includes data packet 1, and data packet 1 is a non-PTP message. The message sending order of client 1 and client 2 is Figure 4 The time slots are assigned from left to right as shown, and in the order in which the time slot numbers are assigned from small to large.

[0056] After time slot allocation, the positions of PTP message and data packet 1 in the two PHYs are as follows: Figure 5 As shown, the first data block of the PTP message occupies time slot 9, which is composed of Figure 3 It can be seen that the data block is the data block corresponding to the SFD of the PTP message. The data block corresponding to the SFD of data packet 1 occupies time slot 10. It can be seen that two data blocks corresponding to SFD will appear consecutively on PHY A. For the sending device, since the timestamp sampling module cannot identify which data block is the data block corresponding to the SFD of the PTP message, it is impossible to timestamp. Taking a step back, even if the sending device identifies the data block corresponding to the SFD of the PTP message and timestamps it, since the data blocks of the PTP message arrive at the receiving device out of order, the receiving device will not be able to timestamp because it cannot determine the data block corresponding to the SFD of the PTP message.

[0057] Figure 4 and Figure 5 This is just a simple example. In actual applications, the number of clients and PHYs is greater, and more complex scenarios may occur, making it more difficult to identify the data block corresponding to the SFD of the PTP message.

[0058] In addition to the above difficulties, since the time division multiplexing layer of FlexE will insert or delete idle blocks when adapting the rate of the client, it is necessary to map the code blocks to time slots and time slots to physical channels. This process will change the relative position of the PTP message in the data stream, and the position of the PTP message cannot be predicted logically. In other words, the PTP message is opaque during the transmission process. This is another major difficulty faced by the application of traditional Ethernet clock synchronization technology in FlexE.

[0059] A method for solving the above problem is that the sending device indicates the data block corresponding to the SFD among multiple data blocks through out-of-band information, so that the sending timestamp can be collected when the SFD reaches the MDI, and the receiving device obtains the receiving timestamp of the data block corresponding to the SFD by sampling the timestamp of the received data block. In this method, due to the skew between multiple PHYs, the method for determining the receiving timestamp provided by the method has a certain error.

[0060] Figure 6 A schematic diagram showing possible skew between multiple PHYs.

[0061] In the TDM mechanism of FlexE, multiple customers are mapped to multiple PHYs. This mapping relationship is random, that is, the data block generated by any customer may appear on any one or more PHYs. In the multi-PHY transmission scenario, although the skew relationship between two PHYs may be fixed (only considering the pure physical link delay), since the data block of a customer may appear on different PHYs at different times, the data blocks of two customers may have different skews at different times.

[0062] like Figure 6 As shown, the data block that should arrive at the receiving device the latest is moved to the PHY that arrives at the receiving device the earliest after the mapping change (after FlexEcalendar switch), thereby changing the skew of data blocks of different customers. Figure 6 The situation shown is only a simple example. In practice, there are many different skew situations. It is also common that a client's data block is distributed on multiple PHYs.

[0063] For the receiving device, if the above-mentioned skew phenomenon occurs between multiple data blocks received belonging to the same message or the same group of messages (for example, synchronization (sync) messages and follow-up (follow_up) messages), it will cause a large error in the receiving timestamp, and even the message cannot be recovered. The reason is that the sending device and the receiving device can only communicate through messages under the premise that the physical channel remains unchanged.

[0064] The solution to the above-mentioned problem provided by the present application will be described in detail below.

[0065] Figure 7 A clock synchronization method provided by the present application is shown. The method 700 includes:

[0066] S701, a receiving device receives a plurality of data blocks through a plurality of PHYs, the plurality of data blocks including a plurality of leading data blocks, the leading data block being a data block that firstly reaches the receiving device among data blocks transmitted in the PHY, and the plurality of leading data blocks correspond one-to-one to the plurality of PHYs.

[0067] S702: The receiving device performs timestamp sampling on the multiple data blocks to generate multiple receiving timestamps.

[0068] S703, the receiving device aligns multiple receiving timestamps based on the first receiving timestamp, the first receiving timestamp is the receiving timestamp corresponding to the first data block among the multiple receiving timestamps, the first data block is the data block transmitted through the first PHY, and the first PHY is the PHY corresponding to the first data block among the multiple first data blocks that arrives at the receiving device latest.

[0069] S704: The receiving device generates a clock synchronization message according to the multiple data blocks.

[0070] S705, the receiving device writes the value of the second receiving timestamp into the clock synchronization message, wherein the second receiving timestamp is the receiving timestamp of the second data block determined based on the aligned multiple receiving timestamps, the second data block is a data block among the multiple data blocks used for sending timestamp sampling, and the sending timestamp of the second data block is the sending timestamp of the clock synchronization message.

[0071] Since the receiving device cannot identify which data block among multiple data blocks is the second data block, the receiving device needs to collect timestamps for each received data, that is, generate multiple receiving timestamps. The multiple receiving timestamps exist as out-of-band information and can only be deleted when the receiving device identifies the second data block. It should be noted that the timestamps of each PHY after alignment are the same, and only one PHY timestamp can be retained, or the timestamps of each PHY can be retained.

[0072] In S703, the last PHY among multiple PHYs to receive the overhead block is, for example, PHY A, and the first data block is, for example, the first data block received by PHY A after receiving the overhead block (the first data block may also be the overhead block, and the present application does not limit the specific position of the first data block). The receiving device performs timestamp sampling on the first data block to obtain a first receiving timestamp, and the sampling point of the first receiving timestamp may be, for example, the first bit of the first data block.

[0073] Since the data received by the receiving device in each receiving cycle may include multiple data blocks, that is, multiple data blocks share a receiving timestamp, the data block whose receiving time is recorded is called a reference data block. The method provided in this embodiment records the number of bits between each data block and the reference data block, so that the receiving time of the first data block can be calculated according to the corresponding relationship between the bit and time, that is, the receiving timestamp of the first data block is determined. In addition, even if the timestamp sampling point in the reference data block is deleted, the method provided in this application can continue to track the position of the timestamp sampling point.

[0074] For example, the receiving device receives 8 data blocks in one receiving cycle, and performs timestamp sampling at the time of receiving the first data block, wherein the number of bits contained in each data block is 66. When the clock synchronization message is restored, the receiving device determines that the third data block among the 8 data blocks is the data block corresponding to the SFD, and the number of bits between the third data block and the first data block is 132. Assuming that the time required for the receiving device to receive one bit is t, the receiving time of the third data block is 132t later than the receiving time of the first data block, so the receiving time of the first data block can be calculated.

[0075] It should be noted that the first data block and the second data block may be the same or different. Accordingly, when the first data block and the second data block are the same, the first receiving timestamp and the second receiving timestamp are the same; when the first data block and the second data block are different, the first receiving timestamp and the second timestamp are also different.

[0076] Before aligning multiple receiving timestamps, the receiving device first aligns multiple lanes included in each PHY. The method of aligning multiple lanes can refer to the method in the prior art, and for the sake of brevity, it will not be repeated here.

[0077] In S704, the receiving device can recover the clock synchronization message according to the overhead multiframe pair. The specific method can refer to the message recovery method in the prior art, which will not be described here for brevity.

[0078] When the clock synchronization message is restored, the receiving device can determine the second data block according to the preset information in the message, and write the receiving timestamp corresponding to the second data block into the clock synchronization message as the receiving timestamp of the clock synchronization message. Since S703 has performed alignment processing on multiple receiving timestamps including the second receiving timestamp, the second receiving timestamp is a receiving timestamp with skew eliminated, thereby solving the problem in the prior art that the receiving timestamp has a large error due to skew, or even the message cannot be restored.

[0079] It should be noted that in S705, in addition to considering the delay caused by aligning the receiving timestamps of multiple PHYs in S703, the compensation for the second timestamp also needs to consider other delays. For example, when the second data block is not a data block for timestamp sampling by the receiving device, the receiving device also needs to calculate the delay of the second data block relative to the timestamp sampling data block according to the above method, and compensate for the second timestamp.

[0080] Optionally, the receiving device aligns multiple receiving timestamps based on the first receiving timestamp, including:

[0081] S706: The receiving device adjusts the values ​​of the multiple receiving timestamps based on the duration of the receiving cycle and the first receiving timestamp.

[0082] The receiving device may adjust the multiple receiving timestamps in the process of aligning the multiple receiving timestamps by the duration of the receiving cycle, such as Figure 8 As shown, PHY C is the PHY that receives the overhead frame the latest among the four PHYs, and the delays of PHY A, PHY B and PHYD relative to PHY C are D1, D2 and D4 respectively. D0 is a buffer delay of each PHY, and the buffer delay is used to compensate D1, D2 or D4 so that the total duration of D1, D2 or D4 plus the buffer delay is equal to an integer multiple of the receiving cycle. For example, the duration of the receiving cycle is T, D1 is equal to 3.5T, D2 is equal to 4.6T, and D4 is equal to 4.7T. Then, the D0 value of PHY A is 0.5T, the D0 value of PHY B is 0.4T, the D0 value of PHY C is T, and the D0 value of PHY D is 0.3T, thereby aligning the receiving timestamps of multiple PHYs.

[0083] As an optional example, the second receiving timestamp is the timestamp of PHY C, and T also belongs to the delay caused by aligning the second timestamp.

[0084] It should be understood that the above method is only an example, and the receiving device can also align the timestamps of multiple PHYs in units of other durations. For example, the receiving device can also align the timestamps of multiple PHYs in units of the duration required to receive 1 bit.

[0085] Optionally, the duration of the receiving cycle is equal to the duration required for the receiving device to receive X bits of data, where X is the smaller value of the data bus width of the receiving device or the data buffer width of the serial-to-parallel conversion port of the receiving device.

[0086] The smaller the bit width, the shorter the receiving cycle, the higher the sampling frequency of the receiving timestamp, and the finer the time granularity of adjusting multiple timestamps at the same time, which is conducive to improving the accuracy of the receiving timestamp of the final clock synchronization message.

[0087] Optionally, before the receiving device generates a clock synchronization message according to the multiple data blocks, the method 700 further includes:

[0088] S707: The receiving device deletes the receiving timestamps other than the receiving timestamp corresponding to the first PHY.

[0089] After the alignment process, the receiving timestamps of the various PHYs are the same, so only the receiving timestamp of one PHY may be retained, thereby reducing the occupation of storage space.

[0090] Optionally, the second data block is a data block corresponding to the SFD of the clock synchronization message.

[0091] SFD is the first field sent and received in the clock synchronization message. Traditional Ethernet uses SFD as the reference point for timestamp sampling. Therefore, using the first bit received in the receiving cycle as the timestamp sampling point can improve the compatibility of the FlexE clock synchronization method.

[0092] Optionally, the clock synchronization message is carried in a FlexE client payload.

[0093] The method provided in this embodiment receives the clock synchronization message through the client payload of FlexE, which is the same as the method of receiving the clock synchronization message of the traditional Ethernet, thereby improving the compatibility of the FlexE clock synchronization method. In addition, in the scenario of FlexE to FlexE direct connection, the sending timestamp is directly passed to the downstream. Compared with the method of sending timestamps through overhead frames in the prior art, this embodiment does not need to extract the sending timestamp from the client payload and put it into the overhead frame in the sending device, nor does it need to extract the sending timestamp from the overhead frame and put it into the client payload in the receiving device, thereby reducing the logic complexity.

[0094] The above describes in detail an example of a method for sending and receiving clock synchronization messages provided by the present application. It is understandable that, in order to implement the above functions, the sending device and the receiving device include hardware structures and / or software modules corresponding to the execution of each function. It should be easily appreciated by those skilled in the art that, in combination with the units and algorithm steps of each example described in the embodiments disclosed herein, the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present application.

[0095] The present application can divide the functional units of the sending device and the receiving device according to the above method example. For example, each functional unit can be divided according to each function, or two or more functions can be integrated into one processing unit. The above integrated unit can be implemented in the form of hardware or in the form of software functional units. It should be noted that the division of units in the present application is schematic and is only a logical functional division. There may be other division methods in actual implementation.

[0096] In the case of an integrated unit, Fig. 9 A possible structural diagram of the receiving device involved in the above-mentioned embodiment is shown. The receiving device 900 includes: a processing unit 902 and a communication unit 903. The processing unit 902 is used to control and manage the actions of the receiving device 900. For example, the processing unit 902 is used to support the receiving device 900 to execute S703 and / or other processes for the technology described herein. The communication unit 903 is used to support the communication between the receiving device 900 and the sending device and the communication between the various modules or units inside the receiving device 900. The receiving device 900 may also include a storage unit 901 for storing the program code and data of the receiving device 900.

[0097] The processing unit 902 controls the communication unit 903 to execute: receiving multiple data blocks through multiple PHYs, the multiple data blocks including multiple first data blocks, the first data block being the data block that first arrives at the receiving device among the data blocks transmitted in the PHY, and the multiple first data blocks corresponding one-to-one to the multiple PHYs.

[0098] The processing unit 902 executes: performing timestamp sampling on the multiple data blocks received by the communication unit to generate multiple receiving timestamps; aligning the multiple receiving timestamps based on the first receiving timestamp, the first receiving timestamp being the receiving timestamp corresponding to the first data block among the multiple receiving timestamps, the first data block being a data block transmitted through a first PHY, the first PHY being the PHY corresponding to the first data block among the multiple first data blocks that arrives at the receiving device latest; generating a clock synchronization message based on the multiple data blocks; writing the value of the second receiving timestamp into the clock synchronization message, wherein the second receiving timestamp is the receiving timestamp of the second data block determined based on the aligned multiple receiving timestamps, the second data block is the data block among the multiple data blocks used for sending timestamp sampling, and the sending timestamp of the second data block is the sending timestamp of the clock synchronization message.

[0099] The processing unit 902 may be a processor or a controller, for example, a central processing unit (CPU), a general processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, transistor logic devices, hardware components or any combination thereof. It may implement or execute various exemplary logic blocks, modules and circuits described in conjunction with the disclosure of this application. The processor may also be a combination that implements a computing function, for example, a combination of one or more microprocessors, a combination of a DSP and a microprocessor, and the like. The communication unit 903 may be a communication interface, etc. The storage unit 901 may be a memory.

[0100] When the processing unit 902 is a processor, the communication unit 903 is a transceiver, and the storage unit 901 is a memory, the receiving device involved in the present application can be Fig.10 NPU1000 shown.

[0101] See also Fig.10 As shown, the NPU 1000 includes: a processor 1002, a communication interface 1003, and a memory 1001. The communication interface 1003, the processor 1002, and the memory 1001 can communicate with each other through an internal connection path to transmit control and / or data signals.

[0102] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described devices and units can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0103] The receiving device 900 or NPU 1000 provided in the present application continuously and periodically stamps (i.e., performs timestamp sampling) the data blocks received by each PHY, generates multiple receiving timestamps, and includes the timestamps corresponding to the data blocks (i.e., the second data blocks) used for sending timestamp sampling in the multiple data blocks, and performs alignment processing on each timestamp, that is, waits for the last PHY (i.e., the first PHY) among the multiple PHYs to receive the overhead block, and adjusts the timestamps of the data blocks received by other PHYs in the multiple PHYs based on the timestamp (i.e., the first timestamp) of the first data block received after the first PHY receives the overhead block, and regards the first timestamp as the common timestamp of the first data block received after all PHYs receive the overhead block, thereby aligning the time when the multiple data blocks arrive at the receiving device. The multiple data blocks include the data blocks corresponding to the clock synchronization message. When the clock synchronization message is restored, the receiving timestamp corresponding to the second data block can be determined, and the timestamp corrects the skew that occurs when multiple data blocks from the same FlexE customer arrive at the receiving device.

[0104] The sending device or receiving device in the device and method embodiments completely corresponds to each other, and the corresponding modules perform the corresponding steps, for example, the sending module or transmitter performs the sending step in the method embodiment, and the receiving module or receiver performs the receiving step in the method embodiment. The other steps except sending and receiving can be performed by the processing module or processor. The functions of the specific modules can refer to the corresponding method embodiments and will not be described in detail.

[0105] In each embodiment of the present application, the size of the serial number of each process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the present application.

[0106] In addition, the term "and / or" in this article is only a description of the association relationship between the associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0107] The steps of the method or algorithm described in conjunction with the disclosure of the present application can be implemented in hardware or by executing software instructions by a processor. The software instructions can be composed of corresponding software modules, which can be stored in random access memory (RAM), flash memory, read-only memory (ROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, mobile hard disks, read-only compact disks (CD-ROMs) or any other form of storage medium known in the art. An exemplary storage medium is coupled to a processor so that the processor can read information from the storage medium and write information to the storage medium. Of course, the storage medium can also be a component of the processor. The processor and the storage medium can be located in an ASIC. In addition, the ASIC can be located in a terminal device. Of course, the processor and the storage medium can also be present in a receiving device as discrete components.

[0108] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented by software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in this application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted through the computer-readable storage medium. The computer instructions can be transmitted from a website site, computer, server or data center to another website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrated. The available medium may be a magnetic medium (eg, a floppy disk, a hard disk, a magnetic tape), an optical medium (eg, a digital versatile disc (DVD), or a semiconductor medium (eg, a solid state disk (SSD)).

[0109] The specific implementation methods described above further illustrate the purpose, technical solutions and beneficial effects of the present application in detail. It should be understood that the above description is only the specific implementation methods of the present application and is not intended to limit the scope of protection of the present application. Any modifications, equivalent substitutions, improvements, etc. made on the basis of the technical solutions of the present application should be included in the scope of protection of the present application.

Claims

1. A method for clock synchronization in a flexible Ethernet FlexE, characterized in that: include: The receiving device receives multiple data blocks through multiple physical layer modules PHY; The receiving device aligns the receiving timestamps of the plurality of PHYs; The receiving device records the receiving timestamps of the plurality of data blocks; The receiving device obtains a clock synchronization message according to the multiple data blocks included in the aligned multiple PHYs, and the clock synchronization message includes a receiving timestamp of the first data block.

2. The method according to claim 1, characterized in that: The sending timestamp of the first data block is the sending timestamp included in the clock synchronization message.

3. The method according to claim 1 or 2, characterized in that: The first data block is a data block corresponding to the frame delimiter start SFD of the clock synchronization message.

4. The method according to claim 1, characterized in that The receiving device aligns the receiving timestamps of the plurality of PHYs, including: The plurality of data blocks include a plurality of first data blocks, the first data block being a data block that firstly arrives at the receiving device among the data blocks transmitted by each of the plurality of PHYs, and the plurality of first data blocks correspond one-to-one to the plurality of PHYs; The receiving device performs timestamp sampling on the multiple data blocks to generate receiving timestamps of the multiple data blocks; The receiving device aligns the receiving timestamps of the multiple data blocks based on a first receiving timestamp, where the first receiving timestamp is the receiving timestamp of the multiple data blocks corresponding to the second data block, and the second data block is a data block transmitted via the first PHY.

5. The method according to claim 4, characterized in that The receiving device aligns the receiving timestamps of the plurality of data blocks based on the first receiving timestamp, including: The receiving device adjusts the values ​​of the receiving timestamps of the multiple data blocks based on the duration of a receiving period as a unit and based on the first receiving timestamp, wherein the receiving period is a period for sampling the timestamps of the multiple data blocks.

6. The method according to claim 4 or 5, characterized in that: The first PHY is a PHY corresponding to a first data block among the plurality of first data blocks that arrives at the receiving device the latest.

7. The method according to claim 5, characterized in that The duration of the receiving cycle is equal to the duration required for the receiving device to receive X bits of data, where X is the smaller value of the data bus width of the receiving device or the data buffer width of the serial-to-parallel conversion port of the receiving device.

8. The method according to claim 4 or 5, characterized in that: Before the receiving device generates the clock synchronization message according to the multiple data blocks, the method further includes: The receiving device deletes the receiving timestamps other than the first receiving timestamp corresponding to the first PHY.

9. The method according to claim 1 or 2, characterized in that: The receiving device obtains a clock synchronization message according to the multiple data blocks included in the aligned multiple PHYs, including: The receiving device writes the value of a second receiving timestamp into the clock synchronization message, wherein the second receiving timestamp is a receiving timestamp of the first data block determined based on the aligned multiple receiving timestamps.

10. The method according to claim 9, characterized in that The multiple data blocks include multiple first data blocks, the first data block is the data block that first arrives at the receiving device among the data blocks transmitted by each PHY in the multiple PHYs, the multiple first data blocks correspond one-to-one to the multiple PHYs, the multiple data blocks include the first data block, the corresponding PHY is the PHY corresponding to the first data block that arrives at the receiving device latest among the multiple first data blocks, and the second reception timestamp is the reception timestamp of the first data block.

11. The method according to claim 1 or 2, characterized in that: The multiple data blocks are carried in the FlexE client payload.

12. A device for clock synchronization in a flexible Ethernet FlexE, characterized in that: including a processing unit and a communication unit, The communication unit is used to: receive multiple data blocks through multiple physical layer modules PHY; The processing unit is used to: align the receiving timestamps of the multiple PHYs; record the receiving timestamps of the multiple data blocks; and obtain a clock synchronization message based on the multiple data blocks included in the aligned multiple PHYs, wherein the clock synchronization message includes the receiving timestamp of the first data block.

13. The device according to claim 12, characterized in that The sending timestamp of the first data block is the sending timestamp included in the clock synchronization message.

14. The device according to claim 12 or 13, characterized in that The first data block is a data block corresponding to the frame delimiter start SFD of the clock synchronization message.

15. The device according to claim 12, characterized in that The multiple data blocks include multiple first data blocks, the first data block is a data block that first arrives at the receiving device among the data blocks transmitted by each of the multiple PHYs, the multiple first data blocks correspond to the multiple PHYs one by one, and the processing unit is specifically used for: Performing timestamp sampling on the multiple data blocks to generate receiving timestamps of the multiple data blocks; The receiving timestamps of the multiple data blocks are aligned based on a first receiving timestamp, where the first receiving timestamp is a receiving timestamp corresponding to a second data block among the receiving timestamps of the multiple data blocks, and the second data block is a data block transmitted through the first PHY.

16. The device according to claim 15, characterized in that The processing unit is specifically configured to adjust the values ​​of the receiving timestamps of the multiple data blocks based on a duration of a receiving period as a unit and based on the first receiving timestamp, wherein the receiving period is a period for sampling the timestamps of the multiple data blocks.

17. The device according to claim 15 or 16, characterized in that The first PHY is a PHY corresponding to a first data block among the plurality of first data blocks that arrives at the receiving device the latest.

18. The device according to claim 16, characterized in that The duration of the receiving cycle is equal to the duration required for the receiving device to receive X bits of data, where X is the smaller value of the data bus width of the receiving device or the data buffer width of the serial-to-parallel conversion port of the receiving device.

19. The device according to claim 15 or 16, characterized in that The processing unit is also used for: The receiving device deletes the receiving timestamps other than the first receiving timestamp corresponding to the first PHY.

20. The device according to claim 12 or 13, characterized in that The processing unit is also used to: The value of a second receiving timestamp is written into the clock synchronization message, wherein the second receiving timestamp is a receiving timestamp of the first data block determined based on the aligned multiple receiving timestamps.

21. The device according to claim 20, characterized in that The multiple data blocks include multiple first data blocks, the first data block is the data block that first arrives at the receiving device among the data blocks transmitted by each PHY in the multiple PHYs, the multiple first data blocks correspond one-to-one to the multiple PHYs, the multiple data blocks include the first data block, the corresponding PHY is the PHY corresponding to the first data block that arrives at the receiving device latest among the multiple first data blocks, and the second reception timestamp is the reception timestamp of the first data block.

22. The device according to claim 12 or 13, characterized in that The multiple data blocks are carried in the FlexE client payload.

23. A clock synchronization device, characterized in that: The method comprises a processor configured to implement the method according to any one of claims 1 to 11.

24. The device according to claim 23, characterized in that The device is a chip.

25. The device according to claim 23, characterized in that The device is a network device, and the type of the network device includes at least one of the following: a router, a switch, or a server.

26. A clock synchronization system, comprising a sending device and a receiving device, characterized in that: The sending device is used to send data to the receiving device, and the receiving device is used to implement the method according to any one of claims 1 to 11.

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