Element substrate, liquid discharge head, and liquid discharge apparatus

Abstract

The present disclosure relates to an element substrate, a liquid discharging head, and a liquid discharging apparatus. An element substrate including a liquid discharging element includes: a memory element capable of storing individual information of the element substrate by writing, the memory element being configured to change an impedance value by writing; a plurality of current supply elements capable of supplying a current to the memory element; and a determination unit configured to determine presence / absence of writing based on a voltage generated in the memory element by a current selectively supplied from the plurality of current supply elements, wherein the plurality of current supply elements constitute a part of a current mirror circuit, and each supply a current in an amount according to a size ratio to the memory element.

Description

Technical Field

[0001] This invention mainly relates to component substrates. Background Technology

[0002] The flushing head used in a printer, for example, employing an inkjet printing method, includes a component substrate with multiple flushing elements arranged on it (see Japanese Patent Publication No. 2014-58130). The component substrate has a memory element that stores whether driving a single flushing element is permitted. According to this configuration, whether driving each flushing element is permitted is determined based on the presence / absence of a write to the corresponding memory element. For example, if a flushing element cannot be driven, another flushing element can be driven to supplement it. As the memory element, a so-called one-time programmable memory, configured to allow only one write, can be used, for example, an antifuse element. The impedance value (mainly resistance value) of the memory element changes depending on the presence / absence of a write to it.

[0003] Japanese Patent Publication No. 2008-299989 describes a configuration that can determine the presence / absence of a write to a memory element by detecting the voltage generated by supplying current to the memory element. However, according to this configuration, for example, if the amount of current supplied to the memory element varies due to ambient conditions such as temperature, the impedance value of the memory element may change. From the viewpoint of improving the accuracy of the determination, there is room for improvement. Summary of the Invention

[0004] An exemplary object of the present invention is to provide a technique that helps to improve the accuracy of determining the presence / absence of writes to memory elements.

[0005] One aspect of the present invention provides a component substrate including a drain element, comprising: a memory element capable of storing individual information of the component substrate by writing, the memory element being configured to change an impedance value by writing; a plurality of current supply elements capable of supplying current to the memory element; and a determining unit configured to determine the presence / absence of writing based on a voltage generated in the memory element by current selectively supplied from the plurality of current supply elements, wherein the plurality of current supply elements constitute part of a current mirror circuit and each supplies current to the memory element in an amount according to the size ratio.

[0006] Other features of the invention will become clear from the following description of exemplary embodiments (with reference to the accompanying drawings). Attached Figure Description

[0007] Figure 1 This is a view showing an example of the configuration of the printing device (drainage device);

[0008] Figure 2 This is a view showing an example of the configuration of a printed component substrate (component substrate);

[0009] Figure 3 This is a view used to explain an example of a method for determining the presence / absence of a write to a memory element;

[0010] Figure 4 This is a cross-sectional schematic diagram showing a portion of the structure of the printed element substrate;

[0011] Figure 5 This is a view showing another example of the configuration of the printed component substrate;

[0012] Figure 6 This is another view showing a configuration of the printed component substrate; and

[0013] Figure 7 This is yet another view showing the configuration of a printed component substrate. Detailed Implementation

[0014] In the following, embodiments will be described in detail with reference to the accompanying drawings. Note that the following embodiments are not intended to limit the scope of the claimed invention. Multiple features are described in the embodiments, but this does not limit the invention to requiring all of these features, and multiple such features can be appropriately combined. Furthermore, in the drawings, the same reference numerals are given the same or similar configuration, and redundant descriptions are omitted.

[0015] In this specification, embodiments will be described by way of example of a printing apparatus using an inkjet printing method. However, the printing method is not limited thereto. Moreover, the printing apparatus may be a single-function printer with only printing capabilities, or it may be a multi-function printer with multiple functions such as printing, faxing, and scanning. In addition, the printing apparatus may be a manufacturing apparatus configured to manufacture, for example, color filters, electronic devices, optical devices, microstructures, etc., using a predetermined printing method.

[0016] Furthermore, the term "printing" in this specification should be interpreted in a broader sense. Therefore, "printing" refers to any situation where the target to be formed on the printing medium is important information such as characters or graphic patterns, and regardless of whether the target is represented in a way that is perceptible to human vision.

[0017] The term "printing media" should also be interpreted in a broader sense, just like "printing." Therefore, the concept of "printing media" includes sheet-like components in general and can use any material capable of receiving ink, including paper, fabric, plastic film, metal, glass, ceramics, resin, wood, and leather.

[0018] The term "ink" should also be interpreted in a broader sense, just like "printing." Therefore, the concept of "ink" can include not only the liquid applied to a printing medium to form images, designs, patterns, etc., but also any accompanying liquid that can be used to treat the printing medium or the ink (e.g., to solidify or prevent the color materials in the ink applied to the printing medium from dissolving). Therefore, in this specification, this can be expressed as "liquid" instead of "ink."

[0019] From these perspectives, a printing device can be called a drainage device, a discharge device, etc. Similarly, the print head within a printing device can be called a drainage head, a discharge head, etc. Likewise, the printing element substrate within the print head can be called a drainage element substrate or a discharge element substrate, or simply a substrate. Furthermore, each of the multiple printing elements arranged on the printing element substrate can be called a drainage element, a discharge element, etc.

[0020] (First Embodiment)

[0021] Figure 1 An example configuration of a printing apparatus 1 according to a first embodiment is shown. The printing apparatus 1 includes a printhead 11 and a driver 12, and in this embodiment, printing is performed by an inkjet printing method. The printhead 11 is configured to perform printing on a predetermined printing medium P and includes a plurality of nozzles NZ and a printing element substrate SB. Each nozzle NZ is a drain port that discharges liquid received from a liquid tank TK storing liquid. The plurality of nozzles NZ are arranged on a surface on one side to perform printing.

[0022] The printing element substrate SB includes multiple printing elements PE corresponding to multiple nozzles NZ. When each printing element PE is driven, liquid is discharged from the corresponding nozzle NZ, thereby performing printing. In this embodiment, a resistive element (or simply a heater) serving as an electrothermal transducer is used as the printing element PE. As another embodiment, a piezoelectric element can be used.

[0023] The driver 12 includes a transfer driver 121 and a head driver 122. The transfer driver 121 transfers the printing medium P disposed in the body of the printing device 1 to the print head 11. The head driver 122 drives the print head 11 relative to the transferred printing medium P so that individual nozzles NZ discharge liquid, thereby performing printing.

[0024] Note that in this embodiment, the printhead 11 is a serial head that prints on the printing medium P while simultaneously scanning in a direction intersecting the transport direction of the printing medium P. Alternatively, the printhead 11 may be a linear head capable of printing over the entire area of ​​the printing medium P in the width direction at a single pass.

[0025] Figure 2An example configuration of the printed element substrate SB is shown. In the plan view (view from a direction perpendicular to the main plane, top view), the printed element substrate SB has a long side (first side) E. L And the shorter side (second side) E S The external shape of the printed element substrate SB. In this embodiment, the printed element substrate SB has a rectangular shape. As another embodiment, the printed element substrate SB may have a square shape, a parallelogram shape, or a trapezoidal shape. In addition to the plurality of printed elements PE described above, the printed element substrate SB includes a driving unit 21, a plurality of memory elements ME, a plurality of writing units 22, a current supply unit 23, and a determination unit 24.

[0026] In this embodiment, the liquid channel LQ is located in the longitudinal direction (parallel to the long side E) in the plan view. L The path extends in the direction of the channel LQ, and multiple printed elements PE are arranged longitudinally on both sides of the channel LQ. Drive units 21 are arranged on each side of the channel LQ, on the long side E. L It is connected to multiple printing elements PE, and multiple printing elements PE can be driven individually. Liquid is supplied from the liquid tank TK above the printing elements PE via the channel LQ, and then foamed and discharged when the printing elements PE are driven by the drive unit 21.

[0027] Here, the drive unit 21 can drive multiple print elements PE using a time-division multiplexing method. That is, the multiple print elements PE are divided into multiple groups, and the drive unit 21 sequentially drives each of the two or more print elements PE in each group as a block. For example, if the number of groups is i, and each group includes j print elements PE as blocks, then the drive unit 21 first drives the first block (i print elements PE) for each of the first to i-th groups. Next, the drive unit 21 drives the second block (i print elements PE) for each of the first to i-th groups. Following the same process, the drive unit 21 sequentially drives the third, fourth, ..., j-th blocks (i print elements PE in each block) for each of the first to i-th groups.

[0028] To drive multiple printed elements (PEs) using a time-division multiplexing method, the driver unit 21 typically includes a decoder, shift register, latch circuit, selector, AND circuit, OR circuit, etc. Note that each of i and j is an integer of 2 or greater. Furthermore, a group can also be called a time-division group, and a block can also be called a time-division block.

[0029] To correspond to the aforementioned multiple printed elements PE, multiple memory elements ME are arranged in the vertical direction, and multiple write units 22 are similarly arranged in the vertical direction. Furthermore, the current supply unit 23 and the determination unit 24 are arranged in the width direction (parallel to the short side E). S(in the direction) placed side by side.

[0030] Additionally, on the short side E of the printed element substrate SB S Near the edge, multiple terminals T are arranged in the width direction. Power supply voltage to the printed element substrate SB and signal transmission / reception to the printed element substrate SB are performed via the multiple terminals T. Figure 2 The power supply voltage V1 shown is 3.3 [V (volts)], and the power supply voltage V2 is 0 [V] (voltage V2 can also be referred to as ground voltage). Note that the voltages described in this specification represent the potential difference between the voltage V1 and ground voltage V2.

[0031] For ease of understanding, Figure 2 Two types of voltages are shown, namely, voltages V1 and V2. However, another power supply voltage different from voltages V1 and / or V2 can be further supplied to the printed element substrate SB. This / these other voltages can be supplied to... Figure 2 Some of the circuit sections shown replace voltages V1 and / or V2.

[0032] The memory element ME can store individual information about the print element substrate SB, such as correction information for various changes in the print element substrate SB, the number of printed sheets, the amount of ink remaining, and whether driving the print element PE is permitted. As the memory element ME, a so-called OTP (One-Time Programmable Memory) that allows only one write operation is used. In this embodiment, an antifuse element is used. Here, an antifuse element with a MOS (Metal-Oxide-Semiconductor) structure is used as the memory element ME.

[0033] Each write unit 22 is configured to perform one or more writes to memory element ME and includes a high breakdown voltage transistor TR1 and a control inverter circuit INV1. The high breakdown voltage transistor TR1 is connected in series with the memory element ME. As will be described in detail later, when in the ON state, the high breakdown voltage transistor TR1 functions as a write transistor in writing to the memory element ME, and also functions as a read transistor to confirm the presence / absence of a write to the memory element ME. A DMOS (double-diffused MOS) transistor is used as the high breakdown voltage transistor TR1.

[0034] The inverter circuit INV1 is connected to the gate terminal of the high breakdown voltage transistor TR1 and controls the high breakdown voltage transistor TR1 (setting the high breakdown voltage transistor TR1 to the on state or the off state) based on the control signal received via node n1.

[0035] Writing to the memory element ME is performed by applying a relatively high voltage (e.g., 32V) to the memory element ME via the write terminal Tx, which is one of a plurality of terminals T, during the on-state of the high breakdown voltage transistor TR1, thereby causing dielectric breakdown of the MOS structure of the memory element ME. Therefore, the impedance value of the memory element ME can be changed by writing. In this embodiment, before writing, the memory element ME is in an insulating state and exhibits a very large resistance value (or, for example, a high impedance of several MΩ). After writing, the memory element ME is in an on-state and exhibits a relatively small resistance value (e.g., several to tens of kΩ). During writing, a high voltage is applied to terminal Tx. Otherwise, terminal Tx is in an open-circuit state.

[0036] Note that, as another embodiment, a fuse element can be used as the memory element ME. In this case, before writing, the memory element ME is in a short-circuit state and exhibits a relatively small resistance value. After writing, the memory element ME is in an open-circuit state and exhibits a very large resistance value.

[0037] The current supply unit 23 includes a current generation unit 231, a selection unit 232, and a current supply controller 233. The current generation unit 231 includes multiple transistors MP10 to MP10. K Resistors R11 and R12 are also present. In this embodiment, p-channel MOS transistors are used as transistors MP10 to MP1. K Note that K is an integer of 2 or greater.

[0038] Transistors MP11 to MP1 K A current mirror circuit is formed with transistor MP10. For example, if transistors MP10 to MP1... K Given transistors MP10 with the same channel length and different channel widths, where m is any integer from 1 to K, the current flowing to MP10 is determined by the ratio of the channel width of MP10 to MP10. m Therefore, transistors MP11 to MP1 K Each of them can output a current based on the size ratio.

[0039] In this embodiment, resistors R11 and R12 are connected in series with transistor MP10, and the voltage between resistors R11 and R12 is used as a reference voltage V. REF Here, resistors R11 and R12 are provided to obtain a reference voltage V at a supply voltage V1 = 3.3 [V]. REF =1[V].

[0040] Selection unit 232 includes transistors MP11 to MP1 KCorresponding switching elements SW11 to SW1 K Furthermore, transistors MP11 to MP1 can be selectively switched. K Connect to memory element ME. For example, let m be any integer from 1 to K, if switching element SW1 m If set to the ON state, then transistor MP1 m It is connected to the memory element ME and supplies current to the memory element ME according to its size ratio. From this point of view, transistors MP11 to MP1... K Each of them serves as a current supply element capable of supplying current to the memory element ME.

[0041] The current supply controller 233 can independently control the switching elements SW11 to SW1 of the selection unit 232. K This will switch the switching elements SW11 to SW1 K Selectively set to the on state. For ease of understanding, in this embodiment, it is assumed that the switching elements SW11 to SW2 are switched by the current supply controller 233. K One of them is set to the on state, that is, transistors MP11 to MP1 K One of them can be selectively connected to the memory element ME. As another embodiment, switching elements SW11 to SW1 can be used. K Two or more of them are set to the on state, that is, transistors MP11 to MP12 can be turned on. K The currents of two or more transistors are superimposed and supplied to the memory element ME. Therefore, the current supply controller 233 only needs to be able to select transistors MP11 to MP12 via the selection unit 232. K At least some of them are connected to the memory element ME.

[0042] In summary, current supply unit 233 and current supply controller 233 output a control signal to control inverter circuit INV1 via node n1, thereby setting high breakdown voltage transistor TR1 to the on state. During this period, current supply controller 233 controls selection unit 232, thereby supplying the desired amount of current from current generation unit 231 to memory element ME via node n2.

[0043] The determining unit 24 is configured to determine the presence / absence of a write to the memory element ME (i.e., whether driving the printing element PE is allowed). In this embodiment, the determining unit 24 compares the voltage Vm generated in the memory element ME (the voltage of node n2) with a reference voltage V. REFA comparator for comparison. During the period when the high breakdown voltage transistor TR1 is set to the on state by controlling the inverter circuit INV1, current from the supply unit 23 (transistors MP11 to MP1) is supplied. K One of the currents is supplied to the memory element ME to determine the determination unit 24. Typically, if the memory element ME is in a write state, the voltage Vm is lower than the voltage Vm in the state before the write operation to the memory element ME. Based on the voltage Vm and the reference voltage V... REF The amplitude relationship between them determines the determination result of the determination unit 24, which is output from node n3 to the circuit part of the subsequent stage, or from the terminal T of the printed element substrate SB via node n3 to the outside.

[0044] In this way, determining unit 24 can determine the presence / absence of a write to memory element ME based on the voltage Vm generated in memory element ME by the current supplied from current supply unit 23. If memory element ME is in a write state, driving unit 21 considers, for example, that the corresponding print element PE cannot be driven, and suppresses the driving of the corresponding print element PE. To supplement this, driving unit 21 can alternatively drive another print element PE that can record at almost the same position as the corresponding print element PE.

[0045] As will be described in detail later, the determination unit 24 is used to determine the presence or absence of a write to the memory element ME, and the determination unit 24 can also be used for another purpose, use or function.

[0046] As described above, the impedance value of the memory element ME can be changed by writing. However, the impedance value can vary depending on the conditions of the printed element substrate SB. It is assumed that the impedance value varies due to factors such as ambient conditions (e.g., temperature), manufacturing variations, the dielectric breakdown mode of the MOS structure, and other factors. When variations in power supply voltage V1 are also considered, variations from transistor MP10 to MP1 are also taken into account. K The output current changes, therefore the reference voltage V REF And the change in voltage Vm.

[0047] Therefore, for example,

[0048] (a) During the evaluation step of manufacturing the printed element substrate SB, confirm whether the MOS structure of the memory element ME is properly formed / confirm whether the memory element ME is in a state prior to writing (for distinction, this is referred to as "manufacturing confirmation of the memory element ME").

[0049] (b) In a different timing condition than (a), specify that the driver of the printing element PE is not allowed to perform a write to the corresponding memory element ME, and then confirm whether the write was properly implemented / confirm whether the memory element ME is in a write state (for distinction, referred to as "confirmation of write completion in memory element ME"), and

[0050] (c) The presence / absence of a write to memory element ME under a different timing condition than (a) and (b) (referred to as "read from memory element ME" for distinction),

[0051] The conditions may differ from one another. As an example, when writing to the memory element ME, a relatively large amount of current is supplied to the memory element ME, so the temperature of the printed element substrate SB is considered to increase.

[0052] Therefore, in determining the unit 24, it is necessary to provide a margin that varies depending on several purposes, uses or functions, and preferably supply current corresponding to these amounts to the memory element ME.

[0053] As described above, in this embodiment, the memory element ME, which serves as an antifuse element, is in an insulating state and exhibits a very large resistance value before being written, and is in a conducting state and exhibits a relatively small resistance value after being written.

[0054] With this in mind, unit 24 is determined, for example:

[0055] Preferably, it is determined whether, in case (a), the resistance value of the memory element ME is greater than R. 1M ,

[0056] Preferably, in case (b), it is determined whether the resistance value of the memory element ME is less than R. 1K (R 1K <R 1M ),as well as

[0057] Preferably, in case (c), it is determined whether the resistance value of the memory element ME is greater than (or less than) R. 2K (R 2K >R 1K R 2K <R 1M ).

[0058] The above events occurred because:

[0059] It can be reliably confirmed that the memory element ME is in a state prior to being written in case (a), and it can be reliably confirmed that the memory element ME is in a state of being written in case (b).

[0060] To prevent errors in determining the presence / absence of a write to memory element ME in case (c).

[0061] Note that, as a typical example of a parameter, the resistance value R 1M The resistance value is 100 kΩ. 1K The resistance is 5 kΩ, and the resistance value R 2K The value is 50 kΩ. However, the parameter is not limited to these values.

[0062] Figure 3 The diagram shows the voltage Vm under the condition K=3 (where current is supplied to memory element ME from one of transistors MP11 to MP13). The horizontal axis represents the resistance value of memory element ME. The vertical axis represents the voltage Vm generated in memory element ME corresponding to the current quantities I11, I12, and I13 output from transistors MP11, MP12, and MP13, respectively. <I13<I12)。

[0063] Note that when the reference voltage V REF A typical example of setting the parameter to 1 [V] is that the current I11 is 10 [μA (microamps)], the current I12 is 200 [μA], and the current I13 is 20 [μA]. However, the parameter is not limited to these values.

[0064] According to this embodiment, from Figure 3 As can be seen from this, unit 24 is determined.

[0065] In case (a), the current I11 can be supplied from transistor MP11 to memory element ME, and the manufacturing of memory element ME can be verified.

[0066] In case (b), current I12 can be supplied from transistor MP12 to memory element ME, and confirmation of completion of writing to memory element ME can be performed.

[0067] In case (c), current I13 can be supplied from transistor MP13 to memory element ME, and read from memory element ME.

[0068] According to this configuration, in case (c), a margin MG for determination is provided relative to cases (a) and (b). Determination errors can be appropriately prevented compared to the case where K=1. The margin MG includes a margin for determination errors in both the write state and the state before writing. In this embodiment, the case where K=3 is illustrated. As another embodiment, K=2 is possible, and K≥4 is also possible. The integer K can be varied depending on the purpose, use, or function.

[0069] Figure 4This is a schematic cross-sectional view of the region including the memory element ME and the high breakdown voltage transistor TR1 on the printed element substrate SB. For example, multiple p-type wells 41 are provided in the p-type semiconductor substrate 40. P and multiple n-type wells 41 N and trap 41 P Or 41 N p-type region 42 P and / or n-type region 42 N In several regions 42 P Or 42 N Between them, a LOCOS (partial oxidation of silicon) film is provided as a thick insulating member OX. A gate electrode GT is provided, such that a portion of it covers the insulating member OX. Using this structure, a MOS structure acting as an antifuse element is formed as a memory element ME, and an n-channel DMOS transistor is formed as a high breakdown voltage transistor TR1.

[0070] Typically, silicon can be used for the semiconductor substrate 40, silicon oxide can be used for the insulating component OX, and polysilicon can be used for the gate electrode GT. The net p-type impurity concentration in the semiconductor substrate 40 is, for example, about 1 × 10⁻⁶. 16 [cm -3 p-type trap 41 P The net concentration of p-type impurities in the sample is, for example, about 1 × 10⁻⁶ 18 [cm -3 ]. n-type trap 41 N The net n-type impurity concentration is, for example, about 1 × 10⁻⁶. 18 [cm -3 p-type region 42 P The net concentration of p-type impurities in the sample is, for example, about 1 × 10⁻⁶ 19 [cm -3 n-type region 42 N The net n-type impurity concentration is, for example, about 1 × 10⁻⁶. 19 [cm -3 Note that net impurity concentrations are not limited to these examples.

[0071] As described above, according to this embodiment, the memory element ME is configured to store whether driving the printing element PE is allowed by writing and to change the impedance value by writing. Transistors MP11 to MP1 K They form part of a current mirror circuit, and each transistor supplies a current to the memory element ME in an amount proportional to its size. Transistors MP11 to MP1 are provided according to their purpose, application, or function. K In this embodiment, from transistor MP11 to MP1 KOne of the methods is to selectively supply current to the memory element ME. The determination unit 24 determines the presence or absence of a write to the memory element ME based on the voltage Vm generated in the memory element ME at this time. According to this configuration, the accuracy of the determination by the determination unit 24 can be improved independently of changes in the impedance value of the memory element ME caused by factors such as changes in the ambient environment or manufacturing process or changes in the power supply voltage V1.

[0072] Here, a single-channel LQ has been illustrated, and a configuration in which multiple printing elements PE, driving units 21, multiple memory elements ME, and multiple write units 22 are arranged on both sides of the channel LQ has been described. The number of channels LQ can be two or more. In this case, the multiple printing elements PE, driving units 21, multiple memory elements ME, and multiple write units 22 are preferably arranged on both sides of each channel LQ.

[0073] Assume two or more channels LQ are juxtaposed in the width direction. However, these can be additionally / alternatively juxtaposed in the longitudinal direction. Note that the long side E of the external shape of the printed element substrate SB can be reversed depending on the number of channels LQ juxtaposed in the width direction. L With the short side E S The relationship between them.

[0074] (Modifications of the first embodiment)

[0075] As described above, since multiple printing elements PE are driven by a time-division method, multiple memory elements ME and multiple write units 22 can be managed on a group basis.

[0076] Figure 5 An example configuration of a printed element substrate SB' according to this embodiment is shown. According to the printed element substrate SB', a plurality of memory elements ME and a plurality of write units 22 are grouped into i groups, just like a plurality of printed elements PE. That is, j memory elements ME and j write units 22 are arranged in each of the first to i groups. A current supply unit 23 may be provided for each group, and a determining unit 24 may be provided for each group.

[0077] The i current supply units 23 and i determining units 24 provided in this manner are preferably arranged in the width direction. The result of each determining unit 24 is obtained as a bit signal for each group. Therefore, a total of i bit signals are obtained, and the i bit signals can be read out as bit data using, for example, i trigger circuits connected in series.

[0078] With this configuration, it is advantageous to accelerate the determination of the presence / absence of a write to the memory element ME through the determination unit 24. Furthermore, it is also advantageous to further accelerate the determination process of the determination unit 24, as the impact of manufacturing variations can be further reduced.

[0079] (Second Embodiment)

[0080] In the first embodiment described above, an example is given in which the current supply unit 23 and the determining unit 24 are located on the two short sides E. S One of them is a configuration where they are placed side-by-side in the width direction. However, these can be mounted on two short sides E. S On both of them.

[0081] Figure 6 An example of the configuration of the printed element substrate SB2 according to the second embodiment is shown. According to this embodiment, the current supply unit 23 and the determination unit 24 are located on the short side E. S one side and the other side ( Figure 6 Each of the top and bottom edges (in the image) is juxtaposed in the width direction. To accommodate this configuration, multiple print elements PE, multiple memory elements ME, and multiple write units 22 are assigned to the short side E. S One side and the other side. Note that the division is made up of... Figure 6 The dashed line indicates this.

[0082] On the shorter side E S The current supply unit 23 on one side supplies current to the memory element ME on that side. Based on the resulting voltage Vm, the determination unit 24 on that side determines the presence / absence of a write to the memory element ME. Similarly, on the short side E... S The current supply unit 23 on the other side supplies current to the memory element ME on that other side. Based on the voltage Vm generated therefrom, the determination unit 24 on that other side determines the presence or absence of a write to the memory element ME.

[0083] Note that in the pair of current supply units 23 of current generation unit 231, selection unit 232 and current supply controller 233, the current supply controller 233 may be provided on only one side.

[0084] According to this embodiment, since the impact of manufacturing variations can be further reduced, it is more advantageous to further accelerate the determination of the determination unit 24.

[0085] (Third Embodiment)

[0086] According to the configuration of the first embodiment described above (see...) Figure 2When the high breakdown voltage transistor TR1 is in a non-conducting state, the node between the high breakdown voltage transistor TR1 and the memory element ME is essentially in a floating state. Therefore, if a high voltage is applied to the memory element ME via the write terminal Tx during this period, unexpected dielectric breakdown may occur in the MOS structure of the memory element ME.

[0087] Figure 7 An example configuration of a printed element substrate SB3 according to a third embodiment is shown. In this embodiment, the printed element substrate SB3 further includes a resistor element R21 connected in parallel with each memory element ME. According to this configuration, writing to the memory element ME can be prevented when a high voltage is applied to the memory element ME via the write terminal Tx during the non-conducting state of the high breakdown voltage transistor TR1.

[0088] In other words, according to this embodiment, erroneous writing to the memory element ME can be prevented. Therefore, according to this embodiment, it is also advantageous to improve the reliability of the printed element substrate SB3.

[0089] While the invention has been described with reference to exemplary embodiments, it should be understood that the invention is not limited to the disclosed exemplary embodiments. The scope of the appended claims is to be interpreted in the broadest possible sense to include all such modifications and equivalent structures and functions.

Claims

1. A component substrate including a drain element, characterized in that, include: A memory element capable of storing individual information of a component substrate by writing, the memory element being configured to change an impedance value by writing; Multiple current supply elements are capable of supplying current to the memory element; and The determining unit is configured to determine the presence / absence of a write operation based on the voltage generated in the memory element by current selectively supplied from the plurality of current supply elements. The plurality of current supply elements include a plurality of MOS transistors and a reference transistor forming part of a current mirror circuit, and each of the plurality of MOS transistors is configured to supply the memory element with a current of an amount based on the size ratio between the channel width of each of the plurality of MOS transistors and the channel width of the reference transistor.

2. The substrate of claim 1, further comprising a selection unit configured to select one of the plurality of MOS transistors to be connected to the memory element.

3. The substrate according to claim 1, wherein, The determining unit is a comparator configured to compare a voltage generated in the memory element by a current supplied from at least one of the plurality of MOS transistors with a reference voltage.

4. The substrate according to claim 1, further comprising a driving unit configured to drive the draining element. in, If the determining unit determines that the memory element is in a write state, the driving unit inhibits the driving of the draining element.

5. The substrate according to claim 1, wherein the memory element is an antifuse element.

6. The substrate according to claim 1, further comprising a resistive element connected in parallel with the memory element.

7. The substrate of claim 1, further comprising a write transistor configured to write to the memory element.

8. The substrate according to claim 7, wherein the write transistor is a DMOS transistor.

9. The substrate according to claim 7, wherein The drainage element is one of a plurality of drainage elements. The memory element is one of a plurality of memory elements corresponding to the plurality of drainage elements. The write transistor is one of a plurality of transistors corresponding to the plurality of memory elements, and The plurality of MOS transistors supply current to memory elements corresponding to the transistors that are in the on state among the plurality of transistors.

10. The substrate according to claim 9, wherein The component substrate has an external shape that includes a first side and a second side in a plan view. The plurality of drainage elements, the plurality of memory elements, and the plurality of transistors are arranged in a direction parallel to the first side, and The determining unit and the current mirror circuit are juxtaposed in a direction parallel to the second side.

11. A drain head, characterized in that, include: The component substrate according to any one of claims 1 to 10; and Drainage port corresponding to the drainage element.

12. A drainage device, characterized in that, include: The drain head according to claim 11; and The driver is configured to drive the discharge head.

Images