Instruction execution method and apparatus, electronic device, and computer-readable storage medium

Abstract

Embodiments of the present application provide an instruction execution method and device, electronic equipment and computer readable storage medium, and relate to the technical field of computers. The method comprises: detecting a first instruction, and in response to the detected first instruction, executing a first process and a second process in parallel; wherein the first instruction comprises an instruction for writing first data to a target address; the first data can comprise an immediate number and a constant. That is, the first data in the first instruction is encoded in the instruction; in this way, when the first instruction is detected, the first data can be directly obtained from the first instruction, and the second instruction is executed based on the first data; thus, the execution of the second instruction does not need to wait until the first instruction is executed, that is, the first data is obtained from the target address after the first data is written to the target address and then executed, but the second instruction is executed in advance, thereby saving instruction processing time and improving instruction processing efficiency.

Description

Technical Field

[0001] This application relates to the field of computer technology, and more specifically, to an instruction execution method, apparatus, electronic device, and computer-readable storage medium. Background Technology

[0002] Currently, with the development and advancement of computer technology, people's performance demands for processors are gradually increasing. Among them, high-performance superscalar processors typically employ out-of-order instruction execution to achieve better instruction-level parallelism (ILP), thereby improving processor performance.

[0003] However, in related technologies, in the design of open-source instruction set architecture (risk-five, RISC-V) processors based on reduced instruction sets, some instructions in the program are usually executed serially, resulting in low instruction processing efficiency. Summary of the Invention

[0004] The purpose of this application is to at least address one of the aforementioned technical defects, particularly the technical defect of low instruction processing efficiency.

[0005] According to one aspect of this application, a method for executing instructions is provided, the method comprising:

[0006] Detect a first instruction, wherein the first instruction includes first data, and the first data is data encoded into the first instruction and intended to be written to a target address;

[0007] In response to the detected first instruction, the first processing and the second processing are executed in parallel;

[0008] The first process includes an instruction processing flow that executes the first instruction to write the first data to the target address;

[0009] The second process includes obtaining the first data from the first instruction and executing a second instruction based on the first data; the execution of the second instruction depends on the first data.

[0010] Optionally, after detecting the first instruction, the method further includes:

[0011] A first identifier is added to the first instruction. The first identifier is used to indicate that the instruction processing flow of the first instruction has been completed, so that the step of obtaining the first data from the first instruction can be performed based on the first identifier.

[0012] Optionally, executing the second instruction based on the first data includes:

[0013] The first data is input to the input port of the second instruction to execute the instruction processing of the second instruction.

[0014] Optionally, the first data may include immediate numbers and / or constants.

[0015] According to another aspect of this application, an instruction execution apparatus is provided, the apparatus comprising:

[0016] An instruction detection module is used to detect a first instruction, wherein the first instruction includes first data, and the first data is data encoded into the first instruction and intended to be written to a target address;

[0017] The instruction execution module is used to execute the first processing and the second processing in parallel in response to the detected first instruction;

[0018] The first process includes an instruction processing flow that executes the first instruction to write the first data to the target address;

[0019] The second process includes obtaining the first data from the first instruction and executing a second instruction based on the first data; the execution of the second instruction depends on the first data.

[0020] Optionally, the device further includes:

[0021] The identifier adding module is used to add a first identifier to the first instruction after the first instruction is detected. The first identifier is used to indicate that the instruction processing flow of the first instruction has been completed, so as to perform the step of obtaining the first data from the first instruction based on the first identifier.

[0022] Optionally, the first instruction execution module is specifically used to input the first data to the input port of the second instruction in order to execute the instruction processing of the second instruction.

[0023] Optionally, the first data may include immediate numbers and / or constants.

[0024] According to another aspect of this application, an instruction execution apparatus is provided, the apparatus comprising:

[0025] The decoding module, in response to a detected first instruction, marks the first instruction and extracts the first data from the first instruction, wherein the first data is data encoded into the first instruction and intended to be written to a target address;

[0026] The renaming module, in response to the marked first instruction, marks at least one second instruction that has a dependency on the first data in the first instruction as pending execution;

[0027] The sending module detects whether the execution module is idle. When it is idle, it sends the first instruction and at least one second instruction to the execution module simultaneously for parallel processing.

[0028] The execution module directly pushes the first data as input data for the second instruction, thereby completing the parallel execution of the first instruction and at least one second instruction.

[0029] Optionally, the first instruction includes an instruction to write the first data to the target address;

[0030] The second instruction includes instructions for performing calculations based on the first data.

[0031] According to another aspect of this application, an electronic device is provided, the electronic device comprising:

[0032] One or more processors;

[0033] Memory;

[0034] One or more applications, wherein the one or more applications are stored in the memory and configured to be executed by the one or more processors, the one or more applications being configured to: perform the instruction execution method according to any one of the first aspects of this application.

[0035] For example, in a third aspect of this application, a computing device is provided, comprising: a processor, a memory, a communication interface, and a communication bus, wherein the processor, the memory, and the communication interface communicate with each other via the communication bus;

[0036] The memory is used to store at least one executable instruction that causes the processor to perform the operation corresponding to the instruction execution method shown in the first aspect of this application.

[0037] According to another aspect of this application, a computer-readable storage medium is provided, wherein when the computer program is executed by a processor, it implements the instruction execution method described in any of the first aspects of this application.

[0038] For example, in a fourth aspect of the present application, a computer-readable storage medium is provided, on which a computer program is stored, which, when executed by a processor, implements the instruction execution method shown in the first aspect of the present application.

[0039] According to one aspect of this application, a computer program product or computer program is provided, comprising computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform the methods provided in various alternative implementations of the first aspect described above.

[0040] The beneficial effects of the technical solution provided in this application are:

[0041] In this embodiment, by detecting a first instruction, a first process and a second process are executed in parallel in response to the detected first instruction. The first instruction includes writing first data to a target address. The first data may include immediate values ​​and constants. That is, the first data in the first instruction is encoded within the instruction itself. Thus, when the first instruction is detected, the first data can be directly obtained from the first instruction, and the second instruction can be executed based on the first data. Therefore, the execution of the second instruction does not need to wait until the first instruction has finished executing (i.e., after writing the first data to the target address, obtaining the first data from the target address, and then executing it), but rather the second instruction is executed ahead of time, thereby saving instruction processing time and improving instruction processing efficiency. Attached Figure Description

[0042] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments of this application will be briefly introduced below.

[0043] Figure 1 A flowchart illustrating an instruction execution method provided in an embodiment of this application;

[0044] Figure 2 A schematic diagram of the instruction processing flow of an instruction execution method provided in an embodiment of this application;

[0045] Figure 3 A schematic diagram illustrating the principle of an instruction execution method provided in an embodiment of this application;

[0046] Figure 4 This is a schematic diagram of the structure of an instruction execution device provided in an embodiment of this application;

[0047] Figure 5 This is a schematic diagram of the structure of an instruction execution device provided in an embodiment of this application;

[0048] Figure 6 This is a schematic diagram of the structure of an electronic device for instruction execution provided in an embodiment of this application. Detailed Implementation

[0049] The embodiments of this application are described below with reference to the accompanying drawings. It should be understood that the embodiments described below with reference to the accompanying drawings are exemplary descriptions for explaining the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions of the embodiments of this application.

[0050] Those skilled in the art will understand that, unless specifically stated otherwise, the singular forms “a,” “an,” “the,” and “the” used herein may also include the plural forms. It should be further understood that the terms “comprising” and “including” as used in embodiments of this application mean that the corresponding feature can be implemented as the presented feature, information, data, step, operation, element, and / or component, but do not exclude implementation as other features, information, data, step, operation, element, component, and / or combinations thereof supported by the art. It should be understood that when we say that an element is “connected” or “coupled” to another element, the one element can be directly connected or coupled to the other element, or it can mean that the one element and the other element establish a connection relationship through an intermediate element. Furthermore, “connected” or “coupled” as used herein can include wireless connection or wireless coupling. The term “and / or” as used herein indicates at least one of the items defined by the term; for example, “A and / or B” can be implemented as “A,” or as “B,” or as “A and B.”

[0051] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0052] First, let's introduce and explain several terms used in this application:

[0053] Reorder buffer: The reorder buffer (ROB) allows instructions to be submitted in their original order after being executed out of order.

[0054] Cache: A high-speed buffer memory, located between the CPU and main memory (DRAM, Dynamic Random Access Memory), is a small but high-speed memory, typically composed of SRAM (Static Random Access Memory). It's a small-capacity but high-speed memory situated between the CPU and main memory. Since the CPU is much faster than main memory, when the CPU directly accesses data from main memory, it has to wait for a certain period. The cache, however, can store data that the CPU has recently used or is frequently used. If the CPU needs to use that data again, it can retrieve it directly from the cache, thus avoiding repeated data access, reducing CPU waiting time, and improving system efficiency. Cache is further divided into L1 Cache (Level 1 cache) and L2 Cache (Level 2 cache). L1 Cache is mainly integrated inside the CPU, while L2 Cache is integrated on the motherboard or on the CPU.

[0055] Immediate value: An immediate value is typically a number given in an immediate addressing instruction. It can be 8-bit, 16-bit, or 32-bit, and the value immediately follows the opcode. If the immediate value is 16-bit or 32-bit, it will be stored in high-high-low-low order.

[0056] The instruction execution method, apparatus, electronic device, and computer-readable storage medium provided in this application are intended to solve the above-mentioned technical problems of the prior art.

[0057] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will be described below with reference to the accompanying drawings.

[0058] In practical applications, high-performance superscalar processors typically employ out-of-order instruction execution to achieve better instruction-level parallelism (ILP), thereby improving processor performance. However, in related technologies, in open-source instruction set architectures based on reduced instruction sets (RISC) (risk-five, Riscv) processor designs, some instructions in the program can only be executed serially, resulting in lower instruction processing efficiency.

[0059] This application addresses the aforementioned technical problem by executing a first process and a second process in parallel upon detecting a first instruction. The first process includes an instruction processing flow that executes the first instruction to write the first data to the target address; the second process includes retrieving the first data from the first instruction and executing a second instruction based on the first data; the execution of the second instruction depends on the first data.

[0060] See Figure 1 This application provides an instruction execution method, optionally applied to an electronic device. For ease of explanation, the following description uses an example of this method applied to a processor. For example, the processor may be a CPU or a Graphics Processing Unit (GPU). Specifically, the method may include the following steps:

[0061] S101: Detect the first instruction, wherein the first instruction includes first data, and the first data is data encoded into the first instruction and intended to be written to the target address.

[0062] Optionally, embodiments of this application can be applied to the field of computer technology; for example, they can be specifically applied to instruction processing scenarios involving multiple instructions.

[0063] In this example, the first instruction includes first data. The first data is data encoded into the first instruction and intended to be written to a target address; optionally, the first data may include immediate values ​​and constants, etc. The target address is the address where the first data is written. It is understood that, in this embodiment, the first data in the first instruction is encoded within the instruction.

[0064] As an example, the first instruction can be the instruction `li src1, imm`. Specifically, this first instruction is an immediate value load instruction, which writes the immediate value `imm` into the register `src1`.

[0065] S102: In response to the detected first instruction, execute the first processing and the second processing in parallel.

[0066] The first process includes an instruction processing flow that executes the first instruction to write the first data to the target address; the second process includes obtaining the first data from the first instruction and executing a second instruction based on the first data; the execution of the second instruction depends on the first data.

[0067] Specifically, the second instruction includes instructions that have a dependency relationship with the first instruction. Optionally, the execution of the second instruction may depend on the first data of the first instruction. For example, in a practical scenario, the second instruction may be to perform a target operation on the first data and the second data.

[0068] As an example two, the second instruction is such as the instruction beq src1,src2,target; specifically, this second instruction is a data comparison instruction, that is, comparing the first data in register src1 and the second data in register src2; wherein, the result of the comparison is stored in the target register.

[0069] It should be noted that the second data may include one or more data; the second data may be of any type; in addition, the target operation may include, for example, comparison operation, addition operation, multiplication operation and other compound operations, etc. The embodiments of this application do not limit the algorithm of the target operation.

[0070] In related technologies, since the first instruction and the second instruction that depends on the first instruction can only be executed serially, that is, the second instruction can only be executed after the first instruction has been completed, this will result in low instruction processing efficiency.

[0071] In this embodiment, the first instruction includes an instruction to write first data to a target address; the first data may include immediate values ​​and constants. That is, the first data in the first instruction is encoded within the instruction. Thus, in response to the detected first instruction, the first data can be directly obtained from the first instruction, and the second instruction can be executed based on the first data. It is understood that in the above processing method, the first data is directly obtained from the first instruction to execute the second instruction; thus, the execution of the second instruction does not need to wait until the first instruction is completed, that is, after the first data is written to the target address, the first data is obtained from the target address and then executed. Instead, the second instruction is executed ahead of time, saving instruction processing time.

[0072] Furthermore, on the other hand, when the first instruction is detected, the instruction processing flow of the first instruction continues to be executed, that is, the first data is written to the target address; that is, the instruction processing flow of the first instruction and the instruction processing flow of the second instruction can be executed in parallel, which improves the instruction processing efficiency.

[0073] As an example three, combined with Figure 2 The instruction execution method of the embodiments of this application will be described as follows:

[0074] like Figure 2The instruction processing flow shown includes seven modules: cache module, fetch module, decode module, dispatch module, rename module, issue module, and execution module.

[0075] Cache module (I-Cache): Used to cache instructions.

[0076] Instruction Fetch Unit (IFU): Used to fetch instructions from the I-Cache using the value of the Program Counter Register (PC) as the address.

[0077] Decoder module: Used to decode the fetched instructions and read the register file based on the decoding results to obtain the source operands of the instructions.

[0078] Dispatcher module: Used to send the decoded instructions to the dispatch module in the original order specified in the program.

[0079] The Renaming module is used to perform renaming processes.

[0080] Issue module: Used to send instructions from the issue queue to the execution module. Specifically, during the execution of the instruction pipeline, instructions that have been fetched, decoded, and dispatched are pushed onto the issue module and cached in the issue queue of the issue module.

[0081] Execution module (Execute or lsu): Used to execute instructions based on the decoding results.

[0082] Reorder Buffer (ROB): Used to cache instructions that have completed the instruction processing flow, so as to perform deprecation processing on instructions that have completed the instruction processing flow.

[0083] In the aforementioned instruction processing flow, the Decoder module can parse and detect the first instruction. Upon detection, the instruction processing flow for the first instruction can continue, including: the Dispatcher module classifying the instruction; the Renaming module renaming the instruction; the Issue module verifying whether the instruction execution conditions are met; and the Execute module writing the first data to the target address. Furthermore, the first data can be obtained from the first instruction to execute the instruction processing flow for the second instruction.

[0084] In this way, the instruction processing flow of the first instruction and the instruction processing flow of the second instruction can be executed in parallel, improving instruction processing efficiency. Furthermore, it should be noted that the second instruction can be a single instruction within the same clock cycle as the first instruction, or it can be multiple instructions within the same clock cycle as the first instruction.

[0085] In this embodiment, by detecting a first instruction, a first process and a second process are executed in parallel in response to the detected first instruction. The first instruction includes writing first data to a target address. The first data may include immediate values ​​and constants. That is, the first data in the first instruction is encoded within the instruction itself. Thus, when the first instruction is detected, the first data can be directly obtained from the first instruction, and the second instruction can be executed based on the first data. Therefore, the execution of the second instruction does not need to wait until the first instruction has finished executing (i.e., after writing the first data to the target address, obtaining the first data from the target address, and then executing it), but rather the second instruction is executed ahead of time, thereby saving instruction processing time and improving instruction processing efficiency.

[0086] In one embodiment of this application, after detecting the first instruction, the method further includes:

[0087] A first identifier is added to the first instruction. The first identifier is used to indicate that the instruction processing flow of the first instruction has been completed, so that the step of obtaining the first data from the first instruction can be performed based on the first identifier.

[0088] Specifically, the first identifier is an identifier indicating that the instruction processing flow of the first instruction has been completed. Optionally, in conjunction with... Figure 2 As shown, the process of adding a first identifier to the first instruction can be executed through the Renaming module. It is understood that the instruction processing flow includes multiple processing steps after the Renaming module's processing, such as checking whether the instruction execution conditions are met via the Issue module, and writing the first data to the target address via the Execute module, etc. In other words, the instruction processing flow is not yet complete when the Renaming module's processing is finished; adding the first identifier to the first instruction in the Renaming module does not mean that the instruction processing flow of the first instruction has actually been completed; it merely uses the first identifier to "falsely" mark the completion of the first instruction's execution. Thus, by "falsely" marking the completion of the first instruction's instruction processing flow, the step of obtaining the first data from the first instruction is executed.

[0089] In one embodiment of this application, executing the second instruction based on the first data includes:

[0090] The first data is input to the input port of the second instruction to execute the instruction processing of the second instruction.

[0091] As an example four, such as Figure 3 As shown, the first instruction is `li src1, imm`; specifically, this first instruction is an immediate value load instruction, which writes the immediate value `imm` into register `src1`. The second instruction is `beq src1, src2, target`; specifically, this second instruction is a data comparison instruction, which compares the first data in register `src1` with the second data in register `src2`; the result of the comparison is stored in register `target`.

[0092] In this embodiment, on one hand, the immediate value `imm` is input to the input port of the first instruction execution module, i.e., the input port of the first execution module; on the other hand, the immediate value `imm` is input to the input port of the second instruction execution module, i.e., the input port of the second execution module. In this way, the first instruction and the second instruction can be executed in parallel, improving instruction processing efficiency.

[0093] In this embodiment, by detecting a first instruction, a first process and a second process are executed in parallel in response to the detected first instruction. The first instruction includes writing first data to a target address. The first data may include immediate values ​​and constants. That is, the first data in the first instruction is encoded within the instruction itself. Thus, when the first instruction is detected, the first data can be directly obtained from the first instruction, and the second instruction can be executed based on the first data. Therefore, the execution of the second instruction does not need to wait until the first instruction has finished executing (i.e., after writing the first data to the target address, obtaining the first data from the target address, and then executing it), but rather the second instruction is executed ahead of time, thereby saving instruction processing time and improving instruction processing efficiency.

[0094] This application provides an instruction execution device, such as... Figure 4 As shown, the instruction execution device 40 may include: an instruction detection module 401 and a first instruction execution module 402, wherein,

[0095] The instruction detection module 401 is used to detect a first instruction, wherein the first instruction includes first data, and the first data is data encoded into the first instruction and intended to be written to a target address.

[0096] The instruction execution module 402 is used to execute the first processing and the second processing in parallel in response to the detected first instruction;

[0097] The first process includes an instruction processing flow that executes the first instruction to write the first data to the target address;

[0098] The second process includes obtaining the first data from the first instruction and executing a second instruction based on the first data; the execution of the second instruction depends on the first data.

[0099] In one embodiment of this application, the apparatus further includes:

[0100] The identifier adding module is used to add a first identifier to the first instruction after the first instruction is detected. The first identifier is used to indicate that the instruction processing flow of the first instruction has been completed, so as to perform the step of obtaining the first data from the first instruction based on the first identifier.

[0101] In one embodiment of this application, the first instruction execution module is specifically used to input the first data to the input port of the second instruction in order to execute the instruction processing of the second instruction.

[0102] In one embodiment of this application, the first data includes immediate numbers and / or constants.

[0103] The apparatus in this application embodiment can execute the method provided in this application embodiment, and the implementation principle is similar. The actions performed by each module in the apparatus of each embodiment of this application correspond to the steps in the method of each embodiment of this application. For detailed functional descriptions of each module of the apparatus, please refer to the descriptions in the corresponding methods shown above, which will not be repeated here.

[0104] In this embodiment, by detecting a first instruction, a first process and a second process are executed in parallel in response to the detected first instruction. The first instruction includes writing first data to a target address. The first data may include immediate values ​​and constants. That is, the first data in the first instruction is encoded within the instruction itself. Thus, when the first instruction is detected, the first data can be directly obtained from the first instruction, and the second instruction can be executed based on the first data. Therefore, the execution of the second instruction does not need to wait until the first instruction has finished executing (i.e., after writing the first data to the target address, obtaining the first data from the target address, and then executing it), but rather the second instruction is executed ahead of time, thereby saving instruction processing time and improving instruction processing efficiency.

[0105] This application provides an instruction execution device, such as... Figure 5 As shown, the instruction execution device 50 may include: a decoding module 501, a renaming module 502, a transmitting module 503, and an execution module 504, wherein...

[0106] Decoding module 501, in response to a detected first instruction, marks the first instruction and extracts the first data from the first instruction, wherein the first data is data encoded into the first instruction and intended to be written to a target address;

[0107] The renaming module 502, in response to the marked first instruction, marks at least one second instruction that has a dependency on the first data in the first instruction as pending execution;

[0108] The transmitting module 503 detects whether the execution module is idle. When it is idle, it transmits the first instruction and at least one second instruction to the execution module simultaneously for parallel processing.

[0109] The execution module 504 directly pushes the first data as input data for the second instruction, thereby completing the parallel execution of the first instruction and at least one second instruction.

[0110] In one embodiment of this application, the first instruction includes an instruction to write the first data to the target address;

[0111] The second instruction includes instructions for performing calculations based on the first data.

[0112] The apparatus in this application embodiment can execute the method provided in this application embodiment, and the implementation principle is similar. The actions performed by each module in the apparatus of each embodiment of this application correspond to the steps in the method of each embodiment of this application. For detailed functional descriptions of each module of the apparatus, please refer to the descriptions in the corresponding methods shown above, which will not be repeated here.

[0113] In this embodiment, by detecting a first instruction, a first process and a second process are executed in parallel in response to the detected first instruction. The first instruction includes writing first data to a target address. The first data may include immediate values ​​and constants. That is, the first data in the first instruction is encoded within the instruction itself. Thus, when the first instruction is detected, the first data can be directly obtained from the first instruction, and the second instruction can be executed based on the first data. Therefore, the execution of the second instruction does not need to wait until the first instruction has finished executing (i.e., after writing the first data to the target address, obtaining the first data from the target address, and then executing it), but rather the second instruction is executed ahead of time, thereby saving instruction processing time and improving instruction processing efficiency.

[0114] This application provides an electronic device comprising: a memory and a processor; at least one program stored in the memory, which, when executed by the processor, can achieve the following compared to existing technologies: In this application, by detecting a first instruction, a first process and a second process are executed in parallel in response to the detected first instruction; wherein, the first instruction includes writing first data to a target address; the first data may include immediate values ​​and constants. That is, the first data in the first instruction is encoded in the instruction; thus, when the first instruction is detected, the first data can be directly obtained from the first instruction, and the second instruction can be executed based on the first data; thereby, the execution of the second instruction does not need to wait until the first instruction is completed, that is, after writing the first data to the target address, obtain the first data from the target address and then execute it, but instead executes the second instruction in advance, thereby saving instruction processing time and improving instruction processing efficiency.

[0115] In one alternative embodiment, an electronic device is provided, such as Figure 6 As shown, Figure 6 The illustrated electronic device 4000 includes a processor 4001 and a memory 4003. The processor 4001 and the memory 4003 are connected, for example, via a bus 4002. Optionally, the electronic device 4000 may further include a transceiver 4004, which can be used for data interaction between the electronic device and other electronic devices, such as sending and / or receiving data. It should be noted that in practical applications, the transceiver 4004 is not limited to one type, and the structure of the electronic device 4000 does not constitute a limitation on the embodiments of this application.

[0116] Processor 4001 may be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. It can implement or execute the various exemplary logic blocks, modules, and circuits described in conjunction with the disclosure of this application. Processor 4001 may also be a combination that implements computational functions, such as including one or more microprocessor combinations, a combination of a DSP and a microprocessor, etc.

[0117] Bus 4002 may include a pathway for transmitting information between the aforementioned components. Bus 4002 may be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus, etc. Bus 4002 can be divided into address bus, data bus, control bus, etc. For ease of representation, Figure 6 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0118] The memory 4003 may be ROM (Read Only Memory) or other types of static storage devices capable of storing static information and instructions, RAM (Random Access Memory) or other types of dynamic storage devices capable of storing information and instructions, or EEPROM (Electrically Erasable Programmable Read Only Memory), CD-ROM (Compact Disc Read Only Memory) or other optical disc storage, optical disc storage (including compressed optical discs, laser discs, optical discs, digital universal optical discs, Blu-ray discs, etc.), magnetic disk storage media or other magnetic storage devices, or any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible by a computer, but not limited thereto.

[0119] The memory 4003 stores application code (computer program) that executes the solution of this application, and its execution is controlled by the processor 4001. The processor 4001 executes the application code stored in the memory 4003 to implement the content shown in the foregoing method embodiments.

[0120] Electronic devices include, but are not limited to: mobile phones, laptops, multimedia players, desktop computers, etc.

[0121] This application provides a computer-readable storage medium storing a computer program that, when run on a computer, enables the computer to execute the corresponding content in the aforementioned method embodiments.

[0122] In this embodiment, by detecting a first instruction, a first process and a second process are executed in parallel in response to the detected first instruction. The first instruction includes writing first data to a target address. The first data may include immediate values ​​and constants. That is, the first data in the first instruction is encoded within the instruction. Thus, when the first instruction is detected, the first data can be directly obtained from the first instruction, and the second instruction can be executed based on the first data. Therefore, the execution of the second instruction does not need to wait until the first instruction is completed (i.e., after writing the first data to the target address, obtaining the first data from the target address, and then executing it), but rather the second instruction is executed ahead of time, thereby saving instruction processing time and improving instruction processing efficiency. The terms "first," "second," "third," "fourth," "1," "2," etc. (if present) in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in a sequence other than that shown in the figures or text.

[0123] It should be understood that although arrows indicate various operation steps in the flowcharts of this application's embodiments, the order in which these steps are implemented is not limited to the order indicated by the arrows. Unless explicitly stated herein, in some implementation scenarios of this application's embodiments, the implementation steps in each flowchart can be executed in other orders as required. Furthermore, some or all steps in each flowchart, based on the actual implementation scenario, may include multiple sub-steps or multiple stages. Some or all of these sub-steps or stages can be executed at the same time, and each sub-step or stage can also be executed at different times. In scenarios where execution times differ, the execution order of these sub-steps or stages can be flexibly configured according to requirements, and this application's embodiments do not limit this.

[0124] The above description is only an optional implementation method for some implementation scenarios of this application. It should be noted that for those skilled in the art, other similar implementation methods based on the technical concept of this application without departing from the technical concept of this application also fall within the protection scope of the embodiments of this application.

Claims

1. A method of instruction execution, the method comprising: include: Detect a first instruction, wherein the first instruction includes first data, and the first data is data encoded into the first instruction and intended to be written to a target address; In response to the detected first instruction, the first processing and the second processing are executed in parallel; The first process includes an instruction processing flow that executes the first instruction to write the first data to the target address; The second process includes obtaining the first data from the first instruction and executing a second instruction based on the first data; the execution of the second instruction depends on the first data.

2. The instruction execution method of claim 1, wherein, After detecting the first instruction, the method further includes: The Renaming module adds a first identifier to the first instruction. The first identifier is used to indicate that the instruction processing flow of the first instruction has been completed, so that the step of obtaining the first data from the first instruction can be performed based on the first identifier.

3. The instruction execution method of claim 1, wherein, The execution of the second instruction based on the first data includes: The first data is input to the input port of the second instruction to execute the instruction processing of the second instruction.

4. The instruction execution method of claim 1, wherein, The first data includes immediate numbers and / or constants.

5. An instruction execution apparatus, characterized by comprising: include: An instruction detection module is used to detect a first instruction, wherein the first instruction includes first data, and the first data is data encoded into the first instruction and intended to be written to a target address; The instruction execution module is used to execute the first processing and the second processing in parallel in response to the detected first instruction; The first process includes an instruction processing flow that executes the first instruction to write the first data to the target address; The second process includes obtaining the first data from the first instruction and executing a second instruction based on the first data; the execution of the second instruction depends on the first data.

6. The instruction execution device according to claim 5, characterized in that, The device further includes: The identifier adding module is used to add a first identifier to the first instruction through the renaming module after the first instruction is detected. The first identifier is used to "falsely" indicate that the instruction processing flow of the first instruction has been completed, so as to perform the step of obtaining the first data from the first instruction based on the first identifier.

7. An instruction execution apparatus, characterized by comprising: include: The decoding module, in response to a detected first instruction, marks the first instruction and extracts first data from the first instruction, wherein the first data is data encoded into the first instruction and intended to be written to a target address; The renaming module, in response to the marked first instruction, marks at least one second instruction that has a dependency on the first data in the first instruction as pending execution; The sending module detects whether the execution module is idle. When it is idle, it sends the first instruction and at least one second instruction to the execution module simultaneously for parallel processing. The execution module directly pushes the first data as input data for the second instruction, thereby completing the parallel execution of the first instruction and at least one second instruction.

8. The instruction execution apparatus according to claim 7, characterized in that, The first instruction includes an instruction to write the first data to the target address; The second instruction includes instructions for performing calculations based on the first data.

9. An electronic device, comprising: The electronic device includes: One or more processors; Memory; One or more applications, wherein the one or more applications are stored in the memory and configured to be executed by the one or more processors, the one or more applications being configured to: execute the instruction execution method according to any one of claims 1 to 4.

10. A computer-readable storage medium having stored thereon a computer program, characterized in that, When the computer program is executed by the processor, it implements the instruction execution method according to any one of claims 1 to 4.

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