A Power Consumption Optimization Method for an SOC Chip, an Electronic Device, and a Sliding Buffer

Abstract

The present application relates to a method for optimizing the power consumption of an SOC chip, an electronic device, and a sliding buffer, belonging to the field of integrated circuits. The chip includes: a sending unit, a sliding buffer, and a receiving unit. The sliding buffer includes: an output buffer, a skid buffer, and a control module. The control module communicates with the receiving unit through a handshake signal including output ready; during the process of writing multiple data to the sliding buffer, the control module is configured to: when it is detected that there is no data in the output buffer, write the received data to the output buffer; when it is detected that there is data in the output buffer and the output ready is at a first electrical level, write the received data to the skid buffer; when it is detected that there is data in the output buffer and the output ready is at a second electrical level, write the received data to the output buffer. By reducing the number of write caches in the sliding buffer, the power consumption overhead of the SOC chip can be reduced.

Description

Technical Field

[0001] This application belongs to the field of integrated circuits, and particularly relates to a method for optimizing the power consumption of an SOC chip, an electronic device, and a skid buffer. Background Art

[0002] In chip design, pipelining design with handshakes is generally involved, and one of them is the handshake method of valid and ready. In the handshake method of valid and ready, the ready signal at the input end needs to use the ready signal at the output end to ensure that data will not be lost or extra bubbles will be generated. However, this will cause the ready signal at the output end to affect the ready signal at the input end, resulting in timing problems when the number of pipeline stages is large. Therefore, some specific modules (such as skid buffer) are needed to interrupt the propagation of the ready signal, thereby optimizing the timing of the design.

[0003] Figure 1 FIG. is a basic functional block diagram of an existing skid buffer, including: a control module, a skid cache, a selector, and an output cache. The logical principle of this skid buffer is: when there is data input, if the input valid is at the second level and the input ready is at the second level, this data will be written into the skid cache or the output cache. Specifically, if there is no data in the output cache at this time, or there is data in the output cache and the output ready is at the second level, the selector will directly write this data into the output cache; if there is data in the output cache but the output ready is at the first level, this data will be written into the skid cache. Among them, when there is data in the output cache, the output valid is at the second level, and when there is no data in the output cache, the output valid is at the first level; when there is data in the skid cache, the input ready is at the first level, and when there is no data in the skid cache, the input ready is at the second level; when the output valid is at the second level and the output ready is at the second level, the selector will write the data in the skid cache into the output cache.

[0004] When the inventor was researching this application, it was found that: According to the principle of the existing skid buffer, during the process of the output ready changing from the first level to the second level, when writing two data entries and outputting two data entries to the skid buffer, there will be three write buffer operations. These three write buffer operations are, in order: when there is no data in the output buffer, the input data is written into the output buffer through a selector; when there is data in the output buffer and the output ready is at the first level, the input data is directly written into the skid buffer; and when there is data in the output buffer and the output ready is at the second level, the input data is written from the skid buffer into the output buffer through a selector. In the case where the data bit widths of the input data and output data of the skid buffer are relatively wide, each write buffer operation for each data entry will incur a relatively large power consumption overhead, which is not conducive to the execution efficiency of the pipeline. Summary of the Invention

[0005] In view of this, an object of this application is to provide a method for optimizing the power consumption of an SOC chip, an electronic device, and a sliding buffer, so as to improve the problem that the existing SOC chip has a large power consumption overhead and is not conducive to the execution efficiency of the pipeline.

[0006] The embodiments of this application are implemented as follows:

[0007] In a first aspect, an embodiment of this application provides an SOC chip, including: a sending unit, a sliding buffer, and a receiving unit, where the sending unit is connected to the receiving unit through the sliding buffer; the sliding buffer includes: an output buffer, a skid buffer, and a control module; the control module communicates with the receiving unit through a handshake signal including output ready; during the process of the sending unit writing multiple data entries to the sliding buffer, the control module is configured to: when it is detected that there is no data in the output buffer, write the received data into the output buffer; when it is detected that there is data in the output buffer and the output ready is at the first level, write the received data into the skid buffer; when it is detected that there is data in the output buffer and the output ready is at the second level, write the received data into the output buffer.

[0008] In the embodiments of the present application, by improving the structure and principle of the sliding buffer involved in the SOC chip, when writing multiple data to the sliding buffer, during the process that the output ready changes from the first level to the second level, the sliding buffer eliminates the operation of writing data from the skid buffer to the output buffer. For the same three write buffer operations, the present application can write one more data than the existing sliding buffer (the present application can write three data for three write buffer operations, while the existing one can only write two data). And the present application only needs two write buffer operations to write two data. Compared with the existing sliding buffer, the number of write buffers is reduced, thereby reducing the power consumption overhead of the sliding buffer, and further improving the problem that the existing SOC chip has a large power consumption overhead and is not conducive to the execution efficiency of the pipeline.

[0009] Combined with a possible implementation manner of the first aspect embodiment, the sliding buffer further includes: a selector, the selector is respectively connected to the output buffer and the skid buffer; the handshake signal further includes output valid, and the control module is further configured to: initially default to control the selector to select the data output in the output buffer; when selecting the data in the output buffer as the output and both the output buffer and the skid buffer have data, if it is detected that the output valid is the second level and the output ready is the second level, after the data in the currently selected output buffer is output, control the selector to switch to select the data output in the skid buffer; when selecting the data in the skid buffer as the output and the skid buffer has data, if it is detected that the output valid is the second level and the output ready is the second level, after the data in the currently selected skid buffer is output, control the selector to switch to select the data output in the output buffer.

[0010] In the embodiments of the present application, by setting a two-way selector to select the data output in the skid buffer or the output buffer, the output port of the sliding buffer can be reduced and the data input port of the receiving unit can be reduced.

[0011] Combined with a possible implementation manner of the first aspect embodiment, the control module is further configured to: when detecting that there is data in the output buffer, or when selecting the data output in the skid buffer, control the output valid to be the second level, and in other cases, control the output valid to be the first level.

[0012] In the embodiments of the present application, only when data is detected in the output buffer or when data in the skid buffer is selected for output, the output valid is controlled to be at the second level to indicate that the skid buffer has data to output, so as to ensure that the data interaction with the receiving unit is not affected while reducing the power consumption overhead of the skid buffer.

[0013] In a possible implementation manner combining the embodiments of the first aspect, the control module communicates with the receiving unit through a handshake signal including input valid and input ready; the control module is further configured to: when detecting that the input valid is at the second level, control whether the skid buffer receives the data sent by the sending unit by controlling the level state of the input ready; wherein, when the input ready is at the second level, the skid buffer receives the data sent by the sending unit.

[0014] In the embodiments of the present application, the level state of the input ready can be controlled as needed to control whether the skid buffer receives the data sent by the sending unit, so as to improve the applicability of the solution.

[0015] In a possible implementation manner combining the embodiments of the first aspect, the control module is further configured to: when selecting the data in the output buffer for output and detecting that there is data in the skid buffer, or when selecting the data in the skid buffer for output and there is data in the output buffer, control the input ready to be at the first level.

[0016] In the embodiments of the present application, when selecting the data in the output buffer for output and detecting that there is data in the skid buffer, or when selecting the data in the skid buffer for output and there is data in the output buffer, the input ready is controlled to be at the first level to indicate that the skid buffer cannot receive input data, so as to avoid causing congestion in the buffer, and to ensure that the normal data interaction between the sending unit and the receiving unit is not affected while reducing the power consumption overhead of the skid buffer.

[0017] In a second aspect, the embodiments of the present application further provide an electronic device, including: an SOC chip provided as described in the embodiments of the first aspect and / or any possible implementation manner combining the embodiments of the first aspect.

[0018] In a third aspect, an embodiment of the present application further provides a method for optimizing the power consumption of a sliding buffer, characterized in that the sliding buffer includes an output buffer, a skid buffer, and a control module, and the control module communicates with a receiving unit at the next level of the sliding buffer through a handshake signal including output ready; the method includes: during the process of writing multiple pieces of data to the sliding buffer, when the control module detects that there is no data in the output buffer, it writes the received data to the output buffer; when the control module detects that there is data in the output buffer and the output ready is at a first level, it writes the received data to the skid buffer; when the control module detects that there is data in the output buffer and the output ready is at a second level, it writes the received data to the output buffer.

[0019] Combined with a possible implementation manner of the third aspect embodiment, the sliding buffer further includes a selector, and the selector is respectively connected to the output buffer and the skid buffer; the handshake signal further includes output valid, and the method further includes: initially defaulting to select the data output in the output buffer; when selecting the data in the output buffer as the output and both the output buffer and the skid buffer have data, if it is detected that the output valid is at a second level and the output ready is at a second level, after the data currently selected in the output buffer is output, select the data output in the skid buffer; when selecting the data in the skid buffer as the output and the skid buffer has data, if it is detected that the output valid is at a second level and the output ready is at a second level, after the data currently selected in the skid buffer is output, select the data output in the output buffer.

[0020] Combined with a possible implementation manner of the third aspect embodiment, the method further includes: when the control module detects that there is data in the output buffer, or when selecting the data output in the skid buffer, it controls the output valid to be at a second level, and in other cases, it controls the output valid to be at a first level.

[0021] Combined with a possible implementation manner of the third aspect embodiment, the control module communicates with a sending unit at the previous level of the sliding buffer through a handshake signal including input valid and input ready; the method further includes: when detecting that the input valid is at a second level, controlling whether the sliding buffer receives the data sent by the sending unit by controlling the level state of the input ready; wherein, when the input ready is at a second level, the sliding buffer receives the data sent by the sending unit.

[0022] Other features and advantages of the present application will be described in the subsequent specification, and in part will be obvious from the specification, or will be understood by implementing the embodiments of the present application. The objectives and other advantages of the present application can be achieved and obtained by the structures specifically pointed out in the written specification and the accompanying drawings. Description of the Drawings

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the accompanying drawings required for use in the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can be obtained based on these drawings. As shown by the accompanying drawings, the above and other objectives, features, and advantages of the present application will be more clearly presented. The same reference numerals in all the accompanying drawings indicate the same parts. The accompanying drawings are not deliberately drawn to scale in actual size, and the focus is on showing the gist of the present application.

[0024] Figure 1 It is a basic functional block diagram of a sliding buffer in the prior art.

[0025] Figure 2 It shows a schematic structural diagram of a SOC chip provided by an embodiment of the present application.

[0026] Figure 3 It shows a schematic structural diagram of a sliding buffer provided by an embodiment of the present application.

[0027] Figure 4 It shows a schematic structural diagram of another sliding buffer provided by an embodiment of the present application.

[0028] Figure 5 It shows a schematic structural diagram of an electronic device provided by an embodiment of the present application.

[0029] Figure 6 It shows a schematic diagram of the principle of a method for optimizing the power consumption of a sliding buffer provided by an embodiment of the present application. Detailed Embodiments

[0030] The following will describe the technical solutions in the embodiments of the present application in combination with the accompanying drawings in the embodiments of the present application.

[0031] It should be noted that like reference numerals and letters refer to like items in the following figures. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. At the same time, in the description of the present application, relational terms such as "first", "second", etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising", "including" or any other variation thereof are intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the phrase "comprising a..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the element.

[0032] In the description of the present application, it should also be noted that, unless otherwise clearly defined and limited, the terms "connected" and "coupled" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can also be an electrical connection; it can be directly connected, or indirectly connected through an intermediate medium, and can be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific situations.

[0033] Furthermore, the term "and / or" in the present application is only a description of the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the term "plural" defaults to 2 or more without special instructions; similarly, "multiple levels" means 2 levels or more.

[0034] In view of the problem that the existing skid buffer has high power consumption and consumes a large amount of storage bandwidth. For example, when writing multiple data to the skid buffer, during the process that the output ready changes from the first level to the second level, the skid buffer will have 3 write cache operations (the first time when there is no data in the output cache, the input data is written to the output cache through the selector, the second time when there is data in the output cache but the output ready is at the first level, the input data is written to the skid cache, and the third time when the output ready is at the second level, the input data is written from the skid cache to the output cache). This will bring a large power consumption overhead and is not conducive to the execution of the pipeline. Based on this, the embodiment of the present application provides a method for optimizing the power consumption of a skid buffer, which optimizes the power consumption of the skid buffer by reducing the number of data write caches.

[0035] For the sake of easy understanding, the SOC (System on Chip) chip provided by the embodiments of the present application will be described below in conjunction with Figure 2 The SOC chip includes a sending unit, a receiving unit, and a sliding buffer located between the sending unit and the receiving unit, that is, the sending unit is connected to the receiving unit through the sliding buffer.

[0036] It should be noted that the above-mentioned sending unit and receiving unit are relative. When sending data, it can be regarded as a sending unit, and when receiving data, it can be regarded as a receiving unit. For example, as a sending unit that sends data to the next level in the pipeline, it can also be regarded as a receiving unit that receives data sent by the previous level in the pipeline. Similarly, the receiving unit can also be used as a sending unit that sends data to the next level in the pipeline.

[0037] In addition, in the pipeline design of the SOC chip, the deeper the pipeline, the more stages are involved. Correspondingly, the number of sending units, receiving units, and sliding buffers is also more. The sending unit and receiving unit in the embodiments of the present application are a relative concept. In different pipeline designs, the specific structures of the sending unit and the receiving unit are different. Taking the 3-stage pipeline of the processor (including: instruction fetch, decoding, execution) as an example, the instruction fetch unit can be used as the sending unit of the decoding unit (at this time, the instruction fetch unit sends instructions to the decoding unit), the decoding unit can be used as the receiving unit of the instruction fetch unit (at this time, the decoding unit receives the instructions sent by the instruction fetch unit), the decoding unit can also be used as the sending unit of the execution unit (at this time, the decoding unit sends the instructions after decoding processing to the execution unit), and the execution unit can be used as the receiving unit of the decoding unit (at this time, the execution unit receives the instructions after decoding processing sent by the decoding unit), etc.

[0038] In the pipeline design of the SOC chip, usually an additional sliding buffer is added between the previous-stage sending unit and the subsequent-stage receiving unit to break the handshake signal timing path of the subsequent-stage receiving unit, so as to solve the anti-pressure timing problem and will not affect the forward path. The pipeline technology is a basic technology of modern SOC chips. The deeper the pipeline, because each stage of the pipeline needs to perform handshakes, the anti-pressure signal of the last stage of the pipeline may crosstalk all the way to the first stage, causing serious anti-pressure (Backpressure) timing problems. Therefore, it is necessary to break the propagation of the handshake signal timing of the subsequent stage.

[0039] The sending unit is configured to send data to the receiving unit through a sliding buffer. The sliding buffer communicates with the receiving unit through handshake signals including output valid and output ready. The sliding buffer communicates with the sending unit through handshake signals including input valid and input ready. The sliding buffer controls whether to write data and read data based on signals from the sending unit (input valid) and the receiving unit (output ready).

[0040] As Figure 3 shown, the sliding buffer includes: an output buffer, a skid buffer, and a control module. The control module is respectively connected to the output buffer and the skid buffer. The control module communicates with the receiving unit through handshake signals including output valid and output ready. The control module communicates with the sending unit through handshake signals including input valid and input ready.

[0041] The control module is configured to control the output buffer or the skid buffer to write data and read data based on the handshake signals from the sending unit and the receiving unit. For example, during the process of the sending unit writing multiple pieces of data to the sliding buffer, the control module is configured to write the received data to the output buffer when it detects that there is no data in the output buffer; write the received data to the skid buffer when it detects that there is data in the output buffer and the output ready is at the first electrical level; write the received data to the output buffer when it detects that there is data in the output buffer and the output ready is at the second electrical level. In the example of this application, when writing multiple pieces of data to the sliding buffer, during the process of the output ready changing from the first electrical level to the second electrical level, the sliding buffer eliminates the operation of writing data from the skid buffer to the output buffer, so that for the same three write buffer operations, this application can write one more piece of data than the existing sliding buffer (this application can write three pieces of data in three write buffer operations, while the existing one can only write two pieces of data), and this application only needs two write buffer operations to write two pieces of data. Compared with the existing sliding buffer, the number of write buffer operations is reduced, thereby reducing the power consumption overhead of the sliding buffer.

[0042] Among them, both the output buffer and the skid buffer are used to cache the input data. The cache includes but is not limited to independent storage devices such as Random Access Memory (RAM), registers, and Flash (flash memory). The priority of the output buffer is higher than that of the skid buffer. When outputting data, if there is data in both the output buffer and the skid buffer, the data in the output buffer is preferentially output. When writing data, if there is no data in both the output buffer and the skid buffer, the data is preferentially written to the output buffer.

[0043] Among them, whether there is data in the output buffer or the skid buffer can be determined by the internal state of the control module, and the state can be, but is not limited to, a state machine and registers. For example, when there is data in the output buffer or the skid buffer, the values of the corresponding state machine and registers are 1, and when there is no data in the output buffer or the skid buffer, the values of the corresponding state machine and registers are 0. Whether there is data in the output buffer or the skid buffer can be learned by detecting the values of the corresponding state machine and registers.

[0044] The control module is further configured to control the timing of the output valid. For example, the control module is configured to make the output valid at the second level when it detects that there is data in the output buffer or when it selects the data output from the skid buffer, and make the output valid at the first level in other cases.

[0045] The control module is further configured to control the timing of the input ready. For example, the control module is further configured to make the input ready at the first level when it selects the data output from the output buffer and detects that there is data in the skid buffer, or when it selects the data output from the skid buffer and there is data in the output buffer, that is, the input ready is at the first level, and make the input ready at the second level in other cases, that is, the input ready is at the second level.

[0046] The control module is further configured to control whether the slip buffer receives the data sent by the sending unit. For example, when it detects that the input valid is at the second level, it controls whether the slip buffer receives the data sent by the sending unit by controlling the level state of the input ready; among them, when the input ready is at the second level, the slip buffer receives the data sent by the sending unit, and when the input ready is at the first level, the slip buffer refuses to receive the data sent by the sending unit.

[0047] Among them, when the first level is a low level (which can be represented by the value 0), the second level is a high level (which can be represented by the value 1), and when the first level is a high level, the second level is a low level.

[0048] If the input ready = 0 (low level), it means that the sliding buffer cannot receive input data. If the input ready = 1 (high level), it means that the sliding buffer can receive input data. If the input valid = 0, it means that there is no data to be input into the sliding buffer. If the input valid = 1, it means that there is data to be input into the sliding buffer. If the output valid = 1, it means that the sliding buffer has data to output. If the output valid = 0, it means that the sliding buffer has no data to output. If the output ready = 1, it means that the next stage (receiving unit) can receive the data output by the sliding buffer. If the output ready = 0, it means that the next stage cannot receive the data output by the sliding buffer. At this time, the first level is the low level and the second level is the high level.

[0049] Conversely, if the input ready = 1, it means that the sliding buffer cannot receive input data. If the input ready = 0, it means that the sliding buffer can receive input data. If the input valid = 1, it means that there is no data to be input into the sliding buffer. If the input valid = 0, it means that there is data to be input into the sliding buffer. If the output valid = 0, it means that the sliding buffer has data to output. If the output valid = 1, it means that the sliding buffer has no data to output. If the output ready = 0, it means that the next stage (receiving unit) can receive the data output by the sliding buffer. If the output ready = 1, it means that the next stage cannot receive the data output by the sliding buffer. At this time, the first level is the high level and the second level is the low level.

[0050] As Figure 4 shown, the sliding buffer further includes: a selector, which is respectively connected to the output buffer and the skid buffer. The selector is a 2-to-1 multiplexer, which is used to select the data output from the skid buffer or the output buffer under the control of the control module. At this time, the control module is further configured to: initially default to control the selector to select the data output from the output buffer. When selecting the data in the output buffer as the output, and both the output buffer and the skid buffer have data, if it is detected that the output valid is the second level and the output ready is the second level, after the data in the currently selected output buffer is output, control the selector to switch to select the data output from the skid buffer. When selecting the data in the skid buffer as the output, and the skid buffer has data, if it is detected that the output valid is the second level and the output ready is the second level, after the data in the currently selected skid buffer is output, control the selector to switch to select the data output from the output buffer.

[0051] For better understanding of the functions of the control module in the sliding buffer of the embodiments of the present application, the functions of the control module are summarized and described below. The control module is used to control the level states of input ready and output valid, as well as the write enable control of the skid buffer and the output buffer, and the control of the selected output data of the selector.

[0052] In the initial state (the initial state is the state after the sliding buffer or the SOC chip is reset), by default, there is no data in both the skid buffer and the output buffer, the output valid is at the first level, and the input ready is at the second level. When there is input data, the input valid is set to the second level at the cycle when the input data arrives. If the input ready is at the second level at this time, the sliding buffer can receive this data, and this data will be written to the skid buffer or the output buffer. If the input ready is at the first level at this time, the sliding buffer cannot receive this data, and this input data needs to wait until the input ready is at the second level to be received.

[0053] When the sliding buffer can receive input data, that is, when the input ready is at the second level. If there is no data in both the output buffer and the skid buffer at this time, the control module will control the input data to be written to the output buffer. If there is data in the output buffer and the output ready is at the second level at this time, the input data will be written to the output buffer. If there is data in the output buffer and the output ready is at the first level at this time, the input data will be written to the skid buffer. If there is data in the skid buffer and the selector selects the data in the skid buffer for output, the input data will be written to the output buffer.

[0054] When there is data in the output buffer, the control module controls the selector to select the data in the output buffer as the output. When there is no data in the output buffer and there is data in the skid buffer, the control module controls the selector to select the data in the skid buffer as the output.

[0055] When there is data in the output buffer, or there is data in the skid buffer and the selector selects the data in the skid buffer for output, the output valid will be set to the second level. At this time, the output valid is at the second level, and in other cases, the output valid is at the first level. When the data in the output buffer is selected for output and it is detected that there is data in the skid buffer, or when the skid buffer is selected for output and there is data in the output buffer, the input ready is at the first level, and in other cases, the input ready is at the second level.

[0056] In an embodiment of the present application, by improving the structure and control principle of the sliding buffer, when writing multiple data to the sliding buffer, in the process of the output ready changing from the first level to the second level, the sliding buffer eliminates the operation of writing data from the skid cache to the output cache, so that the present application only requires two write cache operations to write two data, reducing the number of write cache operations, thereby reducing the power consumption overhead of the sliding buffer.

[0057] The SOC chip provided in the embodiments of the present application may be a SOC including a pipeline design, for example, various processors including a pipeline design. The processor may be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it may also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic devices.

[0058] Based on the same inventive concept, the embodiment of the present application further provides an electronic device, which includes the above-mentioned SOC chip. In an optional embodiment, the structure of the electronic device can be as follows: Figure 5 In addition to the aforementioned SOC chip (such as a processor), the electronic device may also include a transceiver, a memory, a communication bus, and the like.

[0059] The transceiver, memory, and SOC chip components are electrically connected to each other directly or indirectly to achieve data transmission or interaction. For example, these components can be electrically connected to each other through one or more communication buses 230 or signal lines. Among them, the transceiver is used to send and receive data. The memory is used to store a computer program, which includes at least one software function module that can be stored in the memory in the form of software or firmware or solidified in the operating system (OS) of the electronic device. The SOC chip is used to execute the software function module or computer program stored in the memory.

[0060] Among them, the memory can be, but is not limited to, Random Access Memory (RAM), Read Only Memory (ROM), Programmable Read-Only Memory (PROM), Erasable Programmable Read-Only Memory (EPROM), Electric Erasable Programmable Read-Only Memory (EEPROM), etc.

[0061] Among them, the above-mentioned electronic devices include, but are not limited to, mobile phones, tablets, computers, servers, etc.

[0062] For the SOC chip provided by the electronic device embodiment, its implementation principle and the technical effects produced are the same as those of the foregoing SOC chip embodiment. For the sake of brief description, for the parts not mentioned in the electronic device embodiment, reference may be made to the corresponding content in the foregoing SOC chip embodiment.

[0063] Based on the same inventive concept, the embodiment of the present application also provides a method for optimizing the power consumption of a sliding buffer. The sliding buffer includes an output buffer, a skid buffer, and a control module. The control module communicates with a receiving unit at the next level of the sliding buffer through a handshake signal including output ready. The following will be combined with Figure 6 to describe the method for optimizing the power consumption of the sliding buffer provided by the embodiment of the present application.

[0064] S1: During the process of writing multiple pieces of data to the sliding buffer, when the control module detects that there is no data in the output buffer, it writes the received data to the output buffer.

[0065] Among them, when there is no data in both the output buffer and the skid buffer, the control module preferentially writes the received data to the output buffer.

[0066] S2: When the control module detects that there is data in the output buffer and the output ready is at the first level, it writes the received data to the skid buffer.

[0067] S3: When the control module detects that there is data in the output buffer and the output ready is at the second level, it writes the received data to the output buffer.

[0068] The sliding buffer further includes a selector, which is respectively connected to the output buffer and the skid buffer; the handshaking signal of the control module with the receiving unit further includes output valid, and the method further includes: initially defaulting to select the data in the output buffer for output; when selecting the data in the output buffer as the output, and both the output buffer and the skid buffer have data, if it is detected that the output valid is at the second level and the output ready is at the second level, after the data in the currently selected output buffer is output, select the data in the skid buffer for output; when selecting the data in the skid buffer as the output, and the skid buffer has data, if it is detected that the output valid is at the second level and the output ready is at the second level, after the data in the currently selected skid buffer is output, select the data in the output buffer for output.

[0069] The method further includes: when the control module detects that there is data in the output buffer, or when selecting the data in the skid buffer for output, control the output valid to be at the second level, and in other cases control the output valid to be at the first level.

[0070] In addition, the control module communicates with the sending unit at the upper level of the sliding buffer through a handshaking signal including input valid and input ready; the method further includes: when detecting that the input valid is at the second level, control whether the sliding buffer receives the data sent by the sending unit by controlling the level state of the input ready; wherein, when the input ready is at the second level, the sliding buffer receives the data sent by the sending unit.

[0071] The method further includes: when the control module selects the data in the output buffer for output and detects that there is data in the skid buffer, or when selecting the data in the skid buffer for output and there is data in the output buffer, control the input ready to be at the first level.

[0072] The sliding buffer provided by the method embodiment has the same implementation principle and the same technical effects as the sliding buffer in the foregoing SOC chip embodiment. For the sake of brief description, for the parts not mentioned in the method embodiment, reference can be made to the corresponding content in the foregoing SOC chip embodiment.

[0073] It should be noted that the various embodiments in this specification are all described in a progressive manner. Each embodiment focuses on the differences from other embodiments. For the same or similar parts among the various embodiments, reference can be made to each other.

[0074] As described above, it is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of changes or substitutions, which should all be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. An SOC chip, characterized in that, Comprising: A sending unit, a sliding buffer, and a receiving unit, wherein the sending unit is connected to the receiving unit through the sliding buffer; The sliding buffer includes: an output buffer, a skid buffer, and a control module; the control module communicates with the receiving unit through a handshake signal including output ready; During the process of the sending unit writing multiple pieces of data to the sliding buffer, the control module is configured as follows: When it is detected that there is no data in the output buffer, write the received data to the output buffer; When it is detected that there is data in the output buffer and the output ready is at the first level, write the received data to the skid buffer; When it is detected that there is data in the output buffer and the output ready is at the second level, write the received data to the output buffer.

2. The SOC chip according to claim 1, characterized in that, The sliding buffer further includes: a selector, the selector is respectively connected to the output buffer and the skid buffer; the handshake signal further includes output valid, and the control module is further configured as follows: Initially and by default, control the selector to select the data in the output buffer for output; When selecting the data in the output buffer as the output and there is data in both the output buffer and the skid buffer, if it is detected that the output valid is at the second level and the output ready is at the second level, after the data in the currently selected output buffer is output, control the selector to switch to select the data in the skid buffer for output; When selecting the data in the skid buffer as the output and there is data in the skid buffer, if it is detected that the output valid is at the second level and the output ready is at the second level, after the data in the currently selected skid buffer is output, control the selector to switch to select the data in the output buffer for output.

3. The SOC chip according to claim 2, wherein The control module is further configured as follows: When it is detected that there is data in the output buffer, or when selecting the data in the skid buffer for output, control the output valid to be at the second level, and in other cases, control the output valid to be at the first level.

4. The SOC chip according to claim 1, characterized in that, The control module communicates with the receiving unit through a handshake signal including input valid and input ready; The control module is further configured as follows: when it is detected that the input valid is at the second level, control whether the sliding buffer receives the data sent by the sending unit by controlling the level state of the input ready; wherein, when the input ready is at the second level, the sliding buffer receives the data sent by the sending unit.

5. The SOC chip according to claim 4, characterized in that, The control module is further configured as follows: when selecting the data in the output buffer for output and it is detected that there is data in the skid buffer, or when selecting the data in the skid buffer for output and there is data in the output buffer, control the input ready to be at the first level.

6. An electronic device, characterized in that, Comprising: The SOC chip according to any one of claims 1-5.

7. A power consumption optimization method for a sliding buffer, characterized in that, The sliding buffer includes an output buffer, a skid buffer, and a control module. The control module communicates with a receiving unit at the next stage of the sliding buffer through a handshake signal including output ready; the method includes: During the process of writing multiple pieces of data to the sliding buffer, when the control module detects that there is no data in the output buffer, it writes the received data to the output buffer; When the control module detects that there is data in the output buffer and the output ready is at the first level, it writes the received data to the skid buffer; When the control module detects that there is data in the output buffer and the output ready is at the second level, it writes the received data to the output buffer.

8. The method according to claim 7, wherein the sliding buffer further includes a selector, and the selector is respectively connected to the output buffer and the skid buffer; the handshake signal further includes output valid, and the method further includes: Initially, the data in the output buffer is default selected for output; When selecting the data in the output buffer as the output, and there is data in both the output buffer and the skid buffer, if it is detected that the output valid is at the second level and the output ready is at the second level, after the data in the currently selected output buffer is output, the data in the skid buffer is selected for output; When selecting the data in the skid buffer as the output, and there is data in the skid buffer, if it is detected that the output valid is at the second level and the output ready is at the second level, after the data in the currently selected skid buffer is output, the data in the output buffer is selected for output.

9. The method according to claim 8, wherein The method further includes: When the control module detects that there is data in the output buffer, or when selecting the data in the skid buffer for output, it controls the output valid to be at the second level, and in other cases, it controls the output valid to be at the first level.

10. The method according to claim 7, wherein The control module communicates with a sending unit at the previous stage of the sliding buffer through a handshake signal including input valid and input ready; the method further includes: When it is detected that the input valid is at the second level, the control of whether the sliding buffer receives the data sent by the sending unit is achieved by controlling the level state of the input ready; wherein, when the input ready is at the second level, the sliding buffer receives the data sent by the sending unit.

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