Storage device, method of operating the same, and page buffer

Abstract

The present disclosure relates to a memory device, an operating method thereof, and a page buffer. A memory device having improved operating speed includes a memory cell, a page buffer connected to the memory cell through a bit line, and a program operation controller for controlling an operation of the page buffer. The page buffer includes a bit line voltage supplier for supplying a pre-charge voltage to the bit line, a sense node voltage supplier for supplying a sense node pre-charge voltage to a sense node connected to the bit line, a first latch for storing first verification data, a sense node connector for releasing a connection between the bit line and the sense node after storing the first verification data, and a second latch for storing second verification data determined from a voltage of the sense node after the connection between the bit line and the sense node is released.

Description

Technical Field

[0001] This disclosure generally relates to an electronic device, and more specifically to a storage device and a method of operating the same. Background Technology

[0002] A storage device is a device that stores data under the control of a host device such as a computer or smartphone. A storage device can include a storage unit for storing data and a storage controller for controlling the storage unit. Storage devices are classified as volatile storage devices and non-volatile storage devices.

[0003] Volatile memory devices are memory devices that store data only when powered on and lose the stored data when power is interrupted. Volatile memory devices can include static random access memory (SRAM), dynamic random access memory (DRAM), etc.

[0004] Non-volatile memory devices are those whose data is not lost even when the power supply is interrupted. Non-volatile memory devices can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable ROM (EEROM), flash memory, etc. Summary of the Invention

[0005] The embodiments provide a storage device with improved reliability and improved operating speed, as well as a method of operating the storage device.

[0006] According to one aspect of this disclosure, a storage device is provided, the storage device comprising: a storage cell; a page buffer connected to the storage cell via a bit line; and a programming operation controller controlling the operation of the page buffer, wherein the page buffer comprises: a bit line voltage supplier providing a pre-charge voltage to the bit line when a verification voltage is applied to the storage cell; a sense node voltage supplier providing a sense node pre-charge voltage to a sense node connected to the bit line when the bit line is pre-charged; a first latch storing first verification data determined based on a voltage level of the sense node after the sense node is charged; a sense node connector disconnecting the bit line from the sense node after the first verification data is stored; and a second latch storing second verification data determined based on the voltage level of the sense node after the connection between the bit line and the sense node is disconnected.

[0007] According to another aspect of this disclosure, a method for operating a storage device is provided, the storage device including storage cells and page buffers connected to the storage cells via bit lines, the page buffers including a plurality of latches for storing verification data determined based on a voltage level of a sensing node connected to the bit lines, the method comprising the steps of: applying a verification voltage to the storage cells; providing a pre-charge voltage to the bit lines and sensing nodes of the page buffer while the verification voltage is applied; storing first verification data determined based on the voltage level of the sensing nodes in a first latch after the sensing nodes are charged until the connection between the bit lines and the sensing nodes is disconnected; and storing second verification data determined based on the voltage level of the sensing nodes in a second latch after the connection between the bit lines and the sensing nodes is disconnected.

[0008] According to another aspect of this disclosure, a page buffer connected to a memory cell via a bit line is provided, the page buffer comprising: a bit line voltage supplier that provides a pre-charge voltage to the bit line when a verification voltage is applied to the memory cell; a sense node voltage supplier that provides a sense node pre-charge voltage to a sense node connected to the bit line when the bit line is pre-charged; a first latch that stores first verification data determined based on the voltage level of the sense node after the sense node is charged; a sense node connector that disconnects the bit line from the sense node after the first verification data is stored; and a second latch that stores second verification data determined based on the voltage level of the sense node after the connection between the bit line and the sense node is disconnected. Attached Figure Description

[0009] Example embodiments will now be described more fully with reference to the accompanying drawings; however, they may be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will convey the scope of the example embodiments to those skilled in the art.

[0010] In the accompanying drawings, dimensions may be exaggerated for clarity. It should be understood that when an element is referred to as being "between" two elements, it can be the only element between the two elements, or there may be one or more intermediate elements. Similar reference numerals always refer to similar elements.

[0011] Figure 1 This is a diagram illustrating a storage device including a storage device according to an embodiment of the present disclosure.

[0012] Figure 2This is an example Figure 1 A diagram of the storage device shown.

[0013] Figure 3 This is an example Figure 2 A diagram showing the structure of any one of the storage blocks in the diagram.

[0014] Figure 4A and Figure 4B This is a diagram illustrating the threshold voltage distribution of a single-stage cell.

[0015] Figure 5A and Figure 5B This is a diagram illustrating the threshold voltage distribution of a multi-stage unit.

[0016] Figure 6A and Figure 6B This is a diagram illustrating the threshold voltage distribution of a three-level unit.

[0017] Figure 7A and Figure 7B This is a diagram illustrating the threshold voltage distribution of a four-level unit.

[0018] Figure 8 This is a diagram illustrating programming operations.

[0019] Figure 9 This is a diagram illustrating dual verification operation and bit line voltage regulation.

[0020] Figure 10 Examples include Figure 2 A diagram of any page buffer in the input / output circuit shown.

[0021] Figure 11 This is an internal circuit diagram of a page buffer according to an embodiment of the present disclosure.

[0022] Figure 12 This is an example of what is applied to Figure 11 The diagram shows the various control signals of the circuit.

[0023] Figure 13 This is a diagram illustrating a method for performing dual verification operations by precharging a sensing node once, according to an embodiment of the present disclosure.

[0024] Figure 14 This is a flowchart illustrating an operation method of a storage device according to an embodiment of the present disclosure.

[0025] Figure 15 This is a diagram illustrating a method for performing a programming verification operation according to an embodiment of the present disclosure.

[0026] Figure 16 This is a block diagram illustrating a memory card system for an application storage device according to an embodiment of the present disclosure.

[0027] Figure 17 This is a block diagram illustrating a solid-state drive (SSD) system for an application storage device according to an embodiment of the present disclosure.

[0028] Figure 18 This is a block diagram illustrating a user system of an application storage device according to an embodiment of the present disclosure. Detailed Implementation

[0029] The specific structural or functional descriptions disclosed herein are merely for the purpose of describing various embodiments based on the concepts of this disclosure. Embodiments based on the concepts of this disclosure can be implemented in various forms, and the invention should not be construed as limited to the embodiments set forth herein.

[0030] Figure 1 This is a diagram illustrating a storage device including a storage device according to an embodiment of the present disclosure.

[0031] Reference Figure 1 The storage device 50 may include the storage device 100 and a storage controller 200 for controlling the operation of the storage device 100. The storage device 50 may be a device for storing data under the control of a host 300, such as a mobile phone, smartphone, MP3 player, laptop, desktop computer, game console, television, tablet computer, or in-vehicle infotainment system.

[0032] Depending on the host interface used as the communication scheme with host 300, storage device 50 can be manufactured as any of various types of storage devices. Storage device 50 can be implemented using any of the following types of storage devices: solid-state drive (SSD), multimedia card (MMC), embedded MMC (eMMC), miniature MMC (RS-MMC), micro-MMC, secure digital card (SD), mini-SD card, micro-SD card, universal serial bus (USB) storage device, universal flash memory (UFS) device, compact flash memory (CF) card, smart media card (SMC), memory stick, etc.

[0033] Storage device 50 can be manufactured in any of a variety of package types. Storage device 50 can be manufactured in any of a variety of package types such as point-of-purchase (POP), system-in-package (SIP), system-on-chip (SOC), multi-chip package (MCP), chip-on-board (COB), wafer-level fabrication package (WFP), and wafer-level stacked package (WSP).

[0034] Storage device 100 can store data. Storage device 100 can operate under the control of storage controller 200. Storage device 100 may include a storage cell array (not shown) containing a plurality of storage cells for storing data.

[0035] Each storage cell can be configured as a single-level cell (SLC) storing one data bit, a multi-level cell (MLC) storing two data bits, a three-level cell (TLC) storing three data bits, or a four-level cell (QLC) storing four data bits.

[0036] A storage cell array (not shown) may include multiple storage blocks. A storage block may include multiple storage cells. A storage block may include multiple pages. In one embodiment, a page may be a unit for storing data in storage device 100 or retrieving data stored in storage device 100. A storage block may be a unit for erasing data.

[0037] In one embodiment, the storage device 100 may be, for example, Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Generation IV Low Power Double Data Rate (LPDDR4) SDRAM, Graphics Double Data Rate (GDDR) SRAM, Low Power DDR (LPDDR), Rambus Dynamic Random Access Memory (RDRAM), NAND flash memory, Vertical NAND flash memory, NOR flash memory, Resistive Random Access Memory (RRAM), Phase Change Random Access Memory (PRAM), Magnetoresistive Random Access Memory (MRAM), Ferroelectric Random Access Memory (FRAM), Spin-Torque Random Access Memory (STT-RAM), etc. In this specification, the storage device 100 will be described as NAND flash memory, etc.

[0038] Storage device 100 can receive commands CMD and addresses ADDR from storage controller 200 and access the region selected by address ADDR in the storage cell array. Storage device 100 can perform operations instructed by command CMD on the region selected by address ADDR. For example, storage device 100 can perform programming operations, reading operations, and erasing operations. In a programming operation, storage device 100 can program data in the region selected by address ADDR. In a reading operation, storage device 100 can read data from the region selected by address ADDR. In an erasing operation, storage device 100 can erase data stored in the region selected by address ADDR.

[0039] In one embodiment, the storage device 100 may include multiple planes. A plane can be an independently operating unit. For example, the storage device 100 may include two, four, or eight planes. Multiple planes can simultaneously and independently perform programming, reading, or erasing operations.

[0040] The storage controller 200 can control the overall operation of the storage device 50.

[0041] When power is supplied to storage device 50, storage controller 200 can execute instructions, for example, encoded in firmware (FW). When storage device 100 is a flash memory storage device, FW may include a host interface layer (HIL) for controlling communication with host 300, a flash translation layer (FTL) for controlling communication between host and storage device 100, and a flash interface layer (FIL) for controlling communication with storage device 100.

[0042] The storage controller 200 can receive data and logical block addresses (LBAs) from the host 300 and translate the LBAs into physical block addresses (PBAs), which represent the addresses of the storage cells included in the storage device 100 where data will be stored. In this specification, LBA and "logical address" can be used interchangeably. In this specification, PBA and "physical address" can be used interchangeably.

[0043] The storage controller 200 can respond to requests from the host 300 to control the storage device 100 to perform programming operations, read operations, and erase operations. During programming operations, the storage controller 200 can provide the storage device 100 with programming commands, PBAs, and data. During read operations, the storage controller 200 can provide the storage device 100 with read commands and PBAs. During erase operations, the storage controller 200 can provide the storage device 100 with erase commands and PBAs.

[0044] In one implementation, regardless of any request from the host 300, the storage controller 200 can autonomously generate commands, addresses, and data, and send these commands, addresses, and data to the storage device 100. For example, the storage controller 200 can provide the storage device 100 with commands, addresses, and data for performing read and program operations, accompanied by wear leveling, read recycling, garbage collection, etc.

[0045] In one embodiment, the storage controller 200 can control at least two storage devices 100. The storage controller 200 can control the storage devices according to an interleaving scheme to improve operational performance. The interleaving scheme can be a scheme for controlling the overlapping of operations on at least two storage devices 100. Alternatively, the interleaving scheme can be a scheme in which at least two storage devices 100 operate in parallel.

[0046] The buffer memory can temporarily store data provided from the host 300 (i.e., data to be stored in the storage device 100) or temporarily store data read from the storage device 100. In one embodiment, the buffer memory can be a volatile storage device. For example, the buffer memory can be dynamic random access memory (DRAM) or static random access memory (SRAM).

[0047] The host 300 can communicate with the storage device 50 using at least one of a variety of communication methods, such as Universal Serial Bus (USB), Serial AT Accessory (SATA), High Speed ​​Interconnect Chip (HSIC), Small Computer System Interface (SCSI), FireWire, Peripheral Component Interconnect (PCI), PCI Express (PCIe), Non-Volatile Memory Express (NVMe), Universal Flash Memory (UFS), Secure Digital Storage (SD), Multimedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and Low Load DIMM (LRDIMM).

[0048] Figure 2 This is an example Figure 1 A diagram of the storage device shown.

[0049] Reference Figure 2 The storage device 100 may include a storage cell array 110, a voltage generator 120, an address decoder 130, an input / output (I / O) circuit 140, and control logic 150.

[0050] The memory cell array 110 includes multiple memory blocks BLK1 to BLKi. The multiple memory blocks BLK1 to BLKi are connected to address decoding 130 via row lines RL. The multiple memory blocks BLK1 to BLKi are connected to I / O circuitry 140 via column lines CL. In one embodiment, the row line RL may include word lines, source select lines, and drain select lines. In one embodiment, the column line CL may include bit lines.

[0051] Multiple storage blocks BLK1 to BLKi comprise multiple storage cells. In one embodiment, the multiple storage cells may be non-volatile storage cells. Storage cells connected to the same word line among the multiple storage cells may be defined as a physical page. That is, the storage cell array 110 may include multiple physical pages. The storage cells of the storage device 100 may be configured as, for example, any of the following: a single-level cell (SLC) storing one data bit, a multi-level cell (MLC) storing two data bits, a three-level cell (TLC) storing three data bits, and a four-level cell (QLC) storing four data bits.

[0052] In one embodiment, the voltage generator 120, address decoder 130, and I / O circuitry 140 can be collectively designated as peripheral circuitry. This peripheral circuitry can drive the memory cell array 110 under the control of control logic 150. The peripheral circuitry can drive the memory cell array 110 to perform programming, reading, and erasing operations.

[0053] Voltage generator 120 generates multiple operating voltages by using an external power supply voltage provided to storage device 100. Voltage generator 120 operates under the control of control logic 150.

[0054] In one embodiment, the voltage generator 120 can generate an internal power supply voltage by adjusting an external power supply voltage. The internal power supply voltage generated by the voltage generator 120 is used as the operating voltage of the storage device 100.

[0055] In one embodiment, voltage generator 120 can generate multiple operating voltages by using an external power supply voltage or an internal power supply voltage. Voltage generator 120 can generate various voltages required in storage device 100. For example, voltage generator 120 can generate multiple erase voltages, multiple programming voltages, multiple pass voltages, multiple select read voltages, and multiple unselect read voltages.

[0056] In order to generate multiple operating voltages with various voltage levels, voltage generator 120 may include multiple pump capacitors that receive internal power supply voltages, and generate multiple operating voltages by selectively activating the multiple pump capacitors under the control of control logic 150.

[0057] The generated multiple operating voltages can be provided to the memory cell array 110 by the address decoder 130.

[0058] Address decoder 130 is connected to memory cell array 110 via row line RL. Address decoder 130 operates under the control of control logic 150. Address decoder 130 can receive address ADDR from control logic 150. Address decoder 130 can decode the block address in the received address ADDR. Address decoder 130 selects at least one memory block from memory blocks BLK1 to BLKi based on the decoded block address. Address decoder 130 can decode the row address in the received address ADDR. Address decoder 130 can select at least one word line of the selected memory block based on the decoded row address. In an embodiment, address decoder 130 can decode the column address in the received address ADDR. Address decoder 130 can connect I / O circuit 140 and memory cell array 110 to each other based on the decoded column address.

[0059] In one implementation, address decoder 130 may include components such as row decoder, column decoder, and address decoder.

[0060] I / O circuitry 140 may include multiple page buffers. These page buffers can be connected to memory cell array 110 via bit lines. During programming operations, data can be stored in selected memory cells based on the data stored in the multiple page buffers.

[0061] During a read operation, data stored in the selected memory cell can be sensed via bit lines, and the sensed data can be stored in the page buffer.

[0062] In one implementation, control logic 150 can control address decoder 130, voltage generator 120, and / or I / O circuitry 140. Control logic 150 can operate in response to a command CMD transmitted from an external device. Control logic 150 can control peripheral circuitry by generating control signals in response to the command CMD and address ADDR.

[0063] Figure 3 This is an example Figure 2 A diagram showing the structure of any one of the storage blocks in the diagram.

[0064] Storage block BLKi representation Figure 2 The storage blocks BLK1 to BLKi shown are any one of the storage blocks BLKi.

[0065] Reference Figure 3 In a storage block BLKi, multiple word lines arranged parallel to each other can be connected between a first select line and a second select line. The first select line can be a source select line (SSL), and the second select line can be a drain select line (DSL). More specifically, a storage block BLKi can include multiple string STs connected between bit lines BL1 to BLn and the source line SL. Bit lines BL1 to BLn can be connected to string STs individually, and the source line SL can be connected together to string STs. String STs can be configured identically to each other, and therefore, a string ST connected to the first bit line BL1 will be described in detail as an example.

[0066] The string ST may include a source selection transistor SST connected in series between the source line SL and the first bit line BL1, a plurality of memory cells MC1 to MC16, and a drain selection transistor DST. At least one source selection transistor SST and at least one drain selection transistor DST may be included in a string ST, and the number of memory cells included in a string ST may be greater than the number of memory cells MC1 to MC16 shown in the figure.

[0067] The source of the source select transistor SST can be connected to the source line SL, and the drain of the drain select transistor DST can be connected to the first bit line BL1. Memory cells MC1 to MC16 can be connected in series between the source select transistor SST and the drain select transistor DST. The gate of the source select transistor SST included in different string STs can be connected to the source select line SSL, and the gate of the drain select transistor DST included in different string STs can be connected to the drain select line DSL. The gates of memory cells MC1 to MC16 can be connected to multiple word lines WL1 to WL16. A group of memory cells connected to the same word line among the memory cells included in different string STs can be referred to as a physical page PG. Therefore, the memory block BLKi can include physical pages PG corresponding to the number of word lines WL1 to WL16.

[0068] A storage cell can store one bit of data. This storage cell is typically referred to as a single-level cell (SLC). A physical page (PG) can store one logical page (LPG) of data. An LPG of data can include data bits corresponding to the number of cells included in a physical page (PG).

[0069] A storage unit can store two or more bits of data. A physical page (PG) can store two or more physical pages (LPGs).

[0070] Figure 4A and Figure 4B This is a diagram illustrating the threshold voltage distribution of a single-stage cell.

[0071] Reference Figure 4A and Figure 4B The horizontal axis represents the threshold voltage of the memory cell, and the vertical axis represents the number of memory cells.

[0072] Storage devices can perform programming operations on a word line basis. Multiple storage units connected to a word line can form a physical page. A physical page can be the unit of programming or reading operations.

[0073] The storage device can perform programming operations to store data in a storage cell connected to a selected word line among multiple word lines.

[0074] Before performing programming operations, the selected memory cell, which is a memory cell connected to the selected word line, may have Figure 4A The threshold voltage distribution shown corresponds to the erase state E.

[0075] When a memory cell stores data corresponding to a single bit, the memory cell can be programmed to have a threshold voltage corresponding to either the erase state E or the first programming state P1.

[0076] The erase state E can correspond to the data "1", and the first programming state P1 can correspond to the data "0". However, the data corresponding to the first programming state P1 is merely illustrative. The erase state E can correspond to the data "0", and the first programming state P1 can correspond to the data "1".

[0077] When the programming operation is complete, the selected memory unit may have Figure 4B The threshold voltage shown corresponds to either the erase state E or the first programming state P1. The storage device performs a read operation using a first read voltage R1 between the erase state E and the first programming state P1, thereby enabling the reading of data stored in the selected memory cell.

[0078] Figure 5A and Figure 5B This is a diagram illustrating the threshold voltage distribution of a multi-stage unit.

[0079] Reference Figure 5A and Figure 5B The horizontal axis represents the threshold voltage of the memory cell, and the vertical axis represents the number of memory cells.

[0080] Before performing programming operations, the selected memory cell, which is a memory cell connected to the selected word line, may have Figure 5A The threshold voltage distribution shown corresponds to the erase state E.

[0081] When the memory cell stores data corresponding to two bits, the memory cell can be programmed to have a threshold voltage corresponding to any one of the erase state E, the first programming state P1, the second programming state P2, and the third programming state P3.

[0082] The erase state E can correspond to the data "11", the first programming data P1 can correspond to the data "10", the second programming data P2 can correspond to the data "00", and the third programming state P3 can correspond to the data "01". However, the data corresponding to each programming state is merely illustrative and can be changed in various ways.

[0083] When the programming operation is complete, the selected memory unit may have the same characteristics as... Figure 5B The threshold voltages corresponding to any one of the erase state E, the first programming state P1, the second programming state P2, and the third programming state P3 are shown. The storage device performs a read operation using the first read voltage R1 to the third read voltage R3, thereby enabling the reading of data stored in the selected storage cell.

[0084] The first read voltage R1 can be a read voltage used to distinguish between the erase state E and the first programming state P1, the second read voltage R2 can be a read voltage used to distinguish between the first programming state P1 and the second programming state P2, and the third read voltage R3 can be a read voltage used to distinguish between the second programming state P2 and the third programming state P3.

[0085] Figure 6A and Figure 6B This is a diagram illustrating the threshold voltage distribution of a three-level unit.

[0086] Reference Figure 6A and Figure 6B The horizontal axis represents the threshold voltage of the memory cell, and the vertical axis represents the number of memory cells.

[0087] Before performing programming operations, the selected memory cell, which is a memory cell connected to the selected word line, may have Figure 6A The threshold voltage distribution shown corresponds to the erase state E.

[0088] When the memory cell stores data corresponding to three bits, the memory cell can be programmed to have a threshold voltage corresponding to any one of the erase state E, the first programming state P1, the second programming state P2, the third programming state P3, the fourth programming state P4, the fifth programming state P5, the sixth programming state P6, and the seventh programming state P7.

[0089] The erase state E corresponds to the data "111", the first programming state P1 corresponds to the data "110", the second programming state P2 corresponds to the data "101", the third programming state P3 corresponds to the data "100", the fourth programming state P4 corresponds to the data "011", the fifth programming state P5 corresponds to the data "101", the sixth programming state P6 corresponds to the data "001", and the seventh programming state P7 corresponds to the data "000". However, the data corresponding to each programming state is merely illustrative and can be changed in various ways.

[0090] When the programming operation is complete, the selected memory unit may have Figure 6B The threshold voltages shown correspond to any one of the erase state E, first programming state P1, second programming state P2, third programming state P3, fourth programming state P4, fifth programming state P5, sixth programming state P6, and seventh programming state P7. The storage device performs a read operation using the first read voltage R1 to the seventh read voltage R7, thereby enabling the reading of data stored in the selected storage cell.

[0091] The first read voltage R1 can be a read voltage used to distinguish between the erase state E and the first programming state P1; the second read voltage R2 can be a read voltage used to distinguish between the first programming state P1 and the second programming state P2; the third read voltage R3 can be a read voltage used to distinguish between the second programming state P2 and the third programming state P3; the fourth read voltage R4 can be a read voltage used to distinguish between the third programming state P3 and the fourth programming state P4; the fifth read voltage R5 can be a read voltage used to distinguish between the fourth programming state P4 and the fifth programming state P5; the sixth read voltage R6 can be a read voltage used to distinguish between the fifth programming state P5 and the sixth programming state P6; and the seventh read voltage R7 can be a read voltage used to distinguish between the sixth programming state P6 and the seventh programming state P7.

[0092] Figure 7A and Figure 7B This is a diagram illustrating the threshold voltage distribution of a four-level unit.

[0093] Reference Figure 7A and Figure 7B The horizontal axis represents the threshold voltage of the memory cell, and the vertical axis represents the number of memory cells.

[0094] Before performing programming operations, the selected memory cell, which is a memory cell connected to the selected word line, may have Figure 7A The threshold voltage distribution shown corresponds to the erase state E.

[0095] When the memory cell stores data corresponding to four bits, the memory cell can be programmed to have a threshold voltage corresponding to any one of the erase state E and the first programming state P1 to the fifteenth programming state P15.

[0096] The erase state E corresponds to the data "1111", the first programming state P1 corresponds to the data "1110", the second programming state P2 corresponds to the data "1101", the third programming state P3 corresponds to the data "1100", the fourth programming state P4 corresponds to the data "1011", the fifth programming state P5 corresponds to the data "1010", the sixth programming state P6 corresponds to the data "1001", and the seventh programming state P7 corresponds to the data "1000". Furthermore, the eighth programming state P8 corresponds to the data "0111", the ninth programming state P9 corresponds to the data "0110", the tenth programming state P10 corresponds to the data "0101", the eleventh programming state P11 corresponds to the data "0100", the twelfth programming state P12 corresponds to the data "0011", the thirteenth programming state P13 corresponds to the data "0010", the fourteenth programming state P14 corresponds to the data "0001", and the fifteenth programming state P15 corresponds to the data "0000". However, the data corresponding to each programming state is merely illustrative and can be changed in various ways.

[0097] When the programming operation is complete, the selected memory unit may have Figure 7B The threshold voltages shown correspond to any one of the erase state E and the first to fifteenth programming states P1 to P15. The storage device performs a read operation using the first read voltage R1 to the fifteenth read voltage R15, thereby enabling the reading of data stored in the selected storage cell.

[0098] The first read voltage R1 can be a read voltage used to distinguish between the erase state E and the first programming state P1; the second read voltage R2 can be a read voltage used to distinguish between the first programming state P1 and the second programming state P2; the third read voltage R3 can be a read voltage used to distinguish between the second programming state P2 and the third programming state P3; the fourth read voltage R4 can be a read voltage used to distinguish between the third programming state P3 and the fourth programming state P4; the fifth read voltage R5 can be a read voltage used to distinguish between the fourth programming state P4 and the fifth programming state P5; the sixth read voltage R6 can be a read voltage used to distinguish between the fifth programming state P5 and the sixth programming state P6; the seventh read voltage R7 can be a read voltage used to distinguish between the sixth programming state P6 and the seventh programming state P7; and the eighth read voltage R8 can be a read voltage used to distinguish between the seventh programming state P7 and the eighth programming state P8. The voltages are as follows: the ninth read voltage R9 can be used to distinguish between the eighth programming state P8 and the ninth programming state P9; the tenth read voltage R10 can be used to distinguish between the ninth programming state P9 and the tenth programming state P10; the eleventh read voltage R11 can be used to distinguish between the tenth programming state P10 and the eleventh programming state P11; the twelfth read voltage R12 can be used to distinguish between the eleventh programming state P11 and the twelfth programming state P12; the thirteenth read voltage R13 can be used to distinguish between the twelfth programming state P12 and the thirteenth programming state P13; the fourteenth read voltage R14 can be used to distinguish between the thirteenth programming state P13 and the fourteenth programming state P14; and the fifteenth read voltage R15 can be used to distinguish between the fourteenth programming state P14 and the fifteenth programming state P15.

[0099] From Figure 8 In the following initial figures, it is assumed that each of the plurality of memory cells is a multilevel cell (MLC) storing 2 bits of data. However, the scope of this disclosure is not limited thereto, and the plurality of memory cells may be a three-level cell (TLC) storing 3 bits of data or a four-level cell (QLC) storing 4 bits of data.

[0100] Figure 8 This is a diagram illustrating programming operations.

[0101] exist Figure 8 In this context, the programming operation of the storage device 100 may include multiple programming cycles PL1 to PLn. That is, the storage device 100 can program selected storage cells to have a threshold voltage corresponding to any one of multiple programming states P1, P2, and P3 by executing multiple programming cycles PL1 to PLn.

[0102] Multiple programming cycles PL1 to PLn may include a programming voltage application step (PGM step) that applies a programming voltage and a verification step (Verify step) that determines whether a memory cell has been programmed by applying a verification voltage.

[0103] For example, when executing the first programming cycle PL1, after applying the first programming pulse Vpgm1, a first verification voltage Vvfy1 to a third verification voltage Vvfy3 are applied sequentially to verify the programming state of multiple memory cells. Memory cells whose target programming state is the first programming state P1 can be verified by the first verification voltage Vvfy1, memory cells whose target programming state is the second programming state P2 can be verified by the second verification voltage Vvfy2, and memory cells whose target programming state is the third programming state P3 can be verified by the third verification voltage Vvfy3.

[0104] When the threshold voltage of a memory cell is higher than one of the corresponding verification voltages Vvfy1 to Vvfy3, and the memory cell is therefore read as a shutdown cell, it can be determined that the memory cell has the corresponding target programming state, and thus the verification operation can be determined to have passed. This is called the verification passing of the memory cell. That is, the verification passing of the memory cell indicates that the memory cell is read as a shutdown cell by the corresponding verification voltage and therefore passes the verification. Then, the verified memory cell can be disabled for programming in the second programming cycle PL2. A second programming pulse Vpgm2, which is a unit voltage ΔVpgm higher than the first programming pulse Vpgm1, is applied to program the memory cells other than those disabled for programming in the second programming cycle PL2. Subsequently, the verification operation is performed in the same way as the verification operation in the first programming cycle PL1.

[0105] As described above, when the storage device programs a multilevel cell (MLC) that stores two data bits, the storage device 100 verifies the storage cell having a programming state as the target programming state by using a first verification voltage Vvfy1 to a third verification voltage Vvfy3 respectively.

[0106] In the verification operation, a verification voltage is applied to the selected word line to which the selected memory cell is connected, and the page buffer can determine whether the memory cell has passed verification based on the current flowing through the bit lines respectively connected to the selected memory cell or based on the voltage applied to the bit lines respectively connected to the selected memory cell.

[0107] Figure 9 This is a diagram illustrating dual verification operation and bit line voltage regulation.

[0108] Reference Figure 9 The horizontal axis represents the threshold voltage of the memory cell, and the vertical axis represents the number of memory cells.

[0109] exist Figure 9 The following will be used as an example description. Figures 4A to 7B Verification steps for any one of the multiple programming states described.

[0110] When a programming state is verified using a single verification voltage, the width of the threshold voltage distribution may be widened after programming because the programming speeds of the memory cells differ. To achieve a narrower threshold voltage distribution width, a method can be used where two verification voltages are used when verifying a programming state. This method is called Dual Verification Programming (DPGM).

[0111] For traditional DPGM, during the verification step, the auxiliary verification voltage Vprevfy and the main verification voltage Vverify can be applied sequentially to the selected word line. The main verification voltage Vverify can be a reference voltage. Figure 8 Any of the verification voltages described. When the verification step is performed using the auxiliary verification voltage Vprevfy and the main verification voltage Vverify, the threshold voltage of the memory cell can be included in any of zone A, zone B, and zone C.

[0112] In one implementation, a memory cell with a threshold voltage vth1 belonging to region A has a threshold voltage even lower than the auxiliary verification voltage Vprevfy. Therefore, in the next programming cycle, a relatively high programming voltage is applied to the memory cell with threshold voltage vth1 belonging to region A. A memory cell with a threshold voltage vth2 belonging to region B has a threshold voltage higher than the auxiliary verification voltage Vprevfy and lower than the main verification voltage Vverify. Therefore, when a memory cell with threshold voltage vth2 belonging to region B is applied a relatively low programming voltage in the next programming cycle, the threshold voltage can increase to vth4. Therefore, a memory cell with threshold voltage vth2 belonging to region B will be applied a relatively low programming voltage compared to the programming voltage of the memory cell with threshold voltage vth1 belonging to region A. A memory cell with threshold voltage vth3 belonging to region C has a threshold voltage higher than the main verification voltage Vverify. Therefore, a memory cell with threshold voltage vth3 belonging to region C has been fully programmed and will not be applied any programming voltage in the next programming cycle. Programming voltage is typically applied to the memory cell connected to the selected word line, and therefore, the memory device can adjust the effect of the programming voltage applied to the memory cell by adjusting the bit line voltage; this is known as bit line forcing.

[0113] After the verification step, a programming voltage increased by a unit voltage ΔVpgm can be applied to the selected word line in the next programming cycle. While the programming voltage is applied to the selected word line, a programming enable voltage can be applied to the bit line connected to the memory cell having a threshold voltage vth1 belonging to region A. In one embodiment, the programming enable voltage can be 0V. A programming disable voltage can be applied to the bit line connected to the memory cell having a threshold voltage vth3 belonging to region C. In one embodiment, the programming disable voltage can be the magnitude of the power supply voltage Vcc. A programming control voltage can be applied to the bit line connected to the memory cell having a threshold voltage vth2 belonging to region B. In one embodiment, the magnitude of the programming control voltage can be higher than 0V and lower than the magnitude of the power supply voltage Vcc.

[0114] As described above, when multiple verification voltages are used in the verification step to determine the threshold voltage of the memory cell, and a voltage is applied to the bit line connected to the memory cell in the next programming cycle based on the verification result, the width of the threshold voltage distribution can be narrowed. However, the time required in the verification step increases with the number of verification voltages.

[0115] In one implementation, even when the verification step is performed by applying only one main verification voltage Vverify, the verification result is stored twice based on the change of the bit line voltage over time. Therefore, the same result can be achieved as if the verification step were performed using two verification voltages.

[0116] Figure 10 Examples include Figure 2 A diagram of any page buffer 1000 in the input / output circuit shown.

[0117] Reference Figure 10 The storage unit can be connected to the page buffer 1000 via the bit line BL.

[0118] Page buffer 1000 may include bit line connector 1001, bit line voltage supply 1003, sensing node connector 1005, sensing node voltage supply 1007, and verification data storage 1009.

[0119] Bit line connector 1001 can control the connection between the bit line BL connected to the memory cell and the common sense node CSO. Bit line connector 1001 can receive a bit line connection signal BL_CN and control the connection from the memory cell to the common sense node CSO in the page buffer 1000 in response to the received bit line connection signal BL_CN.

[0120] Bit line voltage supplier 1003 can provide bit line precharge voltage to common sensing node CSO connected to the bit line. Bit line voltage supplier 1003 can receive bit line charge signal BLprech and charge common sensing node CSO connected to the bit line based on the received bit line charge signal BLprech.

[0121] The sensor node connector 1005 can connect a common sensor node CSO (connected to a bit line) to a sensor node SO of the page buffer 1000. The sensor node connector 1005 can receive a sensor node connection signal SO_CN and can control the connection between the common sensor node CSO and the sensor node SO based on the received sensor node connection signal SO_CN.

[0122] The sensing node voltage supplier 1007 can provide a sensing node precharge voltage to the sensing node SO. For example, the sensing node voltage supplier 1007 can receive the sensing node charge signal SOprech at, for example, the gate of transistor TR5 (described below), and if, for example... Figure 11 The gate of the transistor TR4 shown has a signal QS that provides a high voltage level to turn on TR4, which can activate the transistor TR5, thereby allowing charge to flow through the transistor TR4 to charge the sensing node SO.

[0123] The verification data storage 1009 can store verification data determined based on the voltage of the sensing node SO. The verification data storage 1009 can receive a verification data storage signal VFY and store the verification data determined based on the voltage of the sensing node SO based on the received verification data storage signal VFY. The verification data can be stored in a latch.

[0124] According to one embodiment of this disclosure, when a verification voltage is applied to the word line of a memory cell connected to the page buffer 1000 via the bit line BL, the bit line voltage supplier 1003 and the sense node voltage supplier 1007 can charge the bit line and the sense node, respectively, and the sense node connector 1005 can connect the sense node SO to a common sense node CSO connected to the bit line. The sense node SO is connected to the bit line BL via the common sense node CSO, and therefore, the voltage of the sense node SO can be linked to the voltage of the bit line BL. Subsequently, the voltage of the bit line BL can be changed depending on whether the memory cell connected to the bit line BL is an enabled or disabled cell. Similarly, the voltage of the sense node SO connected to the bit line BL can be changed. The verification data storage 1009 can store first verification data determined based on the voltage of the sensing node SO based on a first verification data storage signal VFY_1 received before the connection between the bit line BL and the sensing node SO is disconnected by the sensing node connector 1005, and store second verification data determined based on the voltage of the sensing node SO based on a second verification data storage signal VFY_2 received after the connection between the bit line BL and the sensing node SO is disconnected by the sensing node connector 1005.

[0125] Figure 11 This is an internal circuit diagram of a page buffer 1000 according to one embodiment of the present disclosure.

[0126] Reference Figure 11 , Figure 10 The bit line connector 1001, bit line voltage supply 1003, sensing node connector 1005, sensing node supply 1007, and verification data storage 1009 shown can be implemented using the first transistor TR1 to the twelfth transistor TR12.

[0127] Bit line connector 1001 may include a first transistor TR1. A bit line connection signal BL_CN may be input to the gate of the first transistor TR1. The first transistor TR1 can control the connection between bit line BL and common sensing node CSO according to the bit line connection signal BL_CN. The first transistor TR1 may be an NMOS transistor.

[0128] Bit line voltage supply 1003 may include a second transistor TR2 and a third transistor TR3. A bit line charging signal BLprech may be input to the gate of the second transistor TR2. A common sense node connection signal CSO_CN may be connected to the gate of the third transistor TR3. The second transistor TR2 can be charged according to the bit line charging signal BLprech, and the third transistor TR3 can charge the common sense node CSO by controlling the connection between the second transistor TR2 and the common sense node CSO according to the common sense node connection signal CSO_CN. The second transistor TR2 may be a PMOS transistor, and the third transistor TR3 may be an NMOS transistor.

[0129] The sensing node connector 1005 may include a sixth transistor TR6. A sensing node connection signal SO_CN can be input to the gate of the sixth transistor TR6. The sixth transistor TR6 can control the connection between the common sensing node CSO and the sensing node SO according to the sensing node connection signal SO_CN. The sixth transistor TR6 may be an NMOS transistor.

[0130] The sensing node voltage supply 1007 may include a fourth transistor TR4 and a fifth transistor TR5. The sensing node charge signal SOprech may be input to the gate of the fifth transistor TR5. The fifth transistor TR5 may charge the sensing node SO according to the sensing node charge signal SOprech. The fifth transistor TR5 may be an NMOS transistor.

[0131] The verification data storage 1009 may include a seventh transistor TR7, an eighth transistor TR8, a ninth transistor TR9, a tenth transistor TR10, an eleventh transistor TR11, a twelfth transistor TR12, an S-latch, and an M-latch. The S-latch reset signal SRST can be input to the gate of the seventh transistor TR7. The first verification data storage signal VFY_1 can be input to the gate of the eighth transistor TR8. The page buffer reset signal PB_RST can be input to the gate of the ninth transistor TR9. The M-latch reset signal MRST can be input to the gate of the tenth transistor TR10. When clearing the data latched in the S-latch and M-latch, the S-latch reset signal SRST, the M-latch reset signal MRST, and the page buffer reset signal PB_RST can respectively turn on transistors TR7 and TR10 and transistor TR9. The second verification data storage signal VFY_2 can be input to the gate of the eleventh transistor TR11. The voltage of the sensing node SO can be input to the gate of the twelfth transistor TR12. The eighth transistor, TR8, can be controlled by the first verification data storage signal VFY_1 to determine whether to store data in the S-latch. The eleventh transistor, TR11, can be controlled by the second verification data storage signal VFY_2 to determine whether to store data in the M-latch. These S-latch and M-latch will be referred to as the first latch and the second latch, respectively. The seventh transistor, TR7, can be an NMOS transistor. The eighth transistor, TR8, can be an NMOS transistor. The ninth transistor, TR9, can be an NMOS transistor. The tenth transistor, TR10, can be an NMOS transistor. The eleventh transistor, TR11, can be an NMOS transistor. The twelfth transistor, TR12, can be an NMOS transistor.

[0132] The twelfth transistor TR12 of the verification data storage 1009 can operate differently depending on the voltage of the sensing node SO. When the twelfth transistor TR12 is turned on due to the voltage of the sensing node SO, and the verification data storage 1009 receives the verification data storage signals VFY_1 and VFY_2, the data stored in the latch can be changed. When the twelfth transistor TR12 is turned off due to the voltage of the sensing node SO, the data stored in the latch will not change even when the verification data storage 1009 receives the verification data storage signals VFY_1 and VFY_2.

[0133] Figure 12 This is an example of what is applied to Figure 11 The diagram shows the various control signals of the circuit.

[0134] Reference Figure 11 and Figure 12From the initial time point t0 to the third time point t3, the verification voltage Vvfy can be applied to the word line of the memory cell. At the initial time point t0, the bit line connection signal BL_CN with a logic high level can be applied to the first transistor TR1. The first transistor TR1 can be turned on according to the bit line connection voltage Vb1_cn, and the bit line BL and the common sensing node CSO can be connected to each other.

[0135] At time t0, the bit line charging signal BLprech (with charging voltage Vb1_ch) can go low and turn on the second transistor TR2, while the common sense node connection signal CSO_CN, which has a logic high level, can be applied as voltage Vcso_cn to the third transistor TR3. The third transistor TR3 can then turn on. The common sense node CSO connected to the bit line through the turned-on second transistor TR2 and third transistor TR3 can be charged.

[0136] At time t0, the sensing node charging signal SOprech (with the sensing node charging voltage Vso_ch) can go low and turn on the fifth transistor TR5. The sensing node SO can then be charged.

[0137] The sensing node connection signal SO_CN, which is logic high at time t0, can be applied to the sixth transistor TR6 as the sensing node connection voltage Vso_cn. The sixth transistor TR6 can then be turned on, and the common sensing node CSO and the sensing node SO can be connected to each other. Due to the connection between the common sensing node CSO and the sensing node SO, the sensing node SO can be charged to have the voltage level of the common sensing node CSO.

[0138] At the first time point t1, the sensing node charging signal SOprech, which has a logic high level, can be applied to the fifth transistor TR5 as the sensing node charging voltage Vso_ch. The fifth transistor TR5 can be turned off, and the sensing node SO can be fully charged.

[0139] At the second time point t2, the sensing node connection signal SO_CN (with the sensing node connection voltage Vso_cn) can go low and turn off the sixth transistor TR6. This disconnects the common sensing node CSO and the sensing node SO.

[0140] At the third time point t3, since the verification operation is complete, the input of the verification voltage Vvfy to the word line of the memory cell can be paused. The bit line connection signal BL_CN (with bit line voltage Vb1_cn) can go low and turn off the first transistor TR1. The connection between the bit line BL and the common sense node CSO can be disconnected. The common sense node connection signal CSO_CN can go low to turn off the third transistor TR3. The charging of the common sense node CSO can be cut off.

[0141] Reference Figure 10 and Figure 11 During the period between the initial time point t0 and the second time point t2, the sensing node SO can be connected to the common sensing node CSO via the sixth transistor TR6 (see...). Figure 12 The signal SO_CN in the signal, and during the period between the initial time point t0 and the third time point t3, the common sensing node CSO can be connected to the bit line BL via the first transistor TR1 (see Figure 12 The signal BL_CN in the signal. That is, as long as both the first transistor TR1 and the sixth transistor TR6 are turned on (i.e., during the period between the initial time point t0 and the second time point t2), the sensing node SO and the bit line BL can be connected to each other, and therefore both the bit line BL and the sensing node SO can be charged to have the voltage level of the common sensing node CSO.

[0142] After the first time point t1 when the sensing node SO is fully charged, the voltage of the bit line BL can be changed according to the threshold voltage of the memory cell connected to the page buffer. The voltage of the sensing node SO connected to the bit line BL can also be changed. When the threshold voltage of the memory cell is lower than the verification voltage Vvfy, the voltage of the bit line BL can be reduced. As the difference between the threshold voltage of the memory cell and the verification voltage Vvfy increases, the amount of reduction in the voltage of the bit line BL can also increase. (Refer to...) Figure 9 It can be seen that the threshold voltage of the memory cells included in region A is the lowest. The bit line voltage of the memory cells included in region A can be reduced to the greatest extent. The reduction in bit line voltage of the memory cells included in region B can be less than the reduction in bit line voltage of the memory cells included in region A. The bit line voltage of the memory cells included in region C hardly decreases. The voltage of the sensing node SO connected to the bit line BL can also be reduced.

[0143] The verification data storage 1009 can store verification data determined based on the voltage of the sensing node SO between a first time point t1 and a third time point t3. Specifically, the verification data storage 1009 can receive a first verification data storage signal VFY_1 between the first time point t1 and the second time point t2, and store the first verification data determined based on the voltage of the sensing node SO in a first latch (i.e., Figure 11 The verification data storage 1009 can then receive the second verification data storage signal VFY_2 between the second time point t2 and the third time point t3, and store the second verification data determined according to the voltage of the sensing node SO in the second latch (i.e., Figure 11 In the M latch shown.

[0144] The period from the initial time point t0 to the first time point t1 can be the pre-charging period P1 of the sensing node SO, the period from the first time point t1 to the second time point t2 can be the first verification period P2, and the period from the second time point t2 to the third time point t3 can be the second verification period P3.

[0145] According to one embodiment of this disclosure, a first verification can be performed during a first verification period P2, which is a period after the sensing node SO is fully charged (t1) and before the connection between the sensing node SO and the common sensing node CSO, and thus the connection between the sensing node SO and the bit line BL, is released (t2). A second verification can be performed during a second verification period P3, which is a period after the connection between the sensing node SO and the bit line BL is released. In one embodiment, the dual verification operation is performed by a single pre-charging of the sensing node SO, thus reducing the operation time of the dual verification operation.

[0146] Figure 13 This is a diagram illustrating a method for performing dual verification operations by precharging a sensing node once, according to one embodiment of the present disclosure.

[0147] Reference Figure 13 The horizontal axis represents time, and the vertical axis represents the voltage of the sensing node SO.

[0148] The voltage of the sensing node SO can change from a first time point t1 after the sensing node SO is fully charged to a second time point t2 after the connection between the sensing node SO and the bit line BL is severed, depending on the threshold voltage of the memory cell connected to the page buffer. Specifically, when the verification voltage Vvfy is applied to the word line connected to the memory cell, the voltage of the sensing node SO of the memory cell that has not yet been fully programmed to the target programming state decreases. The degree of voltage decrease of the sensing node SO varies depending on the threshold voltage of the memory cell. As the threshold voltage of the memory cell becomes higher, the voltage decrease can become smaller. When the voltage of the sensing node SO of the memory cell does not decrease significantly, the memory cell can be considered to have been programmed to the target programming state.

[0149] Reference Figure 10 and Figure 11 In a dual verification operation according to one embodiment of the present disclosure, a first verification data storage signal VFY_1 may be applied after a first reference time amount Q1 has elapsed from a first time point t1. The verification data storage 1009 stores the first verification data determined based on the voltage of the sensing node SO in a first latch (i.e., ...). Figure 11 The second verification data storage signal VFY_2 can be applied after a second reference time Q2 has elapsed from the second time point t2. The verification data storage 1009 stores the second verification data determined according to the voltage of the sensing node SO in the second latch (i.e., the S latch shown). Figure 11 In the M latch shown.

[0150] exist Figure 13 In the middle, the solid line 1301 can represent having Figure 9 The Vverify shown is the voltage of the sensing node SO of the memory cell with threshold voltage, and the dashed line 1303 can represent the voltage of the sensing node SO. Figure 9 The Vprevfy shown is the voltage of the sensing node SO of the memory cell with threshold voltage. Figure 13 The dashed line 1303 shown may be the first reference voltage associated with the first verification data. Figure 13 The solid line 1301 shown may be a second reference voltage associated with the second verification data.

[0151] Using solid line 1301 and dashed line 1303, the internal area of ​​the chart can be divided into area ①, area ② and area ③. Figure 13 Region ① in the middle can be with Figure 9 Corresponding to area A shown, Figure 13 Region ② in the middle can be with Figure 9 Corresponding to area B shown, and Figure 13 Region ③ in the middle can be with Figure 9 This corresponds to region C shown. Based on the double-verification operation in the current programming cycle, the threshold voltage increment of the memory cell belonging to region ① can be maintained in the next programming cycle, and the threshold voltage increment of the memory cell belonging to region ② can be adjusted in the next programming cycle. Since it can be seen that the memory cell belonging to region ③ is considered programmed to the target programming state in the current programming cycle, this memory cell can be considered to have passed verification, and therefore no further programming voltage will be applied to the memory cell in the next programming cycle.

[0152] When the first verification data storage signal VFY_1 is applied to Figure 11 When the eighth transistor TR8 is shown, the verification data storage 1009 can compare the voltage of the sensing node SO with the first reference voltage 1303. When the voltage of the sensing node SO is lower than the first reference voltage 1303, the verification data storage 1009 can store first verification data in the first latch that means a low value or an enabled cell data. Furthermore, when the voltage of the sensing node SO is higher than or equal to the first reference voltage 1303, the verification data storage 1009 can store first verification data in the first latch that means a high value or an disabled cell data.

[0153] When the second verification data storage signal VFY_2 is applied to Figure 11 When the eleventh transistor TR11 is shown, the verification data storage 1009 can compare the voltage of the sensing node SO with the second reference voltage 1301. When the voltage of the sensing node SO is lower than the second reference voltage 1301, the verification data storage 1009 can store second verification data in the second latch, indicating a low value or enabled cell data. Furthermore, when the voltage of the sensing node SO is higher than or equal to the second reference voltage 1301, the verification data storage 1009 can store second verification data in the second latch, indicating a high value or disabled cell data.

[0154] The voltage applied to the bit line in the next programming cycle can be determined based on the verification data stored in the first and second latches. For example, when both the first and second verification data are low, the memory cell can correspond to region ①, and the threshold voltage increment of the memory cell can be left unchanged. In this next programming cycle, a ground voltage (0V) can be applied to the bit line. When a ground voltage (0V) is applied, the threshold voltage increment of the memory cell does not... Figure 9 The "X" indicates that the value is adjusted. When the first verification data is high and the second verification data is low, the memory cell can correspond to region ②, and the threshold voltage increment of the memory cell can be adjusted. In the next programming cycle, a predetermined programming enable voltage can be applied to the bit line. When the programming enable voltage is applied, the threshold voltage increment of the memory cell can be adjusted as shown in the figure. Figure 9 Adjustments are made as indicated by "Y". When both the first and second verification data are high, a predetermined programming disable voltage can be applied to the bit line in the next programming cycle. When the programming disable voltage is applied, the corresponding memory cell is verified, and therefore the threshold voltage of the corresponding memory cell no longer increases.

[0155] In another embodiment of this disclosure, the voltage applied to the bit line in the next programming cycle can be determined based on whether the first verification data and the second verification data correspond to shutdown cell data or enable cell data. Shutdown cell data may indicate that the threshold voltage of the memory cell is higher than a predetermined reference voltage, and enable cell data may indicate that the threshold voltage of the memory cell is lower than a predetermined reference voltage. The reference voltage for the first verification data may be a first reference voltage 1303. The reference voltage for the second verification data may be a second reference voltage 1301. Specifically, when both the first and second verification data are enable cell data, a ground voltage (0V) can be applied to the bit line. When a ground voltage (0V) is applied, the threshold voltage increment of the memory cell does not... Figure 9 The "X" indicates that the setting is adjusted. When the first verification data is off cell data and the second verification data is on cell data, a predetermined programming enable voltage can be applied to the bit line. When the programming enable voltage is applied, the threshold voltage increment of the memory cell can be as follows: Figure 9 Adjustments are made as indicated by "Y". When both the first and second verification data are shutdown cell data, a predetermined programming disable voltage can be applied to the bit line. When the programming disable voltage is applied, the corresponding memory cell verification passes, and therefore the threshold voltage of the corresponding memory cell no longer increases.

[0156] According to one embodiment of this disclosure, a first reference time quantity Q1, which is the period from a first time point t1 to the application of the first verification data storage signal VFY_1, can be equal to a second reference time quantity Q2, which is the period from a second time point t2 to the application of the second verification data storage signal VFY_2. In another embodiment, the first reference time quantity Q1 can be longer or shorter than the second reference time quantity Q2. After the first time point t1, as the first reference time quantity Q1 becomes longer, the voltage change of the sensing node SO can further increase. After the second time point t2, the voltage change of the sensing node SO is independent of the length of the second reference time quantity Q2.

[0157] Figure 14 This is a flowchart illustrating an operation method of a storage device according to one embodiment of the present disclosure.

[0158] In this implementation, a programming voltage Vpgm can be applied to the memory cell. If the programming verification of the memory cell passes, the programming cycle can end, or the next programming cycle can be executed.

[0159] First, in step S1401, the storage device 100 applies a programming voltage Vpgm to the storage cell. Because storage cells have different characteristics, even when the same programming voltage Vpgm is applied, the storage cells can have different threshold voltages. In step S1403, the storage device 100 determines that the programming verification of the storage cell has passed. The storage device 100 can determine that the programming verification has passed by performing a double verification operation in step S1403. (The following...) Figure 15 The lieutenant general will describe step S1403 in detail.

[0160] For memory cells that fail verification, the storage device 100 can increase the programming voltage Vpgm by a predetermined unit voltage ΔVpgm in the next programming cycle (S1405). In step S1405, the storage device 100 can apply a voltage to the bit line in the next programming cycle based on the change in the programming state of the memory cell. The change in the applied voltage to the bit line can be related to... Figure 9 and Figure 13 The description shown corresponds to this.

[0161] When the memory cell passes the verification in the current programming cycle, the storage device 100 can end the current programming cycle by determining whether the current programming cycle is the last programming cycle (S1407) or apply the programming voltage Vpgm to the memory cell in the next programming cycle (S1401).

[0162] Figure 15 This is a diagram illustrating a method for performing a programming verification operation according to one embodiment of the present disclosure.

[0163] The programming verification operation according to this embodiment can be performed by the storage device 100 and by the page buffer 1000 included in the storage device 100. Figure 15 It can be considered certain Figure 14 A detailed implementation of step S1403, which verifies the successful programming of the shown storage unit.

[0164] First, in step S1501, the storage device 100 applies a verification voltage to the storage cell. The verification voltage is related to... Figure 12 The verification voltage Vvfy shown corresponds to this. In step S1503, the storage device 100 provides a pre-charge voltage to each of the sensing nodes SO of the bit line and page buffer 1000. The method of applying the pre-charge voltage is similar to... Figure 10 and Figure 11 as well as Figure 12The descriptions of the bit line voltage supply 1003 and the sensing node voltage supply 1007 shown correspond to each other.

[0165] In step S1505, after the sensing node is fully charged (t1) until the connection between the bit line and the sensing node is released (t2), the storage device 100 stores the first verification data determined based on the voltage of the sensing node in the first latch. In step S1507, after the connection between the bit line and the sensing node is released (t2), the storage device 100 stores the second verification data determined based on the voltage of the sensing node in the second latch. Steps S1505 and S1507 are... Figure 10 and Figure 11 as well as Figure 12 The descriptions of the sensing node connector 1005, sensing node voltage source 1007, and verification data memory 1009 shown correspond to those of the present invention.

[0166] In step S1509, the storage device 100 applies a bit line voltage to the bit line in the next programming cycle, determined based on whether the first verification data and the second verification data correspond to turn-off cell data or turn-on cell data. The bit line voltage applied in the next programming cycle is compared with... Figure 9 and Figure 13 The description shown corresponds to this.

[0167] Figure 16 This is a block diagram illustrating a memory card system of an application storage device according to one embodiment of the present disclosure.

[0168] Reference Figure 16 The memory card system 2000 includes a memory controller 2100, a memory device 2200, and a connector 2300.

[0169] Storage controller 2100 is connected to storage device 2200. Storage controller 2100 can access storage device 2200. For example, storage controller 2100 can control read operations, programming operations, erase operations, and background operations of storage device 2200. Storage controller 2100 provides storage device 2200 and other... Figure 1 The interface between the host 300 and the host device 2200. The storage controller 2100 drives instructions (e.g., firmware) for controlling the storage device 2200. The storage controller 2100 can be referenced... Figure 1 The storage controller 200 described is implemented in the same way.

[0170] In one embodiment, the storage controller 2100 may include components such as random access memory (RAM), processing unit, host interface, memory interface, and ECC circuitry.

[0171] Storage controller 2100 can communicate with external devices via connector 2300. Storage controller 2100 can communicate with external devices (e.g., a host) according to a specific communication protocol. Storage controller 2100 can communicate with external devices via at least one of various communication protocols such as Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI Express (PCIe), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Memory (UFS), Wi-Fi, Bluetooth, and NVMe. Exemplarily, connector 2300 can be defined by at least one of the aforementioned communication protocols.

[0172] In one embodiment, the storage device 2200 can be implemented with various non-volatile storage devices such as electrically erasable programmable ROM (EEPROM), NAND flash memory, NOR flash memory, phase change RAM (PRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), and spin torque transfer magnetic RAM (STT-MRAM).

[0173] In one embodiment, the storage controller 2100 and the storage device 2200 may be integrated into a single semiconductor device to form a memory card. The storage controller 2100 and the storage device 2200 may form memory cards such as PC cards (Personal Computer Memory Card International Association (PCMCIA)), compact flash (CF) cards, smart media cards (SM and SMC), memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro, and eMMC), SD cards (SD, mini SD, micro SD, and SDHC), and universal flash memory (UFS).

[0174] Figure 17 This is a block diagram illustrating a solid-state drive (SSD) system for an application storage device according to an embodiment of the present disclosure.

[0175] Reference Figure 17 The SSD system 3000 includes a host 3100 and an SSD 3200. The SSD 3200 exchanges signals with the host 3100 through a signal connector 3001 and receives power through a power connector 3002. The SSD 3200 includes an SSD controller 3210, multiple flash memory units 3221 to 322n, an auxiliary power supply 3230, and a buffer memory 3240.

[0176] In one implementation, the SSD controller 3210 can be used as a reference. Figure 1 The storage controller 200 is described.

[0177] SSD controller 3210 can control multiple flash memory devices 3221 to 322n in response to signals received from host 3100. These signals can be based on the interface between host 3100 and SSD 3200. The signals can be signals defined by at least one of the following interfaces: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI Express (PCIe), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Memory (UFS), Wi-Fi, Bluetooth, and NVMe.

[0178] Auxiliary power supply 3230 is connected to host 3100 via power connector 3002. Auxiliary power supply 3230 can receive and charge the power PWR from host 3100. When power supply from host 3100 is unreliable, auxiliary power supply 3230 can provide power to SSD 3200. Auxiliary power supply 3230 can be located inside SSD 3200 or externally to SSD 3200. For example, auxiliary power supply 3230 can be located on the motherboard and provide auxiliary power to SSD 3200.

[0179] Buffer memory 3240 serves as a buffer for SSD 3200. For example, buffer memory 3240 may temporarily store data received from host 3100 or from multiple flash memory modules 3221 to 322n, or temporarily store metadata (e.g., mapping tables) of flash memory modules 3221 to 322n. Buffer memory 3240 may include volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM, or non-volatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0180] Figure 18 This is a block diagram illustrating a user system of an application storage device according to one embodiment of the present disclosure.

[0181] Reference Figure 18 The user system 4000 includes an application processor 4100, a memory module 4200, a network module 4300, a storage module 4400, and a user interface 4500.

[0182] Application processor 4100 can drive components included in user system 4000, operating system (OS), user programs, etc. Application processor 4100 may include, for example, controllers for controlling components, interfaces, graphics engines, etc., included in user system 4000. Application processor 4100 may be provided as a system-on-a-chip (SoC).

[0183] The memory module 4200 can operate as the main memory, working memory, buffer memory, or cache memory of the user system 4000. The memory module 4200 may include volatile random access memory such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDRAM, LPDDR2 SDRAM, and LPDDR3 SDRAM, or non-volatile random access memory such as PRAM, ReRAM, MRAM, and FRAM. The application processor 4100 and the memory module 4200 can be provided as a single semiconductor package via a PoP-based package.

[0184] Network module 4300 can communicate with external devices. Network module 4300 can support wireless communications such as Code Division Multiple Access (CDMA), Global System for Mobile Communications (GSM), Wideband CDMA (WCDMA), CDMA-2000, Time Division Multiple Access (TDMA), Long Term Evolution (LTE), WiMAX, WLAN, UWB, Bluetooth, and Wi-Fi. Network module 4300 can be included in application processor 4100.

[0185] Storage module 4400 can store data. For example, storage module 4400 can store data received from application processor 4100. Alternatively, storage module 4400 can send the data stored therein to application processor 4100. Storage module 4400 can be implemented using a non-volatile semiconductor memory device such as phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), NAND flash memory, NOR flash memory, or NAND flash memory with a three-dimensional structure. Storage module 4400 can be provided as a memory card for user system 4000 or a removable drive for external drives.

[0186] In one embodiment, the storage module 4400 may include a plurality of non-volatile storage devices, and the plurality of non-volatile storage devices may be connected to a reference. Figure 1 The storage device 100 described operates in the same manner. The storage module 4400 can be compared with the referenced... Figure 1 The storage device 50 described operates in the same manner.

[0187] User interface 4500 may include interfaces for inputting data or commands to application processor 4100 or outputting data to external devices. User interface 4500 may include user input interfaces such as keyboards, keypads, buttons, touch panels, touchscreens, touchpads, touch balls, cameras, microphones, gyroscope sensors, vibration sensors, and piezoelectric elements. User interface 4500 may include user output interfaces such as liquid crystal displays (LCDs), organic light-emitting diode (OLED) display devices, active-matrix OLED (AMOLED) display devices, LEDs, speakers, and monitors.

[0188] According to this disclosure, a storage device with improved reliability and improved operating speed, as well as a method of operating the storage device, can be provided.

[0189] While this disclosure has been shown and described with reference to various embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of this disclosure as defined by the appended claims and their equivalents. Therefore, the scope of the invention should not be limited to the foregoing.

[0190] In the above embodiments, all steps may be selectively performed, or some steps may be omitted. In various embodiments, the steps are not necessarily performed in the described order, but may be rearranged. The embodiments disclosed in this specification and accompanying drawings are merely examples to facilitate understanding of this disclosure, and the invention is not limited thereto. That is, it will be apparent to those skilled in the art that various modifications can be made based on the technical scope of this disclosure.

[0191] Furthermore, embodiments of this disclosure have been described in the accompanying drawings and specification. Although specific terminology is used herein, it is only for the purpose of explaining embodiments of this disclosure. Therefore, this disclosure is not limited to the embodiments described above, and many variations are possible within the spirit and scope of this disclosure. Those skilled in the art will understand that various modifications can be made based on the technical scope of this disclosure in addition to the embodiments disclosed herein.

[0192] Cross-reference to related applications

[0193] This application claims priority to Korean Patent Application 10-2021-0025570, filed with the Korean Intellectual Property Office on February 25, 2021, the entire disclosure of which is incorporated herein by reference.

Claims

1. A memory device, the memory device comprising: a memory cell; a page buffer connected to the memory cell through a bit line; and a program operation controller that controls an operation of the page buffer, wherein the page buffer comprises: a bit line voltage supplier that supplies a pre-charge voltage to the bit line when a verify voltage is applied to the memory cell; a sense node voltage supplier that supplies a sense node pre-charge voltage to a sense node connected to the bit line when the bit line is pre-charged; a first latch that stores first verify data determined from a voltage level of the sense node after the sense node is charged; a sense node connector that disconnects the bit line from the sense node after the first verify data is stored; and a second latch that stores second verify data determined from the voltage level of the sense node after the connection between the bit line and the sense node is disconnected. The first latch stores the first verify data determined from the voltage level of the sense node after a first reference amount of time elapses from when the sense node is fully charged.

2. The memory device of claim 1, wherein, The second latch stores the second verify data determined from the voltage level of the sense node after a second reference amount of time elapses from when the connection between the bit line and the sense node is disconnected.

3. The memory device of claim 2, wherein, The first reference amount of time is the same as the second reference amount of time.

4. The memory device of claim 3, wherein, The first reference amount of time is longer than the second reference amount of time.

5. The memory device of claim 3, wherein, The first reference amount of time is shorter than the second reference amount of time.

6. The memory device of claim 3, wherein, The program operation controller applies a bit line voltage to the bit line based on whether the first verify data and the second verify data correspond to off cell data or on cell data when a program voltage is applied to the memory cell.

7. The memory device of claim 1, wherein, 8. The memory device of claim 7, The on cell data means that a threshold voltage of the memory cell is lower than a predetermined reference voltage, and wherein wherein the off cell data means that a threshold voltage of the memory cell is higher than the predetermined reference voltage. The program operation controller applies zero voltage (0V) to the bit line in response to the first verify data being the on cell data.

9. The memory device of claim 7, wherein, The program operation controller applies a predetermined program enable voltage to the bit line in response to the first verify data being the off cell data and the second verify data being the on cell data.

10. The memory device of claim 7, wherein, The program operation controller applies a predetermined program inhibit voltage to the bit line in response to the first verify data being the off cell data and the second verify data being the off cell data.

11. The memory device of claim 7, wherein, 12. A method for operating a memory device, the memory device comprising a memory cell and a page buffer connected to the memory cell through a bit line, the page buffer comprising a plurality of latches for storing verify data determined from a voltage level of a sense node connected to the bit line, the method comprising the steps of: ​ applying a verify voltage to the memory cell; providing a pre-charge voltage to the bit line and a sensing node of the page buffer while the verify voltage is applied; storing, in a first latch, first verify data determined from the voltage level of the sensing node until the connection between the bit line and the sensing node is released after the sensing node is charged; and storing, in a second latch, second verify data determined from the voltage level of the sensing node after the connection between the bit line and the sensing node is released.

13. The method of claim 12, wherein, storing the first verify data determined from the voltage level of the sensing node in the first latch after a first reference amount of time elapses from when the sensing node is fully charged.

14. The method of claim 13, wherein, storing the second verify data determined from the voltage level of the sensing node in the second latch after a second reference amount of time elapses from when the connection between the bit line and the sensing node is released.

15. The method of claim 14, wherein, The first reference amount of time is the same as the second reference amount of time.

16. The method of claim 14, wherein, The first reference amount of time is longer than the second reference amount of time.

17. The method of claim 14, wherein, The first reference amount of time is shorter than the second reference amount of time.

18. The method of claim 12, the method further comprising an applying step of applying a bit line voltage to the bit line determined based on whether the first verify data and the second verify data correspond to off cell data or on cell data while a program voltage is applied to the memory cell, wherein the on cell data means that a threshold voltage of the memory cell is lower than a predetermined reference voltage, and wherein the off cell data means that a threshold voltage of the memory cell is higher than the predetermined reference voltage.

19. The method of claim 18, wherein, The applying step includes determining zero voltage 0V as the bit line voltage when the first verify data is the on cell data.

20. The method of claim 18, wherein, The applying step includes determining a predetermined program enable voltage as the bit line voltage when the first verify data is the off cell data and the second verify data is the on cell data.

21. The method of claim 18, wherein, The applying step includes determining a predetermined program inhibit voltage as the bit line voltage when the first verify data is the off cell data and the second verify data is the off cell data.

22. A page buffer connected to a memory cell by a bit line, the page buffer comprising: a bit line voltage supplier that provides a pre-charge voltage to the bit line when a verify voltage is applied to the memory cell; a sensing node voltage supplier that provides a sensing node pre-charge voltage to a sensing node connected to the bit line when the bit line is pre-charged; a first latch that stores first verify data determined from a voltage level of the sensing node after the sensing node is charged; a sensing node connector that releases the connection between the bit line and the sensing node after the first verify data is stored; and a second latch that stores second verify data determined from the voltage level of the sensing node after the connection between the bit line and the sensing node is released. a second latch that stores second verification data determined from the voltage level of the sense node after the connection between the bit line and the sense node is disengaged.

Images