Heat dissipation structure, semiconductor package device, and method for manufacturing semiconductor package device

Abstract

A heat dissipation structure, a semiconductor package device and a manufacturing method of the semiconductor package device are disclosed. The heat dissipation structure includes a heat dissipation metal cover and a dummy silicon wafer. The heat dissipation metal cover has a cover body and a recess. The recess is formed on one side of the cover body to accommodate a heat source. The dummy silicon wafer is located in the recess. One side of the dummy silicon wafer is fixed to the heat dissipation metal cover, and the other side is used to thermally couple the heat source and electrically isolate the heat source. The semiconductor package device includes a substrate, a working wafer, a heat dissipation metal cover and a silicon heat conduction element. The working wafer is fixed on the substrate and has a working circuit built-in. The silicon heat conduction element thermally couples the working wafer and the heat dissipation metal cover, and electrically isolates the working circuit and the substrate. Thus, the above structure can improve the thermal conductivity coefficient of the heat conduction interface between the working wafer and the heat dissipation metal cover, effectively improve the package heat dissipation performance, and reduce the thermal resistance.

Description

Technical Field

[0001] This invention relates to a heat dissipation structure, a semiconductor packaging device, and a method for manufacturing the semiconductor packaging device. Background Technology

[0002] As the size of semiconductor packaging modules begins to shrink, their performance continues to increase, but this also brings higher heat generation, requiring appropriate heat dissipation methods to effectively dissipate the heat.

[0003] However, the thermal conductivity of the materials commonly used in semiconductor packaging modules is not high, which prevents effective improvement in the heat dissipation performance of these packages. Without a proper heat dissipation method to remove heat from semiconductor packaging modules, the overall stability and lifespan of the modules will be reduced.

[0004] It is evident that the above approach still has inconveniences and shortcomings, and requires further improvement. Therefore, how to effectively solve these inconveniences and shortcomings is indeed one of the important research and development topics at present, and has become a goal that urgently needs improvement in related fields. Summary of the Invention

[0005] To address these issues, the present invention provides a heat dissipation structure, a semiconductor packaging device, and a method for manufacturing the semiconductor packaging device, thereby resolving the difficulties mentioned in the prior art.

[0006] One embodiment of the present invention provides a heat dissipation structure. The heat dissipation structure includes a heat dissipation metal cover and a simulated silicon wafer. The heat dissipation metal cover has a cover body and a recess. The recess is formed on one side of the cover body for accommodating a heat source. The simulated silicon wafer is located in the recess, with one side of the simulated silicon wafer fixed to the heat dissipation metal cover and the other side used for thermal coupling to the heat source and electrically isolated from the heat source.

[0007] According to one or more embodiments of the present invention, in the above-described heat dissipation structure, the simulated silicon wafer includes a silicon body, multiple heat-conducting channels, a heat-conducting layer, and multiple solder bumps. The silicon body has a first surface and a second surface opposite to each other. The heat-conducting channels are arranged side-by-side within the silicon body. Each heat-conducting channel penetrates the silicon body and connects the first surface and the second surface of the silicon body. The heat-conducting layer is located on the first surface of the silicon body and is fixed between the heat-conducting channels and the heat dissipation metal cap. The solder bumps are spaced apart on the second surface of the silicon body. Each solder bump is soldered to one of the heat-conducting channels for fixing to a heat source.

[0008] According to one or more embodiments of the present invention, in the above-described heat dissipation structure, the heat dissipation metal cover includes a cover body and a recess. The cover body has an inner surface and an outer surface that are opposite to each other. The recess is formed on the inner surface of the cover body and accommodates a simulated silicon wafer.

[0009] According to one or more embodiments of the present invention, in the above-described heat dissipation structure, the heat dissipation metal cover includes a protective layer. The protective layer covers the inner surface and recess of the cover, and a simulated silicon wafer is encapsulated within the recess.

[0010] According to one or more embodiments of the present invention, in the above-described heat dissipation structure, the semiconductor packaging device further includes a covering material and a filler layer. The covering material surrounds the heat source. The filler layer fills the space between the protective layer and the covering material, and between the protective layer and the heat source.

[0011] According to one or more embodiments of the present invention, in the above-described heat dissipation structure, the simulated silicon wafer comprises silicon carbide.

[0012] One embodiment of the present invention provides a semiconductor packaging apparatus. The semiconductor packaging apparatus includes a substrate, a working wafer, a heat dissipation metal cap, and a silicon thermal conductive element. The working wafer includes a wafer body and a working circuit. The wafer body is fixed on the substrate. The working circuit is built into the wafer body and electrically connected to the substrate. The silicon thermal conductive element is thermally coupled to the wafer body and the heat dissipation metal cap, and is electrically isolated from the working circuit and the substrate.

[0013] According to one or more embodiments of the present invention, in the above-described semiconductor packaging device, the silicon thermal conductive element includes a silicon body, a thermal conductive layer, and a plurality of thermal conductive channels. The silicon body has a first surface and a second surface opposite to each other. These thermal conductive channels are arranged side by side within the silicon body. Each thermal conductive channel penetrates the silicon body and connects the first surface and the second surface of the silicon body. The thermal conductive layer is located on the first surface of the silicon body and thermally couples these thermal conductive channels and a heat dissipation metal cap.

[0014] According to one or more embodiments of the present invention, in the above-described semiconductor packaging apparatus, the silicon thermally conductive element further includes at least one first solder bump. The first solder bump is located on a second surface of the silicon body and thermally coupled to these thermally conductive channels. The wafer body has at least one second solder bump, a plurality of solder balls, and third and fourth surfaces opposite to each other. The second solder bump is located on the third surface and solders the first solder bump, electrically isolated from the operating circuit. The solder balls are located on the fourth surface, electrically connected to the operating circuit, and respectively solder to a plurality of solder joints on the substrate.

[0015] According to one or more embodiments of the present invention, in the above-described semiconductor packaging apparatus, the silicon thermal conductive element further includes a first filler layer. The first filler layer is located between the wafer body and the substrate, and surrounds the solder balls and solder joints. The silicon thermal conductive element further includes a second filler layer. The second filler layer is sandwiched between the wafer body and the silicon body, and surrounds the first solder bump and the second solder bump.

[0016] According to one or more embodiments of the present invention, in the above-described semiconductor packaging device, the heat dissipation metal cover includes a cover body and a recess. The cover body has an inner surface and an outer surface that are opposite to each other. The inner surface is fixed to the substrate. The recess is formed on the inner surface of the cover body for accommodating the working wafer and the silicon thermal conductive element.

[0017] According to one or more embodiments of the present invention, in the above-described semiconductor packaging device, the heat dissipation metal cover includes a protective layer. The protective layer covers the inner surface of the cover and the recess, and a silicon thermally conductive element is encapsulated within the recess.

[0018] According to one or more embodiments of the present invention, the semiconductor packaging apparatus further includes a cover material and a filler layer. The cover material is sandwiched between a protective layer and a substrate, and surrounds a working wafer. The filler layer is located between the protective layer and the cover material, and within the gap formed between the cover material, the working wafer, and the substrate.

[0019] According to one or more embodiments of the present invention, in the above-described semiconductor packaging apparatus, the silicon thermal conductive element and the wafer body have the same material.

[0020] One embodiment of the present invention provides a method for manufacturing a semiconductor packaging device, comprising the following steps: A working wafer is soldered to one side of a substrate, such that a working circuit built into a wafer body of the working wafer is electrically connected to the substrate. A silicon thermal conductive element is soldered to one side of a heat dissipation metal cap. The heat dissipation metal cap is fixedly covered on the substrate, such that the silicon thermal conductive element is sandwiched between the wafer body and the heat dissipation metal cap, and the silicon thermal conductive element is electrically isolated from the working circuit and the substrate.

[0021] According to one or more embodiments of the present invention, in the above-described method for manufacturing a semiconductor packaging device, the step of fixing a heat dissipation metal cover onto a substrate further includes welding a silicon thermal conductive element to the side of the wafer body opposite to the substrate.

[0022] According to one or more embodiments of the present invention, in the above-described method for manufacturing a semiconductor packaging device, between the steps of soldering the silicon thermal conductive element to the heat dissipation metal cover and fixing the heat dissipation metal cover onto the substrate, the method further includes the following two steps: A protective layer is formed on one side of the heat dissipation metal cover and on the silicon thermal conductive element. The side of the protective layer opposite to the heat dissipation metal cover is polished, exposing the silicon thermal conductive element to the side of the protective layer, thereby forming a heat dissipation structure.

[0023] According to one or more embodiments of the present invention, in the above-described method for manufacturing a semiconductor packaging device, the step between the step of soldering a working wafer onto a substrate and the step of fixing a heat dissipation metal cap onto the substrate further includes the following step: providing a covering material to this surface of the substrate such that the covering material surrounds the wafer body.

[0024] According to one or more embodiments of the present invention, in the above-described method for manufacturing a semiconductor packaging device, the step of fixing a heat dissipation metal cap onto the substrate further includes the following steps: forming a filler layer on the protective layer of the heat dissipation structure and the silicon thermal conductive element; covering the side of the cladding material opposite to the substrate and the side of the working wafer opposite to the substrate with the filler layer of the heat dissipation structure; thermally coupling the working wafer to the silicon thermal conductive element.

[0025] According to one or more embodiments of the present invention, in the above-described method for manufacturing a semiconductor packaging device, the steps of welding the working wafer onto the substrate and welding the silicon thermal conductive element onto the heat dissipation metal cover are performed simultaneously.

[0026] According to one or more embodiments of the present invention, in the above-described method for manufacturing a semiconductor packaging device, the silicon thermal conductive element and the wafer body are made of the same material.

[0027] Thus, through the architecture described in the above embodiments, the present invention can improve the thermal conductivity coefficient of the thermal interface located between the working chip and the heat sink, thereby effectively improving the heat dissipation performance of the package and reducing its thermal resistance.

[0028] The above description is only used to illustrate the problem to be solved by the present invention, the technical means to solve the problem, and the effects produced, etc. The specific details of the present invention will be described in detail in the following embodiments and related drawings. Attached Figure Description

[0029] To make the above and other objects, features, advantages and embodiments of the present invention more apparent and understandable, the accompanying drawings are described below:

[0030] Figure 1 This is a schematic diagram of a semiconductor packaging device according to an embodiment of the present invention;

[0031] Figure 2 for Figure 1 A flowchart of a method for manufacturing a semiconductor packaging device;

[0032] Figures 3A to 3F They are respectively Figure 2 A schematic diagram of the continuous operation of the manufacturing method;

[0033] Figure 4 Presented separately Figure 1 Thermal resistance variation diagram of semiconductor packaging device and known device;

[0034] Figure 5 This is a schematic diagram of a semiconductor packaging device according to an embodiment of the present invention;

[0035] Figures 6A to 6I They are respectively Figure 5A schematic diagram of the continuous operation of the manufacturing method; and

[0036] Figure 7 Presented separately Figure 5 The thermal resistance variation diagram of the semiconductor packaging device and a known device.

[0037] [Symbol Explanation]

[0038] 10, 11: Semiconductor packaging devices

[0039] Steps 21-23

[0040] 100: Heat source

[0041] 110:Substrate

[0042] 111: Solder joint

[0043] 120: Working chip

[0044] 121: Chip Body

[0045] 122: Third page

[0046] 123: Fourth page

[0047] 140: Second welding bump

[0048] 150: Welding ball

[0049] 160: First fill layer

[0050] 200, 201: Heat dissipation structure

[0051] 210, 220: Heat dissipation metal cover

[0052] 211: First cover

[0053] 212: Inner surface

[0054] 213: Outer surface

[0055] 214: Elevated area

[0056] 215: Depression

[0057] 216: Flange

[0058] 221: Second cover

[0059] 222: Inner surface

[0060] 223: Outer surface

[0061] 224: Depression

[0062] 230: Protective layer

[0063] 300: Silicon thermal conductive element

[0064] 310:Silicon body

[0065] 311: First Page

[0066] 312: Second page

[0067] 320: Thermal conductive layer

[0068] 330: Heat conduction channel

[0069] 340: First welding bump

[0070] 350: Second filler layer

[0071] 400: Covering material

[0072] 410: Opening in the middle

[0073] 500: Third filler layer

[0074] 600: Fourth fill layer

[0075] 700: Adhesive

[0076] R1, R2, R3, R4: Thermal resistance values

[0077] S: Solder Detailed Implementation

[0078] The following describes several embodiments of the present invention with reference to the accompanying drawings. For clarity, many practical details will be described in the following description. However, those skilled in the art will understand that these practical details are not essential in some embodiments of the present invention and therefore should not be construed as limiting the invention. Furthermore, for the sake of simplicity, some known and conventional structures and elements will be shown in a simplified schematic manner in the drawings. Additionally, for ease of reading, the dimensions of the elements in the drawings are not drawn to scale.

[0079] Figure 1 This is a schematic diagram of a semiconductor packaging apparatus 10 according to an embodiment of the present invention. Figure 1As shown, the semiconductor packaging device 10 includes a heat source 100 and a heat dissipation structure 200. The heat dissipation structure 200 is used to remove the high heat energy of the heat source 100. The heat source 100 includes a substrate 110 and a working chip 120 (e.g., a silicon wafer). The working chip 120 includes a chip body 121, a packaging unit (not shown), and at least one working circuit (not shown). The chip body 121 is fixed on the substrate 110, and the working circuit is built into the chip body 121 for signal conduction within the chip body 121 to enable the working chip 120 to operate normally. The packaging unit covers the chip body 121 to protect the chip body 121 and the working circuit. The heat dissipation structure 200 includes a heat dissipation metal cap 210 and a silicon thermal conductive element 300. The silicon thermally conductive element 300 is thermally coupled to the working chip 120 and the heat dissipation metal cover 210, and is completely electrically isolated from the working circuitry within the substrate 110 and the chip body 121. In other words, the silicon thermally conductive element 300 can exchange heat with the heat source 100, but will not exchange signals with the working chip 120. More specifically, the silicon thermally conductive element 300 is soldered to both the working chip 120 and the heat dissipation metal cover 210. The heat dissipation metal cover 210 may be, for example, a high thermal conductivity metal plating; however, the invention is not limited thereto.

[0080] The silicon thermal conductive element 300 includes a silicon body 310, a thermally conductive layer 320, and a plurality of thermally conductive channels 330. The silicon body 310 conducts heat from the working wafer 120 to the heat sink 210. For example, the silicon body 310 contains a material such as silicon carbide (SiC), or the silicon body 310 is a known component such as a simulated silicon wafer or silicon wafer. The silicon body 310 and the wafer body 121 have the same material, and the silicon body 310 has a first surface 311 and a second surface 312 facing each other. These thermally conductive channels 330 are arranged side by side within the silicon body 310. Each thermally conductive channel 330 penetrates the silicon body 310 and connects the first surface 311 and the second surface 312 of the silicon body 310, wherein each thermally conductive channel 330 is thermally coupled to the silicon body 310 to conduct heat from the working wafer 120 to the heat sink 210. The thermally conductive layer 320 is located on the first surface 311 of the silicon body 310 and is thermally coupled to the thermally conductive channels 330 and the heat dissipation metal cap 210. The thermally conductive layer 320 is, for example, a highly thermally conductive coating; however, the invention is not limited thereto.

[0081] In one option, the silicon thermal conductive element 300 is, for example, a simulated silicon wafer or a faulty silicon wafer. More specifically, the construction of the silicon thermal conductive element 300 is similar to that of the working wafer 120, except that the working circuits of the two are electrically insulated from each other, and the thermal conductive channel 330 is, for example, a TSV (Through Silicon Via) conductive portion.

[0082] Furthermore, the silicon thermal conductive element 300 also includes a plurality of first solder bumps 340. These first solder bumps 340 are fixed to the second surface 312 of the silicon body 310, between the silicon body 310 and the wafer body 121. Each first solder bump 340 is fixed to one of the thermal conductive channels 330. However, the invention is not limited thereto; in other embodiments, the first solder bumps 340 may be a single quantity and fixed to all thermal conductive channels 330. The wafer body 121 has a third surface 122 and a fourth surface 123 opposite to each other, and the wafer body 121 includes a plurality of second solder bumps 140 and a plurality of solder balls 150. The second solder bumps 140 are located on the third surface 122 and are respectively soldered to the first solder bumps 340. It should be understood that the second solder bumps 140 are still electrically isolated from the working circuitry within the wafer body 121. These solder balls 150 are located on the fourth surface 123, electrically connected to the working circuitry, and respectively solder to a plurality of solder joints 111 of the substrate 110. Figure 3A However, the invention is not limited thereto; in other embodiments, the second welding bump 140 may also be a single quantity.

[0083] The heat dissipation metal cover 210 includes a first cover body 211, a raised portion 214, and a recessed portion 215. The first cover body 211 has an inner surface 212 and an outer surface 213 that are opposite to each other. The raised portion 214 is formed protrudingly on the outer surface 213 of the first cover body 211; in other words, the raised portion 214 protrudes from the inner surface 212 towards the outer surface 213 of the first cover body 211. The recessed portion 215 is formed on the inner surface 212 of the first cover body 211 and is located within the raised portion 214, for accommodating the working chip 120 and the silicon thermal conductive element 300. In addition, the first cover body 211 has a flange 216. More specifically, the flange 216 is U-shaped and completely surrounds the recessed portion 215. The inner surface 212 of the flange 216 of the first cover body 211 is fixed to the substrate 110.

[0084] Figure 2 for Figure 1 A flowchart of a method for manufacturing a semiconductor packaging device 10. (e.g.) Figure 1 and Figure 2 As shown, the manufacturing method of the semiconductor packaging device 10 includes steps 21 to 23. In step 21, a working wafer 120 is soldered onto a substrate 110, such that the working circuit of the working wafer 120 is electrically connected to the substrate 110. In step 22, a silicon thermal conductive element 300 is fixedly attached to a heat dissipation metal cover 210. In step 23, the heat dissipation metal cover 210 is fixedly covered on the substrate 110, such that the silicon thermal conductive element 300 is sandwiched between the working wafer 120 and the heat dissipation metal cover 210.

[0085] It should be understood that in this embodiment, steps 21 and 22 can be completed simultaneously. However, the present invention is not limited to this. In other embodiments, steps 21 and 22 can also be completed sequentially.

[0086] Figures 3A to 3F They are respectively Figure 2 A schematic diagram of the continuous operation of the manufacturing method. For example... Figures 3A to 3B As shown, step 21 further includes several detailed steps, as follows: The solder balls 150 of the working die 120 are respectively soldered to the solder joints 111 of the substrate 110, so that the working circuit of the working die 120 can be electrically connected to the substrate 110 through the solder balls 150; then, a first filler layer 160 is filled between the working die 120 and the substrate 110, such that the first filler layer 160 together surrounds the solder balls 150 and the solder joints 111 to protect them. For example, the first filler layer 160 is an epoxy resin or similar material; however, the present invention is not limited thereto.

[0087] like Figures 3C to 3E As shown, step 22 above further includes several detailed steps, as follows: The thermally conductive layer 320 of the silicon thermally conductive element 300 is soldered to the inner wall of the recess 215 of the heat dissipation metal cover 210 using solder S. Figures 3C to 3D Next, the heat dissipation metal cover 210 is flipped over, and multiple first welding protrusions 340 are respectively fixed onto these heat conduction channels 330. Figure 3E ).

[0088] like Figure 3E and Figure 3F As shown, step 23 above further includes several detailed steps, as follows. The inner surface 212 of the heat dissipation metal cover 210 is fixedly adhered to the substrate 110 using adhesive 700, so that the silicon thermal conductive element 300 is sandwiched between the working wafer 120 and the heat dissipation metal cover 210. Next, the first welding bumps 340 of the silicon thermal conductive element 300 are respectively welded to the second welding bumps 140 of the working wafer 120, so that the working wafer 120 can exchange heat with the heat dissipation metal cover 210 through the silicon thermal conductive element 300, and the substrate 110 can exchange heat with the heat dissipation metal cover 210. Then, a second filler layer 350 is filled into the gaps formed between the working wafer 120 and the silicon thermal conductive element 300, and between the first welding bumps 340 and the second welding bumps 140, so that the second filler layer 350 collectively surrounds the first welding bumps 340 and the second welding bumps 140, thereby protecting the first welding bumps 340 and the second welding bumps 140. Figure 1 For example, the second filler layer 350 may be made of epoxy resin or a similar material; however, the invention is not limited thereto.

[0089] It should be understood that if the wafer body 121 contains solderable material, the first solder bumps 340 of the silicon thermal conductive element 300 can be directly soldered to the surface of the wafer body 121. Therefore, the wafer body 121 does not necessarily have to have second solder bumps 140.

[0090] In this embodiment, as Figure 1 As shown, when a known device without a silicon thermal conductive element and the semiconductor packaging device 10 of this embodiment are subjected to thermal simulation in a system (including a heat dissipation module), the simulated junction temperature of the known device without a silicon thermal conductive element is 88.98°C, and the simulated junction temperature of the semiconductor packaging device 10 of this embodiment is 84.57°C. The simulation conditions are an ambient temperature of 30.0°C, a fan inlet temperature of 36.0°C, and a fan speed of 6700 RPM.

[0091] Figure 4 Presented separately Figure 1 The thermal resistance variation diagram of the semiconductor packaging device 10 and a known device is shown. Figure 4 As shown, the results of thermal simulation indicate that, compared to the known device without a silicon thermal conductive element, whose thermal resistance R1 is approximately 0.20, the silicon thermal conductive element 300 of the semiconductor packaging device 10 in this embodiment has the largest influence on the overall thermal resistance R2, and its thermal resistance (R2) is significantly higher. JC The improvement was approximately 45%.

[0092] Figure 5 This is a schematic diagram of a semiconductor packaging apparatus 11 according to an embodiment of the present invention. Figure 5 As shown, the semiconductor packaging device 11 in this embodiment and Figure 1 The semiconductor packaging device 10 is substantially the same, except that the heat dissipation structure 201 has a heat dissipation metal cover 220 including a second cover 221 and a recess 224. The second cover 221 has an inner surface 222 and an outer surface 223 that are opposite to each other. The recess 224 is formed on the inner surface 222 of the second cover 221 and is recessed toward the outer surface 223 of the second cover 221, but does not protrude from the outer surface 223 of the second cover 221, for accommodating the silicon thermal conductive element 300. In addition, the second cover 221 is flat, and the inner surface 222 of the second cover 221 completely surrounds the recess 224 and is fixed to the substrate 110.

[0093] The semiconductor packaging device 11 further includes a protective layer 230. A portion of the protective layer 230 completely covers the inner surface 222 and the recess 224 of the second cover 221, and a portion of the protective layer 230 also fills the recess 224 and encapsulates the silicon thermal conductive element 300 within the recess 224. The semiconductor packaging device 11 further includes a cover material 400, a third filler layer 500, and a fourth filler layer 600. The cover material 400 is formed between the second cover 221 and the substrate 110, and the cover material 400 surrounds the working die 120 to form a central opening 410. In other words, the working die 120 is housed within the central opening 410, located outside the recess 224 of the heat dissipation metal cover 220. The third filler layer 500 fills the central opening 410 and is located within the gap formed between the cover material 400, the working die 120, and the substrate 110. The fourth filler layer 600 is filled between the protective layer 230 and the covering material 400. For example, the covering material 400 is an epoxy resin or similar material, the third filler layer 500 and the fourth filler layer 600 are rubber or silicone or similar materials, and the protective layer 230 is a resin molding material or similar material. However, the present invention is not limited thereto.

[0094] Figures 6A to 6I They are respectively Figure 5 A schematic diagram of the continuous operation of the manufacturing method. For example... Figures 6A to 6C As shown, step 21 above further includes several detailed steps, as follows: The solder balls 150 of the working chip 120 are respectively soldered to the solder points 111 of the substrate 110, so that the working circuit of the working chip 120 can be electrically connected to the substrate 110 through the solder balls 150. Figure 6A and Figure 6B Next, a third filler layer 500 is filled between the working wafer 120 and the substrate 110, such that the third filler layer 500 together surrounds the solder balls 150 and the solder joints 111 to protect the solder balls 150 and the solder joints 111. Figure 6B Next, a coating material 400 is applied to form a cover material 400 on one side of the substrate 110, surrounding the aforementioned working wafer 120 and the third filler layer 500. Figure 6C ).

[0095] like Figures 6D to 6H As shown, step 22 above further includes several detailed steps, as follows: The thermally conductive layer 320 of the silicon thermally conductive element 300 is soldered to the inner wall of the recess 224 of the heat dissipation metal cover 220 using solder S. Figures 6D to 6E Next, a protective layer 230 is applied to the inner surface 222 of the heat dissipation metal cap 220 and the silicon thermal conductive element 300 in the recess 224 to form a protective layer 230. Figure 6FNext, the protective layer 230 is ground against the heat dissipation metal cover 220 to remove a portion of the protective layer 230, exposing the heat conduction channels 330 of the silicon thermal conductive element 300 to the side of the protective layer 230. Figure 6G Next, the heat dissipation metal cover 220 is flipped over, and the first welding protrusions 340 are respectively fixed onto the heat conduction channels 330. Figure 6H ).

[0096] like Figure 6H As shown, step 22 above further includes several detailed steps, as follows: A fourth filler layer 600 is formed on the protective layer 230 and the silicon thermal conductive element 300, thus forming the above-mentioned heat dissipation structure 201.

[0097] like Figure 5 and Figure 6I As shown, step 23 above further includes several detailed steps, as follows. The heat dissipation structure 201 is covered by the fourth filling layer 600 on one side of the covering material 400 relative to the substrate 110 and the other side of the working wafer 120 relative to the substrate 110, so that the silicon thermal conductive element 300 is sandwiched between the working wafer 120 and the heat dissipation metal cover 220. Figure 5 Next, the first welding bumps 340 of the silicon thermal conductive element 300 are respectively welded to the second welding bumps 140 of the working chip 120, so that the working chip 120 can exchange heat with the heat dissipation metal cover 220 through the silicon thermal conductive element 300.

[0098] It should be understood that if the wafer body 121 contains solderable material, the first solder bumps 340 of the silicon thermal conductive element 300 can be directly soldered to the surface of the wafer body 121. Therefore, the wafer body 121 does not necessarily have to have second solder bumps 140.

[0099] In this embodiment, when a known device without a silicon thermal conductive element 300 and the semiconductor packaging device 11 of this embodiment are thermally simulated in a system (including a heat dissipation module), the simulated junction temperature of the known device without a silicon thermal conductive element 300 is 88.98°C, and the simulated junction temperature of the semiconductor packaging device 11 of this embodiment is 82.07°C. The simulation conditions are an ambient temperature of 30.0°C, a fan inlet temperature of 36.0°C, and a fan speed of 6700 RPM.

[0100] Figure 7 Presented separately Figure 5 The thermal resistance variation diagram of the semiconductor packaging device 11 and a known device is shown. Figure 7As shown, the results of thermal simulation show that, compared to the known device without the silicon thermal conductive element 300, whose thermal resistance R3 is approximately 1.00, the silicon thermal conductive element 300 of the semiconductor packaging device 11 in this embodiment has the largest influence on the overall thermal resistance R4, and its thermal resistance (R... JC The improvement was approximately 65%.

[0101] Thus, through the architecture described above, this embodiment can improve the thermal conductivity of the thermal interface between the working chip and the heat sink, thereby effectively improving the heat dissipation performance of the package and reducing its thermal resistance.

[0102] Finally, the embodiments disclosed above are not intended to limit the present invention. Any modifications and refinements made by those skilled in the art without departing from the spirit and scope of the present invention are protected under this invention. Therefore, the scope of protection of this invention shall be determined by the scope defined in the appended claims.

Claims

1. A heat dissipation structure, characterized in that, include: A heat-dissipating metal cover has a cover body, a recess, and a protective layer. The recess is formed on one side of the cover body to accommodate a heat source, and the protective layer covers the side of the cover body and the recess. A simulated silicon wafer is located within the recessed portion. One side of the simulated silicon wafer is fixed to the heat dissipation metal cap, and the other side is used for thermal coupling to the heat source while being electrically isolated from it. The simulated silicon wafer includes a silicon material body and multiple thermally conductive channels. The silicon material body has a first surface and a second surface opposite to each other. The multiple thermally conductive channels are arranged side-by-side within the silicon material body, each of the multiple thermally conductive channels penetrating the silicon material body and connecting the first surface and the second surface of the silicon material body. The protective layer covers the simulated silicon wafer within the recess, and the side of the protective layer opposite to the cover exposes the second surface of the silicon material body and the plurality of heat conduction channels of the simulated silicon wafer.

2. The heat dissipation structure according to claim 1, characterized in that, This simulated silicon wafer contains: A thermally conductive layer is located on the first surface of the silicon material body and is fixedly connected to the plurality of thermally conductive channels and the heat dissipation metal cap; and Multiple welding bumps are spaced apart on the second surface of the silicon material body, and each welding bump is welded to one of the multiple heat conduction channels to be fixed to the heat source.

3. The heat dissipation structure according to claim 1, characterized in that, Also includes: A covering material, situated on the protective layer and surrounding the heat source; and A filler layer is provided between the protective layer and the covering material, and between the protective layer and the heat source.

4. The heat dissipation structure according to claim 1, characterized in that, The simulated silicon wafer contains silicon carbide.

5. A semiconductor packaging device, characterized in that, include: One substrate; A working chip includes a chip body and a working circuit. The chip body is fixed on the substrate, and the working circuit is built into the chip body and electrically connected to the substrate. A heat dissipation metal cover includes a cover body, a recess, and a protective layer. The cover body has an inner surface and an outer surface facing each other. The inner surface is fixed to a substrate. The recess is formed on the inner surface of the cover body for accommodating a working chip. The protective layer covers the inner surface of the cover body and the recess. A silicon thermal conductive element is housed within the recessed portion, thermally coupled to the wafer body and the heat dissipation metal cover, and electrically isolated from the working circuit and the substrate. The silicon thermal conductive element includes a silicon body and a plurality of thermal conductive channels. The silicon body has a first surface and a second surface opposite to each other. The plurality of thermal conductive channels are arranged side by side within the silicon body. Each of the plurality of thermal conductive channels penetrates the silicon body and connects the first surface and the second surface of the silicon body. A protective layer covers the silicon thermal conductive element within the recessed portion, and the side of the protective layer opposite to the cover exposes the second surface of the silicon body and the plurality of thermal conductive channels of the silicon thermal conductive element.

6. The semiconductor packaging apparatus according to claim 5, characterized in that, This silicon thermal conductive element includes: A thermally conductive layer is located on the first surface of the silicon material body and is thermally coupled to the plurality of thermally conductive channels and the heat dissipation metal cover.

7. The semiconductor packaging apparatus according to claim 6, characterized in that, The silicon thermal conductive element also includes: At least one first welding bump is located on the second surface of the silicon body, and the first welding bump is thermally coupled to the plurality of heat-conducting channels; and The wafer body has at least one second solder bump, a plurality of solder balls, and a third surface and a fourth surface opposite to each other. The second solder bump is located on the third surface and is soldered to the first solder bump, and is electrically isolated from the working circuit. The plurality of solder balls are located on the fourth surface, are electrically connected to the working circuit, and are respectively soldered to a plurality of solder joints on the substrate.

8. The semiconductor packaging apparatus according to claim 7, characterized in that, The working wafer also includes a first filler layer located between the wafer body and the substrate, and surrounding the plurality of solder balls and the plurality of solder joints; and The silicon thermal conductive element also includes a second filler layer sandwiched between the wafer body and the silicon body, and surrounding the first solder bump and the second solder bump.

9. The semiconductor packaging apparatus according to claim 5, characterized in that, Also includes: A cover material, sandwiched between the protective layer and the substrate, and surrounding the working chip; and A filler layer is located between the protective layer and the cladding material, and within the gap formed between the cladding material, the working wafer, and the substrate.

10. The semiconductor packaging apparatus according to claim 5, characterized in that, The silicon thermal conductive element is made of the same material as the wafer body.

11. A method for manufacturing a semiconductor packaging device, characterized in that, include: A working chip is soldered to one side of a substrate, such that a working circuit built into a chip body of the working chip is electrically connected to the substrate. A silicon thermal conductive element is soldered to one side of a heat dissipation metal cover. The silicon thermal conductive element includes a silicon body and a plurality of thermal conductive channels. The silicon body has a first surface and a second surface that are opposite to each other. The plurality of thermal conductive channels are arranged side by side in the silicon body. Each of the plurality of thermal conductive channels penetrates the silicon body and connects the first surface and the second surface of the silicon body. A protective layer is formed on the surface of the heat dissipation metal cover and the silicon thermal conductive element; Grinding the protective layer on the side opposite the heat dissipation metal cover exposes the second surface of the silicon body of the silicon thermal conductive element and the plurality of heat conduction channels to the side of the protective layer opposite the heat dissipation metal cover, thereby forming a heat dissipation structure; and The heat dissipation metal cover is fixedly placed on the substrate, so that the wafer body is sandwiched between the silicon thermal conductive element and the heat dissipation metal cover, wherein the silicon thermal conductive element is electrically isolated from the working circuit and the substrate.

12. The method for manufacturing a semiconductor packaging device according to claim 11, characterized in that, The step of fixing the heat dissipation metal cover onto the substrate further includes: The silicon thermal conductive element is soldered to the side of the wafer body opposite the substrate.

13. The method for manufacturing a semiconductor packaging device according to claim 11, characterized in that, Between the steps of soldering the working chip onto the substrate and fixing the heat dissipation metal cover onto the substrate, the method further includes: A covering material is provided to the surface of the substrate such that the covering material surrounds the chip body.

14. The method for manufacturing a semiconductor packaging device according to claim 13, characterized in that, The step of fixing the heat dissipation metal cover onto the substrate further includes: A filling layer is formed on the protective layer of the heat dissipation structure and the silicon thermal conductive element; The filling layer of the heat dissipation structure covers the side of the cladding material opposite to the substrate and the side of the working chip opposite to the substrate; as well as This allows the working chip to be thermally coupled to the silicon thermal conductive element.

15. The method for manufacturing a semiconductor packaging device according to claim 11, characterized in that, The steps of soldering the working chip onto the substrate and soldering the silicon thermal conductive element onto the heat dissipation metal cover are completed simultaneously.

16. The method for manufacturing a semiconductor packaging device according to claim 11, characterized in that, The silicon thermal conductive element is made of the same material as the wafer body.

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