A stacked fan-out packaging structure and a method for forming the same

Abstract

The present invention relates to a stacked fan-out packaging structure, comprising: a lower packaging structure comprising: a first interconnect structure, the first interconnect structure comprising a plurality of first insulating layers and a plurality of first metal redistribution layers located within the plurality of first insulating layers; a first underbump metallization layer located on the first metal redistribution layers on the front surface of the first interconnect structure; a second underbump metallization layer located on the first metal redistribution layers on the front surface of the first interconnect structure; a first chip disposed on the first underbump metallization layer; an underfill disposed between the first chip and the first interconnect structure; a heat sink attached to the back surface of the first chip; first solder balls disposed on the second underbump metallization layer; a first plastic encapsulation layer encapsulating the area between the front surface of the first interconnect structure and the upper surface of the heat sink; a second solder ball disposed on the back surface of the first interconnect structure; an upper packaging structure flip-chip mounted on the lower packaging structure; and a third plastic encapsulation layer.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor packaging technology, and in particular to a stacked fan-out packaging structure and a forming method thereof. Background Art

[0002] Fan-out wafer-level packaging (FOWLP) technology, with its advantages of high density, thinness, compactness, excellent heat dissipation, and high-frequency performance, has become one of the most promising development directions for heterogeneous integration. An increasing number of end customers are choosing FOWLP to package their chips. FOWLP shares the characteristics of wafer-level packaging with the advantages of low cost and high integration.

[0003] Currently, through molding via (TMV) or mega pillar processes are commonly used in stacked packages. These processes require additional processes and equipment, making them relatively complex. To address these issues, a new research approach and solution are needed. Summary of the Invention

[0004] The task of the present invention is to provide a stacked fan-out packaging structure and a method for forming the same, which uses large-size solder balls instead of copper pillars to achieve vertical interconnection in the packaging structure, without the need for plastic packaging punching and additional processes such as photolithography and electroplating to form copper pillars.

[0005] In a first aspect of the present invention, in order to solve the problems existing in the prior art, the present invention provides a stacked fan-out packaging structure, comprising:

[0006] The lower packaging structure includes:

[0007] a first interconnect structure comprising a plurality of first insulating layers and a plurality of first metal redistribution layers located in the plurality of first insulating layers;

[0008] a first under-bump metallization layer located on the first metal redistribution layer on the front side of the first interconnect structure;

[0009] A second under bump metallization layer is located on the first metal redistribution layer on the front side of the first interconnect structure.

[0010] a first chip disposed on the first under-bump metallization layer;

[0011] an underfill disposed between the first chip and the first interconnect structure;

[0012] a heat sink mounted on the back of the first chip;

[0013] a first solder ball disposed on the second under bump metallization layer;

[0014] a first plastic sealing layer, which seals the area between the front surface of the first interconnection structure and the upper surface of the heat sink;

[0015] a second solder ball disposed on a backside of the first interconnect structure;

[0016] An upper package structure is flip-mounted on the lower package structure, and the upper package structure includes:

[0017] a second interconnect structure having a first side and a second side opposite to the first side, the second interconnect structure comprising a plurality of second insulating layers and a plurality of second metal redistribution layers located in the plurality of second insulating layers;

[0018] a second chip disposed on a second metal redistribution layer located on a second side of the second interconnect structure;

[0019] a third under bump metallization layer electrically connected to the second metal redistribution layer located on the first surface of the second interconnect structure and welded to the heat sink and the first solder ball;

[0020] a second plastic sealing layer, for plastic sealing the second chip;

[0021] A third plastic encapsulation layer is used to encapsulate the first surface of the second interconnect structure between the first plastic encapsulation layer and the first surface of the second interconnection structure.

[0022] Furthermore, the upper surface of the heat sink and the top of the first solder ball are exposed from the first plastic packaging layer.

[0023] Furthermore, the second under bump metallization layer is located on the periphery of the first under bump metallization layer; and

[0024] The first solder balls are located around the first chip.

[0025] Furthermore, the plurality of first metal redistribution layers are electrically connected; and

[0026] The plurality of second metal redistribution layers are electrically connected to each other.

[0027] In a second aspect of the present invention, in order to solve the problems existing in the prior art, the present invention provides a method for forming a stacked fan-out packaging structure, comprising:

[0028] Forming a lower package wafer, including:

[0029] Applying temporary bonding glue on the slide;

[0030] forming a first interconnect structure on the temporary bonding adhesive, wherein the first interconnect structure comprises a plurality of first insulating layers and a plurality of first metal redistribution layers located in the plurality of first insulating layers;

[0031] forming a first under bump metallization layer and a second under bump metallization layer on the first metal redistribution layer located on the front surface of the first interconnect structure, and forming a first solder layer on the first under bump metallization layer and the second under bump metallization layer;

[0032] disposing a first solder ball on the second under bump metallization layer;

[0033] Arranging a first chip on the first under-bump metallization layer, and filling an underfill between the first chip and the first interconnect structure;

[0034] Mounting a heat sink on the back side of the first chip; and

[0035] Plastic-sealing the area between the front surface of the first interconnect structure and the upper surface of the heat sink to form a first plastic-sealing layer;

[0036] Forming the upper package wafer, including:

[0037] forming a second interconnect structure on the front side of the plastic-encapsulated wafer, the plastic-encapsulated wafer including a second chip having a second bump on the front side and a second plastic-encapsulating layer encapsulating the second chip, the second interconnect structure having a first side and a second side opposite to the first side, and including a plurality of second insulating layers and a plurality of second metal redistribution layers located in the plurality of second insulating layers; arranging a third under-bump metallization layer on the first side of the second interconnect structure, and forming a second solder layer on the third under-bump metallization layer; and

[0038] The upper package wafer is flipped onto the lower package wafer to form a stacked fan-out package wafer.

[0039] Furthermore, the method for forming the stacked fan-out packaging structure further includes:

[0040] Performing secondary wafer molding to mold the second interconnect structure to the first molding layer;

[0041] Thinning the second plastic packaging layer to expose the back side of the second chip;

[0042] Remove the slide through a debonding process;

[0043] Arranging second solder balls on the backside of the first interconnect structure of the lower package wafer; and

[0044] Cut the stacked fan-out package wafer into individual stacked fan-out package structures.

[0045] Furthermore, a first insulating layer is formed on the temporary bonding adhesive by coating, deposition, etc., and then the first insulating layer is etched to form a circuit pattern. Metal is electroplated on the circuit pattern to form a first metal redistribution layer. The operation is repeated multiple times to form a first interconnection structure.

[0046] Furthermore, the second under bump metallization layer is larger than the first under bump metallization layer; and / or

[0047] The second under bump metallization layer is located on the periphery of the first under bump metallization layer.

[0048] Furthermore, the first plastic packaging layer is formed by plastic packaging from the front surface of the first interconnect structure to the upper surface of the heat sink using auxiliary thin film packaging technology, and the upper surface of the heat sink and the top of the first solder ball are exposed.

[0049] Furthermore, the upper package wafer is flip-chip mounted on the lower package wafer using wafer-to-wafer or chip-to-wafer assembly technology, wherein the third under-bump metallization layer is welded to the heat sink and the first solder ball.

[0050] The present invention has at least the following beneficial effects: the present invention discloses a stacked fan-out package structure and a method for forming the same, wherein the stacked fan-out package uses large-size solder balls instead of copper pillars to achieve vertical interconnection between the interconnect surface in the lower package structure and the back surface of the package, without the need for plastic encapsulation punching and additional processes such as photolithography and electroplating to form copper pillars; a heat sink is arranged in the lower package structure, and the heat sink is connected to the under-bump metallization layer in the upper package structure, thereby enabling heat conduction in the shortest path in the vertical direction; the manufacturing process of the stacked fan-out package structure is simple and compatible with existing processes. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] To further illustrate the above and other advantages and features of various embodiments of the present invention, a more detailed description of various embodiments of the present invention will be presented with reference to the accompanying drawings. It will be understood that these drawings depict only typical embodiments of the present invention and are not to be considered as limiting the scope thereof. In the drawings, for clarity, identical or corresponding parts will be represented by the same or similar reference numerals.

[0052] Figure 1 A schematic diagram showing a stacked fan-out packaging structure according to an embodiment of the present invention is shown; and

[0053] Figures 2A to 2N A cross-sectional schematic diagram of the formation process of a stacked fan-out packaging structure according to the present invention is shown. DETAILED DESCRIPTION

[0054] It should be noted that components in the drawings may be shown exaggerated for illustrative purposes and are not necessarily true to scale.

[0055] In the present invention, each embodiment is only intended to illustrate the aspects of the present invention and should not be construed as limiting.

[0056] In the present invention, unless otherwise specified, the quantifiers "a" and "an" do not exclude the presence of multiple elements.

[0057] It should also be pointed out that in the embodiments of the present invention, for the sake of clarity and simplicity, only a portion of the parts or components may be shown, but a person skilled in the art will understand that under the teachings of the present invention, the required parts or components may be added according to the needs of the specific scenario.

[0058] It should also be pointed out that within the scope of the present invention, the terms "same", "equal", "equal to" and the like do not mean that the two values are absolutely equal, but allow a certain reasonable error, that is, the terms also cover "substantially the same", "substantially equal", and "substantially equal to".

[0059] It should also be noted that in the description of the present invention, the terms "center," "longitudinal," "lateral," "upper," "lower," "front," "back," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer" and the like, indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate description and simplify the present invention. They do not explicitly or implicitly state that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0060] In addition, the embodiments of the present invention describe the process steps in a specific order, but this is only for the convenience of distinguishing the steps, and does not limit the order of the steps. In different embodiments of the present invention, the order of the steps can be adjusted according to the adjustment of the process.

[0061] Figure 1 A schematic diagram of a stacked fan-out packaging structure according to an embodiment of the present invention is shown.

[0062] like Figure 1 As shown, a stacked fan-out package structure includes an upper package body and a lower package body.

[0063] The lower package includes a first interconnect structure 100 , a first underbump metallization layer 103 , a second underbump metallization layer 104 , a first chip 105 , an underfill 107 , a heat sink 108 , a first solder ball 109 , a first plastic layer 110 , and a second solder ball 111 .

[0064] The first interconnect structure 100 has a front surface and a back surface opposite to the front surface. The first interconnect structure 100 includes a plurality of first insulating layers 101 and a plurality of first metal redistribution layers 102 located in the plurality of first insulating layers, and the plurality of first metal redistribution layers 102 are electrically connected.

[0065] The first under bump metallization layer 103 is located on the first metal redistribution layer 102 on the front side of the first interconnect structure 100 .

[0066] The second UBM layer 104 is located on the first metal redistribution layer 102 on the front side of the first interconnect structure 100 and is located outside the first UBM layer 103. The second UBM layer 104 is larger than the first UBM layer 103.

[0067] A first chip 105 is disposed on the first underbump metallization layer 103. The front surface of the first chip 105 has first bumps 106. The first chip 105 is disposed on the first underbump metallization layer 103 by soldering the first bumps 106 to the first underbump metallization layer 103. Here, there are two first chips. In other embodiments of the present invention, there may be fewer or more first chips.

[0068] An underfill 107 is disposed between the first chip 105 and the first interconnect structure 100 . The underfill 107 is used to protect the connection between the first bump 106 and the first underbump metallization layer 103 .

[0069] The heat sink 108 is attached to the back surface of the first chip 105 via an adhesive material 112 .

[0070] The first solder balls 109 are disposed on the second under-bump metallization layer 104 by soldering. The first solder balls 109 are located around the first chip 105 .

[0071] The first solder layer 113 is located between the first bump 106 and the first underbump metallurgy layer 103 and between the first solder ball 109 and the second underbump metallurgy layer 104 .

[0072] The first plastic encapsulation layer 110 encapsulates the area between the front surface of the first interconnect structure 100 and the upper surface of the heat sink 108. The upper surface of the heat sink 108 and the top of the first solder ball 109 are exposed from the first plastic encapsulation layer 110.

[0073] The second solder ball 111 is disposed on the back side of the first interconnect structure 100 and is electrically connected to the first metal redistribution layer 102. The second solder ball 111 is smaller than the first solder ball 109.

[0074] The upper package includes a second interconnect structure 200 , a second chip 203 , a third under-bump metallization layer 204 and a second plastic layer 205 .

[0075] The second interconnect structure 200 has a first surface and a second surface opposite to the first surface, and includes a plurality of second insulating layers 201 and a plurality of second metal redistribution layers 202 located in the plurality of second insulating layers, wherein the plurality of second metal redistribution layers 202 are electrically connected.

[0076] A second chip 203 is disposed on the second metal redistribution layer 202 on the second side of the second interconnect structure 200. The front side of the second chip 203 has second bumps 206. The second chip 203 is disposed on the second metal redistribution layer 202 on the second side of the second interconnect structure 200 through the second bumps 206 and is electrically connected thereto.

[0077] The third under bump metallization layer 204 is electrically connected to the second metal redistribution layer 202 on the first side of the second interconnect structure 200 . The third under bump metallization layer 204 is soldered to the heat sink 108 and the first solder ball 109 .

[0078] The second plastic packaging layer 205 is used to plastic-package the second chip 203 .

[0079] The upper package body is connected to the lower package body by soldering the third UBM layer 204 to the first solder ball 109 and the heat sink 108. A second solder layer 207 is located between the third UBM layer 204 and the first solder ball 109, and between the third UBM layer 204 and the heat sink 108. In other words, a portion of the third UBM layer 204 is connected to the first solder ball 109. By utilizing the fact that the height of the first solder ball 109 is greater than the thickness of the first chip, vertical interconnection between the interconnect surface and the back surface of the package is achieved. This is compatible with existing processes and is process-feasible.

[0080] Another portion of the third UBM layer 204 is connected to the heat sink mounted on the back of the lower package, which can achieve the shortest path of heat conduction in the vertical direction. Therefore, this portion of the third UBM layer 204 can be regarded as a thermal conductive bump (dummy bump).

[0081] The third molding layer 300 is used to mold the first surface of the second interconnect structure 200 to the first molding layer 110. The third molding layer 300 fills the gap between the upper packaging structure and the lower packaging structure.

[0082] Figures 2A to 2N A cross-sectional schematic diagram of the formation process of a stacked fan-out packaging structure according to the present invention is shown.

[0083] A method for forming a stacked fan-out package structure includes:

[0084] Forming a lower package wafer, including:

[0085] In step 1, if Figure 2A As shown, a temporary bonding glue 402 is coated on a carrier wafer 401 .

[0086] In step 2, if Figure 2B As shown, a first interconnect structure 100 is formed on a temporary bonding adhesive 402. First interconnect structure 100 includes multiple first insulating layers 101 and multiple first metal redistribution layers 102 located within the multiple first insulating layers, with the multiple first metal redistribution layers 102 being electrically connected. First insulating layer 101 is formed on temporary bonding adhesive 402 by coating, deposition, or other methods. The first insulating layer is then etched to form a circuit pattern, and metal is electroplated on the circuit pattern to form first metal redistribution layers 102. The above steps are repeated multiple times to obtain first interconnect structure 100.

[0087] In step 3, if Figure 2C As shown, a first underbump metallurgy (UBM) layer 103 and a second underbump metallurgy (UBM) layer 104 are formed on a first metal redistribution layer 102 located on the front surface of a first interconnect structure 100, and a first solder layer 113 is formed on the first underbump metallurgy (UBM) layer 103 and the second underbump metallurgy (UBM) layer 104. When forming the first and second UBM layers 103 and 104, a photoresist is first applied to the first insulating layer 101. The photoresist on the first metal redistribution layer 102 is removed by photolithography to form a circuit pattern. Metal is electroplated on the circuit pattern to form the first and second UBM layers 103 and 104. Finally, the photoresist is removed. The second UBM layer 104 is larger than the first UBM layer 103. The second UBM layer 104 is located on the periphery of the first UBM layer 103.

[0088] In step 4, if Figure 2D As shown, a first solder ball 109 is arranged on the second UBM layer 104. The first solder ball 109 is soldered to the second UBM layer 104 through a ball planting process. A solder layer is provided between the second UBM layer 104 and the first solder ball 109.

[0089] In step 5, if Figure 2E As shown, a first chip 105 is arranged on the first underbump metallization layer 103, and an underfill 107 is filled between the first chip 105 and the first interconnect structure 100. The front surface of the first chip 105 has a first bump 106, and the first chip 105 is arranged on the first underbump metallization layer 103 by soldering the first bump 106 to the first underbump metallization layer 103. A solder layer is provided between the first underbump metallization layer 103 and the first bump 106.

[0090] In step 6, if Figure 2F As shown, a heat sink 108 is mounted on the back surface of the first chip 105. An adhesive material 112 bonds the back surface of the first chip 105 to the heat sink 108.

[0091] In step 7, if Figure 2G As shown, the area between the front surface of the first interconnect structure 100 and the upper surface of the heat sink 108 is plastic-encapsulated to form a first plastic encapsulation layer 110. The area between the front surface of the first interconnect structure 100 and the upper surface of the heat sink 108 is plastic-encapsulated using an auxiliary thin film encapsulation technology to form the first plastic encapsulation layer 110, exposing the upper surface of the heat sink 108 and the top of the first solder ball 109.

[0092] Forming the upper package wafer, including:

[0093] In step 8, if Figure 2H As shown, a second interconnect structure 200 is formed on the front side of a molded wafer. The molded wafer includes a second chip 203 and a second molding layer 205 that molds the second chip 203. The front side of the second chip 203 has second bumps 206, with the second molding layer 205 exposed on the surface of the second bumps 206. The second interconnect structure 200 includes multiple second insulating layers 201 and multiple second metal redistribution layers 202 located within the multiple second insulating layers, with the multiple second metal redistribution layers 202 being electrically connected to each other. The second insulating layer 201 is formed on the front side of the molded wafer by coating, deposition, or other methods, and then the second insulating layer is etched to form a circuit pattern. The second metal redistribution layer 202 is then electroplated on the circuit pattern to form the second metal redistribution layer 202. The above steps are repeated multiple times to obtain the second interconnect structure 200. The second interconnect structure 200 has a first side and a second side opposite the first side. The second metal redistribution layer 202 located on the second side of the second interconnect structure 200 is electrically connected to the second bumps 206.

[0094] In step 9, if Figure 2I As shown, a third under bump metallization layer 204 is disposed on the first surface of the second interconnect structure 200, and a second solder layer 207 is formed on the third under bump metallization layer 204. The third under bump metallization layer 204 is electrically connected to the second metal redistribution layer 202.

[0095] In step 10, if Figure 2J As shown, the upper package wafer is flip-chipped onto the lower package wafer to form a stacked fan-out package wafer. Wafer-to-wafer or chip-to-wafer assembly technology is used to flip-chip the upper package wafer onto the lower package wafer. The third underbump metallization layer 204 is soldered to the heat sink 108 and the first solder ball 109. A second solder layer 207 is located between the third underbump metallization layer 204 and the first solder ball 109, and between the third underbump metallization layer 204 and the heat sink 108.

[0096] In other words, a portion of the third under-bump metallization layer 204 is connected to the first solder ball 109. Taking advantage of the fact that the height of the first solder ball 109 is greater than the thickness of the first chip, vertical interconnection between the interconnect surface and the back surface of the package is achieved. This is compatible with existing processes and has process feasibility.

[0097] Another portion of the third UBM layer 204 is connected to the heat sink mounted on the back of the lower package, which can achieve the shortest path of heat conduction in the vertical direction. Therefore, this portion of the third UBM layer 204 can be regarded as a dummy bump.

[0098] In step 11, if Figure 2K As shown, a secondary wafer molding is performed to mold the second interconnect structure 200 to the first molding layer 110. The second interconnect structure 200 to the first molding layer 110 is molded to form a third molding layer 300 to fill the gap between the upper packaging wafer and the lower packaging wafer.

[0099] In step 12, if Figure 2L As shown, the second plastic packaging layer 205 is thinned to expose the back side of the second chip 203 .

[0100] In step 13, if Figure 2M As shown, the carrier 401 is removed by a debonding process.

[0101] In step 14, if Figure 2N As shown, second solder balls 111 are arranged on the first metal redistribution layer 102 on the back side of the first interconnect structure 100 .

[0102] In step 15 , the stacked fan-out package wafer is cut into individual stacked fan-out package structures.

[0103] In other embodiments of the present invention, a single packaging structure can be used instead of a packaging wafer to perform steps 7 and 8 to form a single upper packaging body, and multiple single upper packaging bodies can be assembled with a lower packaging wafer, and finally cut to form a single stacked fan-out packaging structure.

[0104] The present invention has at least the following beneficial effects: the present invention discloses a stacked fan-out package structure and a method for forming the same, wherein the stacked fan-out package uses large-size solder balls instead of copper pillars to achieve vertical interconnection between the interconnect surface in the lower package structure and the back surface of the package, without the need for plastic encapsulation punching and additional processes such as photolithography and electroplating to form copper pillars; a heat sink is arranged in the lower package structure, and the heat sink is connected to the under-bump metallization layer in the upper package structure, thereby enabling heat conduction in the shortest path in the vertical direction; the manufacturing process of the stacked fan-out package structure is simple and compatible with existing processes.

[0105] Although certain embodiments of the present invention have been described in this application, those skilled in the art will appreciate that these embodiments are provided by way of example only. Numerous variations, alternatives, and modifications will be contemplated by those skilled in the art in light of the teachings of this disclosure without departing from the scope of the present invention. The appended claims are intended to define the scope of the present invention and are intended to encompass methods and structures within the scope of these claims and their equivalents.

Claims

1. A stacked fan-out packaging structure, comprising: The lower packaging structure includes: a first interconnect structure comprising a plurality of first insulating layers and a plurality of first metal redistribution layers located in the plurality of first insulating layers; a first under-bump metallization layer located on the first metal redistribution layer on the front side of the first interconnect structure; a second under bump metallization layer located on the first metal redistribution layer on the front side of the first interconnect structure; a first chip disposed on the first under-bump metallization layer; an underfill disposed between the first chip and the first interconnect structure; a heat sink mounted on the back of the first chip; a first solder ball disposed on the second under bump metallization layer; a first plastic sealing layer, which seals the area between the front surface of the first interconnection structure and the upper surface of the heat sink; a second solder ball disposed on a backside of the first interconnect structure; An upper package structure is flip-mounted on the lower package structure, and the upper package structure includes: a second interconnect structure having a first side and a second side opposite to the first side, the second interconnect structure comprising a plurality of second insulating layers and a plurality of second metal redistribution layers located in the plurality of second insulating layers; a second chip disposed on a second metal redistribution layer located on a second side of the second interconnect structure; a third under bump metallization layer electrically connected to the second metal redistribution layer located on the first surface of the second interconnect structure and welded to the heat sink and the first solder ball; a second plastic sealing layer, for plastic sealing the second chip; A third plastic encapsulation layer is used to encapsulate the first surface of the second interconnect structure between the first plastic encapsulation layer and the first surface of the second interconnection structure.

2. The stacked fan-out packaging structure according to claim 1, wherein: The first plastic packaging layer is exposed on the upper surface of the heat sink and the top of the first solder ball.

3. The stacked fan-out packaging structure according to claim 1, wherein: The second under bump metallization layer is located at a periphery of the first under bump metallization layer; and The first solder balls are located around the first chip.

4. The stacked fan-out packaging structure according to claim 1, wherein: The plurality of first metal redistribution layers are electrically connected to each other; and The plurality of second metal redistribution layers are electrically connected to each other.

5. A method for forming a stacked fan-out package structure, comprising: Forming a lower package wafer, including: Applying temporary bonding glue on the slide; forming a first interconnect structure on the temporary bonding adhesive, wherein the first interconnect structure comprises a plurality of first insulating layers and a plurality of first metal redistribution layers located in the plurality of first insulating layers; forming a first under bump metallization layer and a second under bump metallization layer on the first metal redistribution layer located on the front surface of the first interconnect structure, and forming a first solder layer on the first under bump metallization layer and the second under bump metallization layer; disposing a first solder ball on the second under bump metallization layer; Arranging a first chip on the first under-bump metallization layer, and filling an underfill between the first chip and the first interconnect structure; Mounting a heat sink on the back side of the first chip; and Plastic-sealing the area between the front surface of the first interconnect structure and the upper surface of the heat sink to form a first plastic-sealing layer; Forming the upper package wafer, including: forming a second interconnect structure on the front side of the plastic-encapsulated wafer, the plastic-encapsulated wafer including a second chip having second bumps on the front side and a second plastic-encapsulating layer encapsulating the second chip, the second interconnect structure having a first side and a second side opposite to the first side, and including a plurality of second insulating layers and a plurality of second metal redistribution layers located in the plurality of second insulating layers; and disposing a third under bump metallization layer on the first side of the second interconnect structure, and forming a second solder layer on the third under bump metallization layer; and The upper package wafer is flipped onto the lower package wafer to form a stacked fan-out package wafer.

6. The method for forming a stacked fan-out package structure according to claim 5, wherein: Also includes: Performing secondary wafer molding to mold the second interconnect structure to the first molding layer; Thinning the second plastic packaging layer to expose the back side of the second chip; Remove the slide through a debonding process; Arranging a second solder ball on the backside of the first interconnect structure of the lower package wafer; as well as Cut the stacked fan-out package wafer into individual stacked fan-out package structures.

7. The method for forming a stacked fan-out package structure according to claim 5, wherein: A first insulating layer is formed on the temporary bonding adhesive by coating, deposition, etc., and then the first insulating layer is etched to form a circuit pattern. Metal is electroplated on the circuit pattern to form a first metal redistribution layer. The operation is repeated multiple times to form a first interconnection structure.

8. The method for forming a stacked fan-out package structure according to claim 5, wherein: The second under bump metallization layer is larger than the first under bump metallization layer; and / or The second under bump metallization layer is located on the periphery of the first under bump metallization layer.

9. The method for forming a stacked fan-out package structure according to claim 5, wherein: The first plastic packaging layer is formed by plastic packaging from the front surface of the first interconnect structure to the upper surface of the heat sink through auxiliary thin film packaging technology, and the upper surface of the heat sink and the top of the first solder ball are exposed.

10. The method for forming a stacked fan-out package structure according to claim 5, wherein: The upper package wafer is flip-chip mounted on the lower package wafer by adopting wafer-to-wafer or chip-to-wafer assembly technology, wherein the third under-bump metallization layer is welded to the heat sink and the first solder ball.

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