Dynamic random access memory based on planar field transistors

Abstract

A fast Fourier transform (FFT)-based dynamic random access memory (DRAM) (FFT-DRAM) is disclosed. The FFT-DRAM includes an epitaxially grown source region including a source extension and an epitaxial source on and in contact with the source extension. The epitaxially grown source region is on a surface of a semiconductor substrate. The FFT-DRAM also includes a trench capacitor integrated structurally into the epitaxially grown source region. The trench capacitor has a first terminal formed by the epitaxially grown source region and a second terminal that is a conductive material filling one or more trenches of the trench capacitor. The second terminal is connected to a ground terminal or a fixed voltage terminal.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure generally relate to the structure and fabrication of Dynamic Random Access Memory (DRAM). More particularly, embodiments of the present disclosure relate to DRAM integrated with Flat-Field Transistor (FFT) technology. BACKGROUND

[0002] High performance technologies (such as FinFET technology, etc.) currently available for fabricating MOS VLSI of about 28 nm and below that provide good transistor performance are highly complex and difficult to fabricate at a reasonable cost. Further, these technologies are not inherently suitable for easy integration with Dynamic Random Access Memory (DRAM) cells embedded in an integrated circuit chip. Any such integration makes the processing of these integrated circuits (ICs) or System on a Chip (SOCs) very complex and expensive, thereby making such chips uncompetitive in consumer Internet of Things (IoT) applications. This problem leads to the use of separate DRAM chips instead of integrating memory cells into the IoT ICs / SOCs, thereby leading to the need to use chip-to-chip interconnects and advanced packaging. Multiple chips increase the size of IoT products, slow down their operation, and increase their power consumption. Sometimes, for applications that require a small amount of DRAM bytes, a complete DRAM chip has to be attached to the IC / SOC, thereby further increasing the cost of the product.

[0003] Rapidly growing IoT applications often require ICs / SOCs to embed some reasonable amount of easily accessible, low cost, fast memory to avoid violating the cost requirements of consumer applications.

[0004] Although the demand for embedded DRAM in IoT segments is growing at a very fast pace, it would be best if any proposed DRAM cell and technology is also available for standalone DRAM standard products, thereby making the DRAM cell and technology a more attractive cell and technology due to its wider use.

[0005] Figure 1A is a schematic diagram of a conventional DRAM cell 100A. It includes a capacitor 102A in series with a pass transistor 101A. The capacitor 102A has one terminal connected to ground 103A. The other terminal of the capacitor 102A is connected to a bit line 105 through the pass transistor 101A. The gate of the pass transistor 101A is connected to a word line 104A that controls the on / off state of the pass transistor 101A.

[0006] During a write to a DRAM, the bit line 105A voltage is raised to a voltage representing the data to be stored, for example, a positive voltage representing data = "1" or zero voltage representing data = "0". The pass voltage is applied to the gate of the pass transistor 101A via the word line 104A, thereby turning on the pass device 101A according to the data to either charge or discharge the capacitor 102A. When the pass transistor 101A is turned off, the charge on the capacitor is retained to represent the data.

[0007] During a read, the word line 104A is used to turn on the pass transistor and allow the capacitor 102A to be connected to the bit line. The charge on the capacitor is now shared with the capacitance of the bit line, which remains at a low voltage for data "0" or increases in voltage in the case of data "1" being written to the capacitor 102A. The charge sharing is proportional to the ratio between the capacitance of the storage capacitor 102A and the capacitance of the bit line 105A. Therefore, it is desirable to have a high value charge storage capacitor connected to a very low bit line capacitance, thereby allowing the voltage on the capacitor to be transferred to the bit line.

[0008] Other points to consider in the operation of a DRAM involving writing, storing and reading data in a capacitor using a pass transistor are:

[0009] 1. Use of a low leakage pass transistor to reduce the loss / gain of charge on the capacitor between write cycles to reduce the need for frequent refresh of the charge representing the stored data.

[0010] 2. Use of a low Vt pass transistor to improve the charge up and discharge voltages from the capacitor. (During capacitor charge up, the pass transistor behaves as a source-follower, limiting the final voltage to the gate voltage Vg minus the threshold voltage Vt.)

[0011] 3. Use of a high current pass device to speed up read and write operations.

[0012] All of the above requirements affect the write, read and hold characteristics of a DRAM, and the write and read requirements of a pass transistor conflict with the hold requirements of the same device. The ability of a chip to meet all of the requirements is severely hampered by any uncertainty in the threshold voltage across the array. Therefore, the use of a pass transistor with superior leakage characteristics and low statistical threshold variation σVt, particularly when it is integrated with a low leakage capacitor, will result in the integration of a superior DRAM.

[0013] What is needed is a pass transistor technology and a storage device technology with some or all of the above characteristics that can be manufactured at a reasonable cost as a standalone DRAM device and that can also be easily embedded in a logic or processing integrated circuit (IC). SUMMARY

[0014] According to an aspect of the present disclosure, there is provided a fast Fourier transform (FFT)-based dynamic random access memory (DRAM), an FFT-based DRAM (FFT-DRAM) including: an epitaxially grown source region including a source extension and an epitaxial source on and in contact with the source extension, the epitaxially grown source region on a surface of a semiconductor substrate; and a trench capacitor integrated structurally into the epitaxially grown source region, the trench capacitor having a first terminal formed by the epitaxially grown source region and a second terminal as a conductive material filling one or more trenches of the trench capacitor, the second terminal connected to a ground terminal or a fixed voltage terminal; the conductive material filling the trenches is separated from the source region by a dielectric separating the first terminal and the second terminal of the trench capacitor; the first terminal of the trench capacitor is connected to a bit line connected to a drain of the FFT-DRAM when the FFT-DRAM is turned on; the first terminal of the trench capacitor is isolated from the bit line connected to the drain of the FFT-DRAM when the FFT-DRAM is turned off.

[0015] According to another aspect of the present disclosure, there is provided an FFT-based DRAM (FFT-DRAM) device capable of being integrated into a silicon IC, the FFT-DRAM device including: a trench capacitor as a storage device, the trench capacitor having at least two terminals including a first terminal and a second terminal isolated from each other by a capacitor dielectric; an epitaxial source structurally connected to the first terminal of the trench capacitor, the trench capacitor being implemented by the epitaxial source such that the epitaxial source is structurally connected to form the first terminal of the trench capacitor, the second terminal of the trench capacitor being formed by a conductive layer within one or more trenches connected to a ground or a fixed voltage source via a metal interconnection; an epitaxial drain formed by epitaxial growth on a surface of a substrate and connected to a bit line; and a gate connected to a word line capable of turning on or turning off the FFT-DRAM device by applying a gate voltage.

[0016] According to another aspect of the disclosure, there is provided a Fast Fourier Transform (FFT)-based Dynamic Random Access Memory (DRAM) device (FFT-DRAM device) comprising: a drain extension and a source extension instantiated on a surface of a substrate using low temperature epitaxial deposition on either side of a conductive gate electrode, the drain extension and the source extension in contact with the substrate, and the drain extension and the source extension isolated from the conductive gate electrode by a first dielectric; a drain deposit on the drain extension using low temperature epitaxial deposition, the drain deposit in contact with the drain extension; and a source deposit on the source extension using low temperature epitaxial deposition, the source deposit in contact with the source extension; the source deposit and the drain deposit isolated from the conductive gate electrode by a second dielectric, wherein the second dielectric is thicker than the first dielectric; the source extension and the source deposit on the source extension form a source region of the FFT-DRAM device; the drain extension and the drain deposit on the drain extension form a drain region of the FFT-DRAM device; the source region has one or more charge storage capacitors, one terminal of the charge storage capacitor coupled to the source region to store charge in response to positive stored data; the charge storage capacitor has a terminal coupled to the source region, the charge storage capacitor comprising one or more trenches filled with a conductive material, the conductive material isolated from the source region by a third dielectric and connected to a ground terminal or a terminal held at a fixed voltage; the trench has the conductive material forming a first electrode, the third dielectric separating the conductive material from a source region epitaxial material of the source region forming a second electrode as a first terminal of the charge storage capacitor, the charge storage capacitor formed together by the conductive material, the third dielectric and the source region epitaxial material, the first terminal of the charge storage capacitor structurally connected to the source region; a channel of the FFT-DRAM device forms a path connecting the first terminal of the charge storage capacitor to a bit line connected to the drain deposit when the FFT-DRAM device is turned on by applying a turn-on voltage at the conductive gate electrode; the channel of the FFT-DRAM device is turned off when the FFT-DRAM device is turned off, isolating the first terminal of the capacitor from the bit line. BRIEF DESCRIPTION OF DRAWINGS

[0017] Embodiments of the disclosure are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings in which like reference numerals refer to similar elements. It should be noted that references made in this disclosure to "an" or "one" embodiment of the disclosure are not necessarily to the same embodiment, and that they mean at least one.

[0018] In the drawings:

[0019] Figure 1A is a schematic diagram 100A of a conventional DRAM with a pass transistor.

[0020] FIG. 1 B Figure IB is a schematic diagram 100B of a DRAM with an FFT as a pass transistor.

[0021] FIG. 2A Figure 2OA is an embodiment 200A of an FFT (N-channel) device structure with amorphous silicon gate conductor.

[0022] FIG. 2B Figure 2OB is an embodiment 200B of an FFT (N-channel) device structure with metal gate for improved performance.

[0023] FIG. 3A Figure 3OA is an embodiment 300A of an FFT-DRAM device with amorphous silicon gate.

[0024] FIG. 3B Figure 3OB is an embodiment 300B of an FFT-DRAM device with metal gate.

[0025] FIG. 3C Figure 3OC is an embodiment 300C of an FFT-DRAM device with capacitor extending into substrate.

[0026] FIG. 4 Table 1 is a table showing an example process flow for fabricating an FFT metal gate transistor.

[0027] FIG. 5 Table 2 is a table showing an example integrated process flow for an FFT-DRAM. FIG. 3B DETAILED DESCRIPTION

[0028] ​According to a first aspect, a fast Fourier transform (FFT)-based dynamic random access memory (DRAM) (FFT-DRAM) is disclosed. The FFT-DRAM includes an epitaxially grown source region including a source extension and an epitaxial source on and in contact with the source extension. The epitaxially grown source region is on a surface of a semiconductor substrate, but in some embodiments does not penetrate the surface of the semiconductor substrate. The FFT-DRAM also includes a trench capacitor integrated structurally into the epitaxially grown source region. The word "trench" as used herein can extend to any of several different structures that penetrate the epitaxial source structure and / or the substrate. Such structures can have a circular cross-section, a rectangular cross-section, or other shaped or formed cross-sections depending on the available lithography and etching techniques. Furthermore, such structures can have substantially straight sidewalls perpendicular to the surface, or they can be tapered, or in the case of a circular cross-section, can be fully or partially conical. The trench capacitor has a first terminal formed by the epitaxially grown source region and a second terminal that is a conductive material filling one or more trenches of the trench capacitor. The second terminal is connected to a ground terminal or a fixed voltage terminal. The conductive material filling the trench is separated from the source region by a dielectric that separates the first and second terminals of the trench capacitor. When the FFT-DRAM is turned on, the first terminal of the trench capacitor is connected to a bit line connected to a drain of the FFT-DRAM. When the FFT-DRAM is turned off, the first terminal of the trench capacitor is isolated from the bit line connected to the drain of the FFT-DRAM.

[0029] According to a second aspect, an FFT-DRAM capable of being integrated into a silicon integrated circuit (IC) is disclosed. The FFT-DRAM device includes a trench capacitor as a storage device. The trench capacitor has at least two terminals including a first terminal and a second terminal isolated from each other by a capacitor dielectric. The FFT-DRAM device also includes an epitaxial source structurally connected to the first terminal of the trench capacitor. The trench capacitor is implemented by the epitaxial source such that the epitaxial source is structurally connected to form the first terminal of the trench capacitor. The second terminal of the trench capacitor is formed by a conductive layer within one or more trenches connected to a ground or fixed voltage source via a metal interconnect. The FFT-DRAM device also includes an epitaxial drain formed by epitaxial growth on a surface of a substrate and connected to a bit line. The FFT-DRAM device also includes a gate connected to a word line capable of turning the FFT-DRAM device on or off by applying a gate voltage.

[0030] According to a third aspect, a FFT-DRAM device is disclosed. The FFT-DRAM device includes a drain extension and a source extension instantiated on a surface of a substrate using low temperature epitaxial deposition on either side of a conductive gate electrode. The drain extension and the source extension are in contact with the substrate and the drain extension and the source extension are isolated from the conductive gate electrode by a first dielectric. The FFT-DRAM device further includes a drain deposit on the drain extension using low temperature epitaxial deposition. The drain deposit is in contact with the drain extension. The FFT-DRAM device further includes a source deposit on the source extension using low temperature epitaxial deposition. The source deposit is in contact with the source extension. The source deposit and the drain deposit are isolated from the conductive gate electrode by a second dielectric, where the second dielectric is thicker than the first dielectric. The source extension and the source deposit on the source extension form a source region of the FFT-DRAM device. The drain extension and the drain deposit on the drain extension form a drain region of the FFT-DRAM device. The source region has one or more than one trench filled with a conductive material that is isolated from the source region by a third dielectric and connected to a ground terminal. The trench has the conductive material forming a first electrode. The third dielectric separates the conductive material from a source region epitaxial material of the source region forming a second electrode as a first terminal of a charge storage capacitor. The charge storage capacitor is formed together by the conductive material, the third dielectric, and the source region epitaxial material. The first terminal of the charge storage capacitor is structurally connected to the source region. When the FFT-DRAM device is turned on by applying a turn-on voltage at the conductive gate electrode, a channel of the FFT-DRAM device forms a path that connects the first terminal of the charge storage capacitor to a bit line connected to the drain deposit. When the FFT-DRAM device is turned off, the channel of the FFT-DRAM device is turned off, isolating the first terminal of the capacitor from the bit line.

[0031] A DRAM is presented that combines flat field transistor (FFT) device technology and uses features of FFT. The flat field technology can be implemented on bulk silicon or silicon-on-insulator substrates. It eliminates the effect of random dopant distribution on threshold voltage (Vt) and reduces short channel effects in MOS transistors. As a result, FFT transistors operate at lower supply voltages while maintaining the required noise margin. Tighter control of Vt of MOS transistors can be used to improve drive current and reduce leakage. A charge storage capacitor is integrated on the silicon surface by using etched features (such as trenches, holes, or fins) at the source of the FFT to increase the storage capacitance.

[0032] The DRAM fabrication process steps used in today's industry are not easily integrated with the FFT process steps. Here, the DRAM processing has only a few additional steps to integrate with the FFT process in the disclosed FFT-DRAM.

[0033] A technique, device structure, and method to implement an FFT-DRAM cell by integrating a charge storage capacitor with a low threshold variance planar field transistor (FFT) device is presented. FFTs are described in U.S. Application No. 15 / 226,118, filed August 2, 2016, with a priority date of August 3, 2015, published as U.S. Publication 20170040449, entitled "Reduced Local Threshold Voltage Variation MOSFET Using Multiple Layers of Epi for Improved Device Operation," the disclosure of which is incorporated by reference herein in its entirety. The disclosed FFT-DRAM cell is believed to be useful in a stand-alone industry standard DRAM chip, where the peripheral circuitry, read / write circuitry, and other support logic circuitry within the chip are implemented using FFT transistor devices. Alternatively, these FFT-DRAM cells with support circuitry can be embedded on a chip along with other logic or processing circuitry required for a special purpose IC or SOC for IoT or similar other applications. Such an implementation can use the FFT devices for other built-in circuitry to fully integrate and take advantage of the benefits provided by the combination of FFT-DRAM with FFT.

[0034] To create an elegant FFT-DRAM structure, a charge storage capacitor is integrated with a pass transistor, in this case an FFT device. For convenience, in weighing this specification, this pass transistor will be referred to as an FFT device. Also, as mentioned previously, it is important to be able to integrate "DRAM functionality" into an FFT-based CMOS process flow for IoT without making the processing too complex or expensive. Therefore, the goal of the FFT-DRAM technology development is to provide the ability to integrate FFT and FFT-DRAM in a single semiconductor chip and allow for the economical fabrication of large FFT-DRAM arrays containing FFT-based sensing and read / write logic. Furthermore, in addition to the ability to embed FFT-DRAM devices in special purpose ICs and SOCs, we also promote a commercially and technically viable industry standard FFT-DRAM device.

[0035] The main advantages of having any integrated DRAM in an IC / SOC are access speed, reduced operating power, improved reliability, ability to optimize its implementation to the required density and array architecture for the desired application, and lower manufacturing cost for the end product.

[0036] It has been proposed to implement CMOS planar field transistor technology (FFT) for implementing transistors with gate dimensions in the range of 28 nm on bulk silicon, bulk silicon with an epitaxial surface layer, or silicon-on-insulator (SOI) substrates. This low-cost CMOS technology (with reduced short channel effects, low leakage, and very low threshold variation sigma Vt based on random dopant distribution) is ideal for the fabrication of high performance CMOS transistors. High performance and low manufacturing cost make it one of the best candidates for IoT applications.

[0037] In IoT applications, it is advantageous to integrate memory cells, especially dynamic random access memory cells (DRAM) for embedded applications, with FFT. These embedded DRAMs are ideal for the storage of collected data and processed results.

[0038] The proposed FFT-DRAM is a capacitor with a low threshold variance transfer transistor, as shown in FIG. 1 B Fig. 3A or 3B or 3C, the FFT-DRAM can be enabled using FFT as the transfer transistor with a single-trench or multi-trench capacitor, either within one epitaxial S / D region or via one epitaxial S / D region. As discussed later, this FFT-DRAM can be easily integrated with the FFT device. Although not shown in FIG. 3A , 3B Fig. 3A or 3B or 3C, a stacked charge storage capacitor can also be used instead of the trench charge storage capacitor in the FFT-DRAM structure.

[0039] FIG. 1 B Fig. 100B shows a circuit diagram of the FFT-DRAM using FFT as the transfer transistor. FIG. 2A Figs. 2A and 2B show embodiments 200A and 200B of the FFT structure, and FIG. 3A , 3B Figs. 3A, 3B, and 3C show embodiments 300A, 300B, and 300C of the integrated FFT-DRAM structure, each having a charge storage capacitor integrated into the processing and structure of the FFT for fabricating the FFT-DRAM cell of the present application. This integration enables FFT-based integrated circuit (IC) system-on-a-chip (SOC) implementation to embed the FFT-DRAM into the chip with minimal additional steps. As discussed, a typical DRAM is a charge storage device, which includes the use ofFIG. 1 B The FFT shown is connected in series with a capacitor storage device 102B via a controllable transfer gate 101B. Although this discussion refers to the storage capacitor 102B as connected to ground, line 103B can be connected to any fixed voltage that may be needed to optimize DRAM performance or reliability. Digital input data can be stored on capacitor 102B by applying a voltage to word line 104B to turn on the transfer gate 101B and applying a digital or data input to bit line 105B. It can be read back by applying a transfer gate 101B turn-on voltage to word line 104B, thereby connecting the capacitor to bit line 105B. This allows the charge stored on capacitor 102B to be shared by bit line 104B. A sensing circuit (not shown) coupled to bit line 105B is used to sense the state of the storage bit indicated by the charge / voltage on bit line 105B due to shared charge.

[0040] FIG. 2A and 2B The flat-field transistor shown and FIG. 3A , 3B The FFT-DRAM device shown in 3C includes a semiconductor substrate 201, and depending on whether a P-channel FFT device or an N-channel FFT device is being used, the semiconductor substrate 201 can be N- or P-doped as a doped well. The semiconductor substrate can be a bulk substrate, an epitaxial layer on a bulk substrate, or a silicon-on-insulator (SOI) substrate. Example figure ( FIG. 2A and 2B Both figures show N-channel FFT structures 200A and 200B constructed on P-wells in a bulk substrate. As shown, the substrate has an active region isolated from the surrounding region by a dielectric isolation portion 202A. The shape of the dielectric isolation portion shown is merely an example. The isolation processing requirements are based on the substrate used, and the resulting isolated structure is well known and understood by those skilled in the art of semiconductor manufacturing. Ideally, the isolation process selected and used facilitates tight packaging of the device on the selected semiconductor substrate. The isolated active region includes surface 203 and the P-doped well in the bulk semiconductor substrate 201. For the example N-channel structure shown, the active substrate is the P-well 201. The FFT device structure is constructed on surface 203 of the active region of the substrate. Below surface 203 is the P-well in the semiconductor substrate 201. The FFT device has three distinct regions on surface 203 between the isolation portions 202A. These three regions are the gate region, the source region, and the drain region. The gate region is defined by a gate dielectric 204 on surface 203 of the active region. The gate region, having a gate dielectric 204, separates the source and drain regions from each other; that is, the source region is on one side of the gate region, and the drain region is on the opposite side. The FFT gate structure includes a conductive gate electrode 205. FIG. 2AIn the illustrated embodiment, the gate electrode 205 is shown as a single conductive gate material 205B, while in FIG. 2B the metal gate implementation of the FFT in the embodiment illustrated in FIG. 1. The gate electrode 205 in the metal gate implementation of the FFT in the embodiment illustrated in FIG. 1 includes a conductive gate material 205B on top of a metal gate material 205A (which can be optional in embodiments). The metal gate material can be selected to have a work function that creates a desired threshold voltage for the transistor. The gate electrode in either implementation overlies a gate dielectric 204, enabling a conductive channel to be formed under the gate dielectric 204 of the gate structure by applying an appropriate voltage to the conductive gate electrode 205. FIG. 2A and FIG. 2B The conductive channel is formed under the gate dielectric 204 of the gate structure by applying an appropriate voltage to the conductive gate electrode 205 in the FFT implementation illustrated in FIG. 1. As is well understood in the industry, the threshold formed by the channel established for the FFT and the magnitude of the voltage applied to the gate electrode controls the conductance of the channel. The gate voltage is applied to the conductive gate electrode 205 on the gate dielectric 204 via a contact plug 214 through the interlevel dielectric 212. The contact plug 214 can be connected to the gate electrode via a silicide contact region 211B (which can be optional in embodiments), as illustrated in FIG. 1. As is well understood in the industry, the connection to any particular metallization layer illustrated is merely an example and should not be considered limiting. FIG. 2A and FIG. 2B The gate electrode is shown in this embodiment as being connected to a first metallization 214B on the first passivation dielectric 212 through the plug 214 and the silicide contact 211B. As is well understood in the industry, the connection to any particular metallization layer illustrated is merely an example and should not be considered limiting.

[0041] The FFT source is formed on the surface of the source region. The FFT source includes an epitaxially deposited source extension 207A on the silicon surface of the source region; the source extension 207A is insulated from the gate electrode 205 by a first dielectric 206A. A second source epitaxial deposit 208A is deposited on the source extension 207A; the source epitaxial deposit 208A is isolated from the gate electrode 205 by a second dielectric 206B that is thicker than the first dielectric 206A. Although shown as a single dielectric layer, the second dielectric 206B can include one or more additional dielectric layers deposited on the first dielectric 206A. The epitaxial source extension 207A and the epitaxial source 208A together form the source of the FFT. The conductive connection to the source is through a via on the source 211C that includes a contact plug 215 and a silicide layer (which can be optional in embodiments). The contact plug can extend through one or more insulating dielectric layers 212 and 218 based on circuit considerations that define the connection of the source to a first interconnect metallization, a second interconnect metallization, or other interconnect metallization, as is well understood in the industry. In FIG. 2A and FIG. 2BIn this case, the source is connected to the first interconnect metallization 215B. As indicated previously, a contact plug connects the metallization 215B to the silicide region 211C of the epitaxial source layer 208A (which can be optional in embodiments); this provides a source contact for the FFT.

[0042] Similarly, an epitaxial drain extension 207B is formed on the surface 203 of the substrate on the opposite side of the gate dielectric 204, but is isolated from the conductive gate electrode 205 by the first protective dielectric 206A, and an epitaxial drain 208B is deposited on the drain extension 207B, insulated from the gate electrode 205 by the dielectric 206B. The epitaxial layers 207B and 208B together form a drain for the FFT. As FIG. 2A and FIG. 2B The drain is shown in contact with a conductive contact plug 213 through a via, which is connected to a conductive metal silicide layer 211A (which can be optional in embodiments) on the conductive epitaxial drain layer 208B. The contact plug within the via can extend through one or more insulating dielectric layers 212 and 218 based on circuit considerations that define the source-to-first interconnect metallization, second interconnect metallization, or other interconnect metallization connections, as well understood in the industry. In FIG. 2A and FIG. 2B In this case, the drain of the FFT is shown connected to the second interconnect metallization 213B via a conductive plug and silicide.

[0043] The silicide contacts 211A, 211B, and 211C are used to reduce the contact resistance of the drain electrode 208B, gate electrode 205, and source electrode 208A, respectively.

[0044] The metal 1 or first interconnect metallization layers 214B and 215B extending on the dielectric layer 212 are shown on vias 214 and 215 for interconnection of the source and gate electrodes, while a stacked via 213 through the dielectric 212 and first intermetallic dielectric 218 is shown connecting the drain of the FFT to FIG. 3A and FIG. 3B the second interconnect metallization 213B in FIGS. 13B and 13C. The use of silicide contacts, interconnect metallization, and use of stacked vias are merely exemplary representations and are not intended to create any limitations on the underlying structure of the FFT.

[0045] In various embodiments, the FFT device has several advantages over prior art planar transistor structures for gate sizes of 28nm or below, which will improve the characteristics of an integrated FFT-DRAM using the FFT transmission device. These advantages stem primarily from the structure and process of the FFT device, in addition to being able to be integrated in an IC or SOC at lower FFT implementation cost. The FFT device is structurally built on top of the substrate surface 203. The source extension 207A and drain extension 207B, which form the bottom surfaces of the doped source and doped drain of the FFT, are epitaxially formed on the substrate surface 203 of the FFT device, and they are substantially co-planar with the gate oxide 204, providing a planar, nearly uniform distribution or flat electric field across the gate and channel. Furthermore, the source extension 207A, drain extension 207B, source 208A, and drain 208B of the FFT are all built on the surface of the silicon using low temperature epitaxial growth. This process avoids implants and diffusion, which have their high temperature requirements. The low temperature processing limits the diffusion of dopants into the substrate, particularly near the gate. This in turn reduces the effects of random dopant distribution and associated Vt variation, allowing the FFT device to be designed for low power supply voltage values (ranging from 0.3 volts to 2.0 volts for 28nm devices). The lack of dopants diffusing into the silicon surface 203 also reduces the effects of short channel effects; this allows for improved gate control of the leakage current in the off state and the high device current in the on state. Thus, the advantages of using the FFT as a transmission device are:

[0046] 1. Low Vt variation.

[0047] 2. Improved control of the channel by the gate voltage.

[0048] 3. Low power supply voltage operation.

[0049] 4. Reduced short channel effects.

[0050] 5. Low leakage in the off state.

[0051] 6. High on channel current.

[0052] These characteristics of the FFT device play an important role in the functionality of the integrated FFT-DRAM. In FIG. 3C and FIG. 3A show structural embodiments of the FFT-DRAM with single type conductive gate electrode implementation 300A and metal gate electrode implementation 300B, respectively. FIG. 3B An enhanced integrated storage capacitance implementation 300C is shown.

[0053] Due to FIG. 3B and FIG. 3AThe FFT-DRAM embodiments described in the foregoing are structurally similar, so for brevity, the FFT-DRAM 300B will be described using the embodiment of the FFT-DRAM with metal gate FFT transfer device shown in FIG. 3A The FFT-DRAM 300B will be described using the embodiment of the FFT-DRAM with metal gate FFT transfer device shown in

[0054] Note that the combination of doped epitaxial source 207A and 208A provides the structure for housing the capacitor storage device (e.g., device 102 in FIG. 1) required to implement the DRAM cell. The capacitor is shown in embodiment 300B as a trench capacitor. The capacitor is formed by one or more than one of a trench or hole filled with a conductive material 310, where the conductive material 310 is isolated from the surrounding source epitaxial material 207A and 208A by a dielectric layer 309. In embodiments, the dielectric 309 has a high dielectric constant (high-K) to provide a high capacitance value per unit area of the capacitor for charge storage. FIG. 3B and 3B Both show multiple etched trenches or alternative holes in the source epitaxial layers 207A, 208A of the FFT-DRAM, each lined with a dielectric 309 and filled with a conductive material 310. The choice of using a trench or a hole depends on the capabilities for trench or hole formation in the fabrication, the trench or hole dielectric isolation and refill capabilities, and also on the need to achieve a maximum capacitance value within the limited space available in the source of the FFT-DRAM device. Furthermore, while FIG. 3A and FIG. 3B Show the capacitor electrode 310 extending into the source extension region 207A, but this structure can penetrate only the source region 208A; this limitation can be imposed by fabrication considerations. The filled trench or hole 310 (hereafter, both are denoted by the term trench) is dielectrically isolated from the surrounding epitaxial regions 207A and 208A by the sidewall and bottom dielectric 309, as shown in FIG. 3A and FIG. 3B The epitaxial regions 207A and 208A form the epitaxial source of the FFT-DRAM 300A or 300B on a silicon substrate, as shown in FIG. 3A and FIG. 3BIn the illustrated embodiment, the conductive material 310 within the trench is connected to a first interconnect metallization layer 215B, shown in FIG. 1A as interconnect 103, via a silicide, TiN, or other etch stop layer 211D and a metal contact plug 215A. As is well understood in the industry, the conductive material 310 filling the trench can include polysilicon, amorphous silicon, or any other conductive metal or metal compound suitable for low temperature trench filling. The FFT transfer transistor 101B of the FFT-DRAM has a gate electrode including a gate conductor 205, which can include a conductive gate material 205B over a gate material 205A of metal over a gate dielectric 204 on the substrate surface 203. Upon application of an appropriate gate voltage via the gate conductor 205, the gate electrode structure is capable of forming a conductive channel in the silicon bottom layer surface 203 under the gate dielectric 204. The gate electrode can be formed by a "gate first" process as indicated in this application or by a "gate last" process as is also well understood in the industry. The gate conductive structure 205, whether amorphous gate or metal gate, has an epitaxial source extension 207A and an epitaxial drain extension 207B on the substrate surface on either side of it. The gate conductor 205 is isolated from the source extension 207A and the drain extension 208B by a dielectric insulator 206A surrounding the gate conductor 205. An epitaxial source layer 208A is deposited on top of the source extension 207A; these two layers together form the source of the FFT-DRAM. An epitaxial drain layer 208B is deposited on top of the drain extension 207B; these two layers together form the drain of the FFT-DRAM. FIG. 1 B or FIG. 1 B The drain of the illustrated FFT-DRAM.

[0055] Compare the schematic diagram in FIG. 3A and FIG. 3B with FIG. 3A In FIG. 3B one can see that the three elements of the FFT_DRAM (one terminal of the capacitor 102B connected to ground 103B, the gate of the FFT 101B connected to the word line 104B, and the drain of the FFT 101B connected to the bit line 105B) are all typically connected by interconnect metallization. Note that the ground terminal of the capacitor 102B is connected to the ground line 103B, while the other terminal of the capacitor forms FIG. 3A and FIG. 2A the integrated portion of the source of the FFT transfer transistor in the integrated FFT-DRAM of FIG. 3A and FIG. 2AIn this process, the interconnect metallization connection is made of conductive material 215A, which is deposited as a conductive plug in the contact or via etched through the interlayer dielectric 212B; this connects layer 211D and capacitor electrode 310 to metal layer 215B, which is connected to ground or to a favorable fixed voltage. FIG. 3A As shown in Figure 3B, the gate of the FFT transmission device is connected to word line 104 or 214B via conductive material 214 deposited in vias etched in the two interlayer dielectrics 212A and 212B; this connects the silicide layer 211B and the gate 205 to metal 214B. Finally, the drain of the FFT is connected to bit line 105B of Figure 1 using conductor 213 deposited in vias passing through the first interlayer dielectric 212A, the second interlayer dielectric 212B, and the intermetallic dielectric 218; this connects the silicide 211A and the drain 208B to bit line metal 213B. Standard industry practice uses chemical vapor deposition tungsten as the conductive via filler and copper as the interconnect metallization, which should not be considered a limitation on the use of other via-filling and interconnect metallization schemes in practice.

[0056] FIG. 3A and 2B FFT transistor structure and FIG. 3A and 3B The FFT-DRAM structure is built on the surface 203 of a silicon substrate. This means that the structure can be used on various substrate types. FIG. 3B , 2B Examples 3A and 3B illustrate block substrates with trench isolation. Typically, shallow trench isolation is used in these embodiments. Depending on cost and performance considerations, FIG. 4 and 3B The FFT-DRAM structure described herein is applicable to a variety of substrates. For example, using an epitaxial layer on a silicon surface or using an SOI wafer with an epitaxial surface layer can provide advantages in establishing a defect-free epitaxial layer for transistor channels; this will further reduce leakage across the FFT source and drain.

[0057] It should be noted that by using an epitaxial material with low defect density as the surface layer, in which the channels are formed on the substrate wafer or SOI wafer, this results in lower leakage than when using a non-epitaxy channel region on the substrate. Reduced leakage will increase the time required between data refresh cycles in an FFT-DRAM cell.

[0058] FIG. 2B and 3Brepresents an embodiment of an FFT-DRAM, but other embodiments can involve deviations from these drawings. For example, the source regions 207A, 208A and drain regions 207B, 208B have approximately the same extent as the gate region 204. To establish sufficient storage capacitance 102, the source regions 207A / 208A can be expanded. As is common in DRAM designs, the word lines 104 are perpendicular to the bit lines 105. In FIG. 4 and FIG. 3B In these same figures, the bit lines are represented by 213B, and they extend parallel to the plane of the drawing. In these same figures, the word lines are indicated by 214B, and they are perpendicular to the plane of the drawing.

[0059] To maximize the bits per unit area, certain features of the FFT-DRAM can be shared. For example, the drains 207B and 208B of the bits in adjacent rows and their common contacts 213 and metal 213B can be shared. Similarly, in the case where the memory layout is positioned in such a way that the drains 207B, 208B of the bits in adjacent rows are shared and the sources 207A, 208A are close to each other, the “ground” line 215B can be shared between adjacent bits. The layout is limited by the lithography and patterning at any particular technology node. Thus, the sharing of one or more terminals of the FFT-DRAM should not be considered as a reason to distinguish the disclosed integrated FFT-DRAM device structure.

[0060] The FFT-DRAM implementation is the integration of a storage capacitor process addition to the FFT process flow. By integrating the storage capacitor with the FFT transfer transistor, the FFT-DRAM has the following technical advantages:

[0061] 1. Since the trench capacitor is formed by a highly doped epitaxial silicon, it provides a very high per unit capacitance value compared to typical trench capacitors formed in the low doped wells of the prior art.

[0062] 2. The low threshold of the FFT transfer device allows the use of lower operating voltages to store and read data in the FFT-DRAM.

[0063] 3. The low leakage across the FFT transfer transistor and the low recombination in the epitaxial layer around the capacitive storage device enable the charge in the storage capacitor to last longer, extending the time to refresh the FFT-DRAM.

[0064] 4. The high charge / discharge current enables high speed FFT-DRAM applications.

[0065] 5. In a standalone standard FFT-DRAM, the FFT-DRAM ease of integration with peripheral logic and read / write logic using FFT results in low voltage, high speed and low cost FFT-DRAM memory.

[0066] 6. The low voltage operation capability of the FFT-DRAM device reduces the power dissipation of the implemented FFT-DRAM memory array.

[0067] 7. The lower leakage of the FFT transfer device resulting in longer time between FFT-DRAM refreshes further reduces the power dissipation of the standalone and embedded FFT-DRAM array.

[0068] 8. The FFT-DRAM process flow ease of integration with logic circuit using FFT reduces the integration implementation cost of the FFT-DRAM in the designed IoT circuit.

[0069] FIG. 5 Table 1 shows the process to fabricate a "gate-first" FFT transistor structure with a metal gate as shown in FIG. 5 Table 1 shows the process to fabricate a "gate-first" FFT transistor structure with a metal gate as shown in FIG. 3B A basis for comparing the process flow of the FFT to that of the FFT-DRAM structure of FIG. 2B is provided. The process flow of the FFT-DRAM is shown in Table 2 of FIG. 3B Both tables refer to a "gate-first" class of process with a metal gate implementation, and the following discussion will refer to the process flow of the FFT-DRAM shown in Table 2 of FIG. 3C Both tables refer to a "gate-first" class of process with a metal gate implementation, and the following discussion will refer to the process flow of the FFT-DRAM shown in Table 2 of

[0070] As discussed above, the FFT-DRAM process can be performed on a variety of substrates ranging from bulk substrate to fully depleted silicon-on-insulator (FDSOI) substrate. The shallow trench isolation as referenced in Sequence 2 is a standard industry practice. Also within standard industry practice, the well region in Sequence 2 will be designed such that its potential is either called ground or another relatively negative voltage for NMOS, or called local power supply voltage or another relatively positive voltage for PMOS. FIG. 3C The depicted FFT-DRAM cell uses NMOS FFT devices as access transistors; this means that the p-type well will be connected to ground or to a potential that is negative with respect to the power supply voltage. While it is typical to use NMOS FFTs as access devices, aspects of the present disclosure should not be considered as limited to FFT-DRAMs using NMOS FFTs, but they are also applicable to FFT-DRAM cells using PMOS FFTs as their access devices.

[0071] The next process step at sequence 3 creates the gate dielectric 204, typically to achieve a favorable combination of capacitance and breakdown voltage, by thermal oxidation of the underlying substrate and / or by deposition of a replacement dielectric. Replacement dielectrics include various high-K dielectric materials and composites, with hafnium silicon nitride oxide being an example. The gate dielectric thickness can be in the range of 1 nm to 5 nm, for example. In sequence 4, a metal layer of the metal gate is deposited on the gate dielectric. While this can be optional, the work function of the metal element or compound can be used to define and optimize the threshold voltage of the FFT device, particularly when the gate length is made small and the power supply voltage needs to be reduced. This is a common practice for all configurations of advanced CMOS transistors, not just FFTs. As part of the transistor design, the p-well / channel doping, the gate dielectric properties, and the gate metal work function work together to define the threshold voltage of the transistor.

[0072] In sequence 5, the gate structure is completed with deposition of an amorphous semiconductor or conductive material, typically amorphous silicon, which is doped to provide the conductivity needed to deliver the drive voltage applied to the gate conductor 205 to the gate for forming the channel and regulating its conductance. Etching includes the stack of gate dielectric 204, gate metal 205A, and gate amorphous conductor 205B to define the spacing between the transistor source and drain. In embodiments, the etched gate dielectric 204 and gate conductor 205 form ​ and ​ the gate structure of the FFT and FFT-DRAM shown in FIGS. 1-2.

[0073] After the gate structure has been defined, the sidewalls of the gate are insulated at sequence 6 with a dielectric 206A of similar thickness to the gate dielectric, e.g., 1 to 7 nm, and capable of withstanding the highest voltage applied to the transistor. Since the sidewall dielectric deposition is typically conformal, the FFT fabrication requires selective removal of the dielectric from the substrate per sequence 7. This is typically achieved using anisotropic reactive ion etching.

[0074] The first step in source / drain formation is to selectively grow a doped epitaxial layer 207A / 207B on the bare substrate source / drain regions. This epitaxial layer forms the source and drain extensions. The selectively grown epitaxial layer is N-type doped for NMOS devices and P-type doped for PMOS devices. A typical doping density can be in the range of 5 x 1018to 5 x 1020ions / cm2, for example. 18 3 20 3 ​​​within the range of 3 nm to 20 nm. This thinness of the source / drain extension layers helps manage the gate-to-source and gate-to-drain parasitic capacitances of the FFT device.

[0075] At sequence 9, a dielectric (typically Si3N4) is conformally deposited to a thickness within the approximate range of 10 nm to 100 nm, and in sequence 10, the dielectric is anisotropically etched to clear the deposition from the top of the epitaxial extensions 207A and 207B, while leaving a thick sidewall dielectric 206B. In sequence 11, the transistor structure is completed by low-temperature selective epitaxial growth of thicker, more highly doped layers 208A and 208B. The source of the transistor structure is formed by the combination of the highly doped source epitaxial layer 208A on the source extension 207A layer, and the drain of the transistor structure is formed by the highly doped drain epitaxial layer 208B on the drain extension 207B layer. These layers are more heavily doped than the extension layers 207A and 207B; for example, typical values can be in the range of 1 x 1018doped ions / cm3to 7 x 1018doped ions / cm3, and the selective epitaxial growth is performed at low temperature (e.g., less than 650 °C), which does not cause any substantial thermal diffusion of the dopants into the substrate surface 203. The thickness of this layer 208A / 208B is defined in the design of the FFT-DRAM capacitor. 19 3 21 3 / cm3, and the selective epitaxial growth is performed at low temperature (e.g., less than 650 °C), which does not cause any substantial thermal diffusion of the dopants into the substrate surface 203. The thickness of this layer 208A / 208B is defined in the design of the FFT-DRAM capacitor.

[0076] At this point, the DRAM process sequence diverges from the general FFT transistor processing. The steps in sequence 12 provide for the deposition of a thin dielectric layer as the first portion 212A of the interlayer dielectric (ILD portion 1). This layer is deposited, and then planarized by chemical mechanical polishing, or CMP, to form the base for the hard mask. The hard mask is typically deposited using a metal layer on the dielectric 212A, and at sequence 13, the hard mask is used to etch controlled trenches or cylindrical pits in the source of the FFT-DRAM (the layers 208A and 207A forming the source). These trenches typically form the basic structure of the charge storage device of the FFT-DRAM. Other surface area increasing structures can be considered, such as “fins or pillars” and the like, in order to form the charge storage device / capacitor of the FFT-DRAM instead of trenches. The intent is to embed a (e.g., 5 fF to 25 fF) capacitor within, below, or above the epitaxial source of the FFT-DRAM.

[0077] ​​​The next step in the formation of the capacitor is sequence 14, deposition of a dielectric layer 309 within the area enhancement structure, trench or pit in the source of the FFT-DRAM. The composition and thickness of this dielectric 309 is a key determinant of the capacitance value (which should be high) and its leakage (which should be low). As an example, the thickness of this dielectric 309 is typically in the range between 1 nm and 7 nm. At sequence 15, the structure of the charge storage capacitor is completed in a way that deposits a conductive material 310 into the dielectric lined hole or trench as the second terminal of the capacitor. This conductive material is typically doped amorphous silicon, but other conductive materials such as tungsten can be used. These conductive materials must be able to conformally fill the hole, trench or other capacitance enhancement geometry. At sequence 16, the excess material filling the trench over the ILD portion 1 212A is removed using CMP or masking and etch back. At sequence 17, the etch stop metal layer 211 D consisting of a masking and residual amorphous silicon or an alternative deposited and masked titanium nitride (TiN) layer is used to protect the filled trench 310 and the inter-trench dielectric insulation 309 of the filled trench. A second dielectric deposition 212B (ILD portion 2) is performed on the ILD portion 1212A to form the composite ILD 212. At sequence 18, CMP is used to planarize the last ILD 212B to complete the ILD process.

[0078] The process element sequences 12 through 18 are unique to the FFT DRAM process. The process starting at sequence 19 is common to both the FFT logic transistors and the FFT-DRAM. As described, the composite interlayer dielectric including 212A and 212B is constructed by depositing a second dielectric layer 212B on the first dielectric hard mask base layer 212A.

[0079] At sequence 19, contacts are formed. The contact process includes, for example, lithography and etching of the dielectric. The contact etch process is selected to have high selectivity to silicon as well as the protection layers on the trench capacitor, where the protection layers act as etch stops for the silicon of the gate electrode, the drain of the FFT-DRAM and on the filled trench protection layers. This can be followed by optionally depositing or forming silicide contacts within the etched contacts. This can be done by depositing and sintering a silicide material or by using silicon that reacts with Ti, Ni or Cr to form self-aligned silicide layers 211 A, 211 B and 211 D, which enhance the contact conductance. After silicide formation, the contacts are filled with CVD metal (typically tungsten) and CMP is performed to clear the glass surface. This sequence results in contact plugs 213, 214 and 215A that are connected to the drain, gate and capacitor terminal of the FFT-DRAM, respectively.

[0080] Once the contact has been formed, the next step is metallization. At this point, there are two different paths: patterned metal or damascene metal. In either case, the FFT-DRAM interconnect requires two different interconnect metal layers. In the representative diagram, the first metal 214B supports word line access to the FFT pass transistor, and the first metal 215B supports the ground or fixed voltage connection to the storage capacitor. The second metal 213B supports bit line access to the memory cell. The intermetal dielectric 218 separates the first metal layers 214B and 215B from the second metal layer 213B. Bit lines are typically perpendicular to word lines. It is assumed that all metallization and related dielectric steps are done according to standard industry practice. Alternative interconnect sequences can be used without violating the basic elements of this DRAM cell design.

[0081] As shown, the FFT-DRAM can be implemented by adding a few specialized steps to the underlying FFT process flow in Table 1. In Table 2, the additional steps are shown in bold. The steps shown are merely examples and can vary depending on the processing resources and capabilities of the fabrication plant. The additional steps are all standard steps for which the capability and process knowledge exists, even if not all of the semiconductor fabrication plants running this advanced technology node at 30 nm or below have it.

[0082] In addition, Table 1 and Table 2 are based on the use of a "gate-first" transistor process. Similar advantages can apply to a gate-last process.

[0083] As well understood in the industry, implementing and integrating the FFT-DRAM into an FFT-based SOC for IoT applications will make the technology cost effective and applicable in the art. Although the FFT-DRAM structure is shown with a trench or hole within the epitaxial source region, the trench can also extend into the substrate to increase the capacitance of the storage capacitor with a sidewall doping to match the source doping type. The formation of such a conductive doped layer, which connects to the source, surrounds the outside of the capacitor dielectric layer and reaches into the well in the substrate, can typically be achieved using low temperature gas doping before depositing or growing the capacitor dielectric layer / film within the trench on the sidewall. An example structure of this device is shown in ​ ​ ​In this case, the trench structure extends into the well below the substrate surface with a conductive fill 310, where the conductive fill 310 is isolated from a doped region 311 in the well that closely surrounds the trench sidewall by a sidewall dielectric. The doped region 311 is a region that surrounds the trench (which has been etched into the well with a doping impurity opposite to the source of the FFT-DRAM) and is doped with the same type of impurity as the source and is connected to the source, thereby forming the first terminal of the charge storage capacitor. This will add an additional step of sidewall doping after the trench capacitor is formed, but it will help to increase the capacitance value of the storage capacitor. In addition, there are other possibilities for implementing the storage device such as a fin capacitor composed of multiple metal layers or polymers separated by a dielectric, etc. which are well understood in the industry. These possibilities can be used to construct an alternative charge storage capacitor or used in combination with the trench capacitor to increase the value of the storage capacitor. When using a fin capacitor for the FFT-DRAM, it can be built on the source of the FFT, where one terminal is connected to ground and the other terminal is connected to the source of the FFT, as with the trench capacitor. As with the fin capacitor, there can be other capacitor structures known in the industry. Such structures can be integrated with the FFT using appropriate process steps to form the FFT-DRAM. These FFT-DRAM structures with alternative capacitor structures are encompassed by the disclosure in this application.

[0084] The FFT technology that enables the integrated FFT-DRAM also provides the following additional advantages to the designers of IoT devices and the market.

[0085] 1. The integrated FFT-DRAM allows for optimization of the FFT-DRAM array for the required number of requirements and interconnection configurations.

[0086] 2. The integrated FFT-DRAM allows the designer to place the FFT-DRAM array flexibly to size, configure and place at the appropriate location within the IC / SOC to meet the needs of the design.

[0087] 3. Lower manufacturing and integration costs allow IoT devices and standalone DRAM manufactured with the FFT-DRAM device technology integrated with the FFT logic circuit to be cost competitive in commercial applications.

[0088] 4. The reduced operating voltage of the FFT and the increased time between refresh cycles of the FFT-DRAM reduces the power dissipation of the system using the disclosed technology.

[0089] While the present disclosure has been described in terms of embodiments, a person of ordinary skill in the art will recognize that the disclosure is not limited to the embodiments described, but can be practiced with modification and alteration within the spirit and scope of the appended claims. Accordingly, the description is to be regarded as illustrative instead of restrictive. There are many other variations to the different aspects of the disclosure which have been described above, and these variations are to be considered as within the scope of the present disclosure.

Claims

1. A Fast Fourier Transform (FFT) based Dynamic Random Access Memory (DRAM), the FFT based DRAM (FFT-DRAM) comprising: an epitaxially grown source region including a source extension and an epitaxial source on and in contact with the source extension, the epitaxially grown source region on a surface of a semiconductor substrate; and a trench capacitor integrated structurally into the epitaxially grown source region, the trench capacitor having a first terminal formed by the epitaxially grown source region and a second terminal as a conductive material filling one or more trenches of the trench capacitor, the second terminal connected to a ground terminal or a fixed voltage terminal; the conductive material filling the trench is separated from the source region by a dielectric separating the first and second terminals of the trench capacitor; when the FFT-DRAM is turned on, the first terminal of the trench capacitor is connected to a bit line connected to a drain of the FFT-DRAM; when the FFT-DRAM is turned off, the first terminal of the trench capacitor is isolated from the bit line connected to the drain of the FFT-DRAM.

2. A Fast Fourier Transform (FFT) based Dynamic Random Access Memory (DRAM) device (FFT-DRAM device) capable of being integrated into a silicon integrated circuit (silicon IC), the FFT-DRAM device comprising: a trench capacitor as a storage device, the trench capacitor having at least two terminals including a first terminal and a second terminal isolated from each other by a capacitor dielectric; an epitaxial source structurally connected to the first terminal of the trench capacitor, the trench capacitor implemented by the epitaxial source such that the epitaxial source is structurally integrated to form the first terminal of the trench capacitor, the second terminal of the trench capacitor formed by a conductive layer within one or more trenches connected to a ground or fixed voltage source via a metal interconnect; an epitaxial drain formed by epitaxial growth on a surface of a substrate and connected to a bit line; and a gate connected to a word line capable of turning the FFT-DRAM device on or off by applying a gate voltage.

3. The FFT-DRAM device of claim 2, wherein: the trench capacitor extends into the substrate, a region of the substrate surrounding the trench capacitor is doped with the same type of dopant as the epitaxial source to form a conductive connection to the epitaxial source, the region forming the first terminal of the trench capacitor. when the FFT-DRAM device is turned on to perform a read operation, the first terminal of the trench capacitor is connected to the bit line and shares a storage charge between the trench capacitor and the bit line. when the FFT device is turned on to perform a write operation, the first terminal of the trench capacitor is connected to the bit line representing a voltage of 1 or 0 and a charge is transferred to or from the trench capacitor to establish a charge storage representing 1 or 0.

4. The FFT-DRAM device of claim 2, wherein, ​ 5. The FFT-DRAM device of claim 2, wherein, ​ 6. The FFT-DRAM device of claim 2, wherein, During a write, the bit line is connected to a data input, the FFT-DRAM device is turned on to charge or discharge the trench capacitor in response to the data input on the bit line, and the FFT-DRAM is turned off to isolate the trench capacitor from the bit line, such that the trench capacitor retains a stored charge representing a 1 or 0.

7. The FFT-DRAM device of claim 2, wherein, During a read, the FFT-DRAM device is turned on to enable the trench capacitor to connect to the bit line and share a stored charge with the bit line, where the bit line is sensed to identify the value of the stored data bit.

8. A field-programmable transistor (FFT)-based dynamic random access memory (DRAM) device (FFT-DRAM device) comprising: a drain extension and a source extension instantiated on a surface of a substrate using low temperature epitaxial deposition on either side of a conductive gate electrode, the drain extension and the source extension in contact with the substrate, and the drain extension and the source extension isolated from the conductive gate electrode by a first dielectric; a drain deposit on the drain extension using low temperature epitaxial deposition, the drain deposit in contact with the drain extension; and a source deposit on the source extension using low temperature epitaxial deposition, the source deposit in contact with the source extension; the source deposit and the drain deposit isolated from the conductive gate electrode by a second dielectric, where the second dielectric is thicker than the first dielectric; the source extension and the source deposit on the source extension form a source region of the FFT-DRAM device; the drain extension and the drain deposit on the drain extension form a drain region of the FFT-DRAM device; the source region has one or more charge storage capacitors, one terminal of the charge storage capacitors coupled to the source region to store charge in response to positive stored data; the charge storage capacitors have a terminal coupled to the source region, the charge storage capacitors comprising one or more trenches filled with a conductive material, the conductive material isolated from the source region by a third dielectric and connected to a ground terminal or a terminal held at a fixed voltage; the trench has a conductive material forming a first electrode, the third dielectric separating the conductive material from a source region epitaxial material of the source region forming a second electrode, the source region epitaxial material forming a first terminal of a charge storage capacitor, the charge storage capacitor formed together by the conductive material, the third dielectric, and the source region epitaxial material, the first terminal of the charge storage capacitor structurally integrated to the source region; when the FFT-DRAM device is turned on by applying a turn-on voltage at the conductive gate electrode, a channel of the FFT-DRAM device forms a path connecting the first terminal of the charge storage capacitor to a bit line connected to the drain deposit; When the FFT-DRAM device is turned off, the channel of the FFT-DRAM device is turned off, isolating the first terminal of the capacitor from the bit line.

9. The FFT-DRAM device of claim 8, wherein, the charge storage capacitor extends into the substrate, a region of the substrate surrounding the charge storage capacitor is doped with the source region epitaxial material to form an electrically conductive connection to the source deposit, the region forming the first terminal of the charge storage capacitor.

10. The FFT-DRAM device of claim 8, wherein, the stored charge in the charge storage capacitor is responsive to data input during a write of the FFT-DRAM device.

11. The FFT-DRAM device of claim 8, wherein, the stored charge in the charge storage capacitor is shared with the bit line during a read of the FFT-DRAM device.

12. The FFT-DRAM device of claim 8, wherein, the FFT-DRAM device is capable of being integrated on an integrated circuit (IC).

13. The FFT-DRAM device of claim 8, wherein, the substrate is a silicon substrate.

14. The FFT-DRAM device of claim 8, wherein, the substrate comprises a silicon wafer having an epitaxial layer on a surface of the silicon wafer, forming the substrate.

15. The FFT-DRAM device of claim 8, wherein, the substrate is a silicon-on-insulator (SOI) substrate.

16. The FFT-DRAM device of claim 8, wherein, the gate dielectric and charge storage capacitor dielectric are high-k dielectrics.

17. The FFT-DRAM device of claim 15, wherein, the SOI substrate comprises a semiconductor epitaxial layer on a dielectric.

18. The FFT-DRAM device of claim 8, wherein, the channel is formed in an epitaxial surface layer on a wafer, wherein the wafer and the epitaxial surface layer form the substrate.

19. The FFT-DRAM device of claim 8, wherein, the charge storage capacitor is a trench capacitor having a circular or rectangular cross-section that is confined in a source terminal or extends into the substrate.

20. The FFT-DRAM device of claim 8, wherein, the charge storage capacitor comprises a multi-finned capacitor instead of a trench capacitor.

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