Array substrate and manufacturing method thereof and display panel

Abstract

The present application discloses an array substrate and a preparation method thereof and a display panel. The array substrate comprises a substrate, a metal oxide active part, a gate insulating part, a gate, an interlayer dielectric layer and a source and drain electrode. The metal oxide active part is arranged on the substrate. The metal oxide active part comprises a semiconductor part and a conducting part which are in the same layer and connected. The thickness of the conducting part is less than the thickness of the semiconductor part. The gate insulating part is arranged on a side of the metal oxide active part away from the substrate and is arranged correspondingly to the semiconductor part. The gate is arranged on a side of the gate insulating part away from the substrate and is arranged correspondingly to the semiconductor part. The interlayer dielectric layer covers the substrate, the metal oxide active part, the gate insulating part and the gate. The source and drain electrode are arranged on the interlayer dielectric layer and are connected to the conducting part. As the thickness of the conducting part is reduced, the number of carriers in the conducting part is reduced, the diffusion distance of the carriers to the semiconductor part is reduced, and the negative bias of the threshold voltage of the transistor is improved, thereby improving the performance of the array substrate.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate and a preparation method thereof, and a display panel. Background Art

[0002] Thin film transistors (TFTs) are key driving components of display panels. The manufacturing process of TFTs determines the display quality of display panels and even the cost of display panels.

[0003] TFTs usually include active layers, gates, and gate insulating layers. The active layer includes a semiconductor portion and a conductor portion. In the prior art, the thickness of the semiconductor portion and the conductor portion are usually the same. This design will result in excessive carrier content in the conductor portion, which will cause the carriers in the conductor portion to easily diffuse to the entire semiconductor portion, thereby causing the threshold voltage of the TFT to be negatively biased, resulting in a short channel effect, which will cause the TFT to deteriorate. Summary of the invention

[0004] The present application provides an array substrate and a manufacturing method thereof and a display panel to reduce the number of carriers in a conducting portion.

[0005] The present application provides an array substrate, comprising:

[0006] substrate;

[0007] A metal oxide active portion, the metal oxide active portion is disposed on the substrate, the metal oxide active portion includes a semiconductor portion and a conductive portion that are in the same layer and connected, the conductive portion is located on both sides of the semiconductor portion, and the thickness of the conductive portion is less than the thickness of the semiconductor portion;

[0008] a gate insulating portion, the gate insulating portion being disposed on a side of the metal oxide active portion away from the substrate and corresponding to the semiconductor portion;

[0009] A gate, the gate being arranged on a side of the gate insulating portion away from the substrate, and the gate being arranged corresponding to the semiconductor portion;

[0010] an interlayer dielectric layer, the interlayer dielectric layer covering the substrate, the metal oxide active portion, the gate insulating portion and the gate; and

[0011] A source and a drain are arranged on the interlayer dielectric layer and connected to the conducting portion.

[0012] Optionally, in some embodiments of the present application, the conductive portion includes a first section and a second section that are in the same layer and connected, the thickness of the first section is smaller than the thickness of the second section, and the first section and the second section are both connected to the source and drain.

[0013] Optionally, in some embodiments of the present application, the second section is located on both sides of the first section.

[0014] The present application also provides a display panel, which includes the array substrate and a light-emitting structure layer arranged on the array substrate.

[0015] The present application also provides a method for preparing the above array substrate, comprising:

[0016] providing a substrate;

[0017] A metal oxide semiconductor portion is provided on the substrate, wherein the metal oxide semiconductor portion includes a semiconductor portion and an intermediate portion which are in the same layer and connected to each other, wherein the intermediate portion is located at both sides of the semiconductor portion, and the thickness of the semiconductor portion is the same as that of the intermediate portion;

[0018] A gate insulating layer and a gate electrode layer are sequentially stacked on the metal oxide semiconductor portion;

[0019] Etching the gate layer and the gate insulating layer, wherein the gate layer forms a gate, the gate insulating layer forms a gate insulating portion, and the gate and the gate insulating portion are both arranged corresponding to the semiconductor portion;

[0020] Performing a first plasma treatment on the middle portion to remove a portion of the middle portion to form a conductive portion, wherein the conductive portion has a thickness smaller than that of the semiconductor portion;

[0021] forming an interlayer dielectric layer on the substrate, the metal oxide active portion, the gate insulating portion, and the gate; and

[0022] A source and a drain are formed on the interlayer dielectric layer, and the source and the drain are connected to the conducting portion.

[0023] Optionally, in some embodiments of the present application, the gate layer and the gate insulating layer are etched, the gate layer forms a gate, and the gate insulating layer forms a gate insulating portion, including:

[0024] Performing wet etching on the gate layer, so that the gate layer forms a gate;

[0025] Performing a first dry etching process on the gate insulating layer, wherein the gate insulating layer forms a gate insulating portion, and the etching gas used in the first dry etching is a first fluorine-containing gas;

[0026] The metal in the surface of the middle portion close to the gate insulating portion reacts with the first fluorine-containing gas to form a first fluorinated metal layer;

[0027] The middle portion is subjected to a first plasma treatment to remove a portion of the middle portion to form a conductive portion, wherein the thickness of the conductive portion is less than the thickness of the semiconductor portion, comprising:

[0028] The metal oxide semiconductor part is subjected to a first plasma treatment, wherein the gas of the first plasma is a first inert gas, and the first metal fluoride layer is removed to form a conductive part, wherein the thickness of the conductive part is smaller than the thickness of the semiconductor part.

[0029] Optionally, in some embodiments of the present application, forming an interlayer dielectric layer on the substrate, the metal oxide active portion, the gate insulating portion, and the gate includes:

[0030] An interlayer material layer is provided on the substrate, the metal oxide active part, the gate insulating part and the gate, and the interlayer material layer is subjected to a second dry etching process, so that the interlayer material layer forms an interlayer dielectric layer having a through hole, and the through hole penetrates the interlayer dielectric layer to expose the conductive part, and the etching gas of the second dry etching is a second fluorine-containing gas, and the metal in a side of the conductive part exposed by the through hole close to the interlayer dielectric layer reacts with the second fluorine-containing gas to form a second fluoride metal layer;

[0031] After forming an interlayer dielectric layer on the substrate, the metal oxide active portion, the gate insulating portion and the gate, the method further includes:

[0032] The conductive portion exposed by the through hole is subjected to a second plasma treatment, wherein the gas of the second plasma is a second inert gas, and a portion of the second metal fluoride layer is removed to form a first section, and the conductive portion not exposed by the through hole is a second section, and the thickness of the first section is less than that of the second section, and both the first section and the second section are connected to the source and drain.

[0033] Optionally, in some embodiments of the present application, the metal oxide semiconductor portion is subjected to a first plasma treatment, the gas of the first plasma is a first inert gas, the first metal fluoride layer is removed to form a conductive portion, and the thickness of the conductive portion is less than the thickness of the semiconductor portion, comprising:

[0034] The middle portion is subjected to a first plasma treatment, wherein the gas of the first plasma is a first inert gas, the first metal fluoride layer is removed, and a conductor treatment is performed to form a conductive portion, wherein the thickness of the conductive portion is smaller than the thickness of the semiconductor portion.

[0035] Optionally, in some embodiments of the present application, the first fluorine-containing gas and the second fluorine-containing gas both include CF 4 , CHF 3 and SF 6 At least one of .

[0036] Optionally, in some embodiments of the present application, the first inert gas and the second inert gas are at least one of He, Ar, Kr and Xe.

[0037] The present application discloses an array substrate, a preparation method thereof and a display panel. The array substrate sets the thickness of the conductive part to be smaller than the thickness of the semiconductor part. As the thickness of the conductive part is reduced, the number of carriers in the conductive part is reduced, and the diffusion distance of the carriers to the semiconductor part is reduced, thereby achieving the purpose of improving the short channel effect, that is, avoiding the problem of negative bias abnormality of the threshold voltage of the transistor caused by the diffusion of carriers to the channel, thereby improving the performance of the array substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0039] Figure 1 It is a structural schematic diagram of an array substrate provided in an embodiment of the present application.

[0040] Figure 2 It is a schematic flow chart of the steps of the method for preparing an array substrate provided in an embodiment of the present application.

[0041] Figure 3-Figure 9 It is a schematic diagram of the step flow structure of the method for preparing an array substrate provided in an embodiment of the present application.

[0042] Reference numerals:

[0043] Array substrate 10; substrate 100; light shielding portion 200; buffer layer 300; metal oxide active portion 400; semiconductor portion 410; conducting portion 420; first sub-portion 421; second sub-portion 422; gate insulating portion 500; gate 600; interlayer dielectric layer 700; source and drain 800; protective insulating layer 900. DETAILED DESCRIPTION

[0044] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, unless otherwise stated, the directional words used, such as "upper" and "lower", generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the accompanying drawings; and "inside" and "outside" refer to the outline of the device. In the present application, "reaction" can be a chemical reaction or a physical reaction.

[0045] The present application discloses an array substrate, a preparation method thereof and a display panel. The array substrate includes a substrate, a metal oxide active portion, a gate insulating portion, a gate, an interlayer dielectric layer and a source and drain electrode. The metal oxide active portion is arranged on the substrate. The metal oxide active portion includes a semiconductor portion and a conductive portion that are in the same layer and connected. The conductive portion is located on both sides of the semiconductor portion. The thickness of the conductive portion is less than the thickness of the semiconductor portion. The gate insulating portion is arranged on a side of the metal oxide active portion away from the substrate and is arranged corresponding to the semiconductor portion. The gate is arranged on a side of the gate insulating portion away from the substrate and is arranged corresponding to the semiconductor portion. The interlayer dielectric layer covers the substrate, the metal oxide active portion, the gate insulating portion and the gate. The source and drain are arranged on the interlayer dielectric layer and are connected to the conductive portion.

[0046] In the present application, the thickness of the conductive part is set to be smaller than the thickness of the semiconductor part. As the thickness of the conductive part is reduced, the number of carriers in the conductive part is reduced, and the diffusion distance of the carriers to the semiconductor part is reduced, thereby achieving the purpose of improving the short channel effect, that is, avoiding the problem of negative bias abnormality of the threshold voltage of the transistor caused by the diffusion of carriers to the channel, thereby improving the performance of the array substrate.

[0047] It should be noted that the short channel effect refers to some effects that occur in the transistor when the conductive channel length of the metal oxide transistor is reduced to less than 10 microns. These effects mainly include the reduction of the threshold voltage as the channel length decreases.

[0048] See also Figure 1 The present application provides an array substrate 10. The array substrate 10 includes a substrate 100, a light shielding portion 200, a buffer layer 300, a metal oxide active portion 400, a gate insulating portion 500, a gate 600, an interlayer dielectric layer 700, a source and drain electrode 800, and a protective insulating layer 900. The detailed description is as follows.

[0049] The light shielding portion 200 is disposed on the substrate 100. The material of the light shielding portion 200 includes at least one of Mo, Al, Cu, Ti, W, Cr, Ni and the above metal alloys. The light shielding portion 200 can be composed of a single film layer or a multi-layer film layer. The light shielding portion 200 is used to block external light from entering the metal oxide active portion 400, thereby ensuring the performance of the metal oxide active portion 400.

[0050] In one embodiment, the thickness of the light shielding portion 200 is 1500-9000 angstroms. Specifically, the thickness of the light shielding portion 200 is 1500 angstroms, 2000 angstroms, 3000 angstroms, 6000 angstroms or 9000 angstroms. Setting the thickness of the light shielding portion 200 within this range makes it difficult for light to enter the metal oxide active portion 400, thereby improving the light shielding effect of the light shielding portion 200.

[0051] The buffer layer 300 is disposed on the substrate 100 and the light shielding portion 200. The material of the buffer layer 300 includes Si 3 N 4 、SiO 2 The buffer layer 300 may be composed of a single film layer or a multi-layer film layer.

[0052] In one embodiment, the thickness of the buffer layer 300 is 1000-5000 angstroms. Specifically, the thickness of the buffer layer 300 is 1000 angstroms, 2000 angstroms, 3000 angstroms, 4000 angstroms or 5000 angstroms.

[0053] The metal oxide active portion 400 is disposed on the substrate 100. Specifically, the metal oxide active portion 400 is disposed on the buffer layer 300. The metal oxide active portion 400 is disposed corresponding to the light shielding portion 200. The metal oxide active portion 400 includes a semiconductor portion 410 and a conductive portion 420 that are in the same layer and connected. The conductive portion 420 is located on both sides of the semiconductor portion 410. The thickness of the conductive portion 420 is less than the thickness of the semiconductor portion 410. Among them, the conductive portion 420 is formed after plasma treatment.

[0054] It should be noted that the corresponding setting means that one film layer is located directly above or directly below another film layer. The corresponding settings that appear later are the same and will not be repeated here.

[0055] In the present application, the thickness of the conducting portion 420 is reduced by setting the thickness of the conducting portion 420 to be smaller than the thickness of the semiconductor portion 410. The reduced thickness of the conducting portion 420 reduces the number of carriers in the conducting portion 420 and reduces the diffusion distance of the carriers to the semiconductor portion 410, thereby achieving the purpose of improving the short channel effect, that is, avoiding the problem of negative bias abnormality of the threshold voltage of the transistor caused by the diffusion of carriers to the channel, thereby improving the performance of the array substrate 10.

[0056] In one embodiment, the material of the metal oxide active portion 400 includes at least one of indium-gallium-zinc oxide (IGZO), zinc oxide (ZnO), tin oxide (SnO), indium-zinc oxide (IZO), gallium-zinc oxide (GaZnO), zinc-tin oxide (ZTO) and indium-tin oxide (ITO).

[0057] In one embodiment, the thickness d of the semiconductor portion 410 is 100-1000 angstroms. Specifically, the thickness d of the semiconductor portion 410 may be 100 angstroms, 500 angstroms, 800 angstroms, 900 angstroms or 1000 angstroms, etc. The thickness d of the semiconductor portion 410 is set within this range to ensure the performance of the transistor.

[0058] In one embodiment, the thickness r of the conductive portion 420 is 99-999 angstroms. Specifically, the thickness r of the conductive portion 420 may be 99 angstroms, 500 angstroms, 800 angstroms, 900 angstroms or 999 angstroms, etc. When the thickness r of the conductive portion 420 is set within this range, the problem of negative bias abnormality of the threshold voltage of the transistor caused by the diffusion of carriers into the channel can be further avoided.

[0059] In one embodiment, the conductive portion 420 includes a first sub-portion 421 and a second sub-portion 422 in the same layer and connected. The thickness of the first sub-portion 421 is less than the thickness of the second sub-portion 422. The first sub-portion 421 and the second sub-portion 422 are both connected to the source and drain 800. That is, the first sub-portion 421 and the second sub-portion 422 are surrounded to form a groove, and the source and drain 800 is filled in the groove.

[0060] In the present application, the thickness of the first subdivision 421 is set to be smaller than the thickness of the second subdivision 422, so that the second subdivision 422 and the first subdivision 421 have a groove due to the difference in thickness, and when the source and drain electrodes 800 are filled in the groove, the side of the source and drain electrodes 800 close to the substrate 100 is in contact with the conduction portion 420, and the side of the source and drain electrodes 800 can also be in contact with the conduction portion 420, so that the adhesion between the source and drain electrodes 800 and the active portion can be enhanced, and the contact characteristics between the source and drain electrodes 800 and the active portion can be improved, thereby improving the performance of the transistor. In addition, the problem of negative bias abnormality of the threshold voltage of the transistor caused by the diffusion of carriers into the channel can be further avoided.

[0061] In one embodiment, the thickness of the second sub-portion 422 is the thickness r of the conductive portion 420, and the thickness h of the first sub-portion 421 is 98-998 angstroms. Specifically, the thickness h of the first sub-portion 421 can be 98 angstroms, 500 angstroms, 800 angstroms, 900 angstroms, or 998 angstroms. Setting the thickness h of the first sub-portion 421 within this range can further avoid the problem of negative bias abnormality of the threshold voltage of the transistor caused by the diffusion of carriers into the channel.

[0062] In one embodiment, the second sub-portion 422 is located on both sides of the first sub-portion 421. In the present application, the second sub-portion 422 is disposed on both sides of the first sub-portion 421 to avoid the first sub-portion 421 being disposed between the second sub-portion 422 and the semiconductor portion 410, thereby preventing the source and drain 800 from contacting the semiconductor portion 410, resulting in poor electrical transmission of the transistor and affecting the performance of the transistor.

[0063] In another embodiment, the first sub-portion 421 is located between the semiconductor portion 410 and the conducting portion 420 to enhance the adhesion between the source / drain 800 and the active portion.

[0064] The gate insulating portion 500 is disposed on a side of the metal oxide active portion 400 away from the substrate 100 , and is disposed corresponding to the semiconductor portion 410 .

[0065] In one embodiment, the thickness of the gate insulating portion 500 is 1000-3000 angstroms. Specifically, the thickness of the gate insulating portion 500 may be 1000 angstroms, 1500 angstroms, 2000 angstroms, 2500 angstroms or 3000 angstroms, etc. Setting the thickness of the gate insulating portion 500 within this range can improve the insulation performance of the gate insulating portion 500 and prevent electrons in the gate 600 from jumping to the metal oxide active portion 400.

[0066] The gate 600 is disposed on a side of the gate insulating portion 500 away from the substrate 100 , and the gate 600 is disposed corresponding to the semiconductor portion 410 .

[0067] In one embodiment, the thickness of the gate 600 is 2000-5000 angstroms. Specifically, the thickness of the gate 600 can be 2000 angstroms, 2500 angstroms, 4000 angstroms, 4500 angstroms or 5000 angstroms, etc. Setting the thickness of the gate 600 within this range can improve the control performance of the gate 600.

[0068] The gate insulating portion 500 is formed by an etching process, such as a dry etching process. During the etching process, the etching gas used is a fluorine-containing gas. The fluorine-containing gas reacts with the metal oxide active portion 400 exposed by the gate insulating portion 500, so that a first fluorinated metal layer MF is formed on the surface of the metal oxide active portion 400 close to the gate insulating portion 500. xWherein, x is 1-20, and M is the metal in the metal oxide active portion 400, such as Ga, In or Zn. The first fluorinated metal layer MF x It is an impurity. If it is not treated, it will cause a large number of metal and F dangling bonds on the surface of the metal oxide active portion 400, resulting in a large number of surface defects on the side of the metal oxide active portion 400 close to the gate insulating portion 500. This surface defect will capture carriers in the metal oxide active portion 400, resulting in a decrease in the number of carriers, thereby affecting the conductive properties, and a large number of surface defects will deteriorate the reliability of the transistor.

[0069] In the present application, after forming the gate insulating portion 500 and the gate 600, the metal oxide active portion 400 is subjected to a first plasma treatment, so that the first fluorinated metal layer MF x The conductive portion 420 is formed so that the thickness of the conductive portion 420 is smaller than the thickness of the semiconductor portion 410, thereby reducing the diffusion distance of the carriers to the semiconductor portion 410. At the same time, the first metal fluoride layer MF x Remove to avoid the first fluorinated metal layer MF between the source and drain 800 and the conductive portion 420 x , which causes the ohmic contact characteristics to deteriorate, thus affecting the conductive properties.

[0070] The interlayer dielectric layer 700 covers the substrate 100, the metal oxide active portion 400, the gate insulating portion 500 and the gate 600. Specifically, the interlayer dielectric layer 700 covers the buffer layer 300, the metal oxide active portion 400, the gate insulating portion 500 and the gate 600. The interlayer dielectric layer 700 includes a through hole and a via hole. The through hole includes a first through hole and a second through hole arranged at intervals. The first through hole penetrates the interlayer dielectric layer 700 to expose a first subdivision 421. The second through hole penetrates the interlayer dielectric layer 700 to expose another first subdivision 421. The via hole penetrates the interlayer dielectric layer 700 and the buffer layer 300 to expose the light shielding portion 200. The second through hole is located between the first through hole and the via hole. The second through hole and the via hole are located on the same side of the semiconductor portion 410.

[0071] In one embodiment, the thickness of the interlayer dielectric layer 700 is 3000-10000 angstroms. Specifically, the thickness of the interlayer dielectric layer 700 may be 3000 angstroms, 4500 angstroms, 8000 angstroms, 9500 angstroms or 10000 angstroms, etc. The thickness of the interlayer dielectric layer 700 is set within this range to improve the insulation performance.

[0072] The source and drain electrodes 800 are disposed on the interlayer dielectric layer 700 and connected to the conductive portion 420. Specifically, the source and drain electrodes 800 include a source electrode and a drain electrode that are disposed on the interlayer dielectric layer 700 in the same layer and spaced apart, and the source electrode is filled in the first through hole and connected to a first sub-portion 421, and the drain electrode is filled in the second through hole and connected to another first sub-portion 421 and is filled in the via hole and connected to the light shielding portion 200.

[0073] In one embodiment, the material of the source and drain electrode 800 includes at least one of Mo, Ti, W, Cr, Ni and alloys of the above metals. The use of such materials to form the source and drain electrode 800 can improve the conductivity of the source and drain electrode 800. The source and drain electrode 800 can be composed of a single layer or multiple layers. Optionally, the material of the source and drain electrode 800 can also be a conductive oxide material. This is not limited here.

[0074] In one embodiment, the thickness of the source and drain electrodes 800 is 2000-10000 angstroms. Specifically, the thickness of the source and drain electrodes 800 can be 2000 angstroms, 3500 angstroms, 5000 angstroms, 8000 angstroms or 10000 angstroms, etc. The thickness of the source and drain electrodes 800 is set within this range to avoid the problem of the source and drain electrodes 800 being broken when filling the through holes and vias.

[0075] The protective insulating layer 900 covers the interlayer dielectric layer 700 and the source and drain electrodes 800 .

[0076] In one embodiment, the thickness of the protective insulating layer 900 is 1000-5000 angstroms. Specifically, the thickness of the protective insulating layer 900 can be 1000 angstroms, 2500 angstroms, 3000 angstroms, 4500 angstroms or 5000 angstroms, etc. The thickness of the protective insulating layer 900 is set within this range to improve the planarization effect of the protective insulating layer 900.

[0077] The present application also provides a display panel, which includes an array substrate 10 provided in the present application and a light emitting structure layer disposed on the array substrate 10 .

[0078] The present application also provides a method for preparing an array substrate 10, which is used to prepare the array substrate 10 provided in the present application. The method for preparing the array substrate 10 includes:

[0079] B11. Provide a substrate.

[0080] B12. A metal oxide semiconductor portion is disposed on the substrate. The metal oxide semiconductor portion includes a semiconductor portion and an intermediate portion which are in the same layer and connected to each other. The intermediate portion is located on both sides of the semiconductor portion. The thickness of the semiconductor portion is the same as that of the intermediate portion.

[0081] B13. A gate insulating layer and a gate electrode layer are sequentially stacked on the metal oxide semiconductor portion.

[0082] B14. Etching the gate layer and the gate insulating layer. The gate layer forms a gate, and the gate insulating layer forms a gate insulating portion. Both the gate and the gate insulating portion are arranged corresponding to the semiconductor portion.

[0083] B15. Perform a first plasma treatment on the middle portion to remove part of the middle portion to form a conductive portion, wherein the thickness of the conductive portion is smaller than the thickness of the semiconductor portion.

[0084] B16. Form an interlayer dielectric layer on the substrate, the metal oxide active portion, the gate insulating portion and the gate.

[0085] B17. Form source and drain electrodes on the interlayer dielectric layer, and connect the source and drain electrodes to the conductive part.

[0086] In the present application, after forming the gate insulating portion and the gate, the metal oxide active portion is subjected to a first plasma treatment so that the first fluorinated metal layer MF x The conductive part is removed to form a conductive part, so that the thickness of the conductive part is smaller than that of the semiconductor part. The thickness of the conductive part is reduced, so that the number of carriers in the conductive part is reduced, thereby reducing the diffusion distance of the carriers to the semiconductor part. At the same time, when the etching gas uses a fluorine-containing gas to treat the gate insulating part, the fluorine-containing gas reacts with the metal in the metal oxide active part to form a first fluoride metal layer MF x Remove to avoid the first fluorinated metal layer MF between the source, drain and the conductive part x , which causes the ohmic contact characteristics to deteriorate, thus affecting the conductive properties.

[0087] See also Figure 2 The present application provides a method for preparing an array substrate 10, comprising:

[0088] B11. Provide a substrate 100.

[0089] See also Figure 3 , specifically, the substrate 100 is cleaned.

[0090] In one embodiment, after B11, it also includes:

[0091] The material of the light shielding portion 200 is deposited on the substrate 100 and patterned to form the light shielding portion 200. Then, the material of the buffer layer 300 is disposed on the substrate 100 and the light shielding portion 200 to form the buffer layer 300.

[0092] B12. A metal oxide semiconductor portion is disposed on the substrate. The metal oxide semiconductor portion includes a semiconductor portion and an intermediate portion which are in the same layer and connected to each other. The intermediate portion is located on both sides of the semiconductor portion. The thickness of the semiconductor portion is the same as that of the intermediate portion.

[0093] See also Figure 4Specifically, the material of the metal oxide active part 400 is disposed on the buffer layer 300 and patterned to form a metal oxide semiconductor part having a semiconductor part 410 and a middle part that are in the same layer and connected. The middle part is located on both sides of the semiconductor part 410. The thickness d of the semiconductor part 410 is the same as the thickness k of the middle part.

[0094] B13. A gate insulating layer and a gate electrode layer are sequentially stacked on the metal oxide semiconductor portion.

[0095] See also Figure 5 Specifically, a gate insulating layer is formed on the metal oxide active part 400 and the buffer layer 300; then, a gate electrode 600 is formed on the gate insulating layer.

[0096] B14. Etching the gate layer and the gate insulating layer. The gate layer forms a gate, and the gate insulating layer forms a gate insulating portion. Both the gate and the gate insulating portion are arranged corresponding to the semiconductor portion.

[0097] Specifically, a photomask is used to define the gate 600 and the gate insulating portion 500 region. Then, the gate 600 layer is wet-etched to form the gate 600.

[0098] Then, the gate insulating layer is subjected to a first dry etching process using the gate 600 pattern as self-alignment, and the gate insulating layer forms a gate insulating portion 500. The etching gas for the first dry etching is a first fluorine-containing gas. Then, the metal in the surface of the middle portion close to the gate insulating portion 500 reacts with the first fluorine-containing gas to form a first fluoride metal layer MF. x .

[0099] In one embodiment, the first fluorine-containing gas includes CF 4 , CHF 3 and SF 6 In the present application, the first fluorine-containing gas is CF 4 Take this as an example to illustrate.

[0100] B15. Perform a first plasma treatment on the middle portion to remove part of the middle portion to form a conductive portion, wherein the thickness of the conductive portion is smaller than the thickness of the semiconductor portion.

[0101] See also Figure 6 Specifically, the metal oxide semiconductor part is subjected to a first plasma treatment, the gas of the first plasma is a first inert gas, the first metal fluoride layer is removed and a conductor treatment is performed to form a conductive part 420, and the thickness h of the conductive part 420 is less than the thickness d of the semiconductor part 410.

[0102] In the present application, an inert gas is used as the gas for the first plasma treatment, so that during physical bombardment, the inert gas does not chemically react with the metal oxide semiconductor part, thereby avoiding the re-generation of impurities on the surface of the metal oxide semiconductor part when the first metal fluoride layer is removed, thereby avoiding the deterioration of the reliability of the transistor.

[0103] In one embodiment, the first inert gas is at least one of He, Ar, Kr and Xe.

[0104] B16. Form an interlayer dielectric layer on the substrate, the metal oxide active portion, the gate insulating portion and the gate.

[0105] See also Figure 7 Specifically, an interlayer material layer is disposed on the substrate 100, the metal oxide active portion 400, the gate insulating portion 500, and the gate 600, and the interlayer material layer is subjected to a second dry etching process, so that the interlayer material layer forms an interlayer dielectric layer 700 having a through hole, and the through hole penetrates the interlayer dielectric layer 700 to expose the conductive portion 420. The through hole includes a first through hole and a second through hole that are arranged at intervals. The first through hole penetrates the interlayer dielectric layer 700 to expose a first subsection 421. The second through hole penetrates the interlayer dielectric layer 700 to expose another first subsection 421. The via hole penetrates the interlayer dielectric layer 700 and the buffer layer 300 to expose the light shielding portion 200. The second through hole is located between the first through hole and the via hole. The second through hole and the via hole are located on the same side of the semiconductor portion 410.

[0106] The etching gas for the second dry etching is a second fluorine-containing gas, and the metal in the surface of the conductive portion 420 exposed by the through hole close to the interlayer dielectric layer 700 reacts with the second fluorine-containing gas to form a second fluorinated metal layer.

[0107] In one embodiment, the second fluorine-containing gas includes CF 4 , CHF 3 and SF 6 In the present application, the second fluorine-containing gas is CF 4 Take this as an example to illustrate.

[0108] In one embodiment, after B16, the following is further included:

[0109] The conductive portion 420 exposed by the through hole is subjected to a second plasma treatment. The gas of the second plasma is a second inert gas. Part of the second metal fluoride layer is removed to form a first section 421. The conductive portion 420 not exposed by the through hole is a second section 422. The thickness of the first section 421 is less than the thickness of the second section 422. Both the first section 421 and the second section 422 are connected to the source and drain 800.

[0110] In one embodiment, the second inert gas is at least one of He, Ar, Kr and Xe.

[0111] B17. Form source and drain electrodes on the interlayer dielectric layer, and connect the source and drain electrodes to the conductive part.

[0112] See also Figure 8 , the material of the source and drain electrodes 800 is disposed on the interlayer dielectric layer 700, and patterning is performed to form the source and drain electrodes 800. The source and drain electrodes 800 include a source electrode and a drain electrode which are disposed on the interlayer dielectric layer 700 in the same layer and are spaced apart, and the source electrode is filled in the first through hole and connected to a first subdivision 421, and the drain electrode is filled in the second through hole and connected to another first subdivision 421 and is filled in the via hole and connected to the light shielding portion 200.

[0113] In one embodiment, after B17, the method further includes:

[0114] See also Fig. 9 , a protective insulating layer 900 is formed on the interlayer dielectric layer 700 and the source and drain electrodes 800 to obtain an array substrate 10 .

[0115] The above is a detailed introduction to an array substrate, a preparation method thereof, and a display panel provided in an embodiment of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. An array substrate, characterized in that: include: substrate; A metal oxide active portion, the metal oxide active portion is disposed on the substrate, the metal oxide active portion includes a semiconductor portion and a conducting portion that are in the same layer and connected, the conducting portion is located on both sides of the semiconductor portion, the thickness of the conducting portion is less than the thickness of the semiconductor portion, the conducting portion includes a first sub-portion and a second sub-portion that are in the same layer and connected, the thickness of the first sub-portion is less than the thickness of the second sub-portion, the first sub-portion and the second sub-portion are surrounded to form a groove, the source and drain are located in the groove, and the first sub-portion and the second sub-portion are both connected to the source and drain; a gate insulating portion, the gate insulating portion being disposed on a side of the metal oxide active portion away from the substrate and corresponding to the semiconductor portion; A gate, the gate being arranged on a side of the gate insulating portion away from the substrate, and the gate being arranged corresponding to the semiconductor portion; an interlayer dielectric layer, the interlayer dielectric layer covering the substrate, the metal oxide active portion, the gate insulating portion and the gate; as well as A source and a drain are arranged on the interlayer dielectric layer and connected to the conducting portion.

2. The array substrate according to claim 1, characterized in that: The second section is located at both sides of the first section.

3. A display panel, characterized in that: The display panel comprises the array substrate according to any one of claims 1 to 2 and a light emitting structure layer arranged on the array substrate.

4. A method for preparing the array substrate according to any one of claims 1 to 2, characterized in that: include: providing a substrate; A metal oxide semiconductor portion is provided on the substrate, wherein the metal oxide semiconductor portion includes a semiconductor portion and an intermediate portion which are in the same layer and connected to each other, wherein the intermediate portion is located at both sides of the semiconductor portion, and the thickness of the semiconductor portion is the same as that of the intermediate portion; A gate insulating layer and a gate electrode layer are sequentially stacked on the metal oxide semiconductor portion; Etching the gate layer and the gate insulating layer, wherein the gate layer forms a gate, the gate insulating layer forms a gate insulating portion, and the gate and the gate insulating portion are both arranged corresponding to the semiconductor portion; Performing a first plasma treatment on the middle portion to remove a portion of the middle portion to form a conductive portion, wherein the conductive portion has a thickness less than that of the semiconductor portion, wherein the conductive portion includes a first sub-portion and a second sub-portion that are in the same layer and connected, wherein the thickness of the first sub-portion is less than that of the second sub-portion, and the first sub-portion and the second sub-portion are surrounded to form a groove; forming an interlayer dielectric layer on the substrate, the metal oxide active portion, the gate insulating portion and the gate; as well as A source and a drain are formed on the interlayer dielectric layer. The source and the drain are located in the groove, and the first section and the second section are both connected to the source and the drain.

5. The method for preparing an array substrate according to claim 4, characterized in that: The gate layer and the gate insulating layer are etched, wherein the gate layer forms a gate and the gate insulating layer forms a gate insulating portion, including: Performing wet etching on the gate layer, so that the gate layer forms a gate; Performing a first dry etching process on the gate insulating layer, wherein the gate insulating layer forms a gate insulating portion, and the etching gas used in the first dry etching is a first fluorine-containing gas; The metal in the surface of the middle portion close to the gate insulating portion reacts with the first fluorine-containing gas to form a first fluorinated metal layer; The middle portion is subjected to a first plasma treatment to remove a portion of the middle portion to form a conductive portion, wherein the thickness of the conductive portion is less than the thickness of the semiconductor portion, comprising: The metal oxide semiconductor part is subjected to a first plasma treatment, wherein the gas of the first plasma is a first inert gas, and the first metal fluoride layer is removed to form a conductive part, wherein the thickness of the conductive part is smaller than the thickness of the semiconductor part.

6. The method for preparing an array substrate according to claim 5, characterized in that: In forming an interlayer dielectric layer on the substrate, the metal oxide active portion, the gate insulating portion and the gate, comprising: An interlayer material layer is provided on the substrate, the metal oxide active part, the gate insulating part and the gate, and the interlayer material layer is subjected to a second dry etching process, so that the interlayer material layer forms an interlayer dielectric layer having a through hole, and the through hole penetrates the interlayer dielectric layer to expose the conductive part, and the etching gas of the second dry etching is a second fluorine-containing gas, and the metal in a side of the conductive part exposed by the through hole close to the interlayer dielectric layer reacts with the second fluorine-containing gas to form a second fluoride metal layer; After forming an interlayer dielectric layer on the substrate, the metal oxide active portion, the gate insulating portion and the gate, the method further includes: The conductive portion exposed by the through hole is subjected to a second plasma treatment, wherein the gas of the second plasma is a second inert gas, and a portion of the second metal fluoride layer is removed to form a first section, and the conductive portion not exposed by the through hole is a second section, and the thickness of the first section is less than that of the second section, and both the first section and the second section are connected to the source and drain.

7. The method for preparing an array substrate according to claim 6, characterized in that: The metal oxide semiconductor portion is subjected to a first plasma treatment, wherein the gas of the first plasma is a first inert gas, and the first metal fluoride layer is removed to form a conductive portion, wherein the thickness of the conductive portion is less than the thickness of the semiconductor portion, comprising: The middle portion is subjected to a first plasma treatment, wherein the gas of the first plasma is a first inert gas, the first metal fluoride layer is removed, and a conductor treatment is performed to form a conductive portion, wherein the thickness of the conductive portion is smaller than the thickness of the semiconductor portion.

8. The method for preparing an array substrate according to claim 6, characterized in that: The first fluorine-containing gas and the second fluorine-containing gas both include at least one of CF4, CHF3 and SF6.

9. The method for preparing an array substrate according to claim 7, characterized in that: The first inert gas and the second inert gas are at least one of He, Ar, Kr and Xe.

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