semiconductor power devices

Abstract

The present invention discloses a semiconductor power device, comprising: a semiconductor substrate; a p-type body region within the semiconductor substrate, the p-type body region in contact with a source metal layer; the semiconductor substrate including at least one first region, the region outside the first region being a second region; a first p-type body region contact region being provided within the p-type body region within the first region, the source metal layer making ohmic contact with the first p-type body region contact region; and no ohmic contact between the p-type body region and the source metal layer within the second region. The present invention can improve voltage oscillation, current oscillation, and EMI issues that can occur in semiconductor power devices during use.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and in particular relates to a semiconductor power device. Background Art

[0002] Semiconductor power devices in the prior art generally increase switching speed to reduce switching losses by reducing the Miller capacitance of the device. However, excessively fast switching speeds can lead to large voltage and current oscillations, which causes serious EMI problems in semiconductor power devices during application. Summary of the Invention

[0003] In view of this, an object of the present invention is to provide a semiconductor power device to reduce the EMI problem generated by the semiconductor power device during application.

[0004] To achieve the above-mentioned object of the present invention, the present invention provides a semiconductor power device, comprising:

[0005] semiconductor substrates;

[0006] a p-type body region located in the semiconductor substrate, wherein the p-type body region is in contact with the source metal layer;

[0007] The semiconductor substrate includes at least one first region, and the region outside the first region is a second region;

[0008] A first p-type body region contact region is provided in the p-type body region in the first region, and the source metal layer contacts the first p-type body region contact region to form an ohmic contact;

[0009] The p-type body region in the second region does not form an ohmic contact with the source metal layer.

[0010] Optionally, the shape of the first area includes at least one of a polygon, a circle or an ellipse.

[0011] Optionally, a second p-type body region contact region is provided in the p-type body region in the second area, and a doping concentration of the second p-type body region contact region is lower than a doping concentration of the first p-type body region contact region.

[0012] Optionally, the source metal layer contacts the second p-type body region contact area but does not form an ohmic contact.

[0013] Optionally, an n-type source region is further included in the p-type body region, and the n-type source region is in contact with the source metal layer.

[0014] Optionally, the semiconductor substrate includes an n-type drain region and an n-type drift region located above the n-type drain region, and the p-type body region and the n-type drift region form a pn junction structure.

[0015] Optionally, a gate structure is further included, and the gate structure includes a gate dielectric layer and a gate.

[0016] Optionally, the method further includes a gate trench recessed in the semiconductor substrate, wherein the gate dielectric layer and the gate are arranged in the gate trench.

[0017] Optionally, a shielding gate is further included, wherein the shielding gate is located at the lower part of the gate trench, the gate is located at the upper part of the gate trench, and the shielding gate is isolated from the semiconductor substrate and the gate by an insulating dielectric layer.

[0018] Optionally, the shielding gate extends upward from the lower portion of the gate trench to the upper portion of the gate trench.

[0019] In the semiconductor power device proposed by the present invention, a first p-type body region contact region is provided in the p-type body region of the first region, and the first p-type body region contact region forms an ohmic contact with the source metal layer, that is, the p-type body region in the first region forms an ohmic contact with the source metal layer, and the p-type body region in the second region does not form an ohmic contact with the source metal layer. The electric potential of the p-type body region without ohmic contact is not fixed, resulting in a change in the threshold voltage Vth. Moreover, the farther away from the p-type body region with ohmic contact, the greater the difference between the threshold voltage Vth of the p-type body region without ohmic contact and the threshold voltage Vth of the p-type body region with ohmic contact. Therefore, the semiconductor power device of the present invention has a slowly changing threshold voltage Vth. When turned on and off, the current and voltage are not easy to change suddenly, thereby reducing the voltage oscillation, current oscillation and EMI problems generated by the semiconductor power device during application. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments.

[0021] Figure 1 is a schematic top view of a first embodiment of a semiconductor power device provided by the present invention;

[0022] Figure 2 yes Figure 1 A schematic cross-sectional view of the structure shown along the AA direction;

[0023] Figure 3 It is a schematic top view of a second embodiment of a semiconductor power device provided by the present invention. DETAILED DESCRIPTION

[0024] The technical solution of the present invention will be fully described below in conjunction with the accompanying drawings in the embodiments of the present invention. It should be understood that the terms such as "having", "including" and "comprising" used in the present invention do not imply the existence of one or more other elements or their combinations.

[0025] Those skilled in the art should understand that a semiconductor power device chip includes a cell region and a terminal region, wherein the cell region is a current working region, and the terminal region is used to improve the withstand voltage of the cells at the outermost edge of the cell region. The semiconductor power device described in the embodiment of the present invention refers to the cell region in the semiconductor power device chip.

[0026] Figure 1 is a schematic top view of a first embodiment of a semiconductor power device provided by the present invention, Figure 2 yes Figure 1 The cross-sectional view of the structure shown in FIG. Figure 1 and Figure 2 As shown, the semiconductor power device of the present invention includes a semiconductor substrate 10, which is usually a silicon substrate and includes an n-type drain region 11 and an n-type drift region 12 located above the n-type drain region 11. A p-type body region 20 is located in the semiconductor substrate 10, and the p-type body region 20 forms a pn junction structure with the n-type drift region 12. The cell region of the semiconductor power device chip includes several p-type body regions. Figure 1 and Figure 2 Only six p-type body regions 20 are shown as examples. The n-type source regions 21 are located within the p-type body regions 20 . Both the p-type body regions 20 and the n-type source regions 21 are in contact with the source metal layer 17 .

[0027] like Figure 1 As shown, in a top view of the upper surface of the semiconductor substrate 10, the semiconductor substrate 10 includes at least one first region 51. The present invention does not specifically limit the number and shape of the first region 51. Figure 1 Only one first area 51 is shown as an example, and the first area 51 is a circular structure, and the area outside the first area 51 is defined as the second area.

[0028] A first p-type body contact region 22 is provided within the p-type body region 20 located within the first region 51. The source metal layer 17 contacts the first p-type body contact region 22, forming an ohmic contact. Because the doping concentration of the first p-type body contact region 22 is greater than the doping concentration of the p-type body region 20, the first p-type body contact region 22 increases the doping concentration at the point of contact between the p-type body region 20 and the source metal layer 17, thereby forming an ohmic contact between the p-type body region 20 and the source metal layer 17 within the first region 51.

[0029] Since the p-type body region 20 in the second region has a low doping concentration, no ohmic contact is formed between the p-type body region 20 in the second region and the source metal layer 17. Optionally, a second p-type body contact region may be formed within the p-type body region 20 in the second region, but the doping concentration of the second p-type body contact region is lower than the doping concentration of the first p-type body contact region 22, so that no ohmic contact is formed between the second p-type body contact region and the source metal layer 17, or the ohmic contact resistance formed between the second p-type body contact region and the source metal layer 17 is relatively large.

[0030] The semiconductor power device of the present invention further comprises a gate structure, which comprises a gate dielectric layer 14 and a gate 15. The gate structure is isolated from the source metal layer 17 by an interlayer insulating layer 16. The gate structure of the semiconductor power device of the present invention can be a planar gate structure or a trench gate structure. Figure 2 In the figure, the gate structure of the present invention is shown as a trench gate structure, and also includes a shielding gate 19, the shielding gate 19 is located in the lower part of the gate trench, the gate 15 is located in the upper part of the gate trench, the shielding gate 19 is isolated from the semiconductor substrate 10 by the insulating dielectric layer 18, and the shielding gate 19 is isolated from the gate 15 by the gate dielectric layer 14. Figure 2 In the embodiment, the gate 15 and the shielding gate 19 are a top-bottom structure. Optionally, the shielding gate 19 can extend upward from the lower part of the gate trench to the upper part of the gate trench. This structure is no longer shown in the embodiment of the present invention.

[0031] In the semiconductor power device of the present invention, the p-type body region 20 in the first region 51 forms an ohmic contact with the source metal layer 17 via the first p-type body region contact region 22. The p-type body region 20 in the second region does not form an ohmic contact with the source metal layer 17. The potential of the p-type body region 20 without an ohmic contact is not constant, causing the threshold voltage Vth to vary. Furthermore, the further the p-type body region 20 without an ohmic contact is from the p-type body region 20 with an ohmic contact, the greater the difference in threshold voltage Vth between the p-type body region with an ohmic contact and the threshold voltage Vth of the p-type body region with an ohmic contact. That is, in the second region, the threshold voltage difference between the p-type body region closer to the first region and the p-type body region in the first region is smaller than the threshold voltage difference between the p-type body region farther from the first region and the p-type body region in the first region. As a result, the semiconductor power device of the present invention has a gradually varying threshold voltage Vth. When turning on and off, the current and voltage are not prone to sudden changes, thereby reducing voltage and current oscillations and EMI problems generated by the semiconductor power device during application. It also improves the reverse recovery characteristics of the semiconductor power device.

[0032] Figure 3 is a top view of a second embodiment of a semiconductor power device provided by the present invention. Figure 3In the figure, the semiconductor substrate 10 includes 6 first regions 51, and the first regions 51 are rectangular. Optionally, the first regions 51 can be regular shapes such as triangles, squares, regular polygons, rectangles, parallelograms, trapezoids, circles, ellipses, etc., or irregular shapes. The embodiment of the present invention does not limit the shape of the first regions 51. The top view shape of the first regions 51 only needs to be a closed figure, such as a closed figure formed by connecting straight lines and / or curves end to end in sequence.

[0033] Further, in Figure 1 and Figure 3 In the top view shown in the figure, the second area surrounds the first area for example. It should be noted that the embodiment of the present invention does not limit the relative position relationship between the first area and the second area. Figure 1 and Figure 3 As shown, the first region may surround the second region, or the first region and the second region may be arranged in sequence along a direction parallel to the plane where the semiconductor substrate is located.

[0034] The above specific implementation methods and examples are specific support for the technical ideas of the present invention and cannot be used to limit the scope of protection of the present invention. Any equivalent changes or equivalent modifications made on the basis of this technical solution in accordance with the technical ideas proposed by the present invention still fall within the scope of protection of the technical solution of the present invention.

Claims

1. A semiconductor power device, characterized in that include: semiconductor substrates; a p-type body region located in the semiconductor substrate, wherein the p-type body region is in contact with the source metal layer; The semiconductor substrate includes at least one first region, and the region outside the first region is a second region; A first p-type body region contact region is provided in the p-type body region in the first region, and the source metal layer contacts the first p-type body region contact region to form an ohmic contact; The p-type body region in the second region does not form an ohmic contact with the source metal layer; An n-type source region is provided in the p-type body region in the first region and the second region, and the n-type source region is in contact with the source metal layer; in the second region, a threshold voltage difference between the p-type body region on the side close to the first region and the p-type body region in the first region is smaller than a threshold voltage difference between the p-type body region on the side away from the first region and the p-type body region in the first region.

2. The semiconductor power device according to claim 1, wherein The shape of the first area includes at least one of a polygon, a circle, or an ellipse.

3. The semiconductor power device according to claim 1, wherein: A second p-type body region contact region is provided in the p-type body region in the second area, and a doping concentration of the second p-type body region contact region is lower than a doping concentration of the first p-type body region contact region.

4. The semiconductor power device according to claim 3, wherein: The source metal layer contacts the second p-type body contact region but does not form an ohmic contact.

5. The semiconductor power device according to claim 1, wherein: The semiconductor substrate includes an n-type drain region and an n-type drift region located above the n-type drain region. The p-type body region and the n-type drift region form a pn junction structure.

6. The semiconductor power device according to claim 1, wherein: It also includes a gate structure, which includes a gate dielectric layer and a gate.

7. The semiconductor power device according to claim 6, wherein: It also includes a gate trench recessed in the semiconductor substrate, wherein the gate dielectric layer and the gate are arranged in the gate trench.

8. The semiconductor power device according to claim 7, wherein: It also includes a shielding gate, which is located at the lower part of the gate trench, and the gate is located at the upper part of the gate trench. The shielding gate is isolated from the semiconductor substrate and the gate by an insulating dielectric layer.

9. The semiconductor power device according to claim 8, wherein: The shield gate extends upward from a lower portion of the gate trench to an upper portion of the gate trench.

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