Thin film transistor based on superjunction structure and display panel

Abstract

The present invention provides a thin film transistor and a display panel based on a superjunction structure. Among them, the thin film transistor based on the superjunction structure includes: a gate layer including a gate; a semiconductor layer located on one side of the gate layer, the semiconductor layer including an N-type semiconductor layer and a P-type semiconductor layer stacked, wherein at least one groove is provided on a side of the N-type semiconductor layer in contact with the P-type semiconductor layer, and part of the P-type semiconductor layer is filled in the groove; a gate insulating layer located between the gate layer and the semiconductor layer; a source-drain layer located on the surface of the semiconductor layer, the source-drain layer including a source electrode and a drain electrode, and the source electrode and the drain electrode are electrically connected to the semiconductor layer respectively. By providing the groove, the present invention reduces the contact resistance between the N-type semiconductor layer and the P-type semiconductor layer, as well as the on-resistance of the fabricated thin film transistor.

Description

Technical Field

[0001] The present invention relates to the field of display technologies, and more particularly to a thin film transistor and a display panel based on a superjunction structure. Background Art

[0002] Flat panel display technologies such as liquid crystal display devices (LCDs) and organic light emitting diode displays (OLEDs) have gradually replaced CRT displays. Among them, OLED displays have many advantages such as self-luminescence, low driving voltage, high luminous efficiency, short response time, high clarity and contrast, a nearly 180° viewing angle, a wide operating temperature range, and the ability to achieve flexible and large-area full-color displays, and are recognized by the industry as the most promising display devices.

[0003] In a liquid crystal display device, a TFT substrate and a CF substrate are disposed opposite to each other. Meanwhile, liquid crystal is sandwiched between the TFT substrate and the CF substrate. Among them, pixel electrodes and thin film transistors (TFTs) are formed in a matrix on the TFT substrate. Since there is a PN junction in the thin film transistor and its resistance is relatively large, the power consumption of the TFT substrate is relatively high. Therefore, it is necessary to reduce the on-resistance in the thin film transistor and the power consumption of the TFT substrate. Summary of the Invention

[0004] Embodiments of the present invention provide a thin film transistor and a display panel based on a superjunction structure to improve the problem that the on-resistance in an existing thin film transistor is too large, resulting in relatively high power consumption.

[0005] The present invention provides a thin film transistor based on a superjunction structure, including: a gate layer including a gate; a semiconductor layer located on one side of the gate layer, the semiconductor layer including an N-type semiconductor layer and a P-type semiconductor layer stacked, wherein at least one groove is provided on a side of the N-type semiconductor layer in contact with the P-type semiconductor layer, and part of the P-type semiconductor layer is filled in the groove; a gate insulating layer located between the gate layer and the semiconductor layer; and a source-drain layer located on the surface of the semiconductor layer, the source-drain layer including a source electrode and a drain electrode, and the source electrode and the drain electrode are electrically connected to the semiconductor layer respectively.

[0006] In some embodiments of the present invention, the P-type semiconductor layer is located on the N-type semiconductor layer and close to the source-drain layer.

[0007] In some embodiments of the present invention, the semiconductor layer includes a first semiconductor portion electrically connected to the source electrode and a second semiconductor portion electrically connected to the drain electrode. The first semiconductor portion includes a P-type first semiconductor portion and an N-type first semiconductor portion. The second semiconductor portion includes a P-type second semiconductor portion and an N-type second semiconductor portion. The P-type first semiconductor portion and the P-type second semiconductor portion are arranged at intervals. The N-type first semiconductor portion and the N-type second semiconductor portion are not arranged at intervals. A plurality of the grooves are provided in the N-type first semiconductor and the N-type second semiconductor portion.

[0008] In some embodiments of the present invention, the plurality of the grooves are evenly distributed.

[0009] In some embodiments of the present invention, in the direction from the first semiconductor portion towards the second semiconductor portion, the number of the plurality of the grooves in the N-type first semiconductor portion decreases; in the direction from the second semiconductor portion towards the first semiconductor portion, the number of the plurality of the grooves in the N-type first semiconductor portion decreases.

[0010] In some embodiments of the present invention, in the direction from the first semiconductor portion towards the second semiconductor portion, the depth of the plurality of the grooves in the N-type first semiconductor portion becomes smaller; in the direction from the second semiconductor portion towards the first semiconductor portion, the depth of the plurality of the grooves in the N-type second semiconductor portion becomes smaller.

[0011] In some embodiments of the present invention, the thickness of the N-type semiconductor layer is greater than the thickness of the P-type semiconductor layer.

[0012] In some embodiments of the present invention, the groove is one of a circular groove, a semi-circular groove, a rectangular groove, and a square groove.

[0013] In some embodiments of the present invention, the materials of the N-type semiconductor layer and the P-type semiconductor layer include one of amorphous silicon, metal oxide, and polycrystalline silicon.

[0014] The present invention provides a display panel, including any one of the thin film transistors based on the superjunction structure described above.

[0015] In the thin-film transistor and display panel based on a superjunction structure provided by an embodiment of the present invention, wherein, in the thin-film transistor based on a superjunction structure, a groove is provided on a side where the N-type semiconductor layer is in contact with the P-type semiconductor layer, and the groove is filled with the P-type semiconductor layer. Compared with the existing technical solution without a groove, the contact area between the N-type semiconductor layer and the P-type semiconductor layer is increased in this embodiment, the contact resistance between the N-type semiconductor layer and the P-type semiconductor layer is reduced. At the same time, the PN junction formed by the N-type semiconductor layer and the P-type semiconductor layer is expanded, achieving the technical effects of quickly extracting excess carriers, improving the carrier mobility, and reducing the on-resistance, thereby effectively reducing the power consumption of the thin-film transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those skilled in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0017] Figure 1 is a schematic structural diagram of a thin-film transistor based on a superjunction structure provided by an embodiment of the present invention;

[0018] Figure 2 is a schematic structural diagram of another thin-film transistor based on a superjunction structure provided by an embodiment of the present invention;

[0019] Figure 3 is a schematic structural diagram of another thin-film transistor based on a superjunction structure provided by an embodiment of the present invention; DETAILED DESCRIPTION OF THE EMBODIMENTS

[0020] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are only some of the embodiments of the present invention, rather than all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope of protection of the present invention. In addition, it should be understood that the specific embodiments described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention. In the present invention, unless otherwise stated, the orientation terms such as "upper" and "lower" usually refer to the upper and lower in the actual use or working state of the device, specifically the plane direction in the drawings; and "inner" and "outer" refer to the outline of the device.

[0021] Specifically, Figure 1 is a schematic structural diagram of a thin-film transistor based on a superjunction structure provided by an embodiment of the present invention, asFigure 1 As shown, the thin film transistor based on the superjunction structure includes: a gate layer 100 including a gate 110; a semiconductor layer 200 located on one side of the gate layer 100, the semiconductor layer 200 including an N-type semiconductor layer 210 and a P-type semiconductor layer 220 stacked, wherein at least one groove 211 is provided on a side of the N-type semiconductor layer 210 in contact with the P-type semiconductor layer 220, and a part of the P-type semiconductor layer 220 is filled in the groove 211; a gate insulating layer 300 located between the gate layer 100 and the semiconductor layer 200; a source-drain layer 400 located on the surface of the semiconductor layer 200, the source-drain layer 400 including a source electrode 410 and a drain electrode 420, and the source electrode 410 and the drain electrode 420 are electrically connected to the semiconductor layer 200 respectively.

[0022] Wherein, a superjunction structure is formed between the stacked N-type semiconductor layer 210 and the P-type semiconductor layer 220, and the superjunction structure is composed of a plurality of reverse-biased PN junction structures. In this embodiment, by providing the groove 211 on a side of the N-type semiconductor layer 210 in contact with the P-type semiconductor layer 220, the groove 211 is filled with the P-type semiconductor layer 220. Compared with the technical solution without grooves, the contact area between the N-type semiconductor layer 210 and the P-type semiconductor layer 220 is effectively increased in this embodiment, the contact resistance between the N-type semiconductor layer 210 and the P-type semiconductor layer 220 is reduced, and the depletion region formed by the N-type semiconductor layer 210 and the P-type semiconductor layer, that is, the region of the formed PN junction, is expanded, realizing the technical effects of quickly extracting excess carriers, improving the carrier mobility, and reducing the on-resistance, and further reducing the energy consumption of the prepared thin film transistor.

[0023] In this embodiment, as Figure 2 shown, the P-type semiconductor layer 220 is located on the N-type semiconductor layer 210 and close to the source-drain layer 400.

[0024] Wherein, the N-type semiconductor layer 210 is located on the gate insulating layer 300.

[0025] Furthermore, as Figure 3As shown, the semiconductor layer 200 includes a first semiconductor portion 200A electrically connected to the source electrode 410 and a second semiconductor portion 200B electrically connected to the drain electrode 420. The first semiconductor portion 200A includes an N-type first semiconductor portion 210A and a P-type first semiconductor portion 220A. The second semiconductor portion 200B includes an N-type second semiconductor portion 210B and a P-type second semiconductor portion 220B. The P-type first semiconductor portion 220A and the P-type second semiconductor portion 220B are arranged at intervals. The N-type first semiconductor portion 210A and the N-type second semiconductor portion 210B are not arranged at intervals. A plurality of the grooves 211 are provided in the N-type first semiconductor portion 210A and the N-type second semiconductor portion 210B.

[0026] It should be noted that, in this embodiment, the P-type first semiconductor portion 220A and the P-type second semiconductor portion 220B are arranged at intervals, that is, the P-type semiconductor layer 220 is composed of two independent structures, namely the P-type first semiconductor portion 220A and the P-type second semiconductor portion 220B. The N-type first semiconductor portion 210A and the N-type second semiconductor portion 210B are not arranged at intervals, that is, the N-type first semiconductor portion 210A and the N-type second semiconductor portion 210B are connected. The N-type semiconductor layer 210 is actually an integral structure. In the present invention, only for clearly explaining that there are a plurality of PN junctions between the N-type semiconductor layer 210 and the P-type semiconductor layer 220, the N-type semiconductor layer 210 and the P-type semiconductor layer 220 are split together and described as a combined structure composed of a plurality of structures.

[0027] In this embodiment, the semiconductor layer 200 is divided into the first semiconductor portion 200A and the second semiconductor portion 200B. The first semiconductor portion 200A is electrically connected to the source electrode 410, and the second semiconductor portion 200B is electrically connected to the drain electrode 420. Among them, in the first semiconductor portion 200A, a first PN junction is formed between the N-type first semiconductor portion 210A and the P-type first semiconductor portion 220A. In the second semiconductor portion 200B, a second PN junction is formed between the N-type second semiconductor portion 210B and the P-type second semiconductor portion 220B. Since there is more than one PN junction in the semiconductor layer 200, and the PN junction has unidirectional conductivity. When a forward voltage is applied to the PN junction, it presents a low resistance and has a large forward diffusion current. When a reverse voltage is applied to the PN junction, it presents a high resistance and has a very small reverse drift current. Therefore, due to the existence of more than one PN junction in the semiconductor layer 200, the leakage problem of the fabricated thin-film transistor in the off state can be significantly improved.

[0028] Optionally, the plurality of the grooves 211 are evenly distributed.

[0029] It can be understood that disposing a plurality of the grooves 211 on the N-type semiconductor layer 210 will affect the stability of other structures located above the N-type semiconductor layer 210. Therefore, in this embodiment, when there are a plurality of the grooves 211, the grooves 211 are evenly distributed on the N-type semiconductor layer 210, thereby improving the stability of the structure of the fabricated thin film transistor.

[0030] Among them, the grooves 211 are generally formed by etching on the N-type semiconductor layer 210. By evenly distributing the grooves 211 on the N-type semiconductor layer, it is beneficial to the preparation of the grooves 211 and avoids the structure of adjacent grooves 211 being affected during the etching process.

[0031] Optionally, in the direction from the first semiconductor portion 200A towards the second semiconductor portion 200B, the number of the plurality of grooves 211 in the N-type first semiconductor portion 210A decreases; in the direction from the second semiconductor portion 200B towards the first semiconductor portion 200A, the number of the plurality of grooves 211 in the N-type first semiconductor portion 210A decreases.

[0032] Among them, the more the number of the grooves 211 provided on the N-type first semiconductor portion 210A and the N-type second semiconductor portion 210B, the more the contact area between the N-type first semiconductor portion 210A and the P-type first semiconductor portion 220A, and between the N-type second semiconductor portion 210B and the P-type second semiconductor portion 220B increases, the more the contact resistance between the N-type semiconductor layer 210 and the P-type semiconductor layer 220 decreases. At the same time, the region of the PN junction formed by the N-type semiconductor layer 210 and the P-type semiconductor layer 220 is expanded, and the reduction amplitude of the on-resistance is greater.

[0033] However, the more the number of the grooves 211 provided on the N-type semiconductor layer 210, the more likely it is to affect the stability of the fabricated thin film transistor. Under the existing process conditions, the grooves 211 are generally obtained by etching on the prepared N-type semiconductor layer 210. Since the prepared N-type semiconductor layer 210 itself is relatively thin, etching a plurality of the grooves 211 thereon easily breaks down the N-type semiconductor layer 210, thereby affecting the function of the N-type semiconductor layer 210, causing damage to the function of the fabricated thin film transistor, and further significantly affecting the quality and service life of the fabricated display panel.

[0034] Further, please refer to Figures 1 to 3The schematic structural diagram of the thin-film transistor shown clearly shows that along the direction away from the thin-film transistor substrate, the cross-sectional lengths of the functional layers decrease in sequence. At the middle part of the semiconductor layer 200, that is, in some regions where the first semiconductor part 200A is close to the second semiconductor part 200B and in some regions where the second semiconductor part 200B is close to the first semiconductor part 200A, the grooves 211 are provided, which has an impact on the stability of the functional layers located above the semiconductor layer 200. Therefore, by reducing the number of the grooves 211 of the N-type first semiconductor part 210A along the direction from the first semiconductor part 200A towards the second semiconductor part 200B, the stability of the prepared thin-film transistor can be improved to a certain extent.

[0035] Similarly, in this embodiment, along the direction from the second semiconductor part 200B towards the first semiconductor part 200A, the number of the grooves 211 of the N-type first semiconductor part 210A is also reduced.

[0036] Furthermore, along the direction from the first semiconductor part 200A towards the second semiconductor part 200B, the depths of the grooves 211 of the N-type first semiconductor part 210A become smaller; along the direction from the second semiconductor part 200B towards the first semiconductor part 200A, the depths of the grooves 211 of the N-type second semiconductor part 210B become smaller.

[0037] In this embodiment, based on the fact that the prepared N-type semiconductor layer 210 itself is relatively thin, when multiple grooves 211 are etched on it, it is easy to break through the N-type semiconductor layer 210, thus affecting the function of the N-type semiconductor layer 210, and setting the grooves 211 on the N-type semiconductor layer 210 will have an impact on the stability of the functional layers located above the semiconductor layer 200. By improving the depths of the grooves 211 provided on the N-type semiconductor layer 210, along the direction from the first semiconductor part 200A towards the second semiconductor part 200B, the depths of the grooves 211 of the N-type first semiconductor part 210A become smaller, and at the same time, along the direction from the second semiconductor part 200B towards the first semiconductor part 200A, the depths of the grooves 211 of the N-type second semiconductor part 210B become smaller, thereby further improving the stability of the prepared thin-film transistor.

[0038] Even further, the thickness of the N-type semiconductor layer 210 is greater than the thickness of the P-type semiconductor layer 220.

[0039] In this embodiment, since it is necessary to form the groove 211 on the N-type semiconductor layer 210, in order to avoid easy breakdown of the N-type semiconductor layer 210 during the manufacturing process, the thickness of the N-type semiconductor layer 210 is increased on the premise that the thickness of the P-type semiconductor layer 220 remains unchanged, thereby improving the stability of the fabricated thin film transistor. Herein, the thickness of the P-type semiconductor layer 220 is not required to be specified in detail, and the P-type semiconductor layer 220 can form a superjunction structure having a plurality of PN junctions with the N-type semiconductor layer 210.

[0040] Optionally, the groove 211 is one of a circular groove, a semi-circular groove, a rectangular groove, and a square groove.

[0041] In this embodiment, the formation of the groove 211 is used to increase the contact area between the N-type semiconductor layer 210 and the P-type semiconductor layer 220. Herein, the groove 211 can be a groove of a single shape or a combination of grooves of multiple shapes. On the premise that the depth of the groove 211 is constant, the surface areas of the circular groove and the semi-circular groove are larger than those of the rectangular groove and the square groove. Therefore, in this embodiment, it is preferred to use one or more of the circular groove or the semi-circular groove.

[0042] Optionally, the materials of the N-type semiconductor layer 210 and the P-type semiconductor layer 220 include one of amorphous silicon, metal oxide, and polycrystalline silicon.

[0043] For example, the material of the N-type semiconductor layer 210 can be one of amorphous silicon doped with phosphorus or arsenic, metal oxide, or polycrystalline silicon, and the material of the P-type semiconductor layer 220 can be one of amorphous silicon doped with boron or gallium, metal oxide, or polycrystalline silicon.

[0044] Optionally, an ohmic contact layer 500 is provided between the P-type first semiconductor portion 220A and the source electrode 410, and between the P-type second semiconductor portion 220B and the drain electrode 420.

[0045] Optionally, a passivation layer 600 is further provided on the surface of the source-drain electrode layer 400. The passivation layer 600 is used to protect the source electrode 410 and the drain electrode 420 of the source-drain electrode layer 400. At the same time, the passivation layer 600 can separate the P-type first semiconductor portion 220A and the P-type second semiconductor portion 220B of the P-type semiconductor layer 220, so that the P-type semiconductor layer 220 is formed of a plurality of structures arranged at intervals. The material of the passivation layer 600 can be one of silicon nitride or silicon oxide.

[0046] An embodiment of the present invention further provides a display panel, including any of the above thin film transistors based on a super junction structure.

[0047] Specific examples are used in this article to elaborate on the principles and implementation manners of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention; at the same time, for those skilled in the art, according to the idea of the present invention, there will be changes in the specific implementation manners and application scopes. In summary, the content of this specification should not be construed as a limitation to the present invention.

Claims

1. A thin film transistor based on a superjunction structure, characterized in that, Comprising: A gate layer including a gate; A semiconductor layer located on one side of the gate layer, the semiconductor layer including an N-type semiconductor layer and a P-type semiconductor layer stacked, wherein at least one groove is provided on a side of the N-type semiconductor layer in contact with the P-type semiconductor layer, and a part of the P-type semiconductor layer is filled in the groove; A gate insulating layer located between the gate layer and the semiconductor layer; A source-drain layer located on the surface of the semiconductor layer, the source-drain layer including a source and a drain, and the source and the drain are electrically connected to the semiconductor layer respectively.

2. The thin film transistor based on a superjunction structure according to claim 1, characterized in that, The P-type semiconductor layer is located on the N-type semiconductor layer and close to the source-drain layer.

3. The thin film transistor based on a superjunction structure according to claim 2, characterized in that, The semiconductor layer includes a first semiconductor portion electrically connected to the source and a second semiconductor portion electrically connected to the drain. The first semiconductor portion includes a P-type first semiconductor portion and an N-type first semiconductor portion. The second semiconductor portion includes a P-type second semiconductor portion and an N-type second semiconductor portion. The P-type first semiconductor portion and the P-type second semiconductor portion are arranged at intervals. The N-type first semiconductor portion and the N-type second semiconductor portion are not arranged at intervals. A plurality of the grooves are provided in the N-type first semiconductor and the N-type second semiconductor portion.

4. The thin film transistor based on a superjunction structure according to claim 3, characterized in that, The plurality of grooves are evenly distributed.

5. The thin film transistor based on a superjunction structure according to claim 3, characterized in that, In a direction from the first semiconductor portion towards the second semiconductor portion, the number of the plurality of grooves in the N-type first semiconductor portion decreases; in a direction from the second semiconductor portion towards the first semiconductor portion, the number of the plurality of grooves in the N-type first semiconductor portion decreases.

6. The thin film transistor based on a superjunction structure according to claim 3, characterized in that, In a direction from the first semiconductor portion towards the second semiconductor portion, the depth of the plurality of grooves in the N-type first semiconductor portion becomes smaller; in a direction from the second semiconductor portion towards the first semiconductor portion, the depth of the plurality of grooves in the N-type second semiconductor portion becomes smaller.

7. The thin film transistor based on a superjunction structure according to claim 3, characterized in that, The thickness of the N-type semiconductor layer is greater than the thickness of the P-type semiconductor layer.

8. The thin film transistor based on a superjunction structure according to claim 4, characterized in that, The groove is one of a circular groove, a semi-circular groove, a rectangular groove and a square groove.

9. The thin film transistor based on a superjunction structure according to claim 1, characterized in that, The materials of the N-type semiconductor layer and the P-type semiconductor layer include one of amorphous silicon, metal oxide, and polycrystalline silicon.

10. A display panel, characterized in that, Comprising a thin film transistor based on a superjunction structure according to any one of claims 1 to 9.

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