Semiconductor device

Abstract

The semiconductor device of one embodiment includes a first electrode, a second electrode, a gate electrode extending in a first direction, a silicon carbide layer provided between the first electrode and the second electrode and including a first silicon carbide region of a first conductivity type having a first region facing the gate electrode and a second region in contact with the first electrode, a second silicon carbide region of a second conductivity type, and a third silicon carbide region of the second conductivity type interposed between the first region and the second silicon carbide region, and the gate electrode. A first width of the first region in a second direction perpendicular to the first direction is greater than or equal to 0.5 μm and less than or equal to 1.2 μm, a second width of the second region in the second direction is greater than or equal to 0.5 μm and less than or equal to 1.5 μm, and a shortest distance between a line segment in the second direction in which a portion of the fourth silicon carbide region in contact with the first electrode is located and a line segment in the second direction in which the second region overlaps, on a center line passing through a center in the second direction of the first region and extending in the first direction, is greater than or equal to three times the first width.

Description

[0001] Related Application

[0002] This application claims priority to Japanese Patent Application No. 2021-29016 (Filing date: February 25, 2021). This application incorporates by reference the entire contents of the base application. TECHNICAL FIELD

[0003] Embodiments relate primarily to semiconductor devices. BACKGROUND

[0004] As a material for a next-generation semiconductor device, silicon carbide is expected. Silicon carbide has superior physical properties such as a band gap that is three times larger, a breakdown electric field strength that is about ten times larger, and a thermal conductivity that is about three times larger than those of silicon. If these characteristics are utilized, a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) that is high in withstand voltage, low in loss, and capable of operating at high temperatures, for example, can be realized.

[0005] A vertical MOSFET using silicon carbide has a pn junction diode as a built-in diode. For example, the MOSFET is used as a switching element connected to an inductive load. In this case, even if the MOSFET is in an off state, a backflow current can flow by using the pn junction diode.

[0006] However, when the backflow current flows using the pn junction diode that operates in a bipolar manner, a growth of a stacking fault in the silicon carbide layer is caused by recombination energy of carriers. If the stacking fault grows in the silicon carbide layer, an increase in on-resistance of the MOSFET occurs. The increase in on-resistance of the MOSFET leads to a decrease in reliability of the MOSFET. For example, by providing a Schottky Barrier Diode (SBD) that operates in a unipolar manner as a built-in diode in the MOSFET, the growth of the stacking fault in the silicon carbide layer can be suppressed.

[0007] When the MOSFET is in an on state, there is a case where a load connected to the MOSFET fails and the load resistance becomes small. In this case, the MOSFET becomes in a short-circuit state, and a large current flows in the MOSFET. A time from when the MOSFET becomes in the short-circuit state to when the MOSFET is destroyed is referred to as a short-circuit endurance. In the MOSFET provided with the SBD, it is also desirable to improve the short-circuit endurance of the MOSFET from the viewpoint of improving the reliability. SUMMARY

[0008] An embodiment of the present application provides a semiconductor device with improved short-circuit endurance.

[0009] The semiconductor device of one embodiment includes a first electrode, a second electrode, a gate electrode extending in a first direction, a silicon carbide layer provided between the first electrode and the second electrode, having a first surface on the first electrode side parallel to the first direction and a second surface on the second electrode side, and including a first silicon carbide region of a first conductivity type having a first region which is in contact with the first surface and is opposite to the gate electrode and extends in the first direction, and a second region which is in contact with the first surface and is in contact with the first electrode, a second silicon carbide region of a second conductivity type provided between the first silicon carbide region and the first surface, at least a part of which is sandwiched between the first region and the second region, is opposite to the gate electrode, and is electrically connected to the first electrode, a third silicon carbide region of the second conductivity type provided between the first silicon carbide region and the first surface, which sandwiches the first region between the second silicon carbide region, is opposite to the gate electrode, and is electrically connected to the first electrode, and a fourth silicon carbide region of the first conductivity type provided between the second silicon carbide region and the first surface, and electrically connected to the first electrode, and a gate insulating layer provided between the gate electrode and the second silicon carbide region, between the gate electrode and the third silicon carbide region, and between the gate electrode and the first region, a first width of the first region in a second direction perpendicular to the first direction is greater than or equal to 0.5 μm and less than or equal to 1.2 μm, a second width of the second region in the second direction is greater than or equal to 0.5 μm and less than or equal to 1.5 μm, a shortest distance between a first line segment and a second line segment is greater than or equal to three times the first width, the first line segment is in the first surface, on a first center line which passes through a first midpoint in the second direction of the first region and extends in the first direction, and a portion of the fourth silicon carbide region which is in contact with the first electrode is positioned in the second direction, and the second line segment is in the first surface, on a second center line which passes through a second midpoint in the second direction of the second region and extends in the first direction, and overlaps with the second region. BRIEF DESCRIPTION OF DRAWINGS

[0010] Figure 1 is a schematic cross-sectional view of a semiconductor device of a first embodiment.

[0011] Figure 2 is a schematic cross-sectional view of a semiconductor device of a first embodiment.

[0012] Figure 3 is a schematic top view of a semiconductor device of a first embodiment.

[0013] Figure 4 is an equivalent circuit diagram of a semiconductor device of a first embodiment.

[0014] Figure 5is a schematic cross-sectional view of a modification of the semiconductor device of the first embodiment.

[0015] Figure 6 is a schematic cross-sectional view of the semiconductor device of the second embodiment.

[0016] Figure 7 is a schematic plan view of the semiconductor device of the second embodiment.

[0017] Figure 8 is a schematic cross-sectional view of the semiconductor device of the second embodiment.

[0018] Figure 9 is a schematic cross-sectional view of the semiconductor device of the second embodiment. DETAILED DESCRIPTION

[0019] Hereinafter, embodiments of the present application will be described with reference to the drawings. In addition, in the following description, the same or similar components, etc. are denoted by the same reference numerals, and sometimes the description thereof will be appropriately omitted for components, etc. that have already been described once.

[0020] In addition, in the following description, in the case where there are marks of n + , n, n － and p + , p, p － , these marks indicate the relative levels of impurity concentrations in each conductivity type. That is, n + indicates that the n-type impurity concentration is relatively high as compared with n, and n － indicates that the n-type impurity concentration is relatively low as compared with n. In addition, p + indicates that the p-type impurity concentration is relatively high as compared with p, and p － indicates that the p-type impurity concentration is relatively low as compared with p. In addition, sometimes n + type and n － type are simply written as n type, and p + type and p － type are simply written as p type.

[0021] In addition, in the present specification, "impurity concentration" means the concentration after compensating for the impurity concentration of the opposite conductivity type, unless specifically noted. That is, the n-type impurity concentration of the silicon carbide region of the n type means the concentration after subtracting the concentration of the p-type impurity from the concentration of the n-type impurity. In addition, the p-type impurity concentration of the silicon carbide region of the p type means the concentration after subtracting the concentration of the n-type impurity from the concentration of the p-type impurity.

[0022] In addition, in the present specification, "impurity concentration of the silicon carbide region" means the maximum impurity concentration of the corresponding silicon carbide region, unless specifically noted.

[0023] The impurity concentration can be determined, for example, by Time of Flight-Secondary Ion Mass Spectrometry (TOF-SIMS). In addition, the relative level of the impurity concentration can be determined, for example, from the level of the carrier concentration obtained by Scanning Capacitance Microscopy (SCM). In addition, the distance of the depth, the thickness, and the like of the impurity region can be obtained by TOF-SIMS. Furthermore, the distance of the depth, the thickness, the width, the interval, and the like of the impurity region can be obtained, for example, by a composite image of the SCM image and the Atomic Force Microscope (AFM) image.

[0024] (First Embodiment)

[0025] The semiconductor device of the first embodiment includes a first electrode, a second electrode, a gate electrode extending in a first direction, a silicon carbide layer provided between the first electrode and the second electrode, having a first surface on the first electrode side parallel to the first direction and a second surface on the second electrode side, and including a first silicon carbide region of a first conductivity type having a first region in contact with the first surface and opposed to the gate electrode and extending in the first direction, and a second region in contact with the first surface and in contact with the first electrode, a second silicon carbide region of a second conductivity type provided between the first silicon carbide region and the first surface, at least a part of which is sandwiched between the first region and the second region, opposed to the gate electrode, and electrically connected to the first electrode, a third silicon carbide region of the second conductivity type provided between the first silicon carbide region and the first surface, sandwiching the first region between the second silicon carbide region, opposed to the gate electrode, and electrically connected to the first electrode, and a fourth silicon carbide region of the first conductivity type provided between the second silicon carbide region and the first surface, and electrically connected to the first electrode, and a gate insulating layer provided between the gate electrode and the second silicon carbide region, between the gate electrode and the third silicon carbide region, and between the gate electrode and the first region, a first width of the first region in a second direction perpendicular to the first direction is 0.5 μm or more and 1.2 μm or less, a second width of the second region in the second direction is 0.5 μm or more and 1.5 μm or less, and a shortest distance between a first line segment in the first surface on a first center line extending in the first direction through a first midpoint in the second direction of the first region and a second line segment in the first surface overlapping the second region on a second center line extending in the first direction through a second midpoint in the second direction of the second region is three times or more the first width, the second line segment being located in the second direction with respect to a part of the fourth silicon carbide region in contact with the first electrode.

[0026] Figure 1 is a schematic cross-sectional view of the semiconductor device of the first embodiment.Figure 2 is a schematic cross-sectional view of a semiconductor device of the first embodiment. Figure 2 is Figure 1 is an enlarged view of a part of Figure 3 is a schematic plan view of a semiconductor device of the first embodiment. Figure 3 is a view showing a silicon carbide region of a surface of a silicon carbide layer and a pattern of an electrode. Figure 2 is Figure 3 is a cross-sectional view of AA' of

[0027] The semiconductor device of the first embodiment is a planar gate type vertical MOSFET 100 using silicon carbide. The MOSFET 100 of the first embodiment is, for example, a Double Implantation MOSFET (DIMOSFET) in which a body region and a source region are formed by ion implantation. In addition, the semiconductor device of the first embodiment is provided with an SBD as a built-in diode.

[0028] Hereinafter, a case where the first conductive type is n-type and the second conductive type is p-type will be described. The MOSFET 100 is an n-channel type MOSFET of a vertical type in which an electron is a carrier.

[0029] The MOSFET 100 is provided with a silicon carbide layer 10, a source electrode 12 (first electrode), a drain electrode 14 (second electrode), a gate insulating layer 16, a gate electrode 18, and an interlayer insulating layer 20. The MOSFET 100 includes a plurality of MOSFET regions and a plurality of SBD regions.

[0030] In the silicon carbide layer 10, a p-type drain region 22, an n-type drift region 24 (first silicon carbide region), a p-type body region 26, an n-type source region 28 (fourth silicon carbide region), and a p-type body contact region 32 (fifth silicon carbide region) are included. + － + + The p-type body region 26 includes a p-type first body region 26a (second silicon carbide region), a p-type second body region 26b (third silicon carbide region), a p-type third body region 26c (sixth silicon carbide region), and a p-type fourth body region 26d.

[0031] The drift region 24 has a JFET region 24a (first region), a JBS region 24b (second region), and a lower region 24c.

[0032] ​​​Source electrode 12 is an example of a first electrode. Drain electrode 14 is an example of a second electrode. Drift region 24 is an example of a first silicon carbide region. First body region 26a is an example of a second silicon carbide region. Second body region 26b is an example of a third silicon carbide region. Third body region 26c is an example of a sixth silicon carbide region. Source region 28 is an example of a fourth silicon carbide region. Body contact region 32 is an example of a fifth silicon carbide region.

[0033] A silicon carbide layer 10 is disposed between the source electrode 12 and the drain electrode 14. The silicon carbide layer 10 is a single crystal SiC. For example, the silicon carbide layer 10 is 4H-SiC.

[0034] The silicon carbide layer 10 has a first surface ( Figure 1 (P1) and the second side ( Figure 1 (P2 in the original text). Hereinafter, the first surface P1 will sometimes be referred to as the surface, and the second surface P2 will sometimes be referred to as the back surface. The first surface P1 is located on the source electrode 12 side of the silicon carbide layer 10. The second surface P2 is located on the drain electrode 14 side of the silicon carbide layer 10. The first surface P1 and the second surface P2 are opposite each other. In addition, hereafter, "depth" refers to the depth in the direction from the first surface toward the second surface.

[0035] The first surface is parallel to both the first and second directions. The second direction is perpendicular to the first direction.

[0036] The first surface P1 is, for example, a surface tilted at an angle of 0 degrees or more but less than 8 degrees relative to the (0001) surface. The second surface P2 is, for example, a surface tilted at an angle of 0 degrees or more but less than 8 degrees relative to the (000-1) surface. The (0001) surface is called the silicon surface. The (000-1) surface is called the carbon surface.

[0037] like Figure 1 As shown, MOSFET100 includes multiple MOSFET regions and multiple SBD regions. MOSFETs are formed in the MOSFET regions. SBDs are formed in the SBD regions.

[0038] The MOSFET region extends in the first direction. The MOSFET region is repeated in the second direction.

[0039] The SBD region extends in the first direction. The SBD region is repeated in the second direction. Two MOSFET regions are arranged between adjacent SBD regions in the second direction. In MOSFET100, the ratio of MOSFET region to SBD region is 2:1.

[0040] The ratio of the MOSFET region to the SBD region is not limited to 2:1. For example, it can also be 1:1, 3:1, or other ratios.

[0041] n + A drain region 22 of an n-type is provided on the back surface side of the silicon carbide layer 10. The drain region 22 contains, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration of the drain region 22 is, for example, 1 x 1018cm-3or more and 1 x 1020cm-3or less. 18 cm -3 The n-type impurity concentration of the drain region 22 is, for example, 1 x 1018cm-3or more and 1 x 1020cm-3or less. 21 cm -3 The n-type impurity concentration of the drain region 22 is, for example, 1 x 1018cm-3or more and 1 x 1020cm-3or less.

[0042] n － A drift region 24 of an n-type is provided between the drain region 22 and the first surface P1. The n － A drift region 24 of an n-type is provided between the source electrode 12 and the drain electrode 14. The n － A drift region 24 of an n-type is provided between the gate electrode 18 and the drain electrode 14.

[0043] n － A drift region 24 of an n-type is provided on the drain region 22. The drift region 24 contains, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration of the drift region 24 is lower than the n-type impurity concentration of the drain region 22. The n-type impurity concentration of the drift region 24 is, for example, 4 x 1018cm-3or more and 1 x 1020cm-3or less. 14 cm -3 The n-type impurity concentration of the drift region 24 is, for example, 4 x 1018cm-3or more and 1 x 1020cm-3or less. 17 cm -3 The n-type impurity concentration of the drift region 24 is, for example, 4 x 1018cm-3or more and 1 x 1020cm-3or less. The thickness of the drift region 24 is, for example, 5 μm or more and 150 μm or less.

[0044] n － The drift region 24 of the n-type has a JFET region 24a, a JBS region 24b, and a lower region 24c.

[0045] The JFET region 24a is provided between the lower region 24c and the first surface P1. The JFET region 24a is in contact with the first surface P1. The JFET region 24a is provided between two adjacent body regions. For example, the JFET region 24a is provided between a first body region 26a and a second body region 26b.

[0046] The JFET region 24a extends in the first direction. The JFET region 24a is opposed to the gate electrode 18 with the gate insulating layer 16 interposed therebetween.

[0047] The JFET region 24a functions as a current path of the MOSFET 100. The n-type impurity concentration of the JFET region 24a is, for example, higher than the n-type impurity concentration of the lower region 24c. The n-type impurity concentration of the JFET region 24a is, for example, 5 x 1018cm-3or more and 2 x 1020cm-3or less. 16 cm -3 The n-type impurity concentration of the JFET region 24a is, for example, 5 x 1018cm-3or more and 2 x 1020cm-3or less. 17 cm -3 The n-type impurity concentration of the JFET region 24a is, for example, 5 x 1018cm-3or more and 2 x 1020cm-3or less.

[0048] The JBS region 24b is provided between the lower region 24c and the first surface P1. The JBS region 24b is in contact with the first surface P1. The JBS region 24b is provided between two adjacent body regions. For example, the JBS region 24b is provided between the first body region 26a and the third body region 26c.

[0049] The JBS region 24b extends in the first direction. The JBS region 24b is in contact with the source electrode 12.

[0050] The JBS region 24b functions as a cathode of the SBD. The n-type impurity concentration of the JBS region 24b is, for example, higher than the n-type impurity concentration of the lower region 24c. The n-type impurity concentration of the JBS region 24b is, for example, 5 x 1018cm-3or more and 2 x 1020cm-3or less. 16 cm-3. -3 The above and 2 x 1020cm-3. 17 cm-3. -3 The above and 2 x 1020cm-3.

[0051] In the first surface P1, the proportion of the JFET region 24a in the prescribed region is, for example, 5% or more and 20% or less. In the first surface P1, the proportion of the JBS region 24b in the prescribed region is, for example, 2% or more and 10% or less.

[0052] For example, the proportion of the JFET region 24a in the prescribed region in the first surface P1 is greater than the proportion of the JBS region 24b in the prescribed region in the first surface P1. Here, the prescribed region is, for example, a region surrounded by a square of 100 pm x 100 pm on the first surface P1.

[0053] The distance (d0) in the second direction between the JFET region 24a and the JBS region 24b is, for example, 1.0 pm or more and 5.0 pm or less. The first width (w1) in the second direction of the JFET region 24a is 0.5 pm or more and 1.2 pm or less. In addition, the second width (w2) in the second direction of the JBS region 24b is 0.5 pm or more and 1.5 pm or less. Figure 2 Figure 2 Figure 3 Figure 2 Figure 3

[0054] The body region 26 of the p-type is provided between the drift region 24 and the first surface P1. The body region 26 extends in the first direction. The body region 26 functions as a channel region of the MOSFET 100.

[0055] The body region 26 contains, for example, aluminum (Al) as the p-type impurity. The p-type impurity concentration of the body region 26 is, for example, 5 x 1018cm-3or more and 2 x 1020cm-3or less. 17 cm-3. -3 ​​​​​above and 5 x 10 19 cm -3 below.

[0056] The depth of the body region 26 is, for example, 0.5 pm or more and 1.0 pm or less.

[0057] The body region 26 is electrically connected to the source electrode 12. The body region 26 is fixed to the potential of the source electrode 12.

[0058] A portion of the body region 26 is in contact with the first face PI. A portion of the body region 26 is opposed to the gate electrode 18. A portion of the body region 26 becomes a channel region of the MOSFET 100. The gate insulating layer 16 is interposed between the portion of the body region 26 and the gate electrode 18.

[0059] The first body region 26a is separated from the second body region 26b in the second direction. The first body region 26a is adjacent to the second body region 26b in the second direction.

[0060] The first body region 26a is separated from the third body region 26c in the second direction. The first body region 26a is adjacent to the third body region 26c in the second direction.

[0061] The third body region 26c is separated from the fourth body region 26d in the second direction. The third body region 26c is adjacent to the fourth body region 26d in the second direction.

[0062] The JFET region 24a is provided between the first body region 26a and the second body region 26b. The JBS region 24b is provided between the second body region 26b and the third body region 26c. The first body region 26a is interposed between the JFET region 24a and the JBS region 24b.

[0063] The JFET region 24a is provided between the third body region 26c and the fourth body region 26d. The third body region 26c is interposed between the JBS region 24b and the JFET region 24a.

[0064] n + The source region 28 of the n-type is provided between the body region 26 and the first face PI. For example, the source region 28 is provided between the first body region 26a and the first face PI. The source region 28 extends in the first direction.

[0065] The source region 28 contains, for example, phosphorus (P) or nitrogen (N) as the n-type impurity. The n-type impurity concentration of the source region 28 is higher than the n-type impurity concentration of the drift region 24.

[0066] The n-type impurity concentration of the source region 28 is, for example, 1 x 10 19 cm -3 above and 1 x 10 21 cm-3 The depth of source region 28 is shallower than the depth of bulk region 26. The depth of source region 28 is, for example, 0.05 μm or more and 0.2 μm or less.

[0067] Source region 28 is connected to source electrode 12. Source region 28 is electrically connected to source electrode 12. The contact between source region 28 and source electrode 12 is, for example, an ohmic contact. Source region 28 is fixed to the potential of source electrode 12.

[0068] p + The body contact region 32 is disposed between the body region 26 and the first surface P1. The body contact region 32 is disposed between the body region 26 and the source electrode 12. The body contact region 32 extends in the first direction.

[0069] The concentration of p-type impurities in the body contact region 32 is higher than that in the body region 26.

[0070] The body contact region 32 contains, for example, aluminum (Al) as a p-type impurity. The concentration of the p-type impurity in the body contact region 32 is, for example, 1 × 10⁻⁶. 19 cm -3 Above and 1×10 21 cm -3 the following.

[0071] The depth of the body contact region 32 is, for example, 0.3 μm or more and 0.6 μm or less.

[0072] The body contact region 32 is connected to the source electrode 12. The body contact region 32 is electrically connected to the source electrode 12. The contact between the body contact region 32 and the source electrode 12 is, for example, an ohmic contact. The body contact region 32 is fixed to the potential of the source electrode 12.

[0073] A gate electrode 18 is disposed on the first surface P1 side of the silicon carbide layer 10. The gate electrode 18 extends in a first direction. A plurality of gate electrodes 18 are arranged in parallel to each other in a second direction.

[0074] The gate electrode 18 is a conductive layer. The gate electrode 18 is, for example, polycrystalline silicon containing p-type or n-type impurities.

[0075] Gate electrode 18 is opposite to body region 26. Gate electrode 18 is opposite to JFET region 24a.

[0076] A gate insulating layer 16 is disposed between the gate electrode 18 and the body region 26. For example, the gate insulating layer 16 is disposed between the gate electrode 18 and the first body region 26a, the gate electrode 18 and the second body region 26b, the gate electrode 18 and the third body region 26c, and the gate electrode 18 and the fourth body region 26d. The gate insulating layer 16 is disposed between the gate electrode 18 and the JFET region 24a. The gate insulating layer 16 is disposed between the gate electrode 18 and the source region 28.

[0077] The gate insulating layer 16 is, for example, silicon oxide. A high-k insulating material (high dielectric constant insulating material) can be applied to the gate insulating layer 16, for example.

[0078] An interlayer insulating layer 20 is disposed on the gate electrode 18 and the silicon carbide layer 10. The interlayer insulating layer 20 is, for example, silicon oxide.

[0079] Source electrode 12 is connected to silicon carbide layer 10. Source electrode 12 is connected to source region 28. Source electrode 12 is connected to bulk contact region 32. Source electrode 12 is connected to JBS region 24b.

[0080] The source electrode 12, for example, has a silicide layer 12a and a metal layer 12b. The silicide layer 12a is disposed between the silicon carbide layer 10 and the metal layer 12b. The silicide layer 12a extends in a first direction.

[0081] The silicide layer 12a is connected to the source region 28. The silicide layer 12a is connected to the bulk contact region 32.

[0082] The source electrode 12 functions as the anode of the SBD.

[0083] The silicide layer 12a of the source electrode 12 contains silicide. The silicide layer 12a is, for example, a nickel silicide or a titanium silicide.

[0084] The contact between the source electrode 12 and the source region 28 is made into an ohmic contact by providing a silicide layer 12a. The contact between the source electrode 12 and the bulk contact region 32 is also made into an ohmic contact by providing a silicide layer 12a.

[0085] The metal layer 12b of the source electrode 12 contains metal. The metal layer 12b is, for example, a stacked structure of titanium (Ti) and aluminum (Al).

[0086] The first interface between the source electrode 12 and the body contact region 32 ( Figure 2 For example, the second interface between the source electrode 12 and the JBS region 24b (I1) Figure 2 The depth of interface I2 is greater than that of interface I1. Figure 2The depth of the first interface I1 is, for example, greater than 0.1 μm and less than 0.3 μm. The depth of the first interface I1 is, for example, greater than the depth of the third interface between the source region 28 and the bulk contact region 32. Figure 2 The depth of I3 in the middle is deep.

[0087] The distance in the second direction between the first interface I1 and the JBS region 24b ( Figure 2 The d2 in the figure is, for example, greater than 0.5 μm and less than 2.0 μm.

[0088] The drain electrode 14 is disposed on the back side of the silicon carbide layer 10. The drain electrode 14 is connected to the drain region 22.

[0089] The drain electrode 14 is, for example, a metal or a metal semiconductor compound. The drain electrode 14 may contain at least one material selected from the group consisting of nickel silicide, titanium (Ti), nickel (Ni), silver (Ag), and gold (Au).

[0090] When the MOSFET100 is in the ON state, current flows from the drain electrode 14 through the drain region 22, the lower region 24c, the JFET region 24a, the channel formed in the body region 26, and the source region 28 to the source electrode 12.

[0091] When a forward bias is applied to the SBD region, current flows from the source electrode 12 through the JBS region 24b, the lower region 24c, and the drain region 22 to the drain electrode 14.

[0092] like Figure 3 As shown, in the first plane P1, any midpoint in the second direction of the JFET region 24a is defined as the first midpoint MP1. The center line passing through the first midpoint MP1 and extending along the first direction is defined as the first center line ML1. The line segment on the first center line ML1 that is in the second direction relative to the portion of the source region 28 that connects with the source electrode 12 is defined as the first line segment LS1.

[0093] In MOSFET 100, the portion of the source region 28 that is connected to the source electrode 12 is... Figure 3 The source region 28 in the middle coincides with the boundary of the silicide layer 12a.

[0094] like Figure 3 As shown, in the first face P1, any midpoint in the second direction of JBS region 24b is defined as the second midpoint MP2. The centerline passing through the second midpoint MP2 and extending along the first direction is defined as the second centerline ML2. The line segment on the second centerline ML2 that overlaps with JBS region 24b is defined as the second line segment LS2.

[0095] The shortest distance between the first line segment LS1 and the second line segment LS2 ( Figure 3dmin) is 3 times or more the first width w1 of the second direction of the JFET region 24a.

[0096] Next, the operation and effects of the MOSFET 100 of the first embodiment will be described.

[0097] Figure 4 is an equivalent circuit diagram of the semiconductor device of the first embodiment. In the MOSFET 100, the pn diode and the SBD are connected in parallel with the transistor as a built-in diode between the source electrode 12 and the drain electrode 14. The body region 26 is an anode of the pn junction diode, and the drift region 24 is a cathode of the pn junction diode. In addition, the source electrode 12 is an anode of the SBD, and the JBS region 24b is a cathode of the SBD.

[0098] For example, consider a case where the MOSFET 100 is used as a switching element connected to an inductive load. When the MOSFET 100 is turned off, a voltage positive with respect to the drain electrode 14 is sometimes applied to the source electrode 12 due to an induced current caused by the inductive load. In this case, a forward current flows through the built-in diode. This state is also referred to as a reverse conduction state.

[0099] Suppose that a forward current flows through the pn junction diode in a case where the MOSFET does not have the SBD. The pn junction diode performs a bipolar operation. When a backflow current flows through the pn junction diode using the bipolar operation, a stacking defect grows in the silicon carbide layer due to a recombination energy of a carrier. If the stacking defect grows in the silicon carbide layer, a problem of an increase in an on-resistance of the MOSFET occurs. The increase in the on-resistance of the MOSFET causes a decrease in the reliability of the MOSFET.

[0100] The MOSFET 100 has the SBD. A forward voltage (Vf) at which a forward current starts to flow through the SBD is lower than a forward voltage (Vf) of the pn junction diode. Thus, the forward current flows through the SBD before the pn junction diode.

[0101] The forward voltage (Vf) of the SBD is, for example, 1.0 V or more and less than 2.0 V. The forward voltage (Vf) of the pn junction diode is, for example, 2.0 V or more and 3.0 V or less.

[0102] The SBD performs a unipolar operation. Therefore, even if the forward current flows, a stacking defect does not grow in the silicon carbide layer 10 due to a recombination energy of a carrier. Thus, an increase in the on-resistance of the MOSFET 100 can be suppressed. Thus, the reliability of the MOSFET 100 is improved.

[0103] When the MOSFET is in the on state, there is a case where a load connected to the MOSFET fails and the load resistance becomes small. In this case, the MOSFET becomes a short-circuit state, and a large current flows in the MOSFET. The time from when the MOSFET becomes the short-circuit state to when it is destroyed is called short-circuit endurance. If the short-circuit endurance decreases, the reliability of the MOSFET decreases.

[0104] It was found by the inventors that in a MOSFET provided with an SBD, a decrease in short-circuit endurance caused by the SBD can occur. In particular, it was found that if the distance between the MOSFET region and the SBD region becomes short, a decrease in short-circuit endurance is likely to occur.

[0105] In the MOSFET 100, the first width w1 of the second direction of the JFET region 24a is 0.5 μm or more and 1.2 μm or less. By making the first width w1 0.5 μm or more, the on resistance of the MOSFET 100 decreases. By making the first width w1 1.2 μm or less, miniaturization of the MOSFET 100 can be achieved. In addition, by making the first width w1 1.2 μm or less, when the MOSFET 100 shorts, the current flowing in the JFET region 24a is limited, and the short-circuit endurance of the MOSFET 100 increases.

[0106] In the MOSFET 100, the second width w2 of the second direction of the JBS region 24b is 0.5 μm or more and 1.5 μm or less. By making the second width w2 0.5 μm or more, the forward current of the SBD increases. In addition, by making the second width w2 1.5 μm or less, miniaturization of the MOSFET 100 can be achieved. In addition, by making the second width w2 1.5 μm or less, the JBS effect is promoted, and the leakage current of the SBD at reverse bias decreases.

[0107] In a MOSFET provided with an SBD, the cause of a decrease in short-circuit endurance caused by the SBD is presumed as follows. When a short circuit of the MOSFET occurs, a large current flows in the MOSFET region, and the temperature of the MOSFET region rises. The heat generated in the MOSFET region is transferred to the SBD region, and the temperature of the SBD region rises. Due to the rise in the temperature of the SBD region, the leakage current of the SBD in the reverse bias state rises. Due to the rise in the leakage current of the SBD, the SBD region heats up, and the temperature of the SBD region further rises.

[0108] It is considered that a positive feedback occurs between the rise in the temperature of the SBD region and the leakage current of the SBD, and eventually the MOSFET is destroyed due to the rise in the temperature of the SBD region. The destruction of the MOSFET due to the rise in the temperature of the SBD region decreases the short-circuit endurance.

[0109] In the MOSFET 100, the shortest distance (dmin) between the first line segment LS1 and the second line segment LS2 is 3 times or more of the first width w1 of the second direction of the JFET region 24a. That is, in the JFET region 24a, the distance between the portion in which the amount of heat generation increases particularly at the time of short circuit of the MOSFET 100 and the JBS region 24b is made 3 times or more of the first width w1 of the JFET region 24a. Figure 3

[0110] By making the shortest distance dmin 3 times or more of the first width w1, the positive feedback between the temperature rise of the SBD region and the leakage current of the SBD is suppressed. Thereby, the short circuit resistance of the MOSFET 100 is improved.

[0111] The amount of heat generation of the JFET region 24a depends on the first width w1 of the JFET region 24a. Qualitatively, the wider the first width w1, the larger the amount of current flowing at the time of short circuit, and the larger the amount of heat generation. By making the shortest distance dmin 3 times or more of the first width w1, the heat transfer from the MOSFET region to the SBD region is sufficiently suppressed. Thus, it is considered that the positive feedback between the temperature rise of the SBD region and the leakage current of the SBD is suppressed.

[0112] From the viewpoint of improving the short circuit resistance of the MOSFET 100, the shortest distance dmin is preferably 3.2 times or more of the first width w1, and more preferably 3.5 times or more.

[0113] In the first face P1, the proportion of the JFET region 24a in the prescribed region is preferably 5% or more and 20% or less. By making the proportion of the JFET region 24a 5% or more, the on-resistance of the MOSFET 100 can be reduced. By making the proportion of the JFET region 24a 20% or less, the amount of heat generation in the MOSFET region of the MOSFET 100 is suppressed, and the short circuit resistance is improved.

[0114] In the first face P1, the proportion of the JBS region 24b in the prescribed region is preferably 2% or more and 10% or less. By making the proportion of the JBS region 24b 2% or more, the forward current of the SBD is increased. By making the proportion of the JBS region 24b 10% or less, the amount of heat generation in the SBD region of the MOSFET 100 is suppressed, and the short circuit resistance is improved.

[0115] It is preferable that the proportion of the JFET region 24a in the prescribed region in the first face P1 be larger than the proportion of the JBS region 24b in the prescribed region in the first face P1. The amount of heat generation in the SBD region is suppressed, and the short circuit resistance is improved.

[0116] It is preferable that the first interface between the source electrode 12 and the body contact region 32 be a Schottky barrier (SB) (see FIG. 2). By making the first interface a Schottky barrier, the on-resistance of the MOSFET 100 can be reduced. Figure 2 ​I1) of the first interface I1 and the second interface I2 in the first embodiment is preferably 0.1 μm or more, more preferably 0.15 μm or more. Figure 2 I2) of the first interface I1 and the second interface I2 in the first embodiment is preferably 0.1 μm or more, more preferably 0.15 μm or more.

[0117] From the viewpoint of suppressing heat generation in the SBD region, the difference (d1) between the depth of the first interface I1 and the depth of the second interface I2 in the first embodiment is preferably 0.1 μm or more, more preferably 0.15 μm or more. Figure 2

[0118] It is preferable that the depth of the first interface I1 be deeper than the depth of a third interface I3 of the source region 28 and the body contact region 32. Figure 2 I3) in the first embodiment. By providing the source electrode 12 at a deeper position of the silicon carbide layer 10 in the vicinity of the JBS region 24b, current rise to the SBD region at the time of short-circuit operation can be suppressed. Thus, short-circuit resistance is improved.

[0119] The distance (d2) in the second direction between the first interface I1 and the JBS region 24b in the first embodiment is preferably 2.0 μm or less, more preferably 1.5 μm or less, and further preferably 1.0 μm or less. By providing the source electrode 12 at a position close to the JBS region 24b, current rise to the SBD region at the time of short-circuit operation can be suppressed. Thus, short-circuit resistance is improved. Figure 2

[0120] Figure 5 is a schematic cross-sectional view of a modification example of the semiconductor device of the first embodiment. Figure 5 is a corresponding view to the MOSFET 100 of the first embodiment. Figure 2

[0121] The MOSFET 101 of the modification example differs from the MOSFET 100 of the first embodiment in that the depth of the interface of the source electrode 12 and the body contact region 32 is substantially the same as the depth of the interface of the source electrode 12 and the JBS region 24b.

[0122] In the above, according to the first embodiment and the modification example thereof, the MOSFET in which reduction in short-circuit resistance caused by the SBD can be suppressed and short-circuit resistance is improved is realized.

[0123] (Second Embodiment)

[0124] The semiconductor device of the second embodiment differs from the first embodiment in that the second region is located in the first direction of the fifth silicon carbide region. Hereinafter, for the contents repeated from the first embodiment, a part of the description is sometimes omitted.

[0125] Figure 6 ​​​is a schematic cross-sectional view of a semiconductor device of a second embodiment. Figure 7 is a schematic plan view of a semiconductor device of the second embodiment. Figure 8 and Figure 9 is a schematic cross-sectional view of a semiconductor device of a second embodiment. Figure 7 is a view showing a pattern of a silicon carbide region of a surface of a silicon carbide layer and an electrode. Figure 6 is Figure 7 a BB' cross-sectional view of Figure 8 is Figure 7 a CC' cross-sectional view of Figure 9 is Figure 7 a DD' cross-sectional view of

[0126] A semiconductor device of a second embodiment is a planar gate type vertical MOSFET 200 using silicon carbide. The MOSFET 200 of the second embodiment is, for example, a DIMOSFET. In addition, the semiconductor device of the second embodiment is provided with an SBD as a built-in diode. The configuration pattern of a MOSFET region and an SBD region of the MOSFET 200 of the second embodiment is different from that of the MOSFET 100 of the first embodiment.

[0127] Hereinafter, a case where a first conductive type is n type and a second conductive type is p type will be described. The MOSFET 200 is an n channel type MOSFET of a vertical type in which an electron is a carrier.

[0128] The MOSFET 200 is provided with a silicon carbide layer 10, a source electrode 12 (first electrode), a drain electrode 14 (second electrode), a gate insulating layer 16, a gate electrode 18, and an interlayer insulating layer 20. The MOSFET 200 includes a plurality of MOSFET regions and a plurality of SBD regions.

[0129] In the silicon carbide layer 10, an n + type drain region 22, an n － type drift region 24 (first silicon carbide region), a p type body region 26, an n + type source region 28 (fourth silicon carbide region), a p + type body contact region 32 (fifth silicon carbide region) are included. The p type body region 26 includes a p type first body region 26a (second silicon carbide region), a p type second body region 26b (third silicon carbide region), a p type third body region 26c, and a p type fourth body region 26d.

[0130] The drift region 24 has a JFET region 24a (first region), a JBS region 24b (second region), and a lower region 24c.

[0131] Source electrode 12 is an example of a first electrode. Drain electrode 14 is an example of a second electrode. Drift region 24 is an example of a first silicon carbide region. First body region 26a is an example of a second silicon carbide region. Second body region 26b is an example of a third silicon carbide region. Source region 28 is an example of a fourth silicon carbide region. Body contact region 32 is an example of a fifth silicon carbide region.

[0132] In MOSFET 200, JBS region 24b is disposed in a first direction of body contact region 32. JBS region 24b is located between two body contact regions 32 that are disposed separately in the first direction.

[0133] JBS region 24b is surrounded by body region 26. JBS region 24b is, for example, surrounded by first body region 26a. JBS region 24b is, for example, surrounded by third body region 26c.

[0134] At least a portion of body region 26 is sandwiched between JFET region 24a and JBS region 24b.

[0135] In the first surface P1, the JFET region 24a occupies, for example, more than 5% and less than 20% of the specified region. In the first surface P1, the JBS region 24b occupies, for example, more than 2% and less than 10% of the specified region.

[0136] In the first surface P1, the proportion of the JFET region 24a in the defined region is, for example, larger than the proportion of the JBS region 24b in the defined region. Here, the defined region is, for example, the region enclosed by a 100μm × 100μm square on the first surface P1.

[0137] The distance in the second direction between JFET region 24a and JBS region 24b ( Figure 7 The d0 in the second direction is, for example, greater than 1.0 μm and less than 5.0 μm. The first width of the second direction of the JFET region 24a ( Figure 6 , Figure 7 The value of w1 in the second direction is greater than 0.5 μm and less than 1.2 μm. Additionally, the second width (in the second direction of JBS region 24b) Figure 7 , Figure 8 The w2 in the range is greater than 0.5 μm and less than 1.5 μm.

[0138] The first interface between the source electrode 12 and the body contact region 32 ( Figure 6 , Figure 9 The I1 in the middle is compared with the second interface between the source electrode 12 and the SBD region ( Figure 8 , Figure 9The depth of interface I2 is greater than that of interface I1. Figure 9 The depth of the first interface I1 is greater than that of the third interface (the source region 28 and the bulk contact region 32). Figure 6 , Figure 9 The depth of I3 in the middle is deep.

[0139] The distance in the first direction between the first interface I1 and the JBS region 24b ( Figure 9 The d2 in the figure is, for example, greater than 0.5 μm and less than 2.0 μm.

[0140] like Figure 7 As shown, in the first plane P1, any midpoint in the second direction of the JFET region 24a is defined as the first midpoint MP1. The center line passing through the first midpoint MP1 and extending along the first direction is defined as the first center line ML1. The line segment on the first center line ML1 that is in the second direction relative to the portion of the source region 28 that connects with the source electrode 12 is defined as the first line segment LS1.

[0141] In MOSFET200, the portion of the source region 28 that is connected to the source electrode 12 is... Figure 7 The source region 28 in the middle coincides with the boundary of the silicide layer 12a.

[0142] like Figure 7 As shown, in the first face P1, any midpoint in the second direction of JBS region 24b is defined as the second midpoint MP2. The centerline passing through the second midpoint MP2 and extending along the first direction is defined as the second centerline ML2. The line segment on the second centerline ML2 that overlaps with JBS region 24b is defined as the second line segment LS2.

[0143] The shortest distance between the first line segment LS1 and the second line segment LS2 ( Figure 7 The dmin in the second direction of the JFET region 24a is more than 3 times the first width w1.

[0144] Next, the function and effect of the MOSFET 200 in the second embodiment will be explained.

[0145] MOSFET 200 has an SBD (Side Filter). Therefore, similar to MOSFET 100 in the first embodiment, the increase in on-resistance can be suppressed. As a result, the reliability of MOSFET 200 is improved.

[0146] The MOSFET 200 has the JBS region 24b disposed between two body contact regions 32 that are separately disposed in the first direction. With this configuration, for example, compared with the MOSFET 100 of the first embodiment, the MOSFET 200 can be miniaturized.

[0147] In MOSFET 200, the first width w1 in the second direction of JFET region 24a is 0.5 μm or more and 1.2 μm or less. By making the first width w1 0.5 μm or more, the on-resistance of MOSFET 200 is reduced. By making the first width w1 1.2 μm or less, miniaturization of MOSFET 200 can be achieved. In addition, by making the first width w1 1.2 μm or less, the current flowing through JFET region 24a is limited when MOSFET 200 is short-circuited, and the short-circuit withstand capability of MOSFET 200 is improved.

[0148] In MOSFET200, the second width w2 of the JBS region 24b in the second direction is 0.5 μm or more and 1.5 μm or less. By making the second width w2 more than 0.5 μm, the forward current of the SBD increases. Furthermore, by making the second width w2 less than 1.5 μm, miniaturization of the MOSFET200 is possible. Additionally, by making the second width w2 less than 1.5 μm, the JBS effect is enhanced, and the leakage current of the SBD during reverse bias is reduced.

[0149] In MOSFET200, the shortest distance between the first segment LS1 and the second segment LS2 ( Figure 7 The distance between the portion of JFET region 24a that experiences significant heat generation, particularly the portion where the MOSFET 200 is short-circuited, and the JBS region 24b, is at least three times the first width w1 of JFET region 24a. It is assumed that when the MOSFET 200 is short-circuited, a large current flows through the portion of JFET region 24a near the source region 28 where it connects to the source electrode 12, resulting in particularly high heat generation.

[0150] By making the shortest distance dmin more than three times the first width w1, the positive feedback between the temperature rise in the SBD region and the leakage current of the SBD can be suppressed. As a result, the short-circuit withstand capability of the MOSFE200 is improved.

[0151] From the viewpoint of improving the short-circuit withstand capability of MOSFE200, the shortest distance dmin is preferably more than 3.2 times the first width w1, and more preferably more than 3.5 times.

[0152] In the first surface P1, the proportion of the JFET region 24a in the specified region is preferably 5% or more and 20% or less. By making the proportion of the JFET region 24a more than 5%, the on-resistance of the MOSFET 200 can be reduced. By making the proportion of the JFET region 24a less than 20%, heat generation in the MOSFET region of the MOSFET 200 can be suppressed, and the short-circuit withstand capability can be improved.

[0153] In the first face P1, the proportion of the JBS region 24b in the specified region is preferably 2% or more and 10% or less. By making the proportion of the JBS region 24b more than 2%, the forward current of the SBD increases. By making the proportion of the JBS region 24b less than 10%, heat generation in the SBD region of the MOSFET 200 can be suppressed, and the short-circuit withstand capability can be improved.

[0154] Preferably, the proportion of the JFET region 24a in the specified area of ​​the first surface P1 is larger than the proportion of the JBS region 24b in the specified area of ​​the first surface P1. This can suppress heat generation in the SBD region and improve short-circuit withstand capability.

[0155] The preferred interface between the source electrode 12 and the bulk contact region 32 ( Figure 6 The I1 in the middle is compared with the second interface between the source electrode 12 and the SBD region ( Figure 8 , Figure 9 The source electrode 12 is located deep within the silicon carbide layer 10 near the JBS region 24b, suppressing the current rise to the SBD region during short-circuit operation. This improves short-circuit withstand capability.

[0156] From the perspective of suppressing heat generation in the SBD region, the depth difference between the first interface I1 and the second interface I2 ( Figure 9 The d1 in the sample is preferably 0.1 μm or more, and more preferably 0.15 μm or more.

[0157] The preferred depth of the first interface I1 is greater than that of the third interface between the source region 28 and the bulk contact region 32. Figure 6 The depth of I3 in the JBS region is deep. By having the source electrode 12 located at a deeper position in the silicon carbide layer 10 near the JBS region 24b, the current rise to the SBD region can be suppressed during short-circuit operation. As a result, the short-circuit withstand capability is improved.

[0158] The distance in the second direction between the first interface I1 and the JBS region 24b ( Figure 9 The d2 in the figure is preferably 2.0 μm or less, more preferably 1.5 μm or less, and even more preferably 1.0 μm or less. By having the source electrode 12 located close to the JBS region 24b, the current rise to the SBD region can be suppressed during short-circuit operation. As a result, the short-circuit withstand capability is improved.

[0159] According to the second embodiment, a MOSFET that can suppress the decrease in short-circuit withstand capability caused by SBD and improve the short-circuit withstand capability has been realized.

[0160] In the first and second embodiments, the case where the crystal structure of SiC is 4H-SiC is described as an example, but the present application can also be applied to devices using SiC having other crystal structures such as 6H-SiC and 3C-SiC. In addition, the present application can also be applied to a surface other than the (0001) surface of the silicon carbide layer 10.

[0161] In the first and second embodiments, the case where the first conductivity type is n-type and the second conductivity type is p-type is described as an example, but the first conductivity type can also be p-type and the second conductivity type can also be n-type.

[0162] In the first and second embodiments, aluminum (Al) is exemplified as the p-type impurity, but boron (B) can also be used. In addition, nitrogen (N) and phosphorus (P) are exemplified as the n-type impurity, but arsenic (As), antimony (Sb), and the like can also be used.

[0163] The several embodiments of the present application are described, but these embodiments are presented as examples and are not intended to limit the scope of the application. These new embodiments can be implemented in other various ways, and various omissions, substitutions, and changes can be made within the scope of the gist of the application. These embodiments and modifications thereof are included in the scope and gist of the application, and are included in the scope of the application and equivalents thereof recited in the claims.

Claims

1. A semiconductor device, wherein, Possessing: a first electrode; a second electrode; a gate electrode extending in a first direction; a silicon carbide layer provided between the first electrode and the second electrode, having a first surface on the first electrode side parallel to the first direction and a second surface on the second electrode side, and including: a first silicon carbide region of a first conductivity type having a first region which is continuous with the first surface and opposite the gate electrode and extends in the first direction, and a second region which is continuous with the first surface and continuous with the first electrode; a second silicon carbide region of a second conductivity type provided between the first silicon carbide region and the first surface, at least a part of which is sandwiched between the first region and the second region, opposite the gate electrode, and electrically connected to the first electrode; a third silicon carbide region of the second conductivity type provided between the first silicon carbide region and the first surface, sandwiching the first region between the second silicon carbide region, opposite the gate electrode, and electrically connected to the first electrode; and a fourth silicon carbide region of the first conductivity type provided between the second silicon carbide region and the first surface, and electrically connected to the first electrode; and a gate insulating layer provided between the gate electrode and the second silicon carbide region, between the gate electrode and the third silicon carbide region, and between the gate electrode and the first region, a first width of the first region in a second direction perpendicular to the first direction is 0.5 μm or more and 1.2 μm or less, a second width of the second region in the second direction is 0.5 μm or more and 1.5 μm or less, a shortest distance between a first line segment and a second line segment is 3 times or more the first width, the first line segment is in the first surface, on a first center line extending in the first direction through a first midpoint of the second direction of the first region, and a part of the fourth silicon carbide region which is continuous with the first electrode is located in the second direction, the second line segment is in the first surface, on a second center line extending in the first direction through a second midpoint of the second direction of the second region, and overlaps the second region, the silicon carbide layer further includes a fifth silicon carbide region between the first electrode and the second silicon carbide region, the fifth silicon carbide region having a second conductivity type impurity concentration higher than a second conductivity type impurity concentration of the second silicon carbide region, a first interface of the first electrode and the fifth silicon carbide region is deeper than a second interface of the first electrode and the second region.

2. The semiconductor device according to claim 1, wherein: a proportion of the first region in a prescribed region in the first surface is 20% or less, a proportion of the second region in the prescribed region in the first surface is 10% or less.

3. The semiconductor device according to claim 1 or 2, wherein: The silicon carbide layer further includes a sixth silicon carbide region of a second conductivity type, which is provided between the first silicon carbide region and the first face, sandwiches the second region between the second silicon carbide region, is opposed to the gate electrode, and is electrically connected to the first electrode.

4. The semiconductor device according to claim 1 or 2, wherein The second region is located in the first direction of the fifth silicon carbide region.

5. The semiconductor device according to claim 1 or 2, wherein The difference between the depths of the first interface and the second interface is 0.1 μm or more.

6. The semiconductor device according to claim 1 or 2, wherein The distance between the first interface and the second region is 0.5 μm or more and 2.0 μm or less.

7. A semiconductor device, wherein, provided with: a first electrode; a second electrode; a gate electrode extending in a first direction; a silicon carbide layer provided between the first electrode and the second electrode, having a first face on the first electrode side parallel to the first direction and a second face on the second electrode side, and including: a first silicon carbide region of a first conductivity type having a first region in contact with the first face, opposed to the gate electrode, and extending in the first direction, and a second region in contact with the first face and in contact with the first electrode; a second silicon carbide region of a second conductivity type provided between the first silicon carbide region and the first face, at least a part of which is sandwiched between the first region and the second region, opposed to the gate electrode, and electrically connected to the first electrode; a third silicon carbide region of the second conductivity type provided between the first silicon carbide region and the first face, sandwiching the first region between the second silicon carbide region, opposed to the gate electrode, and electrically connected to the first electrode; and a fourth silicon carbide region of the first conductivity type provided between the second silicon carbide region and the first face, and electrically connected to the first electrode; and a gate insulating layer provided between the gate electrode and the second silicon carbide region, between the gate electrode and the third silicon carbide region, and between the gate electrode and the first region, a first width of the first region in a second direction perpendicular to the first direction is 0.5 μm or more and 1.2 μm or less, a second width of the second region in the second direction is 0.5 μm or more and 1.5 μm or less, a shortest distance between a first line segment and a second line segment is 3 times or more the first width, the first line segment is in the first face, on a first center line extending in the first direction through a first midpoint of the second direction of the first region, and a part of the fourth silicon carbide region in contact with the first electrode is located in the second direction, the second line segment is in the first face, on a second center line extending in the first direction through a second midpoint of the second direction of the second region, and overlaps the second region, The silicon carbide layer further includes a fifth silicon carbide region between the first electrode and the second silicon carbide region, the fifth silicon carbide region having a second conductivity type impurity concentration higher than that of the second silicon carbide region, The first electrode and the first interface of the fifth silicon carbide region are deeper than the third interface of the fourth silicon carbide region and the fifth silicon carbide region.

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