Charge pump circuit, method of operating the same, and semiconductor device including the same

Abstract

The present application relates to a charge pump circuit, a method of operating the same, and a semiconductor device including the charge pump circuit. A semiconductor device includes: a voltage generator configured to pump a power supply voltage to generate a first pumped voltage in response to an operation clock; a clock generator configured to generate the operation clock having a first frequency during an initial operation period in which a level of the first pumped voltage is at a first level and to generate the operation clock having a second frequency after the initial operation period, the second frequency being generated to be lower than the first frequency in response to the level of the first pumped voltage rising to a second level that is greater than the first level; and an internal circuit configured to perform a predetermined internal operation in response to the first pumped voltage.

Description

Technical Field

[0001] One or more embodiments of this disclosure relate to a charge pump circuit, a method of operating the charge pump circuit, and a semiconductor device including the charge pump circuit. Background Technology

[0002] During the operation of semiconductor devices (e.g., flash memory, EEPROM, DRAM), a specific range of voltages can be used to perform, for example, programming and / or erasing operations. This voltage may internally have a higher level than the external power supply voltage. To generate this voltage, a charge pump circuit comprising multiple pump stages can be used. As the number of active pump stages increases, current efficiency may decrease. This can lead to a significant increase in peak input current, which may limit the power and performance of the semiconductor device. Summary of the Invention

[0003] One or more embodiments of this disclosure relate to a charge pump circuit capable of efficiently generating a pump voltage.

[0004] One or more implementations may generate the pump voltage based on a clock signal whose frequency varies according to the level of the pump voltage.

[0005] One or more embodiments may generate a pump voltage in such a manner when the pump voltage falls within a predetermined range (e.g., including but not limited to a range having a voltage level higher than the supply voltage).

[0006] One or more embodiments may provide a method of operating such a charge pump circuit.

[0007] One or more embodiments may provide a semiconductor device including such a charge pump circuit.

[0008] According to an embodiment of the present invention, a charge pump circuit may include: a first charge pump configured to generate a first pump voltage using a power supply voltage in response to an operating clock, the first charge pump including N pump stages configured to operate based on N first pump control signals, where N is a natural number equal to or greater than 2; a first pump control signal generator configured to enable a first number of signals among the N first pump control signals to raise the first pump voltage to a level higher than the power supply voltage by a first amount, and to enable a second number of signals among the N first pump control signals to raise the first pump voltage to a level higher than the power supply voltage by a second amount, wherein the first number of signals is greater than the second number of signals, and the first amount is greater than the second amount; and a clock generator configured to change the frequency of the operating clock based on whether the number of enabled signals corresponds to the first number of signals or the second number of signals, the clock generator being configured to: generate an operating clock with a first frequency based on the first number of enabled signals, and generate an operating clock with a second frequency based on the second number of enabled signals, wherein the second frequency is higher than the first frequency.

[0009] The first charge pump may include: a second pump control signal generator configured to generate N second pump control signals, the N second pump control signals having the same activation period as the N first pump control signals but having a higher activation level than the N first pump control signals; and N power supplies configured to supply power voltages as operating power for the N pump stages, respectively in response to the N second pump control signals.

[0010] The second pump control signal generator may include: a second charge pump configured to pump a power supply voltage in response to an operating clock to generate a second pump voltage; and N shifters configured to shift the enable level of N first pump control signals to the level of the second pump voltage, and output the level-shifted N first pump control signals as N second pump control signals.

[0011] The N power supplies may include N NMOS transistors, which are configured to selectively supply power voltage to a corresponding one of the N pump stages in response to a corresponding one of the N second pump control signals.

[0012] The first pump control signal generator can enable N first pump control signals in a predetermined order, and can deactivate N first pump control signals in the reverse order of the predetermined order.

[0013] The charge pump circuit may further include a voltage comparator configured to compare the level of a first pump voltage with the level of a pump reference voltage and generate an operation control signal. The first charge pump may include a pump controller configured to switch the operation of each of the N pump stages in response to at least one of an operation clock, an operation control signal, or N first pump control signals.

[0014] The clock generator may include: a drive actuator configured to increase or decrease the level of a drive operating voltage in response to a feedback signal, and to adjust the rate at which the level of the drive operating voltage decreases according to a first number or a second number of signals among the N first pump control signals that enable the drive operating voltage; a feedback signal generator configured to compare the level of the drive operating voltage with a drive reference voltage level, and to determine whether to enable the feedback signal based on the comparison result; and a clock output configured to output the feedback signal as an operating clock. The drive actuator is configured to decrease the rate at which the level of the drive operating voltage decreases when the number of enabled signals among the N first pump control signals increases, and increase the rate at which the level of the drive operating voltage decreases when the number of enabled signals among the N first pump control signals decreases.

[0015] According to an embodiment of the present invention, a semiconductor device may include: a voltage generator configured to pump a power supply voltage in response to an operating clock to generate a first pump voltage; a clock generator configured to generate an operating clock having a first frequency during an initial operating period when the level of the first pump voltage is at a first level and to generate an operating clock having a second frequency after the initial operating period, wherein the second frequency is generated to be lower than the first frequency in response to the level of the first pump voltage rising to a second level greater than the first level; and internal circuitry configured to perform a predetermined internal operation in response to the first pump voltage.

[0016] The clock generator may include: a first pump control signal generator configured to enable a first number of signals among N first pump control signals to raise the level of the first pump voltage to a first amount higher than the level of the power supply voltage, and to enable a second number of signals among N first pump control signals to raise the level of the first pump voltage to a second amount higher than the level of the power supply voltage, wherein the first number of signals is greater than the second number of signals, and the first amount is greater than the second amount; and a clock generator configured to decrease the frequency of the operating clock as the number of enabled signals among the N first pump control signals increases, and increase the frequency of the operating clock as the number of enabled signals among the N first pump control signals decreases, wherein N is a natural number equal to or greater than 2.

[0017] The voltage generator may include a first charge pump configured to generate a first pump voltage using a power supply voltage in response to an operating clock, the first charge pump including N pump stages that are activated in response to N first pump control signals.

[0018] The first charge pump may include: a second pump control signal generator configured to generate N second pump control signals, the N second pump control signals having the same activation period as the N first pump control signals but having a higher activation level than the N first pump control signals; and N power supplies configured to supply power voltages as operating power for the N pump stages in response to the N second pump control signals respectively.

[0019] The second pump control signal generator may include: a second charge pump configured to pump a power supply voltage in response to an operating clock to generate a second pump voltage; and N shifters configured to shift the enable level of N first pump control signals to the level of the second pump voltage, and output the level-shifted N first pump control signals as N second pump control signals.

[0020] The N power supplies may include N NMOS transistors, which are configured to selectively supply power voltage to a corresponding one of the N pump stages in response to a corresponding one of the N second pump control signals.

[0021] The first pump control signal generator can enable N first pump control signals in a predetermined order, and can deactivate N first pump control signals in the reverse order of the predetermined order.

[0022] The voltage generator may include a voltage comparator configured to compare the level of a first pump voltage with the level of a pump reference voltage and generate an operation control signal. The first charge pump block includes a pump controller configured to switch the operation of each of the N pump stages in response to at least one of an operation clock, an operation control signal, or N first pump control signals.

[0023] The clock generator may include: a drive operator configured to increase or decrease the level of a drive operating voltage in response to a feedback signal, and to adjust the rate at which the level of the drive operating voltage decreases according to the number of enabled signals among N first pump control signals; a feedback signal generator configured to compare the level of the drive operating voltage with a drive reference voltage level, and to determine whether to enable the feedback signal based on the comparison result; and a clock output configured to output the feedback signal as an operating clock. When the number of enabled signals among the N first pump control signals is within a first range, the drive operator may decrease the rate at which the level of the drive operating voltage decreases, and when the number of enabled signals among the N first pump control signals is within a second range less than the first range, the drive operator may increase the rate at which the level of the drive operating voltage decreases.

[0024] According to an embodiment of the present invention, a method of operating a charge pump circuit that generates a first pump voltage using a power supply voltage in response to an operating clock, the charge pump circuit including N pump stages having an operation determined in response to a corresponding one of N first pump control signals, wherein N is a natural number equal to or greater than 2, the method of operating may include the following steps: activating a first number of signals among the N first pump control signals to raise the level of the first pump voltage to a first amount higher than the level of the power supply voltage, and activating a second number of signals among the N first pump control signals to raise the level of the first pump voltage to a second amount higher than the level of the power supply voltage, wherein the first number of signals is greater than the second number of signals, and the first amount is greater than the second amount; and generating an operating clock having a first frequency based on activating the first number of signals, and generating an operating clock having a second frequency based on activating the second number of signals, wherein the first frequency is lower than the second frequency.

[0025] The operation method may further include the following steps: generating N second pump control signals, wherein the N second pump control signals have the same activation period as the N first pump control signals and have a higher activation level than the N first pump control signals; and supplying power supply voltage as the operating power of the N pump stages in response to the N second pump control signals respectively.

[0026] The step of generating N second pump control signals may include the following steps: pumping the power supply voltage in response to an operating clock to generate a second pump voltage; shifting the enable level of the N first pump control signals to the level of the second pump voltage, and outputting the level-shifted N first pump control signals as N second pump control signals.

[0027] N first pump control signals can be enabled in a predetermined order and deactivated in the reverse order of the predetermined order.

[0028] According to an embodiment of the present invention, an apparatus may include: a storage region configured to store instructions; and one or more processors, which, when the instructions are executed, are configured to: control the generation of different combinations of control signals to selectively enable different combinations of pump stages of a charge pump circuit based on an operating clock; and output a pump voltage based on one of the different combinations of control signals, wherein, when the instructions are executed, the one or more processors: set the operating clock to a first frequency based on enabling a first number of control signals, and set the operating clock to have a second frequency based on enabling a second number of control signals, wherein the second frequency is higher than the first frequency.

[0029] When the instruction is executed, the one or more processors cause the processors to: enable a first number of signals to raise the first pump voltage to a level a first amount higher than the power supply voltage level, and enable a second number of signals to raise the first pump voltage to a level a second amount higher than the power supply voltage level, wherein the first number of signals is greater than the second number of signals, and the first amount is greater than the second amount.

[0030] According to an embodiment of the present invention, a charge pump circuit may include: a charge pump configured to generate a pump voltage using a power supply voltage in response to an operating clock, the charge pump including a plurality of pump stages configured to operate based on a plurality of pump control signals respectively; a first pump control signal generator configured to selectively enable pump control signals corresponding to a target level of the pump voltage; and a clock generator configured to change the frequency of the operating clock based on the number of enabled pump control signals.

[0031] The clock generator is configured to generate an operating clock with a first frequency based on the activation of a first number of pump control signals from a plurality of pump control signals, and to generate an operating clock with a second frequency based on the activation of a second number of pump control signals from a plurality of pump control signals. The first number may be greater than the second number, and the second frequency may be higher than the first frequency.

[0032] According to an embodiment of the present invention, a method for operating a semiconductor device is provided, the method comprising the steps of: generating a first pump voltage using a power supply voltage in response to an operating clock; generating an operating clock having a first frequency during an initial pumping period; generating an operating clock having a second frequency during a pumping period after the initial pumping period, the second frequency being lower than the first frequency and corresponding to the level of the first pump voltage; and using the first pump voltage to perform a predetermined internal operation.

[0033] The technical problems available in this disclosure are not limited to the embodiments described above, and other technical problems not described herein will be readily apparent to those skilled in the art from the following description. Attached Figure Description

[0034] Figure 1 An embodiment of a charge pump circuit is shown.

[0035] Figures 2A to 2C Show Figure 1 An example of the operation of a charge pump circuit.

[0036] Figure 3 An embodiment of a charge pump circuit is shown.

[0037] Figure 4 An embodiment of the first charge pump block is shown.

[0038] Figure 5 An implementation of the voltage comparator block is shown.

[0039] Figure 6 An implementation of the clock generation block is shown.

[0040] Figures 7A to 7C Show Figure 3 An example of the operation of a charge pump circuit.

[0041] Figure 8 An implementation of the pump stage is shown.

[0042] Figure 9A , Figure 9B and Figure 10 Show Figure 1 The operation of the charge pump circuit and Figure 3 An example of the differences between the operation of charge pump circuits.

[0043] Figure 11 An embodiment of a semiconductor device is shown. Detailed Implementation

[0044] Various examples of this disclosure are described in more detail below with reference to the accompanying drawings. However, aspects and features of the invention may be embodied in different ways to form other embodiments, including variations of any of the disclosed embodiments. Therefore, the invention is not limited to the embodiments set forth herein. Rather, the described embodiments are provided to make this disclosure thorough and complete, and to fully convey the disclosure to those skilled in the art to which this invention pertains. Throughout this disclosure, similar reference numerals denote similar parts throughout the various drawings and examples. It should be noted that references to “implementation,” “another embodiment,” etc., do not necessarily refer to only one embodiment, and different references to any such phrases do not necessarily refer to the same embodiment.

[0045] It will be understood that although the terms “first,” “second,” “third,” etc., may be used in this document to identify various elements, these elements are not limited by these terms. These terms are used to distinguish one element from another element that would otherwise have the same or similar name. Thus, a first element in one instance may be referred to as a second or third element in another instance without indicating any change in the element itself.

[0046] The accompanying drawings are not necessarily to scale, and in some cases, the scale may be exaggerated to clearly show the features of the embodiments. When an element is referred to as being connected to or coupled to another element, it should be understood that the former may be directly connected to or coupled to the latter, or electrically connected to or coupled to the latter via one or more intermediate elements between them. Additionally, it will be understood that when an element is referred to as being “between” two elements, it may be the only element between the two elements, or there may be one or more intermediate elements present.

[0047] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, unless the context clearly indicates otherwise, the singular form is intended to include the plural form, and vice versa. Similarly, unless it is clear from the language or context that it is intended to be only one, the indefinite article means one or more.

[0048] It will also be understood that, when used in this specification, the terms “comprising” and “including” specify the presence of the said element and do not exclude the presence or addition of one or more other elements. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0049] Unless otherwise defined, all terms used herein, including technical and scientific terms, shall have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains in view of this disclosure. It will also be understood that terms such as those defined in common dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and this disclosure, rather than in an idealized or overly formal sense, unless expressly so defined herein.

[0050] Numerous specific details are set forth in the following description in order to provide a thorough understanding of the invention. The invention may be practiced without some or all of these specific details. In other instances, well-known process structures and / or processes have not been described in detail so as not to unnecessarily obscure the invention.

[0051] It should also be noted that in some cases, it will be apparent to those skilled in the art that, unless otherwise specifically indicated, the features or elements described in connection with one embodiment may be used alone or in combination with other features or elements of another embodiment.

[0052] The embodiments of this disclosure are described in detail below with reference to the accompanying drawings, wherein similar reference numerals denote similar elements.

[0053] Figure 1 This diagram illustrates an embodiment of a charge pump circuit comprising N pump stages 11<1:N>, where N is 2 or greater. When generating a pump voltage VPUMP having a level slightly higher than the supply voltage VDD (e.g., within a first range), the charge pump circuit can use a relatively small number of the N pump stages 11<1:N>. When generating a pump voltage VPUMP having a level much higher than the supply voltage VDD (e.g., within a second range), the charge pump circuit can use a relatively large number of the N pump stages 11<1:N>.

[0054] When the target level of the pump voltage VPUMP to be generated is relatively low (e.g., below a predetermined level), the charge pump circuit according to this embodiment can operate a relatively small number of the N pump stages 11<1:N>. As a result, the charge pump circuit can have relatively low drive performance and relatively high efficiency. The larger the number N and / or the larger the number of pump stages operating among the N pump stages 11<1:N>, the greater the drive performance of the charge pump circuit, but the lower the operating efficiency of the charge pump circuit in terms of its ability to generate the target level of the pump voltage VPUMP.

[0055] Reference Figure 1 The charge pump circuit may include: a charge pump block 1 comprising N pump stages 11<1:N>, a control signal generation block (or control signal generator) 2, and a voltage comparator block (or voltage comparator) 3. Additionally, the charge pump block 1 may include a pump control unit (or pump controller) 12 and N power supply units 13<1:N>.

[0056] The charge pump block 1 can generate a pump voltage VPUMP in response to the pump power supply voltage VDD via an operating clock CLK. For example, the pump control unit 12 can generate N toggling control signals STGC<1:N> in response to the operating clock CLK, N pump control signals STG<1:N>, and an operating control signal PUMPON. The pump control unit 12 may include N AND gates AND<1:N>, each receiving one of the N pump control signals STG<1:N>, the operating control signal PUMPON, and the operating clock CLK to generate one of the corresponding N toggling control signals STGC<1:N>.

[0057] For example, when the first signal STG in N pump control signals STG<1:N> <1> When the operation control signal PUMPON is enabled and the operation clock CLK switches, the first signal STGC among the N switching control signals STGC<1:N> is... <1> This can be considered as being in an enabled state. In one example, when the second signal STG in N pump control signals STG<1:N>... <2> When any of the operation control signals PUMPON is disabled, the second signal STGC among the N switching control signals STGC<1:N> <2> It can be considered to be in a disabled state.

[0058] The operation of N pump stages 11<1:N> can be selected in response to N switching control signals STGC<1:N>. For example, the pump stage corresponding to the switching control signal in the enabled state is operable, and the pump stage corresponding to the switching control signal in the disabled state is not operable. As the number of pump stages operating among the N pump stages 11<1:N> increases, the level of the pump voltage VPUMP can increase to a level much higher than the level of the power supply voltage VDD (e.g., higher than a first predetermined amount). Conversely, as the number of pump stages operating decreases, the level of the pump voltage VPUMP can increase to a level slightly higher than the level of the power supply voltage VDD (e.g., higher than a second predetermined amount, lower than the first predetermined amount). Implementation of each of the N pump stages 11<1:N> is described below. Figure 8 To describe.

[0059] Each of the N pump stages 11<1:N> can operate according to a pair of complementary clocks with inverted phases. For example, each of the N pump stages 11<1:N> can generate the output stage voltage by pumping the input stage voltage according to the operating clock CLK and the inverted clock CLKB of the operating clock CLK. In this case, the operating clock CLK and the inverted clock CLKB can have inverted phases and the same period.

[0060] In one embodiment, each of the N pump stages 11<1:N> may include a first transistor M1 to a fourth transistor M4 and a first capacitor C1 and a second capacitor C2. The first transistor M1 may be connected between the input stage and another stage of the first capacitor C1, and may have a gate for receiving an inverted clock CLKB transmitted via the second capacitor C2. The second transistor M2 may be connected between the input stage and another stage of the second capacitor C2, and may have a gate for receiving an operating clock CLK transmitted via the first capacitor C1. The third transistor M3 may be connected between another stage of the first capacitor C1 and the output stage, and may have a gate for receiving an inverted clock CLKB transmitted via the second capacitor C2. The fourth transistor M4 may be connected between another stage of the second capacitor C2 and the output stage, and may have a gate for receiving an operating clock CLK transmitted via the first capacitor C1. The first transistor M1 and the second transistor M2 may be configured as NMOS transistors, and the third transistor M3 and the fourth transistor M4 may be configured as PMOS transistors. In another embodiment, the transistors may have different combinations of conductivity.

[0061] N power supply units 13<1:N> can each supply the power supply voltage VDD as N supply voltages VS<1:N> to N pump stages 11<1:N> in response to N pump control signals STG<1:N>. In one embodiment, the N power supply units 13<1:N> may each include N NMOS transistors MN<1:N>. The N NMOS transistors may have drains connected to the power supply voltage VDD and can output the N supply voltages VS<1:N> to the N pump stages 11<1:N> through their sources in response to the N pump control signals STG<1:N> input to their respective gates.

[0062] Control signal generation block 2 can generate N pump control signals STG<1:N> in response to the operation signals STAGE_UP, STAGE_DN, and PUMP_EN. For example, when the pump operation signal PUMP_UP is enabled, control signal generation block 2 can increase the number of enabled control signals (among the N pump control signals STG<1:N>) in response to the upward operation signal STAGE_UP being switched. When the pump operation signal PUMP_UP is enabled, control signal generation block 2 can decrease the number of enabled control signals among the N pump control signals STG<1:N> in response to the downward operation signal STAGE_DN being switched. When the pump operation signal PUMP_UP is disabled, control signal generation block 2 can disable all N pump control signals STG<1:N>.

[0063] In one implementation, the operation signals STAGE_UP, STAGE_DN, and PUMP_EN can be signals input from a source external to the charge pump circuit. For example, assuming the charge pump circuit is included in a semiconductor device, the operation signals STAGE_UP, STAGE_DN, and PUMP_EN can be generated by a mode register set (MRS) in the semiconductor device.

[0064] Control signal generation block 2 can enable a relatively large number (e.g., more than a predetermined number) of the N pump control signals STG<1:N> to raise the pump voltage VPUMP level to a level much higher than the power supply voltage VDD level. Alternatively, control signal generation block 2 can enable a relatively small number of the N pump control signals STG<1:N> to raise the pump voltage VPUMP level to a level slightly higher than the power supply voltage VDD level.

[0065] Voltage comparator 3 compares the pump voltage VPUMP generated by charge pump block 1 with the pump reference voltage level VREFP and generates an operation control signal PUMPON. For example, when the pump voltage VPUMP generated by charge pump block 1 is lower than the pump reference voltage level VREFP, voltage comparator 3 enables the operation control signal PUMPON. When the pump voltage VPUMP generated by charge pump block 1 is higher than the pump reference voltage level VREFP, voltage comparator 3 disables the operation control signal PUMPON. The pump reference voltage level VREFP can be set, for example, in a bandgap circuit that can maintain the target level regardless of changes in process, voltage, and temperature (PVT).

[0066] Figures 2A to 2C It is shown Figure 1 A diagram illustrating an example of the operation of a charge pump circuit.

[0067] Reference Figure 2A It can be seen how the driving performance varies depending on the level of the pump voltage VPUMP generated by the charge pump circuit and the number of pump stages used (e.g., active or in operation) among the N pump stages 11<1:N> in charge pump block 1.

[0068] For example, when using one pump stage (stage 1) out of N pump stages 11<1:N>, a pump voltage VPUMP of the same level is generated even with relatively lower drive performance compared to using two of its pump stages (stage 2). Similarly, when using two pump stages (stage 2) out of N pump stages 11<1:N>, a pump voltage VPUMP of the same level is generated even with relatively lower drive performance compared to using three of its pump stages (stage 3).

[0069] Reference Figure 2BIt can be seen that the efficiency varies depending on the level of the pump voltage VPUMP generated by the charge pump circuit and the number of pump stages used among the N pump stages 11<1:N>.

[0070] For example, when the pump voltage VPUMP level is relatively low, using two pump stages (2 stages) out of N pump stages 11<1:N> can have higher efficiency than using three pump stages (3 stages). Furthermore, using one pump stage (1 stage) can have higher efficiency than using its two stages (2 stages).

[0071] However, as the pump voltage VPUMP level increases, when using one pump stage (stage 1) out of N pump stages 11<1:N>, the efficiency decreases more rapidly compared to using two pump stages (stage 2). Furthermore, the efficiency decreases more rapidly when using two pump stages (stage 2) compared to using three pump stages (stage 3).

[0072] Reference Figure 2A and Figure 2B Compared to using two pump stages (2 stages), the pump voltage VPUMP can rise to a lower level when using one of N pump stages 11<1:N> (1 stage). Furthermore, compared to using three pump stages (3 stages), the pump voltage VPUMP can rise to a lower level when using two of N pump stages 11<1:N> (2 stages). In other words, when the number of activated or used pump stages is small, the target level of the pump voltage VPUMP may not be achieved. Therefore, the higher the target level of the pump voltage VPUMP, the larger the number of pump stages used. However, in some cases, when the target level of the pump voltage VPUMP is relatively low, it may be desirable to reduce the number of pump stages used.

[0073] Therefore, when a pump voltage VPUMP is generated that is slightly higher than the supply voltage VDD (e.g., higher than the first level), Figure 1 The charge pump circuit shown can be operated using a relatively small number of N pump stages 11<1:N>. When generating a pump voltage VPUMP with a level much higher than the supply voltage VDD (e.g., a second level higher than the first level), the charge pump circuit can be operated using a relatively large number of N pump stages 11<1:N>.

[0074] Reference Figure 2C , showing Figure 1The illustration shows an example of how the drive performance and efficiency of a charge pump circuit can vary depending on the frequency of the operating clock CLK. Here, it can be seen that the charge pump circuit generates the target pump voltage VPUMP with relatively high efficiency because relatively low drive performance is used when the frequency of the operating clock CLK is relatively low. In one embodiment, a low frequency of the operating clock CLK may indicate that generating the pump voltage VPUMP takes a relatively long time.

[0075] However, as the frequency of the operating clock CLK increases, the drive performance used to generate the target pump voltage VPUMP increases, thus reducing efficiency. In one embodiment, a high frequency of the operating clock CLK can indicate that the generation of the pump voltage VPUMP takes relatively little time. The terms high frequency and low frequency can be predetermined frequencies relative to each other and / or determined based on the intended application.

[0076] Figure 3 This is a diagram illustrating an implementation of a charge pump circuit. Figure 4 It is shown Figure 3 A diagram illustrating an embodiment of the first charge pump block of the charge pump circuit shown. Figure 5 It is shown Figure 3 A diagram illustrating an implementation of the voltage comparison block (or comparator) of the charge pump circuit.

[0077] Reference Figure 3 The charge pump circuit includes N pump stages 41<1:N>. When a first pump voltage VPUMP1 is generated that is slightly higher than the supply voltage VDD (e.g., higher than a first quantity), the charge pump circuit can use a relatively small number of the N pump stages 41<1:N> and can operate a relatively small number of pump stages in response to an operating clock CLK with a relatively high frequency. Conversely, when a first pump voltage VPUMP1 is generated that is much higher than the supply voltage VDD (e.g., higher than a second quantity), the charge pump circuit can use a relatively large number of pump stages 41<1:N> and can operate a relatively large number of pump stages in response to an operating clock CLK with a relatively low frequency. The first and second quantities can be predetermined quantities, for example, determined based on the intended application.

[0078] Therefore, when the target level of the first pump voltage VPUMP1 to be generated is relatively low, according to this embodiment, the charge pump circuit can operate a relatively small number of pump stages out of N pump stages 41<1:N>, thus achieving relatively low drive performance and relatively high efficiency. However, simultaneously, the charge pump circuit can use an operating clock CLK with a relatively high frequency, thus achieving relatively high drive performance, relatively low efficiency, and relatively high drive speed. In some cases, the reduction in drive performance and increase in efficiency achieved by operating a relatively small number of pump stages out of N pump stages 41<1:N> can be almost similar to the increase in drive performance and decrease in efficiency achieved by using a relatively high frequency. Therefore, the two effects can cancel each other out. However, the effect of increasing drive speed due to the relatively high frequency can remain unchanged.

[0079] Furthermore, when the target level of the first pump voltage VPUMP1 to be generated is relatively high, according to this embodiment, the charge pump circuit can operate a relatively large number of pump stages out of N pump stages 41<1:N>, thus achieving relatively high drive performance and relatively low efficiency. However, simultaneously, the charge pump circuit can use an operating clock CLK with a relatively low frequency, thus achieving relatively low drive performance, relatively high efficiency, and relatively low drive speed. In some cases, the increase in drive performance and decrease in efficiency achieved by operating a relatively large number of pump stages out of N pump stages 41<1:N> can be almost similar to the decrease in drive performance and increase in efficiency achieved by using a relatively low frequency. Therefore, the two effects can cancel each other out.

[0080] The drive speed may be reduced due to the use of a relatively low frequency, but the target level of the first pump voltage VPUMP1 can be limited to a relatively high period. Therefore, the impact of the reduced drive speed on the overall performance of the charge pump circuit can be reduced or minimized. Here, "N" can be a natural number equal to or greater than 2.

[0081] Reference Figure 3 The charge pump circuit may include: a first charge pump block 4 comprising N pump stages 41<1:N>, a first pump control signal generation block 5, a clock generation block 6, and a voltage comparison block 7.

[0082] The first charge pump block 4 can pump the power supply voltage VDD in response to the operating clock CLK, and can generate the first pump voltage VPUMP1. Whether the N pump stages 41<1:N> are in operation (or active) can be selected in response to the N first pump control signals STG<1:N> respectively.

[0083] The first pump control signal generation block 5 can enable a relatively large number of the N first pump control signals STG<1:N> to raise the level of the first pump voltage VPUMP1 to a level much higher than the power supply voltage VDD. Alternatively, the first pump control signal generation block 5 can enable a relatively small number of the N first pump control signals STG<1:N> to raise the level of the first pump voltage VPUMP1 to a level slightly higher than the power supply voltage VDD.

[0084] Furthermore, the first pump control signal generation block 5 can enable N first pump control signals STG<1:N> in a predetermined order, and can deactivate N first pump control signals STG<1:N> in the reverse order of the predetermined order. For example, the first pump control signal generation block 5 can operate the first pump stage 41 among the N pump stages 41<1:N>. <1> Then operate the second pump stage 41 <2> The sequence of operations is as follows: Each of the N pump stages 41<1:N> is operated sequentially. In this case, the first pump control signal generation block 5 can activate the first first pump control signal STG among the N first pump control signals STG<1:N>. <1> Then activate the second first pump control signal STG. <2> The sequence of the N first pump control signals STG<1:N> is used to enable each of them. The first pump control signal generation block 5 can deactivate each of the N pump control signals STG<1:N> in the reverse order of their enabling sequence.

[0085] Clock generation block 6 can change the frequency of the operating clock CLK based on the number of enabled signals among the N first pump control signals STG<1:N> generated by first pump control signal generation block 5. For example, when the number of enabled signals among the N first pump control signals STG<1:N> is relatively large, clock generation block 6 can generate the operating clock CLK with a relatively low frequency. When the number of enabled signals among the N first pump control signals STG<1:N> is relatively small, clock generation block 6 can generate the operating clock CLK with a relatively high frequency. In response to the clock generation signal OCS_EN being enabled, clock generation block 6 can generate (e.g., switch) the operating clock CLK. At this time, the clock generation signal OCS_EN can be input from a source outside the charge pump circuit. For example, assuming the charge pump circuit is in a semiconductor device, the clock generation signal OCS_EN can be generated by the mode register set (MRS) in the semiconductor device.

[0086] Voltage comparator 7 compares the level of the first pump voltage VPUMP1 (generated by the first charge pump block 4) with the pump reference voltage level VREFP and generates an operation control signal PUMPON. For example, when the level of the first pump voltage VPUMP1 is lower than the pump reference voltage level VREFP, voltage comparator 7 enables the operation control signal PUMPON. When the level of the first pump voltage VPUMP1 is higher than the pump reference voltage level VREFP, voltage comparator 7 disables the operation control signal PUMPON. The pump reference voltage level VREFP can be set, for example, in a bandgap circuit that can maintain the target level regardless of process, voltage, and temperature (PVT) variations. For example, the bandgap circuit can be outside the charge pump circuit; for example, assuming the charge pump circuit is in a semiconductor device, the bandgap circuit can be one of the components in the semiconductor device.

[0087] Reference Figure 3 and Figure 4 The first charge pump block 4 may include N pump stages 41<1:N>, second pump control signal generation units (or generators) 421 and 422<1:N>, N power supply units 43<1:N>, and a pump control unit (or controller) 44. Additionally, the second pump control signal generation units 421 and 422<1:N> may include a second charge pump unit 421 and N shift units 422<1:N>.

[0088] The pump control unit 44 can generate N switching control signals STGC<1:N> in response to the operating clock CLK, N first pump control signals STG<1:N>, and the operating control signal PUMPON. The pump control unit 44 may include N AND gates AND<1:N>, each receiving one of the N first pump control signals STG<1:N>, the operating control signal PUMPON, and the operating clock CLK, and generating one of the N switching control signals STGC<1:N> accordingly. For example, when the operating control signal PUMPON is enabled and the first signal STG<1:N> is one of the N first pump control signals STG<1:N>... <1> When the simultaneous operation clock CLK is switched, the first signal STGC among the N switching control signals STGC<1:N> is enabled. <1> It can be in the enabled state. The first enable signal is STGC. <1> It can switch at the same frequency as the operating clock CLK.

[0089] In one implementation, when the operation control signal PUMPON is enabled and the second signal STG is one of the N first pump control signals STG<1:N> <2> When disabled, the second signal STGC in the N switching control signals STGC<1:N> <2> It can be considered to be in a disabled state, regardless of whether the operating clock CLK is switched.

[0090] In one implementation, when the operation control signal PUMPON is disabled, all N switching control signals STGC<1:N> can be considered to be disabled, regardless of whether each of the N first pump control signals STG<1:N> is enabled or the operation clock CLK is switched.

[0091] Whether the N pump stages 41<1:N> are operational can be selected in response to the N switching control signals STGC<1:N>. For example, the pump stage corresponding to the signal in the enabled state (among the N switching control signals STGC<1:N>) is operational, and the pump stage corresponding to the signal in the disabled state (among the N switching control signals STGC<1:N>) is not operational. As the number of operational pump stages among the N pump stages 41<1:N> increases, the level of the first pump voltage VPUMP1 can rise to a level much higher than the supply voltage VDD. Conversely, as the number of operational pump stages among the N pump stages 41<1:N> decreases, the level of the first pump voltage VPUMP1 can rise to a level slightly higher than the supply voltage VDD. Implementation details for each of the N pump stages 41<1:N> are as follows. Figure 8 To describe.

[0092] Each of the N pump stages 41<1:N> can operate according to a pair of complementary clocks with inverted phases. For example, each of the N pump stages 41<1:N> can generate the output stage voltage by pumping the voltage of the input stage according to the operating clock CLK and the inverted clock CLKB of the operating clock CLK. In this case, the operating clock CLK and the inverted clock CLKB can have inverted phases and the same period.

[0093] For example, each of the N pump stages 41<1:N> may include a first transistor M1 to a fourth transistor M4 and a first capacitor C1 and a second capacitor C2. The first transistor M1 may be connected between the input stage and another stage of the first capacitor C1, and may have a gate for receiving an inverted clock CLKB transmitted through the second capacitor C2. The second transistor M2 may be connected between the input stage and another stage of the second capacitor C2, and may have a gate for receiving an operating clock CLK transmitted through the first capacitor C1. The third transistor M3 may be connected between another stage of the first capacitor C1 and the output stage, and may have a gate for receiving an inverted clock CLKB transmitted through the second capacitor C2. The fourth transistor M4 may be connected between another stage of the second capacitor C2 and the output stage, and may have a gate for receiving an operating clock CLK transmitted through the first capacitor C1. In one embodiment, the first transistor M1 and the second transistor M2 may be configured as NMOS transistors, and the third transistor M3 and the fourth transistor M4 may be configured as PMOS transistors. In another embodiment, these transistors may have different conductivities.

[0094] The second pump control signal generating units 421 and 422<1:N> can have the same activation period as the N first pump control signals STG<1:N>, and can generate N second pump control signals STGL<1:N> with activation levels relatively higher than the N first pump control signals STG<1:N>. For example, when the N first pump control signals STG<1:N> have activation periods corresponding to the power supply voltage VDD, the N second pump control signals STGL<1:N> have activation periods corresponding to levels higher than the power supply voltage VDD.

[0095] The second charge pump unit 421 in the second pump control signal generation units 421 and 422<1:N> can pump the power supply voltage VDD in response to the operating clock CLK and can generate a second pump voltage VPUMP2. In this case, the second charge pump unit 421 may not have a shape including multiple pump stages 41<1:N> like the first charge pump block 4; for example, the second charge pump unit 421 may include only one pump stage. Additionally, the second pump voltage VPUMP2 can be input from an external device. In this case, the second charge pump unit 421 can be excluded from the second pump control signal generation units 421 and 422<1:N>.

[0096] The N shift units 422<1:N> in the second pump control signal generation units 421 and 422<1:N> can respectively level-shift the enable level of the N first pump control signals STG<1:N> sent to the N pump stages 41<1:N>. The enable level can be level-shifted to correspond to the level of the second pump voltage VPUMP2. The level-shifted N first pump control signals STG<1:N> can then be output as N second pump control signals STGL<1:N>. For example, when the N first pump control signals STG<1:N> have an enable period corresponding to the level of the power supply voltage VDD, the N second pump control signals STGL<1:N> can have an enable period corresponding to the level of the second pump voltage VPUMP2, which is higher than the level of the power supply voltage VDD.

[0097] In response to one of the N second pump control signals STGL<1:N>, the N power supply units 43<1:N> can supply the power supply voltage VDD as N supply voltages VS<1:N> to the N pump stages 41<1:N> respectively. The N power supply units 43<1:N> may include N NMOS transistors MN<1:N>, each N NMOS transistor MN<1:N> having a drain connected to the power supply voltage VDD and a source that supplies the N supply voltages VS<1:N> to the N pump stages 41<1:N> in response to the N second pump control signals STGL<1:N> input to the respective gates of the N N NMOS transistors MN<1:N>.

[0098] Assuming that N power supply units 43<1:N> comprise a corresponding one of N N MOS transistors MN<1:N>, each of N second pump control signals STGL<1:N> with an enable level higher than the power supply voltage VDD can be input to the gate. Therefore, the N power supply units 43<1:N> can transfer the power supply voltage from the drain to the source of their respective transistors. In other words, due to the characteristics of NMOS transistors, the level of the voltage applied to their gate can be obtained by combining the level of the voltage transferred from their drain to their source with the level of their threshold voltage. Therefore, the level of the voltage applied to the gate can be higher than the power supply voltage VDD by the level of the threshold voltage, so that the level of the voltage transferred from their drain to their source corresponds to the level of the power supply voltage VDD. In one embodiment, the level of the second pump voltage VPUMP2 can be higher than the level of the power supply voltage VDD by the level of the threshold voltage of the NMOS transistor.

[0099] As described above, since the second pump control signal generation units 421 and 422<1:N> are in the first charge pump block 4, therefore Figure 3 The charge pump circuit shown can be used with Figure 1 The charge pump circuits shown operate differently, for example, as referenced below. Figure 9A and Figure 9B As described.

[0100] Figure 9A Show Figure 1 In the charge pump circuit disclosed herein, the power supply voltage VDD is directly supplied to each of the N pump stages 41<1:N>.

[0101] Figure 9B Show Figure 3 The charge pump circuit disclosed herein applies N second pump control signals STGL<1:N>, and the level of the second pump voltage VPUMP2 is higher than the level of the power supply voltage VDD supplied to the N pump stages 41<1:N> respectively.

[0102] Reference Figure 9A and Figure 9B And in these examples, it is assumed that "N" is 3, when there is only one control signal STG <1> When enabled, a voltage level lower than the supply voltage VDD (e.g., the level of the low threshold voltage) can be supplied (VS). <1> ) to the first pump stage 11 <1> ,like Figure 9A As shown. On the other hand, as Figure 9B As shown, a voltage with a supply voltage level of VDD can be supplied (VS). <1> ) to the first pump stage 41 <1> .

[0103] Subsequently, when the two control signals STG<1:2> are enabled, a voltage level lower than the supply voltage VDD by a threshold voltage level can be supplied (VS). <2> ) to the second pump stage 11 <2> ,like Figure 9A As shown. At this time, the first pump stage 11 <1> It can perform the operation of doubling the level of the supplied voltage (VS) <1> However, because the supplied voltage level is lower than the supply voltage VDD level, the voltage from the first pump stage 11... <1> The output voltage (e.g., the level of the pump voltage VPUMP) is less than the level of the voltage obtained by doubling the supply voltage VDD.

[0104] exist Figure 9B In this context, a voltage with the level of the power supply voltage VDD can be supplied (VS). <2> ) to the second pump stage 41 <2> Additionally, due to the supply to the first pump stage 41 <1> The voltage level has the same level as the power supply voltage VDD, so from the first pump stage 41 <1> The output voltage (e.g., the first pump voltage VPUMP1) has a voltage level obtained by doubling the supply voltage VDD.

[0105] When the three control signals STG<1:3> are enabled, a voltage level lower than the supply voltage VDD (e.g., the low threshold voltage level) can be supplied in [A] (VS). <3> ) to the third pump stage 11 <3> The first and second pump stages 11<1:2> can each perform the operation of doubling the level of the supplied voltage (VS<1:2>). However, since the respective levels of the supplied voltage are lower than the supply voltage VDD, the voltage level from the second pump stage 11... <2> The output voltage is lower than the level obtained by doubling the supply voltage VDD. Additionally, from the first pump stage 11... <1> The output voltage (e.g., the level of the pump voltage VPUMP) is lower than the level of the voltage obtained by tripling the supply voltage VDD.

[0106] On the other hand, Figure 9B In this context, a voltage with the level of the power supply voltage VDD can be supplied (VS). <3> ) to the third pump stage 41 <3> Since the voltage levels supplied to the first and second pump stages 41<1:2> respectively have the level of the power supply voltage VDD, the voltage from the second pump stage 41... <2> The output voltage has a level obtained by doubling the supply voltage VDD. Additionally, from the first pump stage 41... <1> The output voltage (e.g., the first pump voltage VPUMP1) has the level of the voltage obtained by tripling the supply voltage VDD.

[0107] Therefore, since the second pump control signal generation units 421 and 422<1:N> are in the first charge pump block 4, Figure 3 The charge pump circuit is comparable to Figure 1 The charge pump circuit increases the level of the first pump voltage VPUMP1 more quickly.

[0108] Reference Figure 3 and Figure 5 The voltage comparison block 7 may include a voltage distribution unit (or voltage divider) 71 and an operation control signal generation unit (or generator) 72. The voltage distribution unit 71 may distribute the level of the first pump voltage VPUMP1 at a predetermined ratio and may generate a distribution voltage VDIV. For example, the voltage distribution unit 71 may include two resistors R1 and R2 connected in series between the first pump voltage VPUMP1 level and the ground voltage VSS level, and may output a voltage (applied across node ND1 between the two resistors R1 and R2) as the distribution voltage VDIV. The predetermined ratio may be determined, for example, based on the ratio of the resistance values ​​of the two resistors R1 and R2. In one embodiment, the resistance values ​​of the two resistors R1 and R2 may vary, for example, depending on the intended application.

[0109] The operation control signal generation unit 72 may include a first voltage comparator CP1, which compares the level of the distribution voltage VDIV generated by the voltage distribution unit 71 with the pump reference voltage level VREFP, and determines whether to enable the operation control signal PUMPON based on the comparison result. For example, when the level of the distribution voltage VDIV generated by the voltage distribution unit 71 is higher than the pump reference voltage level VREFP, the operation control signal generation unit 72 can disable the operation control signal PUMPON and output a disabled operation control signal PUMPON. Furthermore, when the level of the distribution voltage VDIV generated by the voltage distribution unit 71 is lower than the pump reference voltage level VREFP, the operation control signal generation unit 72 can enable the operation control signal PUMPON and output an enabled operation control signal PUMPON.

[0110] Figure 6 It is shown Figure 3 A diagram illustrating an embodiment of the clock generation block (or clock generator) 6 of the charge pump circuit shown.

[0111] Reference Figure 6 The clock generation block 6 may include a drive operation unit 61, a feedback signal generation unit 62, and a clock output unit 63. The drive operation unit 61 can generate a drive operation voltage VRE in response to N first pump control signals STG<1:N>, a feedback signal FDS, and a clock generation signal OCS_EN. For example, the drive operation unit 61 can increase or decrease the level of the drive operation voltage VRE in response to the feedback signal FDS, and can adjust the rate at which the level of the drive operation voltage VRE decreases according to the number of enabled signals among the N first pump control signals STG<1:N>. Additionally, the drive operation unit 61 can fix the level of the drive operation voltage VRE to a predetermined level in response to the clock generation signal OCS_EN.

[0112] In one embodiment, the drive operation unit 61 may include a PMOS transistor DP1, a current regulating element 611, a first NMOS transistor DN1, and a second NMOS transistor DN2 connected in series between the power supply voltage VDD level and the ground voltage VSS level. The voltage at node ND2 between the PMOS transistor DP1 and the current regulating element 611 can be output as the drive operation voltage VRE.

[0113] In operation, the PMOS transistor DP1 can switch the connection between the power supply voltage VDD (connected to the source of the transistor) and the drive operating voltage VRE ND2 (connected to the drain of the transistor) in response to the feedback signal FDS input to the gate of the transistor.

[0114] The current regulating element 611 can regulate the amount of current flowing from the drive operating voltage VRE level ND2 (connected to its input) to the drain of the first NMOS transistor DN1 (connected to its output) in response to N first pump control signals STG<1:N>. The first NMOS transistor DN1 can switch the connection between the output of the current regulating element 611 (connected to the drain of the transistor) and the drain of the second NMOS transistor DN2 (connected to its source) in response to the feedback signal FDS applied to its gate. The second NMOS transistor DN2 can switch the connection between the source of the first NMOS transistor DN1 (connected to its drain) and the ground voltage VSS level (connected to its source) in response to the clock generation signal OCS_EN applied to its gate.

[0115] When the number of enabled signals among the N first pump control signals STG<1:N> is relatively large, the current regulating element 611 can relatively reduce the current flowing from the drive operating voltage VRE level ND2 to the drain of the first NMOS transistor DN1. Conversely, when the number of enabled signals among the N first pump control signals STG<1:N> is relatively small, the current regulating element 611 can relatively increase the current flowing from the drive operating voltage VRE level ND2 to the drain of the first NMOS transistor DN1.

[0116] The feedback signal generation unit 62 may include a second voltage comparator CP2 and a NAND gate. The second voltage comparator CP2 can compare the level of the drive operating voltage VRE (output from the drive operating unit 61) with the drive reference voltage level VREFC, and can determine whether to enable the pre-feedback signal pFDS based on the comparison result. The NAND gate can output the pre-feedback signal pFDS as the feedback signal FDS in response to the clock generation signal OCS_EN.

[0117] For example, when the level of the drive operation voltage VRE output from the drive operation unit 61 is lower than the drive reference voltage level VREFC, the feedback signal generation unit 62 can enable the feedback signal FDS to a logic high level and output the enabled feedback signal FDS. Conversely, when the level of the drive operation voltage VRE output from the drive operation unit 61 is higher than the drive reference voltage level VREFC, the feedback signal generation unit 62 can disable the feedback signal FDS to a logic low level and output the disabled feedback signal FDS.

[0118] Clock output unit 63 may output a feedback signal FDS (output from feedback signal generation unit 62) as an operating clock CLK. For example, clock output unit 63 may include a trigger for changing the operating clock CLK in response to a predetermined (e.g., rising) edge of the feedback signal FDS output from feedback signal generation unit 62.

[0119] Figures 7A to 7C It is shown Figure 3 A diagram illustrating an example of the operation of a charge pump circuit.

[0120] Reference Figure 7A When a relatively small number of the N first pump control signals STG<1:N> are enabled, an operating clock CLK with a relatively high frequency is used. When a relatively large number of the N first pump control signals STG<1:N> are enabled, an operating clock CLK with a relatively low frequency is used.

[0121] Assuming "N" is 3, it can be seen that in the three first pump control signals STG<1:3>, the first first pump control signal STG <1> When enabled, the operating clock CLK is used with the highest frequency, fCLK1. Additionally, it can be seen that when all three first pump control signals STG<1:3> are enabled, the operating clock CLK is used with the lowest frequency, fCLK3. Furthermore, when the first and second first pump control signals STG<1:2> of the three first pump control signals STG<1:3> are enabled, the operating clock CLK is used with a relatively medium (or intermediate) frequency, fCLK2.

[0122] Reference Figure 7B The driving performance varies depending on the level of the first pump voltage VPUMP1 generated as a result of the operation of the charge pump circuit and the number of pump stages used among the N pump stages 41<1:N> in the first charge pump block 4. For example, when using one pump stage (stage 1) of the N pump stages 41<1:N>, a first pump voltage VPUMP1 with the same level is generated even with a relatively lower driving performance compared to using two pump stages (stage 2). When using two pump stages (stage 2) of the N pump stages 41<1:N>, a first pump voltage VPUMP1 with the same level is generated even with a relatively lower driving performance compared to using three pump stages (stage 3).

[0123] Reference Figure 7C It can be seen how the efficiency varies depending on the level of the first pump voltage VPUMP1 generated as a result of the operation of the charge pump circuit and the number of pump stages used among the N pump stages 41<1:N> in the first charge pump block 4. For example, when the level of the first pump voltage VPUMP1 is relatively low, using two pump stages (stage 2) out of the N pump stages 41<1:N> has higher efficiency than using three pump stages (stage 3). In addition, using one pump stage (stage 1) has higher efficiency than using two pump stages (stage 2).

[0124] However, as the level of the first pump voltage VPUMP1 increases, the efficiency decreases more rapidly when using one pump stage (1 stage) out of N pump stages 41<1:N> compared to using two pump stages (2 stages). Furthermore, the efficiency decreases more rapidly when using two pump stages (2 stages) compared to using three pump stages (3 stages).

[0125] Reference Figure 7B and Figure 7C When using one pump stage (stage 1) out of N pump stages 41<1:N>, the increase in the level of the first pump voltage VPUMP1 is lower than when using two of its pump stages (stage 2). Furthermore, when using two pump stages (stage 2) out of N pump stages 41<1:N>, the increase in the level of the first pump voltage VPUMP1 is lower than when using three of its pump stages (stage 3). In other words, when the number of pump stages used out of the N pump stages 41<1:N> is small, the first pump voltage VPUMP1 may not reach the target level. Therefore, as the target level of the first pump voltage VPUMP1 increases, the number of pump stages used can be increased. However, in some cases, it may be preferable to relatively reduce the number of pump stages used when the target level of the first pump voltage VPUMP1 is relatively low.

[0126] Therefore, when the first pump voltage VPUMP1 generates a level slightly higher than the supply voltage VDD, Figure 3 The charge pump circuit shown can be operated using a relatively small number of the N pump stages 41<1:N>. When a first pump voltage VPUMP1 with a level much higher than the supply voltage VDD is generated, the charge pump circuit can be operated using a relatively large number of the N pump stages 41<1:N>.

[0127] The following descriptions compare Figure 2A and Figure 2B and Figure 7B and Figure 7C Based on this comparison, Figure 2A The performance fluctuation curves of the drive when using one pump stage (stage 1), two pump stages (stage 2), and three pump stages (stage 3) out of N pump stages (11<1:N>) are compared with those of the above. Figure 7B The fluctuation curves of drive performance are basically similar when using one pump stage (stage 1) of N pump stages 41<1:N>, using two pump stages (stage 2), and using three pump stages (stage 3).

[0128] in addition, Figure 2B The efficiency fluctuation curves are shown for using one pump stage (stage 1), two pump stages (stage 2), and three pump stages (stage 3) out of N pump stages (1:N). Figure 7C The efficiency fluctuation curves are basically similar when using one pump stage (stage 1) of N pump stages 41<1:N>, using two of its pump stages (stage 2), and using three of its pump stages (stage 3).

[0129] exist Figure 7C In this context, while the level of the first pump voltage VPUMP1 is relatively low, an operating clock CLK with a relatively high frequency can be used. Conversely, while the level of the first pump voltage VPUMP1 is relatively high, an operating clock CLK with a relatively low frequency can be used. On the other hand, in... Figure 2B In this case, regardless of the pump voltage VPUMP level, an operating clock CLK with a constant frequency can be used.

[0130] Therefore, while the level of the first pump voltage VPUMP1 is relatively low, Figure 3 The charge pump circuit can have a relatively higher Figure 1 The driving speed of the charge pump circuit. While the first pump voltage VPUMP1 is relatively high, Figure 3 The charge pump circuit can have a relatively lower Figure 1 The driving speed of the charge pump circuit.

[0131] However, due to Figure 3 The charge pump circuit has a relatively high drive speed during periods when the first pump voltage VPUMP1 is relatively low. Therefore, when the charge pump circuit has a relatively low drive speed during periods when the first pump voltage VPUMP1 is relatively high, the impact on the overall performance of the charge pump circuit can be reduced or minimized. Figure 3 In a charge pump circuit, according to one implementation, N first pump control signals STG<1:N> can be configured according to... Figure 9B Enabled in the same way, for example, by initially enabling the first pump control signal STG. <1> Then, the second to the Nth first pump control signals STG<1:N> can be activated sequentially. Therefore, when Figure 3 When the target level of the first pump voltage VPUMP1 in the charge pump circuit is very high, the charge pump circuit can operate to initially rapidly increase (e.g., at a first rate) the level of the first pump voltage VPUMP1, and then slowly increase (e.g., at a second rate less than the first rate) the level of the first pump voltage VPUMP1. This can be represented in the following... Figure 10 The curve is shown in the graph. Therefore, it can be seen that the level of the first pump voltage VPUMP1 is comparable to... Figure 1 The charge pump circuit reaches the target level faster.

[0132] Reference Figure 10 It can be seen that Figure 1The operation of the charge pump circuit is indicated by dashed lines, and Figure 3 The operation of the charge pump circuit is indicated by solid lines.

[0133] Reference Figure 10 ,Depend on Figure 3 The rise rate of the first pump voltage VPUMP1 generated by the charge pump circuit is greater than that of the voltage generated by the charge pump circuit. Figure 1 The rate of rise of the pump voltage VPUMP generated by the charge pump circuit.

[0134] Specifically, for Figure 1 In the charge pump circuit, because the frequency of the operating clock CLK is always constant, the pump voltage VPUMP can rise at a first predetermined rate until a certain time point. (that is, at a certain point in time) Afterwards, the pump voltage VPUMP level has risen to a certain level. Here, the time point... This corresponds to the start of operation of the charge pump circuit. The pump voltage VPUMP level can be determined at the point when the pump voltage VPUMP has risen to a certain level. It then rises at a second predetermined rate (e.g., faster or greater than the first predetermined rate) until it reaches a certain point in time. The target level has been reached.

[0135] Therefore, it can be seen that, Figure 1 In the case of a charge pump circuit, since the frequency of the operating clock CLK is always constant, from time point... At the appointed time The amount of current used did not change significantly and remained within a specific range.

[0136] exist Figure 3 In the case of a charge pump circuit, the frequency of the operating clock CLK can initially be relatively high, and then later relatively low. Therefore, in Figure 3 In the case of a charge pump circuit, the level of the first pump voltage VPUMP1 can be determined from the point in time when the charge pump circuit begins operation. According to the ratio Figure 1 The charge pump circuit rises at a faster rate. The level of the first pump voltage VPUMP1 can be reached at a certain point in time. It then continues to rise at a similar rate until it reaches the target level.

[0137] Therefore, in Figure 3 In the case of a charge pump circuit, from time point The time point when the operating clock CLK frequency is relatively high The amount of current used increases very significantly. As a result, the level of the first pump voltage VPUMP1 can increase relatively rapidly, and at a point when the frequency of the operating clock CLK relatively decreases. The amount of current used is then significantly reduced. As a result, the level of the first pump voltage VPUMP1 can be increased relatively slowly.

[0138] At this time, Figure 3 In the case of a charge pump circuit, since the level of the first pump voltage VPUMP1 changes from time point... At the appointed time The level has increased significantly, so even if the level of the first pump voltage VPUMP1 increases at a certain rate at time point... Then decrease, the first pump voltage VPUMP1 can also be compared Figure 1 The charge pump circuit reaches the target level faster.

[0139] In addition, Figure 3 In the case of a charge pump circuit, from time point At the appointed time The amount of current used can be increased very significantly, therefore it is comparable to Figure 1 The charge pump circuit consumes more current. However, due to the time point... The amount of current used afterwards was greatly reduced, so it is comparable to Figure 1 The charge pump circuit consumes less current. In other words, it can be seen that in Figure 3 The total current used to achieve the target level of the first pump voltage VPUMP1 in the charge pump circuit is compared with that in Figure 1 The total current required to reach the target level of the pump voltage VPUMP in a charge pump circuit can be almost the same.

[0140] Figure 11 It shows including Figure 3 A diagram illustrating an embodiment of the semiconductor device 8 of the charge pump circuit (now labeled 81).

[0141] Reference Figure 11 The semiconductor device 8 may include a charge pump circuit 81 and internal circuitry 83. The charge pump circuit 81 may include a voltage generation circuit 812 and a clock generation circuit 814.

[0142] The charge pump circuit 81 included in the semiconductor device 8 can generate a first pump voltage VPUMP1 in response to an operating clock CLK. The charge pump circuit 81 can generate the first pump voltage VPUMP1 using an operating clock CLK that has a relatively high frequency during an initial operating period when the level of the first pump voltage VPUMP1 is relatively low, and a relatively low frequency after the initial operating period in response to a rise in the level of the first pump voltage VPUMP1.

[0143] In one embodiment, the voltage generating circuit 812 in the charge pump circuit 81 can pump the power supply voltage VDD in response to the operating clock CLK to generate a first pump voltage VPUMP1. The clock generating circuit 814 in the charge pump circuit 81 can generate an operating clock CLK with a relatively high frequency during an initial operating period when the level of the first pump voltage VPUMP1 generated by the voltage generating circuit 812 is relatively low. Then, after the initial operating period, the clock generating circuit 814 can generate the operating clock CLK by relatively decreasing the frequency of the operating clock CLK in response to an increase in the level of the first pump voltage VPUMP1.

[0144] Clock generation circuit 814 may include a first pump control signal generation block 5 and a clock generation block 6 (e.g., which may correspond to a reference). Figures 3 to 10 (Those discussed). Similarly, the voltage generating circuit 812 may include a first charge pump block 4 and a voltage comparison block 7 (e.g., which may correspond to a reference). Figures 3 to 10 Those described). In other words, Figures 3 to 10 The same labels used are applied Figure 11 The first charge pump block 4, voltage comparison block 7, first pump control signal generation block 5, and clock generation block 6 are shown, and their operation can also be the same.

[0145] Internal circuitry 83 in semiconductor device 8 may perform predetermined internal operations in response to a first pump voltage VPUMP1. For example, when semiconductor device 8 is a memory device (e.g., a non-volatile memory device), internal circuitry 83 may include a word line driver that operates using a high voltage.

[0146] According to one embodiment, an apparatus includes a storage region and one or more processors. The storage region can be any region within a non-transitory computer-readable medium, corresponding to any region of volatile or non-volatile memory. The storage region can store instructions for execution by one or more processors. The one or more processors can correspond to any signal processor or signal generating element of the embodiments described herein, including any signal generator, clock generator, comparator, shifter, and / or any other element of the disclosed embodiments.

[0147] When instructions in the memory area are executed by one or more processors, the processors may perform operations according to the embodiments described herein. For example, but not limited to, the processors may execute instructions to control the generation of different combinations of control signals to selectively enable different combinations of pump stages of the charge pump circuit described above based on the operating clock. In one embodiment, the processors may output a pump voltage based on one of the different combinations of control signals.

[0148] Additionally, one or more processors may execute instructions to set the operating clock to a first frequency based on enabling a first number of control signals, and to set the operating clock to have a second frequency based on enabling a second number of control signals, wherein the second frequency is higher than the first frequency.

[0149] Additionally, one or more processors may execute instructions to enable a first number of signals to raise the first pump voltage to a level a first amount higher than the supply voltage level, and to enable a second number of signals to raise the first pump voltage to a level a second amount higher than the supply voltage level, wherein the first number of signals is greater than the second number of signals, and the first amount is greater than the second amount.

[0150] The methods, processes, and / or operations described herein may be performed by code or instructions to be executed by a computer, processor, controller, or other signal processing device. The computer, processor, controller, or other signal processing device may be those described herein or other elements besides those described herein. Because the algorithms underlying the methods (or the operation of the computer, processor, controller, or other signal processing device) are described in detail, the code or instructions for implementing the operations of the method embodiments can transform a computer, processor, controller, or other signal processing device into a dedicated processor for executing the methods herein.

[0151] When implemented at least partially in software, controllers, processors, devices, modules, blocks, shifters, stages, comparators, internal circuits, units, multiplexers, generators, logic, interfaces, decoders, drivers, and other signal generation and signal processing features may include, for example, memory or other storage devices for storing, for example, code or instructions to be executed by a computer, processor, microprocessor, controller, or other signal processing device. The computer, processor, microprocessor, controller, or other signal processing device may be those described herein or other elements besides those described herein. Because the algorithms underlying the formation of the method (or the operation of the computer, processor, microprocessor, controller, or other signal processing device) are described in detail, the code or instructions for implementing the operations of the method implementation can transform the computer, processor, controller, or other signal processing device into a dedicated processor that performs the methods described herein.

[0152] According to one or more of the above embodiments, the charge pump circuit can generate a pump voltage with a level higher than the power supply voltage, and can operate using a clock whose frequency can vary according to the level of the pump voltage.

[0153] Additionally, the charge pump circuit can be operated using a clock signal (with a relatively high frequency when the pump voltage level is relatively lower than the supply voltage level) and a clock signal (with a relatively low frequency when the pump voltage level is relatively higher than the supply voltage level).

[0154] Therefore, the area occupied by the charge pump circuit can be reduced, while the operating efficiency and pump drive performance of the charge pump circuit can be significantly increased.

[0155] Although this disclosure has been shown and described with reference to specific embodiments and accompanying drawings, the disclosed embodiments are not intended to be limiting. Furthermore, it should be noted that those skilled in the art will recognize from this disclosure that it can be implemented in various ways through substitutions, changes, and modifications without departing from the spirit and / or scope of this disclosure. For example, the arrangement and type of logic gates and transistors described in the above embodiments can be implemented differently based on the polarity of the input signals. These embodiments can be combined to form additional embodiments.

[0156] Cross-reference to related applications

[0157] This application claims priority to Korean Patent Application No. 10-2021-0021981, filed on February 18, 2021, the entire disclosure of which is incorporated herein by reference.

Claims

1. A charge pump circuit, the charge pump circuit comprising: A first charge pump, which generates a first pump voltage using a power supply voltage in response to an operating clock, includes N pump stages that operate based on N second pump control signals, each of which has the same activation period as the N first pump control signals but has a higher activation level than the N first pump control signals, where N is a natural number equal to or greater than 2. A first pump control signal generator enables a first number of signals from the N first pump control signals to raise the level of the first pump voltage to a first amount higher than the level of the power supply voltage, and enables a second number of signals from the N first pump control signals to raise the level of the first pump voltage to a second amount higher than the level of the power supply voltage, wherein the first number of signals is greater than the second number of signals, and the first amount is greater than the second amount; and A clock generator that changes the frequency of the operating clock based on whether the number of enabled signals corresponds to a first number of signals or a second number of signals. Based on activating the first number of signals, an operating clock with a first frequency is generated, and Based on the activation of the second number of signals, an operating clock with a second frequency is generated, wherein the second frequency is higher than the first frequency.

2. The charge pump circuit according to claim 1, wherein, The first charge pump includes: A second pump control signal generator, which generates the N second pump control signals in response to the N first pump control signals; and N power supplies, each responding to one of the N second pump control signals, supply power voltage as the operating power of the N pump stages.

3. The charge pump circuit according to claim 2, wherein, The second pump control signal generator includes: A second charge pump, which pumps the power supply voltage in response to the operating clock to generate a second pump voltage; and N shifters are used to shift the enable level of the N first pump control signals to the level of the second pump voltage, and output the level-shifted N first pump control signals as the N second pump control signals.

4. The charge pump circuit according to claim 3, wherein, The N power supplies include N NMOS transistors, which selectively supply the power voltage to a corresponding one of the N pump stages in response to a corresponding one of the N second pump control signals.

5. The charge pump circuit according to claim 1, wherein, First pump control signal generator: The N first pump control signals are activated in a predetermined order, and The N first pump control signals are deactivated in the reverse order of the predetermined sequence.

6. The charge pump circuit according to claim 1, further comprising: A voltage comparator compares the level of the first pump voltage with the pump reference voltage level and generates an operation control signal. The first charge pump includes a pump controller that controls the operation of each of the N pump stages in response to at least one of the operating clock, the operating control signal, or the N first pump control signals.

7. The charge pump circuit according to claim 1, wherein, The clock generator includes: A drive actuator that increases or decreases the level of a drive operating voltage in response to a feedback signal, and adjusts the rate at which the level of the drive operating voltage decreases according to the first or second number of the N first pump control signals that enable the signal. A feedback signal generator compares the level of the drive operating voltage with the level of the drive reference voltage, and determines whether to enable the feedback signal based on the comparison result; and A clock output, which outputs the feedback signal as the operating clock, wherein the driving operator: As the number of enabled signals among the N first pump control signals increases, the rate at which the drive operating voltage level decreases is reduced, and When the number of enabled signals among the N first pump control signals decreases, the rate at which the level of the drive operating voltage decreases increases.

8. A semiconductor device comprising: A voltage generator that pumps the power supply voltage to generate a first pump voltage in response to an operating clock and a control signal having an enable level higher than the power supply voltage. A clock generator that generates an operating clock with a first frequency during an initial operating period when the level of the first pump voltage is at a first level and generates an operating clock with a second frequency after the initial operating period, wherein the second frequency is generated as a frequency lower than the first frequency in response to the level of the first pump voltage rising to a second level greater than the first level. as well as An internal circuit that performs a predetermined internal operation in response to the first pump voltage.

9. The semiconductor device according to claim 8, wherein, The clock generator includes: A first pump control signal generator activates a first number of signals from N first pump control signals to raise the level of the first pump voltage to a first amount higher than the level of the power supply voltage, and activates a second number of signals from the N first pump control signals to raise the level of the first pump voltage to a second amount higher than the level of the power supply voltage, wherein the first number of signals is greater than the second number of signals, and the first amount is greater than the second amount; and A clock generator that decreases the frequency of the operating clock as the number of enabled signals among the N first pump control signals increases, and increases the frequency of the operating clock as the number of enabled signals among the N first pump control signals decreases, where N is a natural number equal to or greater than 2.

10. The semiconductor device according to claim 9, wherein, The voltage generator includes: A first charge pump, which generates a first pump voltage using the power supply voltage in response to the operating clock, includes N pump stages that are activated in response to N first pump control signals.

11. The semiconductor device according to claim 10, wherein, The first charge pump includes: A second pump control signal generator generates N second pump control signals, which have the same activation period as the N first pump control signals but have a higher activation level than the N first pump control signals; and N power supplies, each responding to one of the N second pump control signals, supply power voltage as the operating power of the N pump stages.

12. The semiconductor device according to claim 11, wherein, The second pump control signal generator includes: A second charge pump, which pumps the power supply voltage in response to the operating clock to generate a second pump voltage; and N shifters are used to shift the enable level of the N first pump control signals to the level of the second pump voltage, and output the level-shifted N first pump control signals as the N second pump control signals.

13. The semiconductor device according to claim 12, wherein, The N power supplies include N NMOS transistors, which selectively supply the power voltage to a corresponding one of the N pump stages in response to a corresponding one of the N second pump control signals.

14. The semiconductor device according to claim 9, wherein, First pump control signal generator: The N first pump control signals are activated in a predetermined order, and The N first pump control signals are deactivated in the reverse order of the predetermined sequence.

15. The semiconductor device according to claim 10, wherein, The voltage generator includes: A voltage comparator compares the level of the first pump voltage with the pump reference voltage level and generates an operation control signal. The first charge pump includes a pump controller that controls the operation of each of the N pump stages in response to at least one of the operation clock, the operation control signal, or the N first pump control signals.

16. The semiconductor device according to claim 9, wherein, The clock generator includes: A drive actuator that increases or decreases the level of a drive operating voltage in response to a feedback signal, and adjusts the rate at which the level of the drive operating voltage decreases according to the number of enabled signals among the N first pump control signals. A feedback signal generator compares the level of the drive operating voltage with the level of the drive reference voltage, and determines whether to enable the feedback signal based on the comparison result; and A clock output, which outputs the feedback signal as the operating clock, wherein the driving operator: When the number of enabled signals among the N first pump control signals is within a first range, the rate at which the level of the drive operating voltage decreases is reduced, and When the number of enabled signals among the N first pump control signals is within a second range less than the first range, the rate at which the level of the drive operating voltage decreases is increased.

17. A method of operating a charge pump circuit that generates a first pump voltage using a power supply voltage in response to an operating clock, the charge pump circuit comprising N pump stages having an operation determined in response to a corresponding one of N second pump control signals, the N second pump control signals having the same activation period as the N first pump control signals and having a higher activation level than the N first pump control signals, wherein... N is a natural number equal to or greater than 2. The operation method includes the following steps: A first number of the N first pump control signals are activated to raise the level of the first pump voltage to a first amount higher than the level of the power supply voltage, and a second number of the N first pump control signals are activated to raise the level of the first pump voltage to a second amount higher than the level of the power supply voltage, wherein the first number of signals is greater than the second number of signals, and the first amount is greater than the second amount; and Based on activating the first number of signals, an operating clock with a first frequency is generated, and Based on the activation of the second number of signals, an operating clock with a second frequency is generated, wherein the first frequency is lower than the second frequency.

18. The operating method according to claim 17, further comprising the following steps: The N second pump control signals are generated in response to the N first pump control signals; as well as The power supply voltage is supplied in response to the N second pump control signals as the operating power of the N pump stages.

19. The operating method according to claim 18, wherein, The steps for generating the N second pump control signals include the following: In response to the operating clock, the power supply voltage is pumped to generate a second pump voltage; and The enable level of the N first pump control signals is shifted to the level of the second pump voltage, and the N level-shifted first pump control signals are output as the N second pump control signals.

20. The operating method according to claim 17, wherein, The N first pump control signals are enabled in a predetermined order and deactivated in the reverse order of the predetermined order.

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