Apparatus and method for measuring load current with high resolution

Abstract

A method of measuring a load current of a load provided to a switching converter includes obtaining a first reference voltage defining a peak of an inductor current of an inductor passing through the switching converter; generating a pulse based on the first reference voltage and a turn-on time of at least one power switch of the switching converter; generating an output signal by filtering the pulse; and, based on the output signal, setting from a first mode to a second mode when a value of the load current is less than a first threshold. Generating the pulse further includes generating, in the second mode, the pulse having a width that is proportionally lengthened to the turn-on time.

Description

[0001] Cross-references to related applications

[0002] This application is based on and claims priority to Korean Patent Application No. 10-2021-0025966, filed with the Korean Intellectual Property Office on February 25, 2021, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to a switching converter, and more specifically, to an apparatus and method for measuring load current at high resolution. Background Technology

[0004] Switching converters can be used to generate supply voltages that provide power to various electronic components (i.e., loads, which operate by consuming load current supplied by the switching converter due to high power efficiency). Recently, switching converters may be needed to generate information about load power consumption and to produce a stable supply voltage despite changes in load current. For example, information about load current can be used to estimate load power consumption and / or battery levels, and / or to prevent or reduce the likelihood of overheating, and may be particularly important for applications requiring high power efficiency, such as mobile applications using batteries as a power source. Load current can vary over a wide range depending on the load's state. Therefore, accurate measurement of load current can be crucial. Summary of the Invention

[0005] The present invention relates to apparatus and / or methods for accurately or more precisely measuring load current over a wide range of variations.

[0006] According to some exemplary embodiments of the present invention, an apparatus is provided, comprising: a time extension circuit configured to generate an extended signal activated during a time period proportional to the on-time of at least one power switch of a switching converter; logic circuitry configured to generate a first control signal based on the on-time in response to a mode signal indicating a first mode, and the logic circuitry being configured to generate the first control signal based on the extended signal in response to a mode signal indicating a second mode; a switching circuitry configured to receive a first reference voltage defining a peak value of an inductor current through an inductor of the switching converter, and to generate a pulse based on the first control signal; a filter configured to generate an output signal by filtering the pulse; and a first comparator configured to generate the mode signal based on the voltage of the output signal and a second reference voltage. The logic circuitry is configured to be in a second mode based on the mode signal in response to a load current value being less than a first threshold value.

[0007] According to some exemplary embodiments of the present invention, an apparatus is provided, comprising: an inductor connected to an output node that generates an output voltage and an output capacitor connected to the output node; at least one power switch configured to provide an inductor current to the inductor; a peak current detector circuit configured to generate a peak signal by detecting a peak value of the inductor current, the peak value being based on a first reference voltage; a switch driver circuit configured to control the at least one power switch based on the peak signal; and a load current meter configured to generate a pulse based on the first reference voltage and the on-time of the at least one power switch, and to generate an output signal representing the magnitude of a load current by filtering the pulse. The load current meter is configured to change from a first mode to a second mode based on the output signal in response to a load current value being less than a first threshold, and in the second mode, to extend the pulse width.

[0008] According to some exemplary embodiments of the present invention, a method is provided comprising: obtaining a first reference voltage defining a peak value of an inductor current passing through an inductor of a switching converter; generating a pulse based on the first reference voltage and the on-time of at least one power switch of the switching converter; generating an output signal by filtering the pulse; and changing from a first mode to a second mode based on the output signal in response to a load current value being less than a first threshold. Generating the pulse further comprises generating a pulse having a width proportional to the on-time in the second mode. Attached Figure Description

[0009] Some exemplary embodiments of the inventive concept will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 This is a block diagram illustrating some exemplary embodiments of a switch converter according to a concept of the present invention;

[0011] Figure 2 This is a block diagram illustrating some example embodiments of a peak current detector according to a concept conceived in this invention;

[0012] Figure 3 This is a block diagram illustrating some exemplary embodiments of a load current meter according to a concept of the present invention;

[0013] Figure 4 This is a timing diagram illustrating an example of the operation of a switch converter according to some exemplary embodiments of the present invention;

[0014] Figure 5 This is a block diagram illustrating some exemplary embodiments of a load current meter according to a concept of the present invention;

[0015] Figure 6 This is a graph illustrating the switching of measurement modes of a load current meter according to some exemplary embodiments of the present invention;

[0016] Figure 7 These are circuit diagrams illustrating switching circuits and filters according to some exemplary embodiments of the concept of the present invention;

[0017] Figure 8 This is a circuit diagram illustrating some exemplary embodiments of a time extension circuit according to a concept of the present invention;

[0018] Figure 9 This is a timing diagram illustrating an example of the operation of a time extension circuit according to some exemplary embodiments of the present invention;

[0019] Figure 10 This is a block diagram illustrating some exemplary embodiments of a system according to a concept proposed in this invention;

[0020] Figure 11 This is a flowchart illustrating a method for measuring load current according to some exemplary embodiments of the present invention;

[0021] Figure 12 This is a flowchart illustrating a method for measuring load current according to some exemplary embodiments of the present invention;

[0022] Figure 13 This is a flowchart illustrating a method for measuring load current according to some exemplary embodiments of the present invention;

[0023] Figure 14 This is a flowchart illustrating a method for measuring load current according to some exemplary embodiments of the present invention;

[0024] Figure 15 This is a flowchart illustrating a method for measuring load current according to some exemplary embodiments of the present invention;

[0025] Figure 16 These are block diagrams illustrating some exemplary embodiments of a system according to the concept of the present invention; and

[0026] Figure 17 This is a block diagram illustrating some example embodiments of a system based on a concept according to the present invention. Detailed Implementation

[0027] Figure 1 This is a block diagram illustrating some exemplary embodiments of a switch converter 10 according to the present invention. For example... Figure 1As shown, the switch converter 10 may include an inductor L, an output capacitor C_OUT, a first power switch PS1, a second power switch PS2, a switch driver 12, a voltage feedback circuit 14, a peak current detector 16, and a load current meter 18. In some example embodiments, the components of the switch converter 10 may be included in a single semiconductor package. In some example embodiments, the switch converter 10 may include a printed circuit board (PCB), and at least two components of the switch converter 10 may be mounted on the PCB as separate semiconductor packages.

[0028] refer to Figure 1 The switching converter 10 can be based on the input voltage V received through the first terminal P1. IN An output voltage V is generated at the second terminal P2. OUT Output voltage V OUT It can be used as the power supply voltage for other electronic components (e.g., one or more loads), and the switching converter 10 can provide load current I to one or more loads via the second terminal P2. LOAD The switching converter 10 can refer to a converter that generates an output voltage V through a conducting / turning-off element. OUT Any electronic circuit, and may be referred to as a switching regulator. For example, the first power switch PS1 and the second power switch PS2 of the switching converter 10 may be turned on or off based on a first drive signal DRV1 and a corresponding second drive signal DRV2 provided by the switch driver 12. In some example embodiments, the first power switch PS1 may be or may include a p-type field-effect transistor (PFET) as a power transistor, and may be turned on in response to the first drive signal DRV1 having a low level. Furthermore, in some example embodiments, the second power switch PS2 may be or may include an n-type field-effect transistor (NFET) as a power transistor, and may be turned on in response to the second drive signal DRV2 having a high level. In some example embodiments, the second power switch PS2 may be replaced by a diode having an anode with an applied ground potential and a cathode connected to an inductor L. In this document, it is assumed that the first drive signal DRV1 is an active-low signal and the second drive signal DRV2 is an active-high signal.

[0029] In this document, the state of a switch (or power switch) "on" can refer to the state where the two ends of the switch are electrically connected, and the state of a switch "off" can refer to the state where the two ends of the switch are electrically disconnected. Furthermore, two or more components electrically connected to a "conducting" state via a switch and / or wires can simply be referred to as a connection, and two or more components that are always electrically connected via wires can be referred to as a coupling.

[0030] In some example embodiments, the input voltage V IN and output voltage V OUT The voltage can be positive direct current (DC), and the switching converter 10 can be a DC-DC converter. For example, the switching converter 10 can be a buck converter, capable of generating voltages less than the input voltage V. IN Output voltage V OUT It can be called a step-down converter. Alternatively or additionally, the switching converter 10 can be a boost converter, capable of generating a voltage higher than the input voltage V. IN Output voltage V OUT It can be called a step-up converter. Alternatively or additionally, the switching converter 10 can be a buck-boost converter and can generate a voltage lower than the input voltage V. IN or higher than the input voltage V IN Output voltage V OUT In the following description, the switching converter 10 will be primarily referred to as a buck converter. However, it should be understood that exemplary embodiments of the present invention can be applied to AC-to-DC (AC-DC) converters that receive AC voltage, as well as other types of DC-to-DC converters.

[0031] The voltage feedback circuit may include one or more voltage feedback circuits 14. The voltage feedback circuit 14 can transmit the output voltage V... OUT The voltage is compared with a target voltage, and a feedback signal FB representing the comparison result can be provided to the switch driver 12. For example, the voltage feedback circuit 14 can provide the output voltage V. OUT and / or from the output voltage V OUT The divided voltage is compared with at least one reference voltage, and a feedback signal FB representing the comparison result can be generated. The switch driver 12 can identify the output voltage V based on the feedback signal FB. OUT The voltage level. In some example embodiments, the voltage feedback circuit 14 can generate a voltage level at the output voltage V. OUT Or from the output voltage V OUT The feedback signal FB is activated when the voltage output is lower than the reference voltage, and the switch driver 12 can activate the first drive signal DRV1 in response to the activated feedback signal FB.

[0032] The peak current detector circuit may be or may include one or more peak current detectors 16. The peak current detector 16 can detect the inductor current I passing through the inductor L.L The peak value can be detected, and the peak signal PK can be provided to the switch driver 12. For example, the peak current detector 16 can sense the inductor current I. L And can respond to / in response to the sensed inductor current I L The magnitude corresponds to the value based on the first reference voltage V. REF1 A peak signal PK is generated when the defined value is reached. Switch driver 12 can deactivate the first drive signal DRV1 in response to the peak signal PK, and the inductor current I... L This can be reduced. As a result, the inductor current I... L The peak value can be limited based on the first reference voltage V. REF1 The defined size, and the requirements or expectations of the switching converter 10 (e.g., electromagnetic interference (EMI) requirements or expectations) can be partially or fully met. In some example embodiments, the first reference voltage V REF1 The inductor current I can be changed, for example, by a switch driver 12. L The peak value can be controlled. In some example embodiments, with Figure 1 Unlike other detectors, peak current detector 16 can sense (instead of inductor current I) L Or besides the inductor current I L The current passing through the first power switch PS1 (excluding the current outside of the circuit) can be detected, and the peak value of the current passing through the first power switch PS1 can be detected. (This will be discussed later.) Figure 2 An example describing the peak current detector 16.

[0033] The load current meter 18 can measure the load current I supplied by the switching converter 10 to the load through the second terminal P2. LOAD .like Figure 1 As shown, the load current meter 18 can receive the first reference voltage V from the peak current detector 16. REF1 It can receive a first drive signal DRV1 and a second drive signal DRV2 from the switch driver 12, and can generate a signal representing the load current I. LOAD The output signal OUT is of the specified magnitude. Load current I LOAD This can include the inductor current I through the inductor L. L And / or the current generated by the discharge of the output capacitor C_OUT. Because the output capacitor C_OUT is generated by the inductor current I... L Because it's charging, the accumulated inductor current I over a period of time... L It can be compared with the load current I accumulated in the same time period LOAD The same or nearly the same. Therefore, the load current meter 18 can be based on information including the inductor current I. L The first reference voltage V for peak information REF1And including information about generating inductor current I L The timing information is obtained from the first drive signal DRV1 and the second drive signal DRV2, and the load current I is measured. LOAD In this paper, the load current meter 18 can be referred to as the meter used to measure the load current I. LOAD The device. In some example embodiments, the load current meter 18 may only receive the first drive signal DRV1.

[0034] In some example embodiments, the output signal OUT generated by the load current meter 18 can be used to estimate the power consumption of the load. For example, as Figure 1 As shown, the output signal OUT can be output through the third terminal P3, and consumes the load current I. LOAD The load and / or a power estimator included in another component can identify the load current I based on the output signal OUT. LOAD The size of the load current I. The power estimator can be based on the identified load current I. LOAD The power estimator estimates the load's power consumption by measuring the output signal OUT. The estimated power consumption can be used for several useful functions, such as estimating battery levels, preventing or reducing the likelihood of load overheating, and detecting at least one of the following abnormal events. In this paper, it is assumed that the output signal OUT is provided to the power estimator.

[0035] In some example embodiments, the load current I LOAD It can change or fluctuate within a wide range. For example, the load can be set to a power-saving mode to reduce power consumption, and the load current I will be lower than that in normal mode. LOAD In power-saving mode, the magnitude can be significantly reduced. As described later with reference to the accompanying drawings, the output signal OUT can accurately or nearly accurately represent the load current I over a wide range of variations. LOAD This allows the power consumption of the load to be estimated almost accurately or precisely. For example, the load current meter 18 can measure low load current I at high resolution. LOAD This allows the load's power consumption to be estimated more accurately (e.g., precisely) even when it is low (e.g., in power-saving mode). (See later...) Figure 3 Examples describing load current meter 18, etc.

[0036] The switch driver circuit may be or may include one or more switch drivers 12. The switch driver 12 may generate both a first drive signal DRV1 and a second drive signal DRV2, such that the output voltage V... OUT It is maintained at a voltage close to the target voltage. For example... Figure 1As shown, the switch driver 12 can receive a feedback signal FB from the voltage feedback circuit 14, a peak signal PK from the peak current detector 16, and can generate one or both of a first drive signal DRV1 and a second drive signal DRV2 based on the peak signal PK and / or the feedback signal FB. In some example embodiments, the switch driver 12 may include a plurality of logic gates and can generate the first drive signal DRV1 and the second drive signal DRV2 by performing logical operations on one or both of the peak signal PK and the feedback signal FB. For example, the switch driver 12 can generate a deactivated first drive signal DRV1 and an activated second drive signal DRV2 in response to an activated peak signal PK, such that the inductor current I... L This can be reduced. Alternatively or additionally, the switch driver 12 can generate an active first drive signal DRV1 and a deactivated second drive signal DRV2 in response to an active feedback signal FB, causing the inductor current I... L It can be added. See below for reference. Figure 4 An example describing the operation of switch driver 12.

[0037] Figure 2 This is a block diagram illustrating some exemplary embodiments of a peak current detector 20 according to a concept proposed in this invention. (Refer to the above...) Figure 1 As described, the peak current detector 20 can detect the inductor current I. L The peak value can be generated, and a peak signal PK can be produced. For example... Figure 2 As shown, the peak current detector 20 may include a current sensor 22, a reference voltage generator 24, and a comparator 26.

[0038] Current sensor 22 can sense inductor current I L To generate sensing voltage V SEN And can sense voltage V SEN Provided to comparator 26. For example, current sensor 22 can generate a signal related to inductor current I. L Proportional sensing voltage V SEN In some example embodiments, as referenced above... Figure 1 As described, the current sensor 22 can sense (instead of the inductor current I) L Or besides the inductor current I L (Outside) Passing through Figure 1 The current of the first power switch PS1.

[0039] Reference voltage generator 24 can generate a first reference voltage V REF1 And the first reference voltage V can be REF1 Provided to comparator 26. Reference voltage generator 24 may be included therein to generate a first reference voltage V.REF1 Any structure. For example, the reference voltage generator 24 may include a resistor and a current source that generates a reference current, and the first reference voltage V REF1 This can correspond to the voltage generated by the reference current passing through the resistor. In some example embodiments, the reference voltage generator 24 can receive a control signal from an external source and can generate a first reference voltage V that varies based on the control signal. REF1 .

[0040] Comparator 26 can convert the sensed voltage V SEN With the first reference voltage V REF1 A comparison is used to generate the peak signal PK. For example, as... Figure 2 As shown, comparator 26 can receive the sensed voltage V from current sensor 22 via a non-inverting input. SEN And it can receive the first reference voltage V from the reference voltage generator 24 via the inverting input. REF1 Therefore, in response to the sensed voltage V SEN Higher than the first reference voltage V REF1 When this occurs, comparator 26 can generate the active peak signal PK. In this paper, it is assumed that the peak signal PK is a high-level active signal, such that the active peak signal PK can have a high level.

[0041] like Figure 2 As shown, the peak current detector 20 can output a signal that is compared with the sensed voltage V by the comparator 26. SEN The first reference voltage V for comparison REF1 And the first reference voltage V REF1 It can be provided Figure 1 The load current meter 18. With Figure 2 Unlike in the previous case, when the peak current detector 20 outputs from the first reference voltage V... REF1 The voltage being converted (e.g., from a first reference voltage V by two or more resistors) REF1 When the voltage is divided, it is provided to Figure 1 The voltage of the load current meter 18 may include errors caused by variations between two or more resistors (e.g., resistance variations between two or more resistors), making it possible to measure the load current I. LOAD Errors are introduced in the load current meter 18. However, as... Figure 2 As shown, the first reference voltage V REF1 It can be provided to the load current meter 18 so that the load current meter 18 can measure the load current I accurately or more precisely. LOAD .

[0042] Figure 3This is a block diagram illustrating some exemplary embodiments of a load current meter 30 according to the present invention. (Refer to the above...) Figure 1 As described, the load current meter 30 can receive a first reference voltage V. REF1 The system includes a first drive signal DRV1 and a second drive signal DRV2, and can generate a signal representing the load current I. LOAD The magnitude of the output signal OUT. For example... Figure 3 As shown, the load current meter 30 may include a pulse generator 32 and a filter 34. Referring below... Figure 1 To describe Figure 3 .

[0043] The pulse generator 32 can be based on a first reference voltage V REF1 The first drive signal DRV1 and the second drive signal DRV2 generate a pulse (or pulse signal) PL. In some example embodiments, the pulse generator 32 can generate a pulse signal PL based on a first reference voltage V. REF1 The amplitude or absolute value of the amplitude, and the pulse PL based on the width (or activation width) of the first drive signal DRV1 and the second drive signal DRV2. (See above reference.) Figure 1 The first reference voltage V is described. REF1 This can include information about the inductor current I. L The information includes the peak value, and one or both of the first drive signal DRV1 and the second drive signal DRV2 may include information about the generation of the inductor current I. L The timing information. Therefore, the pulse PL can include information about the accumulated inductor current I over a specific time period. L The information, and filter 34 can generate an indication of the load current I by filtering the pulse PL. LOAD The output signal OUT is of the specified size. In this paper, it is assumed that the pulse PL is a high-level active signal, that is, it is at a high level when the pulse PL is activated, and the width of the pulse PL can refer to the duration of the high level.

[0044] refer to Figure 3 The pulse generator 32 can receive an output signal OUT and can generate a mode signal MD. In some example embodiments, the pulse generator 32 can be configured to be in one of multiple measurement modes. For example, the pulse generator 32 can identify the load current I based on the output signal OUT. LOAD The size of the pulse generator 32 can be based on the identified load current I. LOAD The size is set at high load current I LOAD It is in the first mode and can be set to operate at low load current I. LOADThe system is currently in the second mode. The pulse generator 32 can extend the width of the pulse PL (e.g., the pulse width) to measure the load current I in the second mode with a higher resolution than in the first mode. LOAD Therefore, in the second mode, filter 34 can filter the pulse PL with an extended width, and the output signal OUT can represent the load current I. LOAD The magnification size. In this paper, the second mode can be referred to as the extended mode.

[0045] Pulse generator 32 can generate a mode signal MD representing the set measurement mode, and the mode signal MD can be provided to and / or output to a switching converter including load current meter 30 (e.g., Figure 1 The external of 10). As mentioned above, because the output signal OUT can represent the load current I in the second mode. LOAD The load current meter 30 can output a mode signal MD to notify the power estimator, which receives the output signal OUT, of the measurement mode that generated the output signal OUT. In some example embodiments, the power estimator can identify the measurement mode of the load current meter 30 based on the mode signal MD and can process the output signal OUT based on the identified measurement mode. For example, when a second mode is identified based on the mode signal MD, the power estimator can compensate for the value corresponding to the output signal OUT based on the ratio of the pulse PL width extension. In this document, it is assumed that the mode signal MD is low in the first mode and high in the second mode. Reference will be made later. Figure 5 Example describing pulse generator 32.

[0046] Filter 34 can generate an output signal OUT by filtering the pulse PL. For example, as mentioned above, the amplitude of the pulse PL can be based on the inductor current I. L The peak value, and can have a value based on the inductor current I. L The width of the timing. For example... Figure 3 As shown, filter 34 can function as a low-pass filter, filtering the pulse PL to generate the output signal OUT. Therefore, the output signal OUT can have a relationship with the load current I. LOAD A proportional physical quantity (e.g., voltage). Filter 34 can have any structure for filtering the pulse PL, which will be discussed later. Figure 7 Example describing filter 34.

[0047] Figure 4 This is a timing diagram illustrating an example of the operation of a switch converter 10 according to some exemplary embodiments of the present invention. Specifically, Figure 4 Show Figure 1The signal in the switch converter 10 and Figure 3 The variation of the mode signal MD and pulse PL in the load current meter 30 over time. In the following text, reference will be made to... Figure 1 To describe Figure 4 And assume Figure 1 The load current meter 18 generates Figure 3 The mode signal MD and pulse PL. Furthermore, in Figure 4 In the example, it is assumed that the load current meter 18 is set to a first mode during the period from time t41 to time t46, and is set to a second mode during the period from time t51 to time t55.

[0048] refer to Figure 4 At time t41, the first drive signal DRV1 can be activated / is activated. For example, the switch driver 12 can generate the activated first drive signal DRV1 in response to the activated feedback signal FB. Therefore, the first power switch PS1 can be turned on, and the input voltage V can be applied. IN The first terminal P1 supplies current, and as Figure 4 As shown, the inductor current I can be increased. L The load current meter 18 can activate the pulse PL in response to the activated first drive signal DRV1, and the pulse PL can have a voltage equal to the first reference voltage V. REF1 The amplitude is the same as the amplitude and / or determined by the first reference voltage V. REF1 Defined amplitude.

[0049] At time t42, the peak signal PK can be activated / is activated. For example, as Figure 4 As shown by the dashed line, the inductor current I... L It can achieve the result from the first reference voltage V REF1 The defined peak value allows the peak current detector 16 to generate an active peak signal PK. The switch driver 12 can generate a deactivated first drive signal DRV1 and an active second drive signal DRV2 in response to the active peak signal PK. Therefore, the first power switch PS1 can be turned off, the second power switch PS2 can be turned on, current can be supplied from the ground node, and so on. Figure 4 As shown, the inductor current I can be gradually reduced. L .

[0050] At time t43, the inductor current I L It can be zero or approximately zero. In some example embodiments, the peak current detector 16 may include a current sensor (e.g., Figure 2 22) and / or a zero-current detector. The switch driver 12 can identify the inductor current I from the peak current detector 16. LThe event becomes zero, and a second drive signal DRV2 can be generated to deactivate it. Therefore, the second power switch PS2 can be turned off, and the load current I... LOAD This can be provided by the output capacitor C_OUT. The load current meter 18 can deactivate the pulse PL in response to the deactivation second drive signal DRV2, such that the pulse PL can have a width corresponding to the time interval between time t41 and time t43. In some example embodiments, the load current meter 18 may not receive the second drive signal DRV2 and can identify the inductor current I from the peak current detector 16. L The event becomes zero, and can activate the pulse PL.

[0051] like Figure 4 As shown, between time t41 and time t43, the first drive signal DRV1 and / or the second drive signal DRV2 can be activated, the first power switch PS1 and / or the second power switch PS2 can be turned on, and the inductor current I... L It can be positive, and the pulse PL can be activated. In this document, the time period between time t41 and time t43 (e.g., the period during which at least one power switch of the switch converter 10 (e.g., the first power switch PS1 and / or the second power switch PS2) is maintained in the on state) can be referred to as the on-time t. ON Therefore, in the first mode, the pulse PL can be applied during the on-time t. ON It is activated during this period, and the width of the pulse PL can be related to the conduction time t. ON same.

[0052] At time t44, the first drive signal DRV1 can be activated again. For example, the output voltage V OUT The output capacitor C_OUT can decrease as it discharges from time t43, allowing the feedback signal FB to be activated. The switch driver 12 can then activate the first drive signal DRV1 in response to the activated feedback signal FB, causing the inductor current I... L This can be increased again. Similar to times t42 and t43, the peak signal PK can be activated at time t45, and the second drive signal DRV2 and the pulse PL can be deactivated at time t46. (The rest of the text appears to be unrelated and possibly machine-generated.) Figure 4 As shown, the conduction time t ON The time interval between time t44 and time t46 can be the same as the time interval between time t41 and time t43 and the time interval between time t51 and time t53, which will be described later.

[0053] like Figure 4As shown, during the duration between time t41 and time t46, the switching period of the switching converter 10 can correspond to the first time period T1, and the pulse PL can also have the first time period T1. Due to the high load current I... LOAD The first time period T1 can be shorter than the second time period T2, which will be described later, and due to the essentially uniform conduction time t ON The output signal OUT can have a large physical quantity.

[0054] At time t51, the first drive signal DRV1 can be activated / is activated. For example, the output voltage V OUT The discharge of the output capacitor C_OUT can reduce the current, allowing the feedback signal FB to be activated / received. The switch driver 12 can activate the first drive signal DRV1 in response to the activated feedback signal FB, causing the inductor current I... L It can be increased. Similar to time t42 and time t45, at time t52, the peak signal PK can be activated, the first drive signal DRV1 can be deactivated, and the second drive signal DRV2 can be activated.

[0055] At time t53, the inductor current I L The value can be approximated to zero, and the second drive signal DRV2 can be deactivated / deactivated. In the second mode, the load current meter 18 can increase and / or extend the width of the pulse PL, and can deactivate the pulse PL at time t54 instead of deactivating it in response to the deactivated second drive signal DRV2. At time t55, the first drive signal DRV1 can be reactivated, and due to the low load current I... LOAD The duration between time t51 and time t55 (e.g., the second time period T2) can be longer than the first time period T1. Figure 4 The difference is that when the width of the pulse PL is equal to the conduction time t... ON (with load current I in the first mode) LOAD In a low-state condition (similar to the case here), the output signal OUT may correspond to a very low value due to the second time period T2, making it potentially difficult or even more challenging to accurately detect the load current I. LOAD The size. Alternatively or additionally, when the physical quantity of the output signal OUT is in the load current I. LOAD When amplified in a low state, the load current I increases due to noise and amplifier input offset. LOAD It may not have been measured precisely or may have been measured with a greater error.

[0056] As described later with reference to the accompanying drawings, the load current meter 18 can be used in a second mode with an on-time t. ONThe width of the pulse PL is increased / extended proportionally so that the output signal OUT generated by filtering the pulse PL corresponds to an appropriate physical quantity, and the load current I detected based on the output signal OUT in the second mode is... LOAD The magnitude can be compensated based on the ratio of increase or decrease in the width of the pulse PL. Therefore, the load current meter 18 can measure low load currents I at high or higher resolution. LOAD .

[0057] Figure 5 This is a block diagram illustrating some exemplary embodiments of a load current meter 50 according to the present invention. (Refer to the above...) Figure 1 and Figure 3 As described, the load current meter 50 can receive a first reference voltage V. REF1 The system includes a first drive signal DRV1 and a second drive signal DRV2, and can generate an output signal OUT and a mode signal MD. For example... Figure 5 As shown, the load current meter 50 may include a pulse generator 52 and a filter 54, and the pulse generator 52 may include a time extension circuit 52_1, a logic circuit 52_3, a switching circuit 52_5, a reference voltage generator 52_7, and a comparator 52_9.

[0058] The switching circuit may be or may include one or more switching circuits 52_5. The switching circuit 52_5 may receive a first reference voltage V. REF1 And a first control signal CTR1, and can generate a pulse PL. For example, the switching circuit 52_5 may include at least one switch controlled by the first control signal CTR1, and the at least one switch can be controlled by a first reference voltage V. REF1 And / or ground potential is provided to filter 54 to generate pulse PL. (See later...) Figure 7 Here is an example to describe the switching circuit 52_5.

[0059] Reference voltage generator 52_7 can generate a second reference voltage V REF2 And the second reference voltage V can be REF2 Provided to comparator 52_9. Comparator 52_9 can convert the second reference voltage V... REF2 The mode signal MD is generated by comparing it with the output signal OUT. For example, as shown below. Figure 5 As shown, comparator 52_9 can receive the second reference voltage V from reference voltage generator 52_7 via a non-inverting input. REF2 Furthermore, the output signal OUT can be received from filter 54 via its inverting input. Therefore, when the voltage of the output signal OUT is greater than the second reference voltage V... REF2(For example, in the first mode) the mode signal MD can be deactivated, and when the voltage of the output signal OUT is less than the second reference voltage V REF2 (For example, in the second mode) the mode signal MD can be activated. Figure 5 As shown, the mode signal MD can be provided to logic circuit 52_3 and can be output to the outside of pulse generator 52. In some example embodiments, as referred to later... Figure 6 As described, comparator 52_9 and / or reference voltage generator 52_7 can provide hysteresis for mode switching. In this document, comparator 52_9 may be referred to as the first comparator.

[0060] The logic circuit may be or may include one or more logic circuits 52_3. The logic circuit 52_3 may receive a first drive signal DRV1, a second drive signal DRV2, a mode signal MD, and an extended signal EXT, and may generate a first control signal CTR1 and a second control signal CTR2. In some example embodiments, the logic circuit 52_3 may include multiple logic gates, and may generate the first control signal CTR1 and the second control signal CTR2 based on the first drive signal DRV1, the second drive signal DRV2, the mode signal MD, and the extended signal EXT.

[0061] Logic circuit 52_3 can identify the measurement mode based on the mode signal MD, and can identify the conduction time t based on the first drive signal DRV1 and the second drive signal DRV2. ON When the first mode is identified based on the mode signal MD, the logic circuit 52_3 can generate a first control signal CTR1, such that the control signal has a conduction time t. ON The corresponding pulse PL width can be generated by the switching circuit 52_5. Furthermore, when the second mode is identified based on the mode signal MD, the logic circuit 52_3 can generate a second control signal CTR2, causing the time extension circuit 52_1 to generate an extended signal EXT, and can generate a first control signal CTR1 based on the extended signal EXT, so that the pulse PL has a conduction time t... ON The pulse PL with a proportionally extended width is generated by the switching circuit 52_5.

[0062] The time extension circuit may be or may include one or more time extension circuits 52_1. The time extension circuit 52_1 may receive a second control signal CTR2 from the logic circuit 52_3, and may generate a time extension circuit based on the second control signal CTR2, corresponding to the on-time t. ONAn extended signal EXT is activated within a proportional time period. The extended signal EXT can be provided to logic circuit 52_3 and, as described above, can be used to generate a pulse PL with an extended width in the second mode. In some example embodiments, the extended signal EXT can be activated within a proportional time period t. ON Activated (or deactivated) within a timeframe that is precisely or almost precisely proportional to the timeframe. (See later for reference.) Figure 8 Here is an example to describe the time extension circuit 52_1.

[0063] Figure 6 This is a graph illustrating the switching of measurement modes of a load current meter according to some exemplary embodiments of the present invention. Specifically, Figure 6 The graph illustrates the hysteresis loop that occurs when the load current meter's measurement mode is switched. In some example embodiments, Figure 6 The hysteresis loop can be derived from Figure 5 The reference voltage generator 52_7 and / or comparator 52_9 are provided, which will be referenced below. Figure 5 Describe it.

[0064] As described above with reference to the attached diagram, when the load current I... LOAD When the load current is high, the load current meter 50 can be set to the first mode, and when the load current I... LOAD At low speeds, the load current meter 50 can be set to a second mode. To prevent or reduce the possibility of errors and / or inaccuracies due to frequent switching of measurement modes, the reference voltage generator 52_7 and / or comparator 52_9 can provide hysteresis for switching measurement modes. For example, as Figure 6 As shown, when the load current I LOAD When the value is less than the first threshold THR1, the load current meter 50 can be set to the second mode, and when the load current I... LOAD When the value is greater than the second threshold THR2, the load current meter 50 can be set to the first mode. The second threshold THR2 can be greater than the first threshold THR1 (THR2>THR1).

[0065] Figure 6 The hysteresis loop can be implemented using any method. In some example embodiments, such as Figure 5 As shown, comparator 52_9 may have a hysteresis corresponding to the difference between the first threshold THR1 and the second threshold THR2, and reference voltage generator 52_7 may generate a second reference voltage V having a value corresponding to the median of the first threshold THR1 and the second threshold THR2. REF2 Provided to comparator 52_9. Alternatively or additionally, in some example embodiments, with Figure 5Unlike other voltage generators, comparator 52_9 can operate without hysteresis, and reference voltage generator 52_7 can receive the mode signal MD output by comparator 52_9. Based on the mode signal MD, reference voltage generator 52_7 can generate a second reference voltage V. REF2 It is set to be at a first level corresponding to the first threshold THR1 in the first mode and at a second level corresponding to the second threshold THR2 in the second mode.

[0066] Figure 7 This is a circuit diagram illustrating a switching circuit 72 and a filter 74 according to some exemplary embodiments of the concept of the present invention. For example... Figure 7 As shown, the first control signal CTR1 may include two control signals CTR11 and CTR12, and the output signal OUT may have a relationship with the load current I. LOAD The corresponding physical quantity is voltage.

[0067] refer to Figure 7 The switching circuit 72 can receive the first reference voltage V. REF1 And the first control signal CTR1, and can generate pulse PL. The first switch SW61 can respond to the activated control signal CTR11 to set the first reference voltage V. REF1 Provided to filter 74, and can be used in response to deactivation control signal CTR11 to set the first reference voltage V REF1 The first switch SW61 is separated from filter 74. In some example embodiments, the first switch SW61 may include a p-channel field-effect transistor (PFET), and the control signal CTR11 may be an active low signal; however, the example embodiments are not limited thereto. Furthermore, the second switch SW62 may provide ground potential to filter 74 in response to the activated control signal CTR12, and may separate the ground potential from filter 74 in response to the deactivated control signal CTR12. In some example embodiments, the second switch SW62 may include an n-channel field-effect transistor (NFET), and the control signal CTR12 may be an active high signal; however, the example embodiments are not limited thereto. Therefore, the switching circuit 72 may generate the above reference based on the first control signal CTR1. Figure 4 The described pulse PL. In some example embodiments, the switching circuit 72 may also include a voltage buffer with high input impedance and low output impedance. The first switch SW61 can be activated from a peak current detector (e.g., Figure 1 16) Receive the first reference voltage V REF1 The voltage buffer receives the first reference voltage V REF1 The corresponding voltage.

[0068] Filter 74 may be or include a low-pass filter, and may include a resistor R and a capacitor C that can be connected in series. The cutoff frequency of filter 74 may be defined based on the time range of pulse PL, and the resistance of resistor R and the capacitance of capacitor C may be determined by the cutoff frequency. In some example embodiments, filter 74 may have a higher order and may have a higher capacitance than... Figure 7 The structure shown is a more complex structure.

[0069] Figure 8 This is a circuit diagram illustrating a time extension circuit 80 according to some exemplary embodiments of the concept of the present invention, and Figure 9 This is a timing diagram illustrating an example of the operation of a time extension circuit 80 according to some exemplary embodiments of the concept of the present invention. (Refer to the above...) Figure 5 As described, Figure 8 The time extension circuit 80 can receive the second control signal CTR2 and generate the extension signal EXT.

[0070] refer to Figure 8 The time extension circuit 80 may include a current source 82, a comparator 84, a first capacitor C1, a second capacitor C2, and first switches SW71 to fourth switches SW74. The current source 82 can generate a constant current I from the positive supply voltage VDD. CON The current source 82 can generate a constant current I. CON The structure can be arbitrary and may include, for example, a current sink and a current mirror. A first switch SW71 may be connected between the current source 82 and the first capacitor C1, and a second switch SW72 may be connected between the current source 82 and the second capacitor C2. Furthermore, a third switch SW73 may be connected in parallel to the first capacitor C1, and a fourth switch SW74 may be connected in parallel to the second capacitor C2. The second control signal CTR2 may include multiple control signals and can be turned on and / or off by each of the first switches SW71 to the fourth switches SW74. The multiple switches SW71 to SW74 may be transistors such as NFET transistors and / or PFET transistors; however, the example embodiment is not limited thereto.

[0071] The first capacitor C1 can be connected between the first node N1 and the ground node, and the second capacitor C2 can be connected between the second node N2 and the ground node. As will be described later, for a constant current I... CONDue to the varying charging speed, the second capacitor C2 can have a larger capacitance than the first capacitor C1. In some example embodiments, the second capacitor C2 can have a capacitance corresponding to an integer multiple of the capacitance of the first capacitor C1. For example, the second capacitor C2 may include multiple capacitors connected in parallel with each other, and each of the multiple capacitors is identical to the first capacitor C1 and has the same capacitance as the first capacitor C1.

[0072] Comparator 84 can be connected to the first switch SW71, the third switch SW73, and the first capacitor C1 in the first node N1, and can be connected to the second switch SW72, the fourth switch SW74, and the second capacitor C2 in the second node N2. Comparator 84 can compare the voltage at the first node N1 with the voltage at the second node N2 and can generate an extended signal EXT representing the comparison result. In this document, the voltage at the first node N1 connected to the first capacitor C1 (e.g., the first voltage V1) can be referred to as the voltage of the first capacitor C1, and the voltage at the second node N2 connected to the second capacitor C2 (i.e., the second voltage V2) can be referred to as the voltage of the second capacitor C2. Furthermore, in this document, comparator 84 can be referred to as the second comparator.

[0073] refer to Figure 9 Between time t91 and time t92, the conduction time t ON It can happen. For example... Figure 9 As shown, before time t91 (e.g., at the conduction time t), ON Previously, the first switch SW71 and the second switch SW72 could be turned off, and the third switch SW73 and the fourth switch SW74 could be turned on. Therefore, the first capacitor C1 and the second capacitor C2 could discharge, and as... Figure 9 As shown, each of the first voltage V1 and the second voltage V2 can be approximated as zero (or ground potential).

[0074] At time t91, the conduction time t ON We can begin. For example... Figure 9 As shown, the first switch SW71 can be turned on, and the third switch SW73 can be turned off. Therefore, the first capacitor C1 can be connected to a constant current I. CON Charging is performed, and the first voltage V1 can be increased. Furthermore, the second switch SW72 can be maintained in the off state, and the fourth switch SW74 can be maintained in the on state. Therefore, the second voltage V2 can be maintained at zero (ground potential), and the comparator 84 can generate a deactivated extended signal EXT in response to a first voltage V1 higher than the second voltage V2.

[0075] At time t92, the conduction time t ON It can be terminated. For example... Figure 9As shown, the first switch SW71 can be turned off, and the third switch SW73 can be kept off. Therefore, charging of the first capacitor C1 can end, the charge stored in the first capacitor C1 can be maintained due to the electrically floating first node N1, and the first voltage V1 can be maintained constant. The first voltage V1 can depend on the charging time of the first capacitor C1 (e.g., the on-time t). ON This allows the magnitude of the first voltage V1 to correspond to the conduction time t. ON The length of the capacitor. Furthermore, at time t92, the second switch SW72 can be turned on, and the fourth switch SW74 can be turned off. Therefore, the second capacitor C2 can be connected to a constant current I. CON The capacitor is charged, and the second voltage V2 can be increased. As mentioned above, the second capacitor C2 can have a larger capacitance than the first capacitor C1, such that the rate at which the second voltage V2 increases between time t92 and time t93 can be lower than the rate at which the first voltage V1 increases between time t91 and time t92.

[0076] At time t93, the second voltage V2 can reach the first voltage V1. Therefore, comparator 84 can generate an activated extended signal EXT, and Figure 5 The logic circuit 52_3 can deactivate the pulse PL in response to the activated extended signal EXT. Furthermore, the first switch SW71 and the second switch SW72 can be turned off, and the third switch SW73 and the fourth switch SW74 can be turned on. Therefore, the first capacitor C1 and the second capacitor C2 can discharge, and as... Figure 9 As shown, each of the first voltage V1 and the second voltage V2 can be approximated as zero (or ground potential). As mentioned above, because the first voltage V1 can have a voltage that is related to the conduction time t... ON Corresponding sizes, and the first capacitor C1 and the second capacitor C2 carry the same current (i.e., a constant current I). CON Therefore, the charging period of the second capacitor C2 (i.e., the period between time t92 and time t93) can be based on the ratio between the capacitance of the first capacitor C1 and the capacitance of the second capacitor C2, and the conduction time t. ON Proportional. For example, when the capacitance of the second capacitor C2 is twice the capacitance of the first capacitor C1, the time interval between time t92 and time t93 can be the conduction time t. ON Therefore, when the capacitance of the second capacitor C2 is N times the capacitance of the first capacitor C1 (N is a positive real number), the width t of the pulse PL is twice that of the first capacitor C1. PL It can be defined in [Equation 1] as follows.

[0077] [Equation 1]

[0078] t PL=(1+N)t ON

[0079] As a result, in the second mode, the pulse PL can have a frequency response time t. ON Proportionally extended width t PL Furthermore, because the first capacitor C1 and the second capacitor C2 share the same constant current I... CON The current source is 82, so the conduction time is t. ON and the width t of pulse PL PL The ratio between them can depend solely on the ratio between the capacitance of the first capacitor C1 and the capacitance of the second capacitor C2, meaning that N in [Equation 1] and the error caused by other variations can be removed.

[0080] At time t94, the conduction time t ON It can be restarted, and the pulse PL can be reactivated. Due to the increase in the first voltage V1, the extended signal EXT can be deactivated. Furthermore, at time t95, the conduction time t... ON It can be terminated, and despite the conduction time t ON The process terminates, but the pulse PL can be kept active.

[0081] When the switching period T is long (i.e., when the load current I...), LOAD (in a low state), with Figure 9 The difference is that when the pulse PL has a conduction time t ON With a corresponding width, the voltage of the output signal OUT generated by filtering the pulse PL can be relatively small, and due to noise and amplifier input offset, it may not be easy to accurately or precisely detect the load current I from the output signal OUT. LOAD The size. However, in the second mode, the time extension circuit 80 can be extended from the on-time t. ON Starting from the termination time, it occurs at the conduction time t. ON An extended signal EXT is activated precisely or more accurately within a proportional time period, and the voltage of the output signal OUT can be tailored to detect the load current I due to the width of the pulse PL, which is based on the extended signal EXT. LOAD The size of the size.

[0082] Figure 10 This is a block diagram illustrating some exemplary embodiments of a system 100 according to the present invention. Specifically, Figure 10 The block diagram shows a system 100 including a switching converter 120 and a load 140 to which power is supplied by the switching converter 120.

[0083] refer to Figure 10 The switching converter 120 can draw voltages from the input voltage V.IN Generate output voltage V OUT And can convert the load current I LOAD It is supplied to load 140. Furthermore, as described above with reference to the accompanying drawings, the switching converter 120 can measure the load current I. LOAD And can represent the load current I LOAD The magnitude of the output signal OUT and the value of the load current I LOAD The measurement mode mode signal MD is provided to the load 140.

[0084] Load 140, which may be referred to as a load circuit and / or load device, can receive the output voltage V from the switching converter 120. OUT And it can consume load current I LOAD .like Figure 10 As shown, load 140 may include analog-to-digital converter (ADC) 142 and processing circuitry 144. In some example embodiments, it consumes load current I. LOAD The load 140 may also include additional components that provide various functions. In some example embodiments, to monitor the power consumption of the load 140, the ADC 142 and processing circuitry 144 may be external to the load 140 and may not consume load current I. LOAD At least a part of it. (See later for reference.) Figure 17 Here's an example to describe load 140.

[0085] The ADC 142 can generate a digital signal DIG by converting the output signal OUT. As described above with reference to the attached diagram, the output signal OUT can be related to the load current I. LOAD The analog signal corresponds to the magnitude of the load current I, and the ADC 142 can provide the digital signal DIG, which is a multi-bit signal, to the processing circuit 144 by converting the output signal OUT. Therefore, the digital signal DIG can have a magnitude corresponding to the load current I. LOAD The value corresponding to the size.

[0086] Processing circuit 144 can receive digital signal DIG from ADC 142 and mode signal MD from switching converter 120. Processing circuit 144 can identify load current I based on digital signal DIG and mode signal MD. LOAD The magnitude of the load current I corresponding to the value of the digital signal DIG. For example, the processing circuit 144 can identify the load current I corresponding to the value of the digital signal DIG in response to the mode signal MD representing the first mode. LOAD The size of the load current I. Furthermore, the processing circuit 144 can, in response to the mode signal MD representing the second mode, identify the load current I corresponding to the compensation value from the digital signal DIG. LOAD The size of the pulse PL used to generate the output signal OUT. When the pulse PL has a width t [Equation 1]PL At that time, the processing circuit 144 can identify the load current I corresponding to the value obtained by dividing the value of the digital signal DIG by (1+N) in the second mode. LOAD The size of N. In some example embodiments, in order to facilitate division operations by the processing circuit 144, N in [Equation 1] can satisfy the following [Equation 2].

[0087] [Equation 2]

[0088] N=2 k -1

[0089] In [Equation 2], k can be an integer greater than 0, and when N satisfies [Equation 2], in the second mode, the processing circuit 144 can compensate for the value of the digital signal DIG by shifting the digital signal DIG k times.

[0090] In some example embodiments, the processing circuit 144 may be based on the identified load current I LOAD The magnitude of the power consumption is used to estimate the real-time power consumption of load 140. Processing circuitry 144 may directly utilize information about the estimated power consumption and / or may provide this information to other components of load 140 and / or devices external to load 140. Processing circuitry 144 may have any structure in which digital signals (DIGs) can be processed. In some example embodiments, processing circuitry 144 may include programmable components such as microcontrollers and processors, reconfigurable components such as field-programmable gate arrays (FPGAs), and / or components providing fixed functionality such as intellectual property (IP) cores.

[0091] Figure 11 This is a flowchart illustrating a method for measuring load current according to some exemplary embodiments of the concept of the present invention. For example... Figure 11 As shown, the method for measuring load current may include multiple operations S20, S40, S60, and S80. In some example embodiments, Figure 11 The method can be derived from Figure 3 The load current meter 30 is executed, and will be referenced below. Figure 3 To describe Figure 11 .

[0092] refer to Figure 11 In operation S20, the measurement mode can be set. For example, the pulse generator 32 can identify the load current I based on the output signal OUT provided by the filter 34. LOAD The size of the pulse generator 32. The pulse generator 32 can operate at a load current I. LOAD The first mode is set when the load current I is relatively high, and the load current I can be set at a relatively high value. LOADA second mode is set when the current is relatively low. In some example embodiments, the load current meter 30 can be activated to measure low load current I. LOAD The second mode. For example, when power is supplied to the load current meter 30 and / or the load current meter 30 receives an activated reset signal, the pulse generator 32 can set the measurement mode to the second mode. (See later...) Figure 12 Here is an example to describe operation S20.

[0093] In operation S40, the first reference voltage V can be obtained. REF1 For example, the load current meter 30 can be obtained from a peak current detector (e.g., Figure 1 16) Receive the first reference voltage V REF1 And the peak current detector can use the first reference voltage V REF1 To detect inductor current I L The peak value. Therefore, the load current meter 30 can be measured from the first reference voltage V. REF1 Obtain information about the inductor current I L Information on the peak value.

[0094] In operation S60, the on-time t of at least one power switch can be used as a basis. ON and the first reference voltage V REF1 To generate pulses. For example, pulse generator 32 can receive control... Figure 1 The first drive signal DRV1 and control of the first power switch PS1 Figure 1 The second drive signal DRV2 of the second power switch PS2, and based on the first drive signal DRV1 and the second drive signal DRV2, the conduction time t, which is the period during which the first power switch PS1 and / or the second power switch PS2 are turned on, can be identified. ON Furthermore, pulse generator 32 can generate a pulse with the same voltage as the first reference voltage V obtained in operation S40. REF1 A pulse PL of corresponding amplitude. When the first mode is set in operation S20, the pulse generator 32 can generate a pulse with an amplitude corresponding to the conduction time t. ON A pulse PL of corresponding width. On the other hand, when the second mode is set in operation S20, the pulse generator 32 can generate a pulse with a width corresponding to the conduction time t. ON A pulse PL with a proportionally extended width. (See later...) Figure 13 Here is an example to describe the operation of S60.

[0095] In operation S80, an output signal OUT can be generated. For example, filter 34 can receive a pulse PL from pulse generator 32 and generate the output signal OUT by filtering the pulse PL. The pulse PL generated in operation S60 can have a value based on the inductor current I.L The amplitude and the conduction time t based on the power switch ON The width of the signal allows the output signal OUT generated by removing the high-frequency component of the pulse PL to have a value that depends on the load current I. LOAD The magnitude of a physical quantity (e.g., voltage).

[0096] Figure 12 This is a flowchart illustrating a method for measuring load current according to some exemplary embodiments of the present invention. Specifically, Figure 12 The flowchart shows Figure 11 Example of operation S20. See the reference above. Figure 11 As described, in Figure 12 In operation S20', the measurement mode can be set. For example... Figure 12 As shown, operation S20' may include multiple operations S22, S24, S26, and S28. In some example embodiments, operation S20' may be performed by... Figure 5 The pulse generator 52 performs the operation, and references will be made below. Figure 5 and Figure 6 To describe Figure 12 .

[0097] refer to Figure 12 In operation S22, the load current I can be... LOAD The value is compared with a first threshold THR1. For example, the first threshold THR1 may be less than a second threshold THR2, which will be described later, and the comparator 52_9 can represent the load current I. LOAD The magnitude of the output signal OUT and the second reference voltage V REF2 A comparison is made. In some example embodiments, the reference voltage generator 52_7 can generate a second reference voltage V with a constant level. REF2 Furthermore, the first threshold THR1 and the second threshold THR2 can be determined by the second reference voltage V. REF2 The hysteresis determination of comparator 52_9. In some example embodiments, reference voltage generator 52_7 may receive the output of comparator 52_9 (i.e., mode signal MD) and may generate a second reference voltage V at a level corresponding to the first threshold THR1 in a second mode. REF2 Furthermore, in the first mode, a second reference voltage V can be generated at a level corresponding to the second threshold THR2. REF2 .like Figure 12 As shown, when the load current I LOAD When the value is less than the first threshold THR1, a second mode can be set in operation S24, and when the load current I... LOAD When the value is equal to or greater than the first threshold THR1, operation S26 can be performed subsequently.

[0098] In operation S26, the load current I can be... LOAD The value is compared with the second threshold THR2. For example, the second threshold THR2 can be greater than the first threshold THR1 mentioned above, and the comparator 52_9 can represent the load current I. LOAD The magnitude of the output signal OUT and the second reference voltage V REF2 Compare. For example... Figure 12 As shown, when the load current I LOAD When the value is greater than the second threshold THR2, the first mode can be set in operation S28, and when the load current I LOAD When the value is equal to or less than the second threshold THR2, operation S20' can be terminated, and the mode set before operation S20' can be maintained. Therefore, hysteresis can be provided for the switching of measurement modes, and the possibility of frequent switching between the first mode and the second mode can be prevented or reduced.

[0099] Figure 13 This is a flowchart illustrating a method for measuring load current according to some exemplary embodiments of the present invention. Specifically, Figure 13 The flowchart shows Figure 11 An example of S60 operation. See the reference above. Figure 11 As described, in Figure 13 In operation S60', the on-time t of at least one power switch can be used as a basis. ON and the first reference voltage V REF1 To generate pulses. For example... Figure 13 As shown, operation S60' may include multiple operations S62, S64, and S66. In some example embodiments, operation S60' may be performed by... Figure 5 The pulse generator 52 performs the operation, and references will be made below. Figure 5 To describe Figure 13 .

[0100] refer to Figure 13 The measurement mode can be identified in operation S62. For example, logic circuit 52_3 can identify a high load current I measured based on the mode signal MD provided by comparator 52_9. LOAD First mode and / or measured low load current I LOAD The second mode. For example... Figure 13 As shown, when the first mode is identified, operation S64 can be executed subsequently, and when the second mode is identified, operation S66 can be executed subsequently.

[0101] In operation S64, it is possible to generate a time t during conduction. ONThe pulse PL is activated during the period. For example, in the first mode, the logic circuit 52_3 can generate a first control signal CTR1 based on the first drive signal DRV1 and the second drive signal DRV2, such that during the identified on-time t... ON The pulse PL activated during this period can be generated by the switching circuit 52_5.

[0102] In operation S66, a value with a conduction time t can be generated. ON A pulse PL with a proportionally extended width. For example, in the second mode, logic circuit 52_3 can generate a second control signal CTR2 based on the first drive signal DRV1 and the second drive signal DRV2. Time extension circuit 52_1 can generate a pulse with a width proportional to the conduction time t based on the second control signal CTR2. ON The extended signal EXT is deactivated (or activated) proportionally within a certain time period, and the logic circuit 52_3 can generate a first control signal CTR1 based on the extended signal EXT, such that it has a duration proportional to the conduction time t. ON A proportionally extended pulse PL can be generated by switching circuit 52_5. (Refer to...) Figure 14 Here is an example to describe operation S66'.

[0103] Figure 14 This is a flowchart illustrating a method for measuring load current according to some exemplary embodiments of the present invention. Specifically, Figure 14 The flowchart shows Figure 13 An example of operation S66. See the reference above. Figure 13 As described, in Figure 14 In operation S66', a function with a conduction time t can be generated. ON A pulse PL with a proportionally extended width. For example... Figure 14 As shown, operation S66' may include multiple operations S66_2, S66_4, S66_6, and S66_8. In some example embodiments, operation S66' may be... Figure 5 The pulse generator 52 executes. Reference will be made below. Figure 5 and Figure 8 To describe Figure 14 And assume Figure 5 The pulse generator 52 includes Figure 8 Time extension circuit 80.

[0104] refer to Figure 14 In operation S66_2, the first capacitor C1 and the second capacitor C2 can be discharged. For example, the third switch SW73 and the fourth switch SW74 can be turned on in response to the second control signal CTR2 provided by the logic circuit 52_3, so that the first capacitor C1 and the second capacitor C2 can be discharged.

[0105] In operation S66_4, the first capacitor C1 can be turned on during the conduction time t. ON Charging occurs during this period. For example, during the conduction time t. ON During this period, in response to the second control signal CTR2, the first switch SW71 can be turned on, and the third switch SW73 can be turned off. Therefore, the first capacitor C1 can be supplied with a constant current I by the current source 82. CON It charges, and the first voltage V1 can be increased.

[0106] In operation S66_6, the node of the first capacitor C1 can be floated, and the second capacitor C2 can be charged. For example, during the conduction time t... ON Subsequently, in response to the second control signal CTR2, the first switch SW71 can be turned off, and the second switch SW72 can be turned on. Therefore, the constant current I... CON The node applied to the first capacitor C1 (e.g., the first node N1) can be floated, and the first voltage V1 can be substantially maintained. Furthermore, the second capacitor C2 can be supplied with a constant current I provided by the current source 82. CON Charging occurs, and the second voltage V2 can be increased. Since the capacitance of the second capacitor C2 is greater than that of the first capacitor C1, the rate at which the second voltage V2 increases in operation S66_6 may be lower than the rate at which the first voltage V1 increases in operation S66_4, and the ratio between these two rates can be based on the ratio between the capacitance of the first capacitor C1 and the capacitance of the second capacitor C2.

[0107] In operation S66_8, a pulse PL can be generated based on the voltage of the first capacitor C1 and the voltage of the second capacitor C2. For example, when the conduction time t... ON At the start of operation S66_4 (i.e., when the first voltage V1 begins to increase), pulse PL can be activated. Furthermore, when the second voltage V2, increased in operation S66_6, reaches the first voltage V1, pulse PL can be deactivated. Therefore, pulse PL can have a frequency response time t. ON The width is increased / extended precisely or more precisely proportionally.

[0108] Figure 15 This is a flowchart illustrating a method for measuring load current according to some exemplary embodiments of the present invention. Specifically, Figure 15 The flowchart illustrates the detection of load current I based on the output signal OUT. LOAD The method of determining the size. In some example embodiments, Figure 15 The S90 can operate in Figure 11 The operation is executed after S80. For example... Figure 15As shown, operation S90 may include multiple operations S92, S94, S96, and S98. In some example embodiments, operation S90 may be performed by... Figure 10 The load 140 is executed, and will be referenced below. Figure 10 To describe Figure 15 .

[0109] refer to Figure 15 In operation S92, the output signal OUT can be converted into a digital signal DIG. For example, the output signal OUT can be a signal with a voltage equal to the load current I. LOAD The analog signal is a physical quantity (e.g., voltage) proportional to the magnitude of the signal, and the ADC142 can generate a digital signal DIG by converting the output signal OUT.

[0110] In operation S94, the measurement mode can be identified. For example, processing circuit 144 can receive mode signal MD from switch converter 120 and can identify load current I based on mode signal MD. LOAD Measurement modes. For example... Figure 15 As shown, when the first mode is identified, operation S98 can be executed subsequently, and when the second mode is identified, operation S96 can be executed subsequently.

[0111] In operation S96, the value of the digital signal DIG can be compensated. For example, in the second mode, the processing circuit 144 can divide the value of the digital signal DIG by a specific (or alternatively, predetermined) divisor. The divisor may correspond to the ratio of the pulse PL width extension in the switch converter 120. The divisor may be pre-stored in the processing circuit 144 and / or may be provided by the switch converter 120.

[0112] In operation S98, the load current I can be identified. LOAD The magnitude of the load current I. For example, in the first mode, the processing circuit 144 can identify the value of the digital signal DIG generated in operation S92. LOAD The size of the load current I. Furthermore, in the second mode, the processing circuit 144 can identify the load current I corresponding to the value obtained by compensating the value of the digital signal DIG in operation S96. LOAD Size.

[0113] Figure 16 This is a block diagram illustrating some example embodiments of a system 160 according to the concept of the present invention. For example... Figure 16 As shown, system 160 may include power management integrated circuit (PMIC) 162 and load 164.

[0114] System 160 can provide any function by consuming power and performing operations for the function through load 164. For example, system 160 may be or may include at least one of a computing system (such as a personal computer (PC), server, mobile phone and / or wearable device), a transportation unit (such as a vehicle, ship and / or electric skateboard) and / or a subsystem included in one of the above systems.

[0115] PMIC 162 may include the switch converter 162_2 described above with reference to the accompanying drawings, and may provide a positive supply voltage VDD generated by the switch converter 162_2 to the load 164. Furthermore, PMIC 162 may provide a status signal STA, including information about the power consumption of the load 164, to the load 164. For example, the switch converter 162_2 may generate a load current I as described above with reference to the accompanying drawings, which is supplied to the load 164. LOAD The magnitude of the output signal OUT corresponds to the value of the output signal OUT, and the PMIC162 can output the signal OUT and / or include information about the load current I detected based on the output signal OUT. LOAD The status signal STA, which provides information about the size of the load, is provided to the load 164.

[0116] Load 164 can receive a positive supply voltage VDD from PMIC 162 and can operate based on the positive supply voltage VDD. Furthermore, load 164 can receive a status signal STA from PMIC 162 and can estimate and / or identify the power consumption of load 164 based on the status signal STA. As described above with reference to the accompanying drawings, due to the precise or more accurate measurement of the load current I... LOAD Therefore, load 164 can estimate and / or identify the correct power consumption. Load 164 can control PMIC 162 via control signal CTR. For example, load 164 can provide the magnitude of the positive supply voltage VDD and enter and / or exit power-saving mode to PMIC 162 via control signal CTR. PMIC 162 can control the magnitude of the positive supply voltage VDD based on control signal CTR, and / or can stop and / or resume the generation of the positive supply voltage VDD.

[0117] Figure 17 This is a block diagram illustrating some example embodiments of a system 170 according to the present invention. In some example embodiments, system 170 may be an integrated circuit included in a semiconductor package (such as a system-on-a-chip (SoC)). In some example embodiments, system 170 may include a PCB and a semiconductor package mounted on the PCB. Figure 17 As shown, system 170 may include at least one processor 171, input and output interfaces 172, modem 173, memory 174, and PMIC 175.

[0118] At least one processor 171, input and output interface 172, modem 173, and memory 174 can operate based on power supplied by a first positive supply voltage VDD1 to a fourth positive supply voltage VDD4 provided by PMIC 175. For example, at least one processor 171 can execute a series of instructions and / or can process signals based on the first positive supply voltage VDD1. Input and output interface 172 can process inputs received from outside the system 170 and can generate outputs provided to outside the system 170 based on a second positive supply voltage VDD2. Modem 173 can process signals received through a communication channel and / or can generate signals to be transmitted through the communication channel based on a third positive supply voltage VDD3. Memory 174 can store data based on the fourth supply voltage VDD4 and can include volatile memory devices (such as dynamic random access memory (DRAM) and / or static RAM (SRAM)) and / or non-volatile memory devices (such as flash memory and / or resistive RAM (RRAM)).

[0119] PMIC 175 may include multiple switching converters 175_2, and each of the multiple switching converters 175_2 can draw power from the input voltage V. IN One of the first positive supply voltages VDD1 to the fourth positive supply voltage VDD4 is generated. As described above with reference to the accompanying drawings, each of the plurality of switching converters 175_2 can more accurately (e.g., precisely) measure the load current supplied by it, although the range of variation is wide.

[0120] Any element disclosed above may include and / or be implemented in processing circuitry (such as hardware including logic circuitry); hardware / software combinations (such as a processor executing software); or combinations thereof. For example, more specifically, processing circuitry may include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field-programmable gate array (FPGA), a system-on-a-chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc.

[0121] The above example embodiments are not necessarily mutually exclusive. For example, some example embodiments may include features described with reference to one or more accompanying drawings, and may also include features described with reference to other accompanying drawings. The example embodiments are not limited thereto.

[0122] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. An apparatus for measuring the load current supplied to a load of a switching converter, the apparatus comprising: A time extension circuit is configured to generate an extended signal that is activated during a time period proportional to the on-time of at least one power switch of the switch converter. A logic circuit is configured to generate a first control signal based on the on-time in response to a mode signal indicating a first mode, and the logic circuit is configured to generate the first control signal based on the extended signal in response to a mode signal indicating a second mode. A switching circuit is configured to receive a first reference voltage that defines the peak value of the inductor current passing through the inductor of the switching converter, and to generate pulses based on the first control signal; A filter is configured to generate an output signal by filtering the pulses; as well as A first comparator is configured to generate the mode signal based on the voltage of the output signal and a second reference voltage. The logic circuit is configured to be in the second mode based on the mode signal in response to the load current value being less than a first threshold.

2. The apparatus according to claim 1, wherein, The time extension circuit includes: The current source is configured to generate a constant current. A second comparator is configured to output the extended signal; A first capacitor connected to the second comparator and a second capacitor connected to the second comparator; and Multiple switches are configured to receive a second control signal. The logic circuit is configured to generate the second control signal in the second mode to charge the first capacitor with the constant current during the on-time and to charge the second capacitor with the constant current after the on-time.

3. The apparatus according to claim 2, wherein, The logic circuit is configured to generate the second control signal in the second mode, such that when the second capacitor is charged based on the constant current, the node to which the first capacitor and the second comparator are connected is floating.

4. The apparatus according to claim 2, wherein, The second comparator is configured to generate the extended signal activated in response to the voltage of the second capacitor being higher than the voltage of the first capacitor, and The logic circuit is configured to generate the first control signal in the second mode, such that the pulse is active from the first time point when the conduction time starts to the second time point when the extended signal is deactivated.

5. The apparatus according to claim 2, wherein, The plurality of switches includes: A first switch connected in parallel to the first capacitor; and The second switch is connected in parallel to the second capacitor. The logic circuit is configured to generate the second control signal in the second mode, such that the first switch and the second switch are turned on before the turn-on time.

6. The apparatus according to claim 2, wherein, The capacitance of the second capacitor is greater than the capacitance of the first capacitor.

7. The apparatus according to claim 1, wherein, The logic circuit is configured to respond to a load current value greater than a second threshold, based on the mode signal being in the first mode, and The second threshold is greater than the first threshold.

8. The apparatus according to claim 1, wherein, The device is configured to output the mode signal to the outside.

9. A switching converter configured to generate an output voltage from an input voltage, the switching converter comprising: An inductor connected to the output node that generates the output voltage and an output capacitor connected to the output node; At least one power switch is configured to provide inductor current to the inductor; A peak current detector circuit is configured to generate a peak signal by detecting the peak value of the inductor current, the peak value being based on a first reference voltage; A switch driver circuit is configured to control the at least one power switch based on the peak signal; as well as A load current meter is configured to generate pulses based on the first reference voltage and the on-time of the at least one power switch, and to generate an output signal representing the magnitude of the load current by filtering the pulses. The load current meter is configured to change from a first mode to a second mode based on the output signal in response to the value of the load current being less than a first threshold, and to extend the pulse width in the second mode.

10. The switching converter according to claim 9, wherein, The load current meter includes a first capacitor, a second capacitor, and a current source configured to generate a constant current. The load current meter is configured to charge the first capacitor with the constant current during the on-time, charge the second capacitor with the constant current after the on-time, and generate the pulse in the second mode based on the voltage of the first capacitor and the voltage of the second capacitor.

11. The switching converter according to claim 10, wherein, The load current meter is configured to float the node of the first capacitor that applies the constant current when the second capacitor is being charged by the constant current in the second mode.

12. The switching converter according to claim 10, wherein, The load current meter is configured to generate, in the second mode, the pulse active from the start of the conduction time to the point when the voltage of the second capacitor reaches the voltage of the first capacitor.

13. The switching converter according to claim 10, wherein, The load current meter is configured to discharge the first capacitor and the second capacitor before the on-time in the second mode.

14. The switching converter according to claim 9, wherein, The load current meter is configured to change from the second mode to the first mode based on the output voltage in response to the value of the load current being greater than a second threshold, wherein the second threshold is greater than the first threshold.

15. The switching converter according to claim 9, wherein, The peak current detector includes: A current sensor is configured to sense the inductor current; and A comparator is configured to generate the peak signal based on the output of the current sensor and the first reference voltage. The load current meter is configured to receive the first reference voltage from the peak current detector.

16. A method for measuring the load current supplied to a load of a switching converter, the method comprising: Obtain a first reference voltage that defines the peak value of the inductor current passing through the inductor of the switching converter; A pulse is generated based on the first reference voltage and the on-time of at least one power switch of the switching converter; The output signal is generated by filtering the pulse; as well as In response to the load current value being less than a first threshold, the system switches from a first mode to a second mode based on the output signal. The pulse generation further includes generating a pulse with a width that is proportionally extended to the conduction time in the second mode.

17. The method according to claim 16, wherein, Generating pulses with extended widths also includes: During the on-time, the first capacitor is charged by a constant current. After the on-time, the node to which the constant current is applied to the first capacitor is floated, and the second capacitor is charged by the constant current; and The pulse is generated based on the voltage of the first capacitor and the voltage of the second capacitor.

18. The method according to claim 17, wherein, Generating a pulse with an extended width further includes discharging the first capacitor before the on-time in the second mode, and discharging the second capacitor before the on-time in the second mode.

19. The method of claim 16, further comprising, in response to the value of the load current being greater than a second threshold, changing the output signal from the second mode to the first mode based on the output signal. in, The second threshold is greater than the first threshold.

20. The method of claim 16, further comprising: The magnitude of the load current is detected based on the output signal. The detection of the load current also includes: compensating for the value corresponding to the output signal in the second mode, the compensation being based on the ratio of the pulse width extension.

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