Power converter and transformation method

Abstract

A power converter and transformation method are disclosed. The power converter includes a power stage circuit, a ramp generation circuit, and a control circuit. The power stage circuit generates an output signal based on an input signal and a control signal. The ramp generation circuit generates a ramp signal based on the control signal, the input signal, and the output signal. The control circuit generates a control signal based on the output signal, a reference signal, and the ramp signal. Thus, the power converter can have better transient response and lower power consumption.

Description

Technical Field

[0001] The embodiments described in this disclosure relate to power conversion technology, and more particularly to a power converter and a transformation method. Background Technology

[0002] With the development of technology, various power converters have been applied to various circuit systems. Power converters include control circuitry to generate pulse-width modulation (PWM) signals based on feedback signals related to the output signal of the power converter. Power converters also include ramp generation circuitry to generate ramp signals, and the control circuitry adjusts the duty cycle of the PWM signal according to the ramp signal. In some related technologies, the ramp generation circuitry is implemented with active components and does not utilize the output signal to generate the ramp signal. Consequently, the output impedance of the power converter in these related technologies is relatively high, resulting in poor transient response. Summary of the Invention

[0003] Some embodiments disclosed herein relate to a power converter. The power converter includes a power stage circuit, a ramp generation circuit, and a control circuit. The power stage circuit generates an output signal based on an input signal and a control signal. The ramp generation circuit generates a ramp signal based on the control signal, the input signal, and the output signal. The control circuit generates a control signal based on the output signal, a reference signal, and the ramp signal.

[0004] In some embodiments, the ramp generation circuit includes a first impedance circuit and a second impedance circuit. The first impedance circuit is coupled between an output node and a ramp generation node and is used to receive an output signal from the output node. The second impedance circuit is coupled between an input node and a ramp generation node and is used to receive an input signal from the input node. The ramp signal is generated at the ramp generation node.

[0005] In some embodiments, the ramp generation circuit further includes a first switch and a second switch. The first switch is coupled between the first impedance circuit and the ramp generation node. The second switch is coupled between the second impedance circuit and the ramp generation node, or coupled between the second impedance circuit and the input node.

[0006] In some embodiments, the first switch and the second switch are controlled to be turned on within the same time interval.

[0007] In some embodiments, one of the first switch and the second switch is controlled by a control signal, and the other is controlled by a complementary control signal, wherein the complementary control signal is complementary to the control signal.

[0008] In some embodiments, one of the first impedance circuit and the second impedance circuit includes a capacitor.

[0009] In some embodiments, the first impedance circuit includes a first resistor and a capacitor, with the capacitor and the first resistor connected in parallel.

[0010] In some embodiments, the second impedance circuit includes a second resistor.

[0011] In some embodiments, the control circuit includes an error amplifier circuit, a comparator circuit, and a control signal generation circuit. The error amplifier circuit generates an amplified error signal based on the output signal and a reference signal. The comparator circuit generates a comparator signal based on the amplified error signal and a ramp signal. The control signal generation circuit generates a control signal based on the comparator signal.

[0012] In some embodiments, the control signal generation circuit includes an AND gate, an on-time controller, an off-time controller, a delay circuit, and an OR gate. The AND gate performs an AND operation on a comparison signal and an off-time control signal to generate a logic signal. The on-time controller generates an on-time control signal based on the logic signal. The off-time controller generates an off-time control signal based on the on-time control signal. The delay circuit delays the comparison signal to generate a delayed signal. The OR gate performs an OR operation on the delayed signal and the on-time control signal to generate a control signal.

[0013] In some embodiments, the power stage circuit includes a first switch, a second switch, and a filter circuit. The first switch is used to receive an input signal and is coupled to a node. The second switch is coupled between the node and a ground terminal. The first and second switches are controlled by a control signal. The filter circuit is coupled to the node and is used to output an output signal.

[0014] In some embodiments, when the control signal has a first logic level, the first switch is off and the second switch is on, and a voltage at the node is generated in response to the input signal. When the control signal has a second logic level, the first switch is on and the second switch is off, and a voltage at the node is generated in response to a ground voltage at the ground terminal.

[0015] Some embodiments disclosed herein relate to a voltage transformation method. The voltage transformation method includes: generating an output signal through a power stage circuit based on an input signal and a control signal; generating a ramp signal through a ramp generation circuit based on the control signal, the input signal, and the output signal; and generating a control signal through a control circuit based on the output signal, a reference signal, and the ramp signal.

[0016] In some embodiments, the transformation method further includes: receiving an output signal from an output node through a first impedance circuit of the ramp generation circuit; and receiving an input signal from an input node through a second impedance circuit of the ramp generation circuit. The ramp signal is generated at a ramp generation node.

[0017] In some embodiments, the ramp generation circuit further includes a first switch and a second switch, the first switch being coupled between the first impedance circuit and the ramp generation node, and the second switch being coupled between the second impedance circuit and the ramp generation node or coupled between the second impedance circuit and the input node.

[0018] In some embodiments, the transformer method further includes: turning on the first switch and the second switch within the same time interval.

[0019] In some embodiments, the transformer method further includes: controlling one of a first switch and a second switch using a control signal; and controlling the other of the first switch and the second switch using a complementary control signal, wherein the complementary control signal is complementary to the control signal.

[0020] In some embodiments, the transformation method further includes: receiving an input signal via a first switch in a power stage circuit, wherein the first switch is coupled to a node; controlling the first switch and a second switch in the power stage circuit via a control circuit, wherein the second switch is coupled between the node and a ground terminal; and outputting an output signal via a filter circuit in the power stage circuit. The filter circuit is coupled to the node.

[0021] In some embodiments, when the control signal has a first logic level, the first switch is off and the second switch is on, and a voltage at the node is generated in response to the input signal. When the control signal has a second logic level, the first switch is on and the second switch is off, and a voltage at the node is generated in response to a ground voltage at the ground terminal. Attached Figure Description

[0022] To make the above and other objects, features, advantages and embodiments disclosed herein more apparent and understandable, the accompanying drawings are described below:

[0023] Figure 1 This is a schematic diagram of a power converter illustrated according to some embodiments of the present disclosure;

[0024] Figure 2 This is a schematic diagram of a ramp wave generating circuit illustrated according to some embodiments of this disclosure;

[0025] Figure 3 It is illustrated in accordance with some embodiments of this disclosure. Figure 2 A schematic diagram of the ramp wave generating circuit in its first operation;

[0026] Figure 4 It is illustrated in accordance with some embodiments of this disclosure. Figure 2 A schematic diagram of the ramp wave generating circuit in a second operation;

[0027] Figure 5 This is a schematic diagram of a ramp wave generating circuit illustrated according to some embodiments of this disclosure;

[0028] Figure 6 It is illustrated in accordance with some embodiments of this disclosure. Figure 5 A schematic diagram of the ramp wave generating circuit in its first operation;

[0029] Figure 7 It is illustrated in accordance with some embodiments of this disclosure. Figure 5 A schematic diagram of the ramp wave generating circuit in a second operation; and

[0030] Figure 8 This is a flowchart illustrating a transformer method according to some embodiments of the present disclosure.

[0031] [Symbol Explanation]

[0032] 100: Power Converter

[0033] 110: Power stage circuit

[0034] 111: Filtering circuit

[0035] 112: Load

[0036] 120, 120A, 120B: Slope wave generation circuit

[0037] 122 A ,124 A 122 B ,124 B Impedance circuit

[0038] 130: Control Circuit

[0039] 131: Error Amplifier Circuit

[0040] 132: Comparator Circuit

[0041] 133: Control signal generation circuit

[0042] 1331: with the door

[0043] 1332: On-time controller

[0044] 1333: Deadline Controller

[0045] 1334: Delay Circuit

[0046] 1335: OR Gate

[0047] 800: Transformation Method

[0048] V IN Input signal

[0049] M P M N SW1 A SW2 A SW1 B SW2 B :switch

[0050] L X :node

[0051] GND: ground terminal

[0052] LS: Logic Signal

[0053] R LS ,R CO R1 A R2 A R1 B R2 B :resistance

[0054] C O C1 A C1 B :capacitance

[0055] V O Output signal

[0056] CS,S1 A S2 A S1 B S2 B Control signals

[0057] CS': Complementary control signal

[0058] V REF Reference signal

[0059] V C Error amplification signal

[0060] V PSR :Ramp signal

[0061] V COMP Comparison signal

[0062] V TOFF Deadline control signal

[0063] V TON On-time control signal

[0064] V COMP_B Delayed signal

[0065] IN: Input node

[0066] OUT: Output node

[0067] PSR: Oblique Wave Generating Node

[0068] L S :inductance

[0069] S810, S820, S830: Operation Detailed Implementation

[0070] The term "coupled" as used in this article can also refer to "electrical coupling," and the term "connection" can also refer to "electrical connection." "Coupled" and "connection" can also refer to two or more components cooperating or interacting with each other.

[0071] refer to Figure 1 . Figure 1 This is a schematic diagram of a power converter 100 illustrated in accordance with some embodiments of this disclosure.

[0072] by Figure 1 For example, power converter 100 includes power stage circuitry 110, ramp generation circuitry 120, and control circuitry 130. Power stage circuitry 110 is coupled to ramp generation circuitry 120 and control circuitry 130. Ramp generation circuitry 120 is coupled to control circuitry 130.

[0073] Control circuit 130 generates a control signal CS, which is a pulse width modulation (PWM) signal. Power stage circuit 110 is used to generate a control signal CS based on the input signal V. IN And the control signal CS generates the output signal V O .by Figure 1 For example, power stage circuit 110 includes switch M P Switch M N 111 filter circuit and 112 load.

[0074] Switch M P The first terminal is used to receive the input signal V IN Switch M P The second end coupling node L X And switch M P The control terminal is used to receive the control signal CS. Switch M N The first terminal is coupled to ground terminal GND, switch M N The second end coupling node L X And switch M N The control terminal is used to receive the control signal CS. The control signal CS is used to control switch M. P and switch M N To turn on or off. For example, when the control signal CS has a first logic level (e.g., a high logic level), switch M... P Cut off and switch MN On, located at node L X The voltage response to the input signal V IN This is generated when the control signal CS has a second logic level (e.g., a low logic level), switch M... P On and switch M N Deadline, located at node L X The voltage is generated in response to the ground voltage at the ground terminal GND.

[0075] Filter circuit 111 coupling node L X And used to output signal V O Output. Specifically, the filter circuit 111 includes an inductor L. S Resistance R LS Capacitor C O and resistance R CO Inductor L S First end coupling node L X And inductance L S The second terminal is coupled to the resistor R. LS The first terminal. Resistor R LS The second terminal is used to output signal V O Output and coupling capacitor C O The first terminal. Capacitor C O The second terminal is coupled to the resistor R. LS The first terminal, and the resistance R LS The second terminal is coupled to the ground terminal GND.

[0076] As described above, the control signal CS is used to control switch M. P and switch M N To turn on or off. In other words, the duty cycle of the control signal CS determines the state of switch M. P On-time and switch M N The conduction time is used to output signal V O Output. Output signal V O Essentially equal to the input signal V IN The product of the duty cycle (e.g., 30%) of the control signal CS.

[0077] The ramp generation circuit 120 is used to generate ramps based on the control signal CS and the input signal V. IN and output signal V O Generate ramp signal V PSR .

[0078] Control circuit 130 is used to determine the output signal V O Reference signal V REF and ramp signal V PSR Generate a control signal CS. Figure 1For example, control circuit 130 includes error amplifier circuit 131, comparator circuit 132, and control signal generation circuit 133.

[0079] The first terminal of the error amplifier circuit 131 is used to receive the output signal V. O Furthermore, the second terminal of the error amplifier circuit 131 is used to receive the reference signal V. REF The error amplifier circuit 131 operates based on the output signal V. O and reference signal V REF Generate error amplification signal V C .

[0080] The first input terminal of the comparator circuit 132 is used to receive the error amplification signal V. C The second input terminal of the comparator circuit 132 is used to receive the ramp signal V. PSR Comparator circuit 132 amplifies the error signal V. C and ramp signal V PSR Comparison to generate comparison signal V COMP .

[0081] The control signal generation circuit 133 generates the signal based on the comparison signal V. COMP A control signal CS is generated. Specifically, the control signal generation circuit 133 includes an AND gate 1331, an on-time controller 1332, an off-time controller 1333, a delay circuit 1334, and an OR gate 1335.

[0082] The first input of AND gate 1331 is used to receive the comparison signal V. COMP The second input of AND gate 1331 is used to receive the cutoff time control signal V. TOFF AND gate 1331 compares the signal V. COMP and the deadline control signal V TOFF Execute and perform operations to generate logic signals LS.

[0083] The on-time controller 1332 is used to receive the logic signal LS and generate the on-time control signal V based on the logic signal LS. TON The on-time controller 1332 is triggered by the rising edge and determines the width of the logic value 1.

[0084] Additionally, the cutoff time controller 1333 is used to receive the on-time control signal V. TON And based on the conduction time control signal V TON Generate cutoff time control signal V TOFF The deadline controller 1333 is triggered by a falling edge and determines the width of the logic value 0.

[0085] Delay circuit 1334 is used to receive comparison signal V COMP And for the comparison signal V COMP Delay for a certain period of time to generate a delayed signal V COMP_B The delay circuit 1334 can avoid noise.

[0086] The first input of OR gate 1335 is used to receive the delayed signal V. COMP_B The second input of OR gate 1335 is used to receive the on-time control signal V. TON OR gate 1335 for delayed signal V COMP_B and the on-time control signal V TON Perform an OR operation to generate the control signal CS.

[0087] The implementation and operation of the ramp generation circuit 120 will be described in the following paragraphs.

[0088] refer to Figure 2 . Figure 2 This is a schematic diagram of a ramp wave generating circuit 120A illustrated according to some embodiments of this disclosure. In some embodiments, Figure 1 The ramp wave generating circuit 120 in the middle is composed of Figure 2 The 120A ramp wave generation circuit is implemented in the middle.

[0089] by Figure 2 For example, the ramp generation circuit 120A includes an impedance circuit 122. A Switch SW1 A Impedance circuit 124 A and switch SW2 A Impedance circuit 122 A Coupled to output node OUT and switch SW1 A It is used to receive the output signal V from the output node OUT. O Switch SW1 A Coupled to impedance circuit 122 A Between the slope wave generating node PSR and impedance circuit 124. A Coupled to the ramp generation node PSR and switch SW2 A Between. Switch SW2 A Coupled to impedance circuit 124 A It is connected to the input node IN and used to receive the input signal V received from the input node IN. IN Switch SW1 A Control signal S1 A Controlled, and switch SW2 A Control signal S2 A Controlled. Slope signal V PSR It originates at the oblique wave generation node PSR.

[0090] refer to Figure 3 . Figure 3 It is illustrated in accordance with some embodiments of this disclosure. Figure 2 A schematic diagram of the ramp wave generating circuit 120A in its first operation.

[0091] by Figure 3 For example, impedance circuit 122 A Including resistor R1 A and capacitor C1 A Impedance circuit 124 A Including resistor R2 A In other words, impedance circuit 122 A and impedance circuit 124 A It is formed by passive components, and the impedance circuit 122 A and impedance circuit 124 A At least one of them contains a capacitor. Resistor R1 A and capacitor C1 A Parallel coupling. Specifically, resistor R1 A The first terminal and capacitor C1 A The first end is coupled to the output node OUT, and the resistor R1 A The second terminal and capacitor C1 A The second terminal coupling switch SW1 A Resistor R2 A The first end is coupled to the slope wave generating node PSR, resistor R2 A The second terminal coupling switch SW2 A .

[0092] exist Figure 3 In the example, Figure 1 The control signal CS generated by the control circuit 130 is used as the control signal S2. A And control signal S2 A Used to turn switch SW2 on or off A Additionally, the complementary control signal CS', which is the complement of the control signal CS, is used as the control signal S1. A And control signal S1 A Used to turn on or off switch SW1 A In other words, when switch SW2... A On, switch SW1 A Cut-off. In another embodiment, the control signal CS is used as the control signal S1. A Furthermore, the complement of the control signal CS serves as the control signal S2. A .

[0093] refer to Figure 4 . Figure 4It is illustrated in accordance with some embodiments of this disclosure. Figure 2 A schematic diagram of the ramp wave generating circuit 120A in its second operation.

[0094] exist Figure 4 In the example, switch SW1 A and switch SW2 A They conduct within the same time interval. For example, if switch SW1... A and switch SW2 A Implemented using an N-type transistor, control signal S1 A and control signal S2 A Both have a logic value of 1 within the same time interval, and switch SW1 A and switch SW2 A Control signals S1, each with a logic value of 1 A and control signal S2 A Conduction.

[0095] refer to Figure 5 . Figure 5 This is a schematic diagram of a ramp wave generating circuit 120B illustrated according to some embodiments of this disclosure. In some embodiments, Figure 1 The ramp wave generating circuit 120 in the middle is composed of Figure 5 The ramp wave generation circuit 120B is implemented in the middle.

[0096] by Figure 5 For example, the ramp generation circuit 120B includes an impedance circuit 122. B Switch SW1 B Impedance circuit 124 B and switch SW2 B Impedance circuit 122 B Coupled to output node OUT and switch SW1 B It is used to receive the output signal V from the output node OUT. O Switch SW1 B Coupled to impedance circuit 122 B Between the slope wave generating node PSR and switch SW2. B Coupled to the slope generation node PSR and impedance circuit 124 B Between. Impedance circuit 124 B Coupled to switch SW2 B It is connected to the input node IN and used to receive the input signal V from the input node IN. IN Switch SW1 B Control signal S1 B Control, and switch SW2 B Control signal S2 B Control. Slope signal VPSR It originates at the oblique wave generation node PSR.

[0097] refer to Figure 6 . Figure 6 It is illustrated in accordance with some embodiments of this disclosure. Figure 5 A schematic diagram of the ramp wave generating circuit 120B in its first operation.

[0098] by Figure 6 For example, impedance circuit 122 B Including resistor R1 B and capacitor C1 B Impedance circuit 124 B Including resistor R2 B In other words, impedance circuit 122 B and impedance circuit 124 B It is formed by passive components, and the impedance circuit 122 B and impedance circuit 124 B At least one of them contains a capacitor. Resistor R1 B and capacitor C1 B Parallel coupling. Specifically, resistor R1 B The first terminal and capacitor C1 B The first end is coupled to the output node OUT, and the resistor R1 B The second terminal and capacitor C1 B The second terminal coupling switch SW1 B Resistor R2 B First-end coupling switch SW2 B And resistance R2 B The second end is coupled to the input node IN.

[0099] exist Figure 6 In the example, control signal S2 B for Figure 1 The control signal CS generated by the control circuit 130 is used as the control signal S2. B And control signal S2 B Used to turn switch SW2 on or off B Additionally, the complementary control signal CS' is the complementary control signal CS' to control signal S1. B And control signal S1 B Used to turn on or off switch SW1 B In other words, when switch SW2... B On, switch SW1 B Cut-off. In another embodiment, the control signal CS is used as the control signal S1. B Furthermore, the complement of the control signal CS serves as the control signal S2.B .

[0100] refer to Figure 7 . Figure 7 It is illustrated in accordance with some embodiments of this disclosure. Figure 5 A schematic diagram of the ramp wave generating circuit 120B in its second operation.

[0101] exist Figure 7 In the example, switch SW1 B and switch SW2 B They conduct within the same time interval. For example, if switch SW1... B and switch SW2 B Implemented using an N-type transistor, control signal S1 B and control signal S2 B Both have a logic value of 1 within the same time interval, and switch SW1 B and switch SW2 B Control signals S1, each with a logic value of 1 B and control signal S2 B Conduction.

[0102] In some traditional technologies, ramp generation circuits are implemented using active components and do not utilize the output signal to generate the ramp signal. Consequently, the output impedance of the power converter in these technologies is relatively high, resulting in poor transient response.

[0103] Compared to the aforementioned conventional technologies, the ramp generation circuit 120 disclosed herein uses a passive impedance circuit (without amplification, voltage-to-voltage conversion, or voltage-to-current conversion) and utilizes the output signal V O Generate ramp signal V PSR Thus, the power converter 100 exhibits better transient response and lower power consumption. Next, the control circuit 130 can detect the output signal V. O To generate an error amplification signal V C Furthermore, the conduction time of the logic signal LS is extended to generate the control signal CS, thereby controlling the switch M. P and switch M N .

[0104] refer to Figure 8 . Figure 8 This is a flowchart illustrating a transformer method 800 according to some embodiments of the present disclosure. The transformer method 800 includes operations S810, S820, and S830. In some embodiments, the transformer method 800 can be applied to... Figure 1 The power converter 100 is described herein, but this disclosure is not limited thereto. For ease of understanding, the following paragraphs will be accompanied by... Figure 1 The transformer method 800 is described.

[0105] In operation of S810, the power stage circuit 110 operates according to the input signal V. IN And the control signal CS generates the output signal V O .by Figure 1 For example, the control signal CS can turn switch M on or off. P and switch M N To control the node L in response to the duty cycle of the control signal CS. X The voltage. Next, the filter circuit 111 can adjust the voltage based on the voltage located at node L. X The voltage generates an output signal V O .

[0106] When operating S820, the ramp generation circuit 120 operates based on the control signal CS and the input signal V. IN and output signal V O Generate ramp signal V PSR The ramp wave generating circuit 120 can be composed of... Figure 2 The ramp wave generation circuit 120A is implemented or is made by Figure 5 The ramp generation circuit 120B in the middle implements the generation of ramp signal V. PSR .

[0107] During operation of S830, control circuit 130 determines the output signal V based on... O Reference signal V REF and ramp signal V PSR Generate a control signal CS. Figure 1 For example, the error amplifier circuit 131 calculates based on the output signal V. O and reference signal V REF Generate error amplification signal V C Comparator circuit 132 compares the error amplification signal V. C and ramp signal V PSR To generate comparison signal V COMP The control signal generation circuit 133 generates the signal based on the comparison signal V. COMP Generates control signal CS.

[0108] In summary, the power converter disclosed herein exhibits superior transient response and lower power consumption.

[0109] Although this disclosure has been described above with reference to embodiments, it is not intended to limit this disclosure. Any person skilled in the art can make various modifications and refinements without departing from the spirit and scope of this disclosure. Therefore, the scope of protection of this disclosure shall be determined by the scope defined in the appended claims.

Claims

1. A power converter, characterized in that, Include: A power stage circuit for generating an output signal based on an input signal and a control signal; A ramp generation circuit is used to generate a ramp signal based on the control signal, the input signal, and the output signal; and A control circuit is used to generate the control signal based on the output signal, a reference signal, and the ramp signal. The ramp wave generating circuit includes: A first impedance circuit is coupled between an output node and a ramp generation node; A second impedance circuit is coupled between an input node and the ramp generation node; A first switch is coupled between the first impedance circuit and the ramp generation node; A second switch is coupled between the second impedance circuit and the ramp generation node, or coupled between the second impedance circuit and the input node. The first impedance circuit includes a capacitor, a first terminal of which is coupled to the first switch, and a second terminal of which is the output node.

2. The power converter according to claim 1, characterized in that, The first impedance circuit is used to receive the output signal from the output node; and The second impedance circuit is used to receive the input signal from the input node. The ramp signal is generated at the ramp generation node.

3. The power converter according to claim 2, characterized in that, The first switch and the second switch are controlled to be turned on within the same time interval.

4. The power converter according to claim 2, characterized in that, One of the first switch and the second switch is controlled by the control signal, and the other is controlled by a complementary control signal, wherein the complementary control signal is complementary to the control signal.

5. The power converter according to claim 2, characterized in that, The first impedance circuit includes a first resistor and a capacitor, which are connected in parallel with the first resistor.

6. The power converter according to claim 5, characterized in that, The second impedance circuit includes a second resistor.

7. The power converter according to claim 1, characterized in that, The control circuit includes: An error amplifier circuit is used to generate an error amplification signal based on the output signal and the reference signal; A comparator circuit is used to generate a comparison signal based on the error amplification signal and the ramp signal; as well as A control signal generation circuit is used to generate the control signal based on the comparison signal.

8. The power converter according to claim 7, characterized in that, The control signal generation circuit includes: An AND gate is used to perform an AND operation on the comparison signal and a cutoff time control signal to generate a logic signal; An on-time controller is used to generate an on-time control signal based on the logic signal; A cutoff time controller for generating a cutoff time control signal based on the on-time control signal; A delay circuit is used to delay the comparison signal to generate a delayed signal; and An OR gate is used to perform an OR operation on the delay signal and the on-time control signal to generate the control signal.

9. The power converter according to claim 1, characterized in that, The power stage circuit includes: A third switch is used to receive the input signal and is coupled to a node; A fourth switch is coupled between the node and a ground terminal, wherein the third switch and the fourth switch are controlled by the control signal; as well as A filter circuit is coupled to the node and used to output the output signal.

10. The power converter according to claim 9, characterized in that, in When the control signal has a first logic level, the third switch is off and the fourth switch is on, and a voltage at the node is generated in response to the input signal. When the control signal has a second logic level, the third switch is turned on and the fourth switch is turned off, and the voltage at the node is generated in response to a ground voltage at the ground terminal.

11. A transformer method, characterized in that, Include: An output signal is generated by a power stage circuit based on an input signal and a control signal. A ramp signal is generated by a ramp generation circuit based on the control signal, the input signal, and the output signal; and The control signal is generated by a control circuit based on the output signal, a reference signal, and the ramp signal. The ramp wave generating circuit includes: A first impedance circuit is coupled between an output node and a ramp generation node; A second impedance circuit is coupled between an input node and the ramp generation node; A first switch is coupled between the first impedance circuit and the ramp generation node; A second switch is coupled between the second impedance circuit and the ramp generation node, or coupled between the second impedance circuit and the input node. The first impedance circuit includes a capacitor, a first terminal of which is coupled to the first switch, and a second terminal of which is the output node.

12. The transformer method according to claim 11, characterized in that, Also includes: The output signal is received from the output node through the first impedance circuit of the ramp generation circuit; and The input signal is received from the input node through the second impedance circuit of the ramp generation circuit. The ramp signal is generated at the ramp generation node.

13. The transformer method according to claim 12, characterized in that, Also includes: The first switch and the second switch are turned on within the same time interval.

14. The transformer method according to claim 12, characterized in that, Also includes: The control signal is used to control one of the first switch and the second switch; and The first switch and the other of the second switch are controlled by a complementary control signal, wherein the complementary control signal is complementary to the control signal.

15. The transformer method according to claim 12, characterized in that, Also includes: The input signal is received through a third switch in the power stage circuit, wherein the third switch is coupled to a node. The control circuit controls the first switch and a fourth switch in the power stage circuit, wherein the fourth switch is coupled between the node and a ground terminal; and The output signal is output through a filter circuit in the power stage circuit. The filter circuit is coupled to this node.

16. The transformer method according to claim 15, characterized in that, in When the control signal has a first logic level, the third switch is off and the fourth switch is on, and a voltage at the node is generated in response to the input signal. When the control signal has a second logic level, the third switch is turned on and the fourth switch is turned off, and the voltage at the node is generated in response to a ground voltage at the ground terminal.

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