Level conversion circuit, chip and electronic device

Abstract

The present invention discloses a level conversion circuit, chip, and electronic device. The level conversion circuit includes: an input unit connected to a signal input terminal and configured to perform voltage limiting processing on an input signal at the signal input terminal to obtain a first voltage; a substrate bias conversion unit connected to the input unit and configured to generate a first current and a second current based on different substrate bias effects under the action of the first voltage; a current mirror unit connected to the substrate bias conversion unit and configured to compare the first current and the second current; and an output voltage conversion unit connected to the current mirror unit and a signal output terminal and configured to perform voltage conversion on the comparison result to obtain an output signal, which is then outputted through the signal output terminal. Thus, a low-power, large-swing level conversion function is achieved, improving the applicability of the level conversion circuit.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and particularly to a level conversion circuit, a chip and an electronic device. Background Art

[0002] With the advent of the information and intelligent era, devices with various functions are integrated together. Due to different working characteristics, the signal levels of different devices are diverse. Therefore, it is necessary to design a circuit that can adapt to the level conversion between different voltage domains to achieve fast conversion between different signal levels, so as to realize signal transmission between devices with various functions.

[0003] Traditional level conversion circuits can meet the level conversion between fixed voltage domains inside the chip to meet the signal transmission between known systems in the corresponding voltage domains inside the chip. For example, Figure 1 shows a low-level to high-level conversion circuit. This circuit completes the level conversion between fixed voltage domains through a differential feedback structure. However, the differential feedback structure requires the input terminal to give differential signals with opposite logics. This differential signal not only limits the input signal range of the level conversion circuit, but also the phase error of the differential signal will cause relatively large power consumption during the high-voltage conversion process. At the same time, for a single-polarity input signal with an uncertain level, this level conversion circuit is difficult to meet the requirements. Summary of the Invention

[0004] The present invention aims to solve at least one of the technical problems in the related art to some extent. For this purpose, the first object of the present invention is to propose a level conversion circuit. By compressing and limiting the input signal, it can realize a single-polarity large swing of the input signal, meet a wider range of signal level input applications, and by adopting a substrate biasing structure, it can realize fine control of level conversion and reduce power consumption during the high-voltage conversion process, thereby realizing the level conversion function with low power consumption and large swing, and improving the applicability of the level conversion circuit.

[0005] The second object of the present invention is to propose a chip.

[0006] The third object of the present invention is to propose an electronic device.

[0007] To achieve the above object, an embodiment of the first aspect of the present invention provides a level conversion circuit, including: an input unit connected to a signal input terminal for performing voltage limiting processing on an input signal of the signal input terminal to obtain a first voltage; a substrate bias conversion unit connected to the input unit for generating a first current and a second current based on different substrate bias effects under the action of the first voltage; a current mirror unit connected to the substrate bias conversion unit for comparing the first current and the second current; and an output voltage conversion unit connected to the current mirror unit and a signal output terminal for performing voltage conversion on a comparison result to obtain an output signal and outputting the output signal through the signal output terminal.

[0008] According to the level conversion circuit of the embodiment of the present invention, by performing compression limiting on the input signal, a single-polarity large swing of the input signal can be achieved, meeting a wider range of signal level input applications. By adopting a substrate bias structure, fine control of level conversion can be achieved, reducing power consumption during the high-voltage conversion process, thereby realizing the level conversion function with low power consumption and large swing, and improving the applicability of the level conversion circuit.

[0009] According to an embodiment of the present invention, the input unit includes: a limiting circuit connected to the signal input terminal for performing voltage limiting processing on the input signal to obtain a second voltage; and a voltage dividing circuit connected to the limiting circuit for performing voltage dividing processing on the second voltage to obtain a first voltage.

[0010] According to an embodiment of the present invention, the limiting circuit includes: a first resistor, one end of the first resistor is connected to the signal input terminal; a zener diode, the cathode of the zener diode is connected to the other end of the first resistor and a first node is formed, and the anode of the zener diode is grounded.

[0011] According to an embodiment of the present invention, the voltage dividing circuit includes: a second resistor, one end of the second resistor is connected to the first node; a first switching transistor, the control electrode and the first electrode of the first switching transistor are respectively connected to the other end of the second resistor and a second node is formed, the second electrode of the first switching transistor is grounded, and the second node is connected to the substrate bias conversion unit.

[0012] According to an embodiment of the present invention, the substrate bias conversion unit includes: a second switching transistor, the control electrode of the second switching transistor is connected to the input unit, the first electrode of the second switching transistor is connected to the current mirror unit, and the substrate of the second switching transistor is grounded; a third switching transistor, the control electrode of the third switching transistor is connected to the control electrode of the second switching transistor, the first electrode of the third switching transistor is connected to the current mirror unit, and the second electrode, the substrate of the third switching transistor and the second electrode of the second switching transistor are connected and a third node is formed; a third resistor, one end of the third resistor is connected to the third node, and the other end of the third resistor is grounded.

[0013] According to an embodiment of the present invention, the current mirror unit includes: a fourth switching transistor, the control electrode and the first electrode of the fourth switching transistor are respectively connected to the first electrode of the second switching transistor, and the second electrode of the fourth switching transistor is connected to the power supply; a fifth switching transistor, the control electrode of the fifth switching transistor is connected to the control electrode of the fourth switching transistor, the first electrode of the fifth switching transistor is connected to the first electrode of the third switching transistor and a fourth node is formed, the second electrode of the fifth switching transistor is connected to the power supply, and the fourth node is connected to the output voltage conversion unit.

[0014] According to an embodiment of the present invention, the current mirror unit further includes: a clamping circuit, the clamping circuit is disposed between the first electrode of the fourth switching transistor and the first electrode of the fifth switching transistor, and is used for clamping the voltage of the fourth node.

[0015] According to an embodiment of the present invention, the clamping circuit includes: a sixth switching transistor, the control electrode and the first electrode of the sixth switching transistor are connected to the fourth node, and the second electrode of the sixth switching transistor is connected to the first electrode of the fourth switching transistor.

[0016] According to an embodiment of the present invention, the voltage conversion circuit further includes: an isolation unit, the isolation unit is disposed between the substrate bias conversion unit and the current mirror unit, and is used for isolating and protecting the substrate bias conversion unit.

[0017] According to an embodiment of the present invention, the isolation unit includes: a voltage dividing circuit, the voltage dividing circuit is used for dividing the voltage of the power supply to obtain a third voltage; an isolation circuit, the isolation circuit is connected to the voltage dividing circuit, and is used for isolating and protecting the substrate bias conversion unit under the action of the third voltage.

[0018] According to an embodiment of the present invention, the voltage dividing circuit includes: a fourth resistor, one end of the fourth resistor is connected to the power supply; a seventh switching transistor, the control electrode and the first electrode of the seventh switching transistor are respectively connected to the other end of the fourth resistor and a fifth node is formed, and the fifth node is connected to the isolation circuit; an eighth switching transistor, the control electrode and the first electrode of the eighth switching transistor are respectively connected to the second electrode of the seventh switching transistor, and the second electrode of the eighth switching transistor is grounded.

[0019] According to an embodiment of the present invention, the isolation circuit includes: a ninth switching transistor, the control electrode of the ninth switching transistor is connected to the voltage dividing circuit, the first electrode of the ninth switching transistor is connected to the first electrode of the fourth switching transistor, and the second electrode of the ninth switching transistor is connected to the first electrode of the second switching transistor; a tenth switching transistor, the control electrode of the tenth switching transistor is connected to the control electrode of the ninth switching transistor, the first electrode of the tenth switching transistor is connected to the first electrode of the fifth switching transistor, and the second electrode of the tenth switching transistor is connected to the first electrode of the third switching transistor.

[0020] According to an embodiment of the present invention, the output voltage conversion unit includes: an eleventh switching transistor, the control electrode of the eleventh switching transistor is connected to the current mirror unit, the first electrode of the eleventh switching transistor is connected to the signal output terminal, and the second electrode of the eleventh switching transistor is connected to the power supply; a fifth resistor, one end of the fifth resistor is connected to the first electrode of the eleventh switching transistor, and the other end of the fifth resistor is connected to the reference ground.

[0021] To achieve the above object, an embodiment of the second aspect of the present invention provides a chip, including the foregoing level conversion circuit.

[0022] The chip according to the embodiment of the present invention adopts the foregoing level conversion circuit. By performing compression limiting on the input signal, a single-polarity large swing of the input signal can be achieved, meeting a wider range of signal level input applications. By adopting a substrate bias structure, fine control of level conversion can be achieved, reducing power consumption during the high-voltage conversion process, thereby realizing the level conversion function with low power consumption and large swing, improving the applicability of the chip and reducing the power consumption of the chip.

[0023] To achieve the above object, an embodiment of the third aspect of the present invention provides an electronic device, including the foregoing chip.

[0024] The electronic device according to the embodiment of the present invention adopts the foregoing chip. By performing compression limiting on the input signal, a single-polarity large swing of the input signal can be achieved, meeting a wider range of signal level input applications. By adopting a substrate bias structure, fine control of level conversion can be achieved, reducing power consumption during the high-voltage conversion process, thereby realizing the level conversion function with low power consumption and large swing, improving the applicability of the electronic device and reducing the power consumption of the electronic device.

[0025] Additional aspects and advantages of the present invention will be given in part in the following description, become apparent in part from the following description, or be learned through the practice of the present invention. Description of the Drawings

[0026] Figure 1 It is a circuit diagram of a low-level to high-level conversion circuit in the related art;

[0027] Figure 2 It is a schematic structural diagram of a level conversion circuit according to an embodiment of the present invention;

[0028] Figure 3 It is a circuit diagram of a level conversion circuit according to an embodiment of the present invention;

[0029] Figure 4 It is a voltage compression conversion schematic diagram of an input unit according to an embodiment of the present invention;

[0030] Figure 5Schematic diagram of voltage conversion clamped by a clamping unit according to an embodiment of the present invention;

[0031] Figure 6 Circuit diagram of a level conversion circuit according to another embodiment of the present invention;

[0032] Figure 7 Schematic diagram of input-output level conversion according to an embodiment of the present invention;

[0033] Figure 8 Schematic diagram of the structure of a chip according to an embodiment of the present invention;

[0034] Figure 9 Schematic diagram of the structure of an electronic device according to an embodiment of the present invention. Detailed implementation manners

[0035] Embodiments of the present invention will be described in detail below. Examples of the embodiments are shown in the accompanying drawings, where the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to explain the present invention, and should not be construed as limiting the present invention.

[0036] A level conversion circuit, a chip, and an electronic device proposed according to an embodiment of the present invention will be described below with reference to the accompanying drawings.

[0037] Figure 2 Schematic diagram of the structure of a level conversion circuit according to an embodiment of the present invention.

[0038] Refer to Figure 2 As shown, the level conversion circuit 100 includes: an input unit 110, a substrate bias conversion unit 120, a current mirror unit 130, and an output voltage conversion unit 140.

[0039] Among them, the input unit 110 is connected to the signal input terminal VIN and is used to perform voltage limiting processing on the input signal of the signal input terminal VIN to obtain a first voltage; the substrate bias conversion unit 120 is connected to the input unit 110 and is used to generate a first current and a second current based on different substrate bias effects under the action of the first voltage; the current mirror unit 130 is connected to the substrate bias conversion unit 120 and is used to compare the first current and the second current; the output voltage conversion unit 140 is connected to the current mirror unit 130 and the signal output terminal VOUT, and is used to perform voltage conversion on the comparison result to obtain an output signal and output it through the signal output terminal VOUT.

[0040] Specifically, the input unit 110, as the receiving and processing part of the input signal, is provided with a limiting structure. Through the limiting structure, the input signal at the signal input terminal VIN is compressed in voltage range to obtain a first voltage, so that the first voltage meets the operating voltage range of the substrate bias conversion unit 120, thereby enabling a single-polarity large swing of the input signal. The substrate bias conversion unit 120 is provided with a substrate bias structure, and a structure for realizing differential current comparison is based on the substrate bias structure. The substrate bias structure has different substrate bias effects, and generates a first current and a second current under the action of the first voltage. Due to the substrate bias effect, low-power fine control of voltage-current conversion can be achieved, so the power consumption during the high-voltage conversion process can be reduced, and low-power level conversion under high voltage can be realized. The current mirror unit 130 is mainly used to complete the current mirror comparison of the first current and the second current. The output voltage conversion unit 140 is mainly used to convert the comparison result of the first current and the second current into the logic level required at the output terminal, and output it through the signal output terminal VOUT.

[0041] In the above embodiment, by compressing and limiting the input signal, a single-polarity large swing of the input signal can be achieved, meeting a wider range of signal level input applications. By adopting the substrate bias structure, low-power fine control of level conversion can be achieved, reducing the power consumption during the high-voltage conversion process, thereby realizing the level conversion function with low power consumption and large swing, and improving the applicability of the level conversion circuit.

[0042] In some embodiments, referring to Figure 3 as shown, the input unit 110 includes: a limiting circuit 111 and a voltage dividing circuit 112. The limiting circuit 111 is connected to the signal input terminal VIN and is used to perform voltage limiting processing on the input signal to obtain a second voltage; the voltage dividing circuit 112 is connected to the limiting circuit 111 and is used to perform voltage dividing processing on the second voltage to obtain a first voltage.

[0043] Further, continuing to refer to Figure 3 as shown, the limiting circuit 111 includes: a first resistor R1 and a zener diode Z. One end of the first resistor R1 is connected to the signal input terminal VIN; the cathode of the zener diode Z is connected to the other end of the first resistor R1 and a first node J1 is formed, and the anode of the zener diode Z is grounded to GND.

[0044] The voltage dividing circuit 112 includes: a second resistor R2 and a first switching transistor M1. One end of the second resistor R2 is connected to the first node J1; the control electrode and the first electrode of the first switching transistor M1 are respectively connected to the other end of the second resistor R2 and a second node J2 is formed, the second electrode of the first switching transistor M1 is grounded to GND, and the second node J2 is connected to the substrate bias conversion unit 120.

[0045] Specifically, the limiting circuit 111 is mainly used to compress the voltage range of the input signal at the signal input terminal VIN to achieve a large single-polarity swing of the input signal.

[0046] As shown in the reference Figure 3 the first resistor R1 and the zener diode Z form a series limiting structure. The zener diode Z mainly plays a role in voltage limiting and protection for the first node J1. Among them, when the voltage of the input signal at the signal input terminal VIN is relatively large, the second voltage at the corresponding first node J1 will be greater than the set value VT (i.e., the reverse breakdown voltage of the zener diode Z), and the zener diode Z conducts, allowing a large current to flow. Through the current limiting effect of the first resistor R1, the voltage of the input signal is concentrated at both ends of the first resistor R1. At this time, the second voltage at the first node J1 is VT; when the voltage of the input signal at the signal input terminal VIN is relatively small, the second voltage at the corresponding first node J1 is less than the set value VT, the zener diode Z does not conduct, and the inflowing current is very small. At this time, the second voltage at the first node J1 is mainly generated by the series connection of the first resistor R1, the second resistor R2, and the first switching transistor M1. For the voltage and current drive range of the input signal, by reasonably setting the parameters of the first resistor R1 and the zener diode Z, the large voltage range of the input signal can be converted into a change range of 0 to VT. Thus, by means of voltage detection and current discharge, the voltage range of the input signal is compressed, and a large single-polarity swing of the input signal can be achieved.

[0047] Furthermore, the voltage dividing circuit 112 can further compress the second voltage to obtain the first voltage, so as to meet the working voltage range of the substrate bias conversion unit 120. As shown in the reference Figure 3 the series connection of the second resistor R2 and the first switching transistor M1 determines the change range of the first voltage (i.e., the voltage at the second node J2). Among them, the second resistor R2 acts as a voltage divider to achieve the conversion of the second voltage to the first voltage, while protecting the first switching transistor M1 and reducing the power consumption current at the input end.

[0048] As a specific example, as shown in the reference Figure 4 assuming that the reverse breakdown voltage of the zener diode Z is 3V, then when the voltage of the input signal is 50V, the second voltage at the first node J1 will be higher than the reverse breakdown voltage of the zener diode Z, and the zener diode Z conducts. At this time, the second voltage at the first node J1 is the reverse breakdown voltage of the zener diode Z, which is 3V. After voltage division, the first voltage at the second node J2 is 1.8V; when the voltage of the input signal is 2V, the second voltage at the first node J1 will be lower than the reverse breakdown voltage of the zener diode Z, and the zener diode Z does not conduct. After voltage division, the second voltage at the second node J2 is 1V, thereby converting the large voltage range of the input signal into a change range of 0 to 1.8V.

[0049] It should be noted that the zener diode Z can also be replaced by a limiting device or circuit similar to voltage detection and current discharge, that is, all circuit structures that maintain a small voltage fluctuation by detecting and discharging current through a fixed-value voltage at the first node J1 should be within the protection scope of this application. The first switching transistor M1 is equivalent to a diode structure, and the first switching transistor M1 can also be replaced by a device or circuit similar to a diode structure, and all should be within the protection scope of this application.

[0050] In the above embodiments, by utilizing the current-voltage conduction properties of the zener diode, switching transistor, and resistor, through amplitude limiting, current limiting, and voltage division conversion, the dynamic range of the input signal is compressed, achieving the reception of a high-voltage single-polarity large swing of the input signal and meeting a wider range of input applications of signal levels. That is to say, the reception and processing part of the input signal can achieve a single-polarity large swing of the input signal by adopting a signal compression protection structure.

[0051] In some embodiments, referring to Figure 3 As shown, the substrate bias conversion unit 120 includes: a second switching transistor M2, a third switching transistor M3, and a third resistor R3. The control electrode of the second switching transistor M2 is connected to the input unit 110, the first electrode of the second switching transistor M2 is connected to the current mirror unit 130, and the substrate of the second switching transistor M2 is grounded to GND; the control electrode of the third switching transistor M3 is connected to the control electrode of the second switching transistor M2, the first electrode of the third switching transistor M3 is connected to the current mirror unit 130, and the second electrode of the third switching transistor M3, the substrate of the third switching transistor M3, and the second electrode of the second switching transistor M2 are connected and form a third node J3; one end of the third resistor R3 is connected to the third node J3, and the other end of the third resistor R3 is grounded to GND.

[0052] Specifically, the second switching transistor M2, the third switching transistor M3, and the third resistor R3 constitute a differential input structure. Among them, the second switching transistor M2 and the third switching transistor M3 are of the same type but different in size. For example, both the second switching transistor M2 and the third switching transistor M3 are PMOS transistors. Considering the influence of matching layout, the aspect ratios of the second switching transistor M2 and the third switching transistor M3 are N:1, where N is greater than 1, that is, the aspect ratio of the second switching transistor M2 is greater than that of the third switching transistor M3.

[0053] When both the second switching transistor M2 and the third switching transistor M3 are PMOS transistors, the substrate of the second switching transistor M2 is directly grounded to GND, and the source is grounded to GND through the third resistor R3. That is to say, a body bias voltage is applied between the source and the substrate of the second switching transistor M2, and the magnitude of this body bias voltage is determined by the voltage across the third resistor R3. As the body bias voltage increases, the current of the second switching transistor M2 is affected by the body effect and increases; the substrate and the source of the third switching transistor M3 are directly connected, that is, there is no body bias voltage between the substrate and the source of the third switching transistor M3, and the third switching transistor M3 is not affected by the body effect. Since the gate voltages of the second switching transistor M2 and the third switching transistor M3 are the same, at the same gate voltage (i.e., the first voltage), based on different body effects and sizes, the input first voltage can be converted into the current difference between the first current and the second current. At this time, both the second switching transistor M2 and the third switching transistor M3 operate in the non-saturation region.

[0054] Specifically, when the gate voltage of the second switching transistor M2 and the third switching transistor M3, that is, the first voltage, is small, the current flowing through the third resistor R3 is very small, the voltage across the third resistor R3 is very small, and the body effect of the second switching transistor M2 can be ignored. At this time, the drain-source current of the second switching transistor M2, that is, the first current, and the drain-source current of the third switching transistor M3, that is, the second current, are mainly affected by the aspect ratio of the switching transistor itself. Since the aspect ratio of the second switching transistor M2 and the third switching transistor M3 is N:1 and N is greater than 1, the first current of the second switching transistor M2 > the second current of the third switching transistor M3.

[0055] As the first voltage increases, the first current and the second current gradually increase, the voltage across the third resistor R3 gradually increases, and the body effect of the second switching transistor M2 gradually strengthens, causing the first current to gradually decrease. When the influence of the body effect on the current is equal to the influence of the aspect ratio of the switching transistor itself on the current, the first current of the second switching transistor M2 = the second current of the third switching transistor M3. At this time, the first voltage is the voltage conversion threshold, and this voltage conversion threshold determines the level conversion value of the overall circuit. It should be noted that since the voltage conversion threshold is jointly determined by the aspect ratio of the switching transistor and the body bias voltage (i.e., the voltage across the third resistor R3), and the body bias voltage is related to the third resistor R3 and the aspect ratio of the switching transistor, by selecting the appropriate device type and adjusting the aspect ratio of the switching transistor and the resistance value of the third resistor R3, the level conversion value and power consumption can be flexibly adjusted to meet the functional requirements of the overall circuit.

[0056] When the first voltage continues to increase, the influence of the body bias effect of the second switching transistor M2 on the current will be greater than the influence of the aspect ratio of the switching transistor itself on the current. At this time, the first current of the second switching transistor M2 < the second current of the third switching transistor M3, and the current difference between the first current and the second current will increase with the increase of the first voltage, thereby realizing the conversion of the first voltage into the current difference between the first current and the second current, so as to obtain the corresponding conversion voltage based on the current difference in the subsequent stage.

[0057] In the above embodiments, by adopting the current differential input structure with a substrate bias structure, based on the sizes of different switching transistors and the body bias effect, low-power fine control of the level conversion threshold can be achieved. Specifically, the level conversion circuit with a traditional differential feedback structure mainly compares the current difference by controlling the on-current through the gate-source voltage. The voltage and current control are in an exponential relationship. When the voltage changes greatly, the power consumption change during level conversion is very large. However, the conversion based on the body bias effect can well suppress the exponential control relationship between voltage and current. Cooperating with the third resistor, the balance between body bias suppression and gate-source voltage control can be achieved, ensuring that the power consumption change is very small throughout the level conversion interval. At the same time, cooperating with the voltage compression function of the input unit, low-power fine control of the overall circuit can be realized. That is, the voltage compression of the input unit can greatly reduce the large power consumption change during level conversion, the body bias effect can further suppress the exponential control relationship between the gate-source voltage and current, and by flexibly adjusting the sizes of the switching transistor and the third resistor, the level conversion value and the power consumption can be finely controlled.

[0058] In some embodiments, continue to refer to Figure 3 As shown, the current mirror unit 130 includes: a fourth switching transistor M4 and a fifth switching transistor M5. The control electrode and the first electrode of the fourth switching transistor M4 are respectively connected to the first electrode of the second switching transistor M2, and the second electrode of the fourth switching transistor M4 is connected to the power supply VDD; the control electrode of the fifth switching transistor M5 is connected to the control electrode of the fourth switching transistor M4, the first electrode of the fifth switching transistor M5 is connected to the first electrode of the third switching transistor M3 and a fourth node J4 is formed, the second electrode of the fifth switching transistor M5 is connected to the power supply VDD, and the fourth node J4 is connected to the output voltage conversion unit 140.

[0059] Specifically, the fourth switching transistor M4 and the fifth switching transistor M5 form a mirror current mirror. The types, structures, and sizes of the fourth switching transistor M4 and the fifth switching transistor M5 are the same. For example, the fourth switching transistor M4 and the fifth switching transistor M5 are NMOS transistors with the same size and structure to achieve the complete mirror function of the differential circuit. By setting the voltage of the power supply VDD, the fourth switching transistor M4 and the fifth switching transistor M5 can both operate in the saturation region. Since the fourth switching transistor M4 and the fifth switching transistor M5 have the same type, structure, and size, and their gate-source voltages are the same, the drain-source current of the fourth switching transistor M4 is equal to the drain-source current of the fifth switching transistor M5. And the drain-source current of the fourth switching transistor M4 is the same as the first current. Therefore, the output current at the fourth node J4 is the current difference between the first current and the second current, that is, the comparison result of the differential current.

[0060] Thus, through the current mirror circuit composed of the fourth switching transistor and the fifth switching transistor, the comparison of the first current and the second current output by the substrate bias conversion unit is realized, and the comparison result is output to the output voltage conversion unit.

[0061] In some embodiments, with continued reference to Figure 3 as shown, the current mirror unit 130 further includes: a clamping circuit 131. The clamping circuit 131 is disposed between the first pole of the fourth switching transistor M4 and the first pole of the fifth switching transistor M5 and is used to clamp the voltage of the fourth node J4 to protect the subsequent circuit.

[0062] Specifically, as the input signal increases, the current difference between the first current and the second current becomes larger and larger, and the corresponding voltage difference between the first pole of the fourth switching transistor M4 and the first pole of the fifth switching transistor M5 also becomes larger and larger, and the output voltage at the fourth node J4 becomes larger and larger. Therefore, a clamping circuit 131 can be added between the first pole of the fourth switching transistor M4 and the first pole of the fifth switching transistor M5 to control the output voltage within a reasonable voltage range to protect the subsequent circuit.

[0063] Further, with reference to Figure 3 as shown, the clamping circuit 131 includes: a sixth switching transistor M6. The control pole and the first pole of the sixth switching transistor M6 are connected to the fourth node J4, and the second pole of the sixth switching transistor M6 is connected to the first pole of the fourth switching transistor M4.

[0064] Specifically, the sixth switching transistor M6 is of the same type as the fourth switching transistor M4 and the fifth switching transistor M5. The sixth switching transistor M6 can be a PMOS transistor. The fourth switching transistor M4 and the sixth switching transistor M6 both adopt a diode-connected manner, so that the current and voltage in the branches where they are located change in an exponential relationship, that is, a very small voltage change causes a large current to conduct, thereby providing a large current conversion range for the substrate bias conversion unit 120. When the output voltage at the fourth node J4 is higher than a certain value, it means that the voltage at this point exceeds the tolerance voltage of the subsequent circuit, and the difference between the corresponding first current and second current is too large. Then the sixth switching transistor M6 conducts, and the output voltage of the fourth node J4 is clamped at a fixed value to protect the subsequent circuit.

[0065] As a specific example, referring to Figure 5 As shown, when the first voltage at the second node J2 rises to the voltage shown by the dotted line in the figure, the voltage difference between the first poles of the fourth switching transistor M4 and the fifth switching transistor M5 will exceed a certain value, and at this time the sixth switching transistor M6 conducts. The fourth switching transistor M4 and the sixth switching transistor M6 are connected in a diode manner, and the current in the branch where they are located flows from the power supply VDD through the fourth switching transistor M4 and the sixth switching transistor M6 to the ground terminal. Since the current-voltage relationship of this branch changes in an exponential relationship, that is, within a large current change range, the voltage change is very small, so that the voltage at the fourth node J4 basically changes near VDD - 2VTH. This voltage change is very small and is manifested as being clamped at VDD - 2VTH, where VTH is the conduction threshold voltage of the fourth switching transistor M4 (that is, the sixth switching transistor M6), thereby protecting the subsequent circuit, such as protecting Figure 6 the control pole of the eleventh switching transistor M11 in [], so that the voltage of the control pole of the eleventh switching transistor M11 changes between VDD and VDD - 2VTH during the entire conversion process.

[0066] It should be noted that the clamping circuit 131 can be selected as two or more MOS transistors in parallel, or an NMOS transistor connected in reverse, or other forms of clamping circuits such as diodes and triodes, and specific details are not limited here.

[0067] Thus, the clamping function of the voltage of the fourth node is realized, protecting the safe use of the level conversion circuit.

[0068] In some embodiments, referring to Figure 6 As shown, the level conversion circuit 100 further includes: an isolation unit 150. The isolation unit 150 is arranged between the substrate bias conversion unit 120 and the current mirror 130 unit for isolating and protecting the substrate bias conversion unit 120.

[0069] Specifically, since the switching transistors of the substrate bias conversion unit 120 all operate in the non-saturation region, which requires a relatively high voltage for the switching transistors. Adding an isolation unit 150 between the substrate bias conversion unit 120 and the current mirror unit 130 can prevent the voltage of the power supply VDD from being injected into the substrate bias conversion unit 120 through the current mirror unit 130, which may cause the switching transistors of the substrate bias conversion unit 120 to have incorrect operating logic. At the same time, it can provide a greater selection space for the switching transistors of the substrate bias conversion unit 120, thereby increasing the design flexibility, improving the accuracy of voltage conversion, and enabling high-voltage conversion.

[0070] Thus, by adding the isolation unit, the operating voltage of the substrate bias conversion unit is not affected by the current mirror unit, protecting the substrate bias conversion unit, while increasing the design flexibility and improving the accuracy of voltage conversion.

[0071] Further, continue to refer to Figure 6 As shown, the isolation unit 150 includes: a voltage dividing circuit 151 and an isolation circuit 152. The voltage dividing circuit 151 is used to divide the voltage of the power supply VDD to obtain a third voltage; the isolation circuit 152 is connected to the voltage dividing circuit 151 and is used to isolate and protect the substrate bias conversion unit 120 under the action of the third voltage.

[0072] Further, the voltage dividing circuit 151 includes: a fourth resistor R4, a seventh switching transistor M7, and an eighth switching transistor M8. One end of the fourth resistor R4 is connected to the power supply VDD; the control electrode and the first electrode of the seventh switching transistor M7 are respectively connected to the other end of the fourth resistor R4 and form a fifth node J5, and the fifth node J5 is connected to the isolation circuit 152; the control electrode and the first electrode of the eighth switching transistor M8 are respectively connected to the second electrode of the seventh switching transistor M7, and the second electrode of the eighth switching transistor M8 is grounded to GND.

[0073] The isolation circuit 152 includes: a ninth switching transistor M9 and a tenth switching transistor M10. The control electrode of the ninth switching transistor M9 is connected to the voltage dividing circuit 151, the first electrode of the ninth switching transistor M9 is connected to the first electrode of the fourth switching transistor M4, and the second electrode of the ninth switching transistor M9 is connected to the first electrode of the second switching transistor M2; the control electrode of the tenth switching transistor M10 is connected to the control electrode of the ninth switching transistor M9, the first electrode of the tenth switching transistor M10 is connected to the first electrode of the fifth switching transistor M5, and the second electrode of the tenth switching transistor M10 is connected to the first electrode of the third switching transistor M3.

[0074] Specifically, refer to Figure 6As shown, the fourth resistor R4 functions as a voltage divider and current limiter to reduce the power consumption of the voltage division circuit. The seventh switching transistor M7 and the eighth switching transistor M8 both adopt the diode connection method. By adjusting the fourth resistor R4 and selecting appropriate switching transistors, it can be ensured that the two switching transistors are stably turned on under the drive of the power supply VDD. At this time, the voltage at the fifth node J5, i.e., the third voltage, is approximately twice the threshold voltage VTH. The voltage division circuit 151 provides this voltage to the isolation unit 152.

[0075] The ninth switching transistor M9 and the tenth switching transistor M10 in the isolation unit 152 are of the same type, which can be PMOS transistors. Through their body diode characteristics, unidirectional voltage isolation can be achieved, avoiding the influence of the voltage of the power supply VDD on the substrate bias conversion unit 120. At the same time, by adjusting the third voltage, the on-voltage drop of the ninth switching transistor M9 and the tenth switching transistor M10 can be reduced so that it does not affect the voltage conversion function of the substrate bias conversion unit 120. In practical applications, by reasonably selecting the parameters of the fourth resistor R4, the seventh switching transistor M7, and the eighth switching transistor M8, the relationship between power consumption and voltage can be balanced, and low-power isolation output can be achieved for the ninth switching transistor M9 and the tenth switching transistor M10 without affecting the conversion function of the substrate bias conversion unit 120. Thus, without affecting the conversion function of the substrate bias conversion unit, the substrate bias conversion unit, the current mirror unit, and the output voltage conversion unit are isolated, avoiding the influence of the external voltage provided by the power supply on the substrate bias conversion unit, and protecting the level conversion circuit.

[0076] In some embodiments, referring to Figure 3 As shown, the output voltage conversion unit 140 includes: an eleventh switching transistor M11 and a fifth resistor R5. The control electrode of the eleventh switching transistor M11 is connected to the current mirror unit 130. The first electrode of the eleventh switching transistor M11 is connected to the signal output terminal VOUT. The second electrode of the eleventh switching transistor M11 is connected to the power supply VDD. One end of the fifth resistor R5 is connected to the first electrode of the eleventh switching transistor M11, and the other end of the fifth resistor R5 is connected to the reference ground VSS.

[0077] Specifically, the eleventh switching transistor M11 can be an NMOS transistor. It forms a common-source amplifier structure with the fifth resistor R5, amplifying and converting the gate voltage of the eleventh switching transistor M11, i.e., the output voltage at the fourth node J4, into an output signal. Among them, by adjusting the parameters of the fifth resistor R5 and the eleventh switching transistor M11, the level conversion time and the magnitude of the power consumption current can be controlled. Moreover, in addition to its current-limiting function, the fifth resistor R5 can also flexibly select the potential of the reference ground VSS to flexibly configure the voltage range of the output signal, thereby achieving a large swing of the output signal.

[0078] As a specific example, referring toFigure 7 As shown, when the input signal is 2V or 50V, the voltage of the output signal is the voltage of the power supply VDD, thus realizing the conversion of unipolar input signals with different voltages into a definite logic level. Moreover, the voltage of the reference ground VSS and the power supply voltage VDD can be flexibly selected to realize the flexible configuration of the voltage range of the output signal. At the same time, as Figure 7 shown, when the input signal drops to 2V, there is an obvious delay in the level conversion time, and the level conversion time can be controlled by adjusting the parameters of the eleventh switching transistor M11 and the fifth resistor R5. It should be noted that an auxiliary circuit can be added based on the difference in the voltage range of the output signal to reduce power consumption.

[0079] In the above embodiments, through the common-source amplification structure composed of switching transistors and resistors, not only can the differential current comparison result be converted into an output signal, but also a large swing of the output signal can be realized through the fifth resistor, effectively improving the flexibility of setting the voltage range of the output signal and making the level conversion circuit applicable to signal transmission between different system levels.

[0080] In summary, according to the level conversion circuit of the embodiments of the present invention, by adopting the signal compression protection structure, a large swing of the unipolar input signal can be realized, meeting a wider range of signal level input applications; by adopting the structure of current differential input with the substrate bias structure, fine control of the level conversion threshold with low power consumption can be realized, reducing the power consumption during the conversion process, especially the power consumption during the high-voltage conversion process; through current comparison, high-voltage protection, and active amplification structures, the level of the output signal can be flexibly configured according to requirements, meeting the large swing of the output signal. The entire circuit can realize signal level conversion between different voltage domains, realize signal transmission between devices with different functions, solve the problems of single voltage range and poor versatility of traditional level conversion circuits, and has strong applicability.

[0081] In some embodiments, a chip is further provided.

[0082] Referring to Figure 8 shown, the chip 1000 includes the aforementioned level conversion circuit 100.

[0083] The chip according to the embodiment of the present invention adopts the aforementioned level conversion circuit. By adopting a signal compression protection structure, a single-polarity large swing of the input signal can be achieved, meeting a wider range of input applications of signal levels; by adopting a current differential input structure with a substrate bias structure, low-power fine control of the level conversion threshold can be achieved, reducing the power consumption during the conversion process, especially during the high-voltage conversion process; through current comparison, high-voltage protection, and active amplification structures, the level of the output signal can be flexibly configured according to requirements, meeting the large swing of the output signal, thereby realizing a low-power and large-swing level conversion function, improving the applicability of the chip and reducing the power consumption of the chip.

[0084] In some embodiments, an electronic device is proposed.

[0085] Reference Figure 9 As shown, the electronic device 10000 includes the aforementioned chip 1000.

[0086] According to the embodiment of the present invention, by adopting the aforementioned level conversion circuit, a single-polarity large swing of the input signal can be achieved through the adoption of a signal compression protection structure, meeting a wider range of input applications of signal levels; by adopting a current differential input structure with a substrate bias structure, low-power fine control of the level conversion threshold can be achieved, reducing the power consumption during the conversion process, especially during the high-voltage conversion process; through current comparison, high-voltage protection, and active amplification structures, the level of the output signal can be flexibly configured according to requirements, meeting the large swing of the output signal, thereby realizing a low-power and large-swing level conversion function, improving the applicability of the electronic device and reducing the power consumption of the electronic device.

[0087] In the description of this specification, the description with reference to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples.

[0088] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" can explicitly or implicitly include at least one of the features. In the description of the present invention, "a plurality" means at least two, such as two, three, etc., unless otherwise specifically defined.

[0089] In the present invention, unless otherwise clearly specified or limited, the terms "installed", "connected", "coupled", "fixed", etc. shall be construed broadly. For example, it may be a fixed connection, a detachable connection, or integrated; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the internal communication of two components or the interaction relationship between two components, unless otherwise clearly limited. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0090] Although the embodiments of the present invention have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present invention.

Claims

1. A level conversion circuit, characterized in that, Comprising: An input unit, which is connected to a signal input terminal and is used to perform voltage limiting processing on the input signal of the signal input terminal to obtain a first voltage; A substrate bias conversion unit, which is connected to the input unit and is used to generate a first current and a second current based on different substrate bias effects under the action of the first voltage; A current mirror unit, which is connected to the substrate bias conversion unit and is used to compare the first current and the second current; An output voltage conversion unit, which is connected to the current mirror unit and a signal output terminal and is used to perform voltage conversion on the comparison result to obtain an output signal and output it through the signal output terminal.

2. The level conversion circuit according to claim 1, wherein The input unit includes: A limiting circuit, which is connected to the signal input terminal and is used to perform voltage limiting processing on the input signal to obtain a second voltage; A voltage dividing circuit, which is connected to the limiting circuit and is used to perform voltage dividing processing on the second voltage to obtain the first voltage.

3. The level conversion circuit according to claim 2, wherein The limiting circuit includes: A first resistor, one end of which is connected to the signal input terminal; A zener diode, the cathode of which is connected to the other end of the first resistor to form a first node, and the anode of the zener diode is grounded.

4. The level conversion circuit according to claim 3, characterized in that, The voltage dividing circuit includes: A second resistor, one end of which is connected to the first node; A first switching tube, the control electrode and the first electrode of which are respectively connected to the other end of the second resistor to form a second node, the second electrode of the first switching tube is grounded, and the second node is connected to the substrate bias conversion unit.

5. The level conversion circuit according to any one of claims 1-4, characterized in that, The substrate bias conversion unit includes: A second switching tube, the control electrode of which is connected to the input unit, the first electrode of which is connected to the current mirror unit, and the substrate of which is grounded; A third switching tube, the control electrode of which is connected to the control electrode of the second switching tube, the first electrode of which is connected to the current mirror unit, and the second electrode, the substrate of the third switching tube and the second electrode of the second switching tube are connected to form a third node; A third resistor, one end of which is connected to the third node and the other end of which is grounded.

6. The level conversion circuit according to claim 5, wherein The current mirror unit includes: A fourth switching tube, the control electrode and the first electrode of which are respectively connected to the first electrode of the second switching tube, and the second electrode of which is connected to a power supply; A fifth switching tube, the control electrode of which is connected to the control electrode of the fourth switching tube, the first electrode of which is connected to the first electrode of the third switching tube to form a fourth node, the second electrode of which is connected to the power supply, and the fourth node is connected to the output voltage conversion unit.

7. The level conversion circuit according to claim 6, wherein The current mirror unit further includes: A clamping circuit, which is arranged between the first electrode of the fourth switching tube and the first electrode of the fifth switching tube and is used to perform clamping processing on the voltage of the fourth node.

8. The level conversion circuit according to claim 7, characterized in that, The clamping circuit includes: A sixth switching transistor, the control electrode and the first electrode of the sixth switching transistor are connected to the fourth node, and the second electrode of the sixth switching transistor is connected to the first electrode of the fourth switching transistor.

9. The level conversion circuit according to claim 6, wherein It further includes: An isolation unit, which is arranged between the substrate bias conversion unit and the current mirror unit, and is used for isolating and protecting the substrate bias conversion unit.

10. The level conversion circuit according to claim 9, characterized in that, The isolation unit includes: A voltage dividing circuit, which is used for dividing the supply power supply to obtain a third voltage; An isolation circuit, which is connected to the voltage dividing circuit and is used for isolating and protecting the substrate bias conversion unit under the action of the third voltage.

11. The level conversion circuit according to claim 10, characterized in that, The voltage dividing circuit includes: A fourth resistor, one end of the fourth resistor is connected to the supply power supply; A seventh switching transistor, the control electrode and the first electrode of the seventh switching transistor are respectively connected to the other end of the fourth resistor and form a fifth node, and the fifth node is connected to the isolation circuit; An eighth switching transistor, the control electrode and the first electrode of the eighth switching transistor are respectively connected to the second electrode of the seventh switching transistor, and the second electrode of the eighth switching transistor is grounded.

12. The level conversion circuit according to claim 10, characterized in that, The isolation circuit includes: A ninth switching transistor, the control electrode of the ninth switching transistor is connected to the voltage dividing circuit, the first electrode of the ninth switching transistor is connected to the first electrode of the fourth switching transistor, and the second electrode of the ninth switching transistor is connected to the first electrode of the second switching transistor; A tenth switching transistor, the control electrode of the tenth switching transistor is connected to the control electrode of the ninth switching transistor, the first electrode of the tenth switching transistor is connected to the first electrode of the fifth switching transistor, and the second electrode of the tenth switching transistor is connected to the first electrode of the third switching transistor.

13. The level conversion circuit according to any one of claims 1-4, characterized in that, The output voltage conversion unit includes: An eleventh switching transistor, the control electrode of the eleventh switching transistor is connected to the current mirror unit, the first electrode of the eleventh switching transistor is connected to the signal output terminal, and the second electrode of the eleventh switching transistor is connected to the supply power supply; A fifth resistor, one end of the fifth resistor is connected to the first electrode of the eleventh switching transistor, and the other end of the fifth resistor is connected to the reference ground.

14. A chip, characterized in that, It includes the level conversion circuit according to any one of claims 1-13.

15. An electronic device, characterized in that, It includes the chip according to claim 14.

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