Self-correcting operational amplifier, adjustable-precision analog-to-digital converter and electronic device

Abstract

The present disclosure relates to a self-correcting operational amplifier, an adjustable-precision analog-to-digital converter and an electronic device; wherein the self-correcting operational amplifier comprises a first sub-operational amplification unit, a second sub-operational amplification unit and a third sub-operational amplification unit; the first sub-operational amplification unit is connected with the second sub-operational amplification unit; the third sub-operational amplification unit is connected between the first sub-operational amplification unit and the second sub-operational amplification unit; the second sub-operational amplification unit and the third sub-operational amplification unit are grounded through a plurality of polarity capacitors respectively; the first sub-operational amplification unit, the second sub-operational amplification unit and the third sub-operational amplification unit are commonly connected with a power supply end voltage.

Description

Technical Field

[0001] The present disclosure relates to the technical field of electronic components, and more specifically, to a self-correcting operational amplifier, an analog-to-digital converter with adjustable precision, and an electronic device. Background Art

[0002] In the process of sensor chip design, a low-power and high-precision analog-to-digital converter (ADC) is usually required. The architecture of traditional ADC is as follows: Figure 1 As shown in the figure, a traditional ADC is a second-order modulator sigma delta ADC (ADC). In actual sensor design and application scenarios, different requirements for ADC accuracy often arise depending on the application environment. When addressing different accuracy requirements, the existing ADC mainly designs a very high-precision ADC, thereby ensuring that the accuracy of this ADC is backward compatible. However, this existing approach can lead to power consumption problems. For example, in sensor design and application scenarios with relatively low accuracy requirements, the power consumption of a high-precision ADC is relatively high. Summary of the Invention

[0003] The invention aims to solve the technical problem that the analog-to-digital converter in the prior art has high power consumption and cannot meet user needs.

[0004] To achieve the above technical objectives, the present disclosure provides a self-correcting operational amplifier, comprising:

[0005] a first sub-operational amplifier unit, a second sub-operational amplifier unit, and a third sub-operational amplifier unit;

[0006] The first sub-operational amplifying unit is connected to the second sub-operational amplifying unit;

[0007] The third sub-operational amplifying unit is connected in parallel between the first sub-operational amplifying unit and the second sub-operational amplifying unit;

[0008] The second sub-operational amplifier unit and the third sub-operational amplifier unit are respectively grounded through a plurality of polarized capacitors;

[0009] The first sub-operational amplifying unit, the second sub-operational amplifying unit, and the third sub-operational amplifying unit are commonly connected to a power supply voltage.

[0010] Furthermore, the first sub-operational amplification unit specifically includes:

[0011] a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first NMOS transistor, and a second NMOS transistor;

[0012] The source of the first PMOS transistor and the source of the third PMOS transistor are connected, and the source of the first PMOS transistor and the source of the third PMOS transistor are connected to the drain of the second PMOS transistor;

[0013] The gate of the first PMOS tube is connected to an input voltage signal;

[0014] The gate of the third PMOS tube is connected to the input voltage signal;

[0015] The source of the second PMOS tube is connected to the power supply voltage;

[0016] The drain of the first PMOS transistor is connected to the drain of the first NMOS transistor;

[0017] The source of the first NMOS transistor and the source of the second NMOS transistor are connected and grounded together;

[0018] The drain and gate of the first NMOS transistor are connected, the drain and gate of the second NMOS transistor are connected, and the drain of the first NMOS transistor and the source of the second NMOS transistor are respectively connected to the second sub-operational amplification unit, and the drain of the first NMOS transistor and the drain of the second NMOS transistor are respectively connected to the third sub-operational amplification unit;

[0019] The drain of the third PMOS tube is connected to the third sub-operational amplifier unit;

[0020] The drain of the third PMOS tube is connected to the second sub-operational amplifier unit;

[0021] The drain of the third PMOS transistor is connected to the drain of the second NMOS transistor;

[0022] The gate of the first NMOS transistor and the gate of the second NMOS transistor are respectively connected to the second sub-operational amplification unit.

[0023] Furthermore, the third sub-operational amplification unit specifically includes:

[0024] a fourth PMOS transistor, a fifth PMOS transistor, and a sixth PMOS transistor;

[0025] The source of the fifth PMOS tube is connected to the source of the sixth PMOS tube and is connected to the drain of the fourth PMOS tube;

[0026] The source of the fourth PMOS tube is connected to the power supply voltage;

[0027] The gate of the fifth PMOS tube is grounded via a first polarized capacitor;

[0028] The gate of the fifth PMOS tube is connected to the second sub-operational amplifier unit through a switch;

[0029] The gate of the sixth PMOS tube is grounded via a second polarized capacitor;

[0030] The gate of the sixth PMOS tube is connected to the second sub-operational amplifier unit;

[0031] The drain of the fifth PMOS tube and the drain of the sixth PMOS tube are respectively connected to the first sub-operational amplifier unit;

[0032] The drain of the fifth PMOS transistor is connected to the drain of the first NMOS transistor;

[0033] The drain of the sixth PMOS transistor is connected to the drain of the third PMOS transistor and the drain of the second NMOS transistor.

[0034] Furthermore, the second sub-operational amplification unit specifically includes:

[0035] a seventh PMOS transistor, an eighth PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor;

[0036] The gate of the seventh PMOS transistor is connected to the gate of the eighth PMOS transistor;

[0037] The source of the seventh PMOS transistor and the source of the eighth PMOS transistor are connected to the power supply voltage;

[0038] The drain of the seventh PMOS transistor is connected to the gate of the fifth PMOS transistor through a first switch;

[0039] The drain of the seventh PMOS transistor is connected to the drain of the third NMOS transistor;

[0040] The drain of the eighth PMOS transistor is connected to the drain of the fourth NMOS transistor;

[0041] The drain of the eighth PMOS transistor and the drain of the fourth NMOS transistor are grounded via a fourth polarized capacitor;

[0042] The drain of the eighth PMOS transistor and the drain of the fourth NMOS transistor are connected to the gate of the sixth NMOS transistor through a switch;

[0043] The gate of the third NMOS transistor and the gate of the fourth NMOS transistor are connected to the power supply voltage;

[0044] The source of the third NMOS transistor is connected to the drain of the fifth NMOS transistor;

[0045] The source of the fourth NMOS transistor is connected to the drain of the sixth NMOS transistor;

[0046] The source of the fifth NMOS transistor and the source of the sixth NMOS transistor are connected and grounded;

[0047] The gate of the first NMOS transistor is connected to the gate of the fifth NMOS transistor and to the gate of the sixth NMOS transistor.

[0048] In order to solve the above technical problems, the present disclosure further provides an analog-to-digital converter with adjustable precision, comprising:

[0049] A first analog-to-digital converter of a successive approximation SAR architecture, a second analog-to-digital converter of a sampling converter SD architecture, and a logic capacitor array;

[0050] The first analog-to-digital converter is connected to the second analog-to-digital converter;

[0051] The logic capacitor array is connected to the first analog-to-digital converter;

[0052] The first analog-to-digital converter and / or the second analog-to-digital converter has a self-calibrating comparator;

[0053] The second analog-to-digital converter has the above-mentioned self-correcting operational amplifier.

[0054] Furthermore, the highest two capacitors of the logic capacitor array are connected to the first analog-to-digital converter by opening and closing a capacitor control switch.

[0055] Furthermore, the second analog-to-digital converter comprises a first operational amplifier and a second operational amplifier;

[0056] The first operational amplifier is connected to the second operational amplifier via a capacitor;

[0057] The second operational amplifier is connected to the self-calibration comparator;

[0058] The first operational amplifier is the self-correcting operational amplifier described above;

[0059] The self-calibration comparator is composed of the self-calibration operational amplifier and the latch circuit connected in series.

[0060] Furthermore, it also includes: a logic switch, used to short-circuit the first analog-to-digital converter of the SAR architecture.

[0061] In order to solve the above technical problems, the present disclosure further provides an electronic device equipped with the above-mentioned analog-to-digital converter with adjustable precision.

[0062] The disclosed analog-to-digital converter with adjustable precision has a simple structure, can adjust the precision of the analog-to-digital converter according to the actual sensor chip design application scenario, and reduces power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] Figure 1 A schematic diagram of the SD ADC structure of the prior art is shown;

[0064] Figure 2 FIG2 shows a schematic structural diagram of a self-correcting operational amplifier according to a first embodiment of the present disclosure;

[0065] Figure 3 A schematic structural diagram of an analog-to-digital converter with adjustable precision according to a second embodiment of the present disclosure is shown;

[0066] Figure 4 A schematic structural diagram of an analog-to-digital converter with adjustable precision according to a third embodiment of the present disclosure is shown;

[0067] Figure 5 A schematic structural diagram of an analog-to-digital converter with adjustable precision according to a fourth embodiment of the present disclosure is shown;

[0068] Figure 6 Schematic diagrams of the structures of the self-calibration comparators in the second to fourth embodiments of the present disclosure are shown. DETAILED DESCRIPTION

[0069] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely illustrative and are not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0070] The accompanying drawings illustrate various schematic diagrams of structures according to embodiments of the present disclosure. These figures are not drawn to scale, and certain details are exaggerated and may be omitted for clarity. The shapes of the various regions and layers shown in the figures, as well as their relative sizes and positional relationships, are merely exemplary and may deviate in practice due to manufacturing tolerances or technical limitations. Those skilled in the art may design regions / layers with different shapes, sizes, and relative positions as needed.

[0071] Example 1:

[0072] like Figure 2 As shown:

[0073] The present disclosure provides a self-correcting operational amplifier, comprising:

[0074] a first sub-operational amplifier unit, a second sub-operational amplifier unit, and a third sub-operational amplifier unit;

[0075] The first sub-operational amplifying unit is connected to the second sub-operational amplifying unit;

[0076] The third sub-operational amplifying unit is connected in parallel between the first sub-operational amplifying unit and the second sub-operational amplifying unit;

[0077] The second sub-operational amplifier unit and the third sub-operational amplifier unit are respectively grounded through a plurality of polarized capacitors;

[0078] The first sub-operational amplifying unit, the second sub-operational amplifying unit, and the third sub-operational amplifying unit are commonly connected to a power supply voltage.

[0079] Furthermore, the first sub-operational amplification unit specifically includes:

[0080] A first PMOS transistor P1, a second PMOS transistor P2, a third PMOS transistor P3, a first NMOS transistor N1 and a second NMOS transistor N2;

[0081] The source of the first PMOS transistor P1 is connected to the source of the third PMOS transistor P3, and the source of the first PMOS transistor P1 and the source of the third PMOS transistor P3 are connected to the drain of the second PMOS transistor P2;

[0082] The gate of the first PMOS transistor P1 is connected to the input voltage signal;

[0083] The gate of the third PMOS transistor P3 is connected to the input voltage signal;

[0084] The source of the second PMOS transistor P2 is connected to the power supply voltage VDD;

[0085] The drain of the first PMOS transistor P1 is connected to the drain of the first NMOS transistor N1;

[0086] The source of the first NMOS transistor N1 and the source of the second NMOS transistor N2 are connected and grounded together;

[0087] The drain and gate of the first NMOS transistor N1 are connected, the drain and gate of the second NMOS transistor N2 are connected, and the drain of the first NMOS transistor and the source of the second NMOS transistor are respectively connected to the second sub-operational amplifier unit, and the drain of the first NMOS transistor and the drain of the second NMOS transistor are respectively connected to the third sub-operational amplifier unit;

[0088] The drain of the third PMOS tube P3 is connected to the third sub-operational amplifier unit;

[0089] The drain of the third PMOS tube P3 is connected to the second sub-operational amplifier unit;

[0090] The drain of the third PMOS transistor P3 is connected to the drain of the second NMOS transistor N2;

[0091] The drain of the third PMOS tube P3 is connected to the second sub-operational amplifier unit;

[0092] The gate of the first NMOS transistor N1 and the gate of the second NMOS transistor N2 are respectively connected to the second sub-operational amplification unit.

[0093] Furthermore, the third sub-operational amplification unit specifically includes:

[0094] a fourth PMOS transistor P4, a fifth PMOS transistor P5, and a sixth PMOS transistor P6;

[0095] The source of the fifth PMOS transistor P5 is connected to the source of the sixth PMOS transistor P6 and is also connected to the drain of the fourth PMOS transistor P4;

[0096] The source of the fourth PMOS transistor P4 is connected to the power supply voltage VDD;

[0097] The gate of the fifth PMOS transistor P5 is grounded via the first polarized capacitor C1;

[0098] The gate of the fifth PMOS transistor P5 is connected to the second sub-operational amplifier unit through a switch;

[0099] The gate of the sixth PMOS transistor P6 is grounded via a second polarized capacitor;

[0100] The gate of the sixth PMOS transistor P6 is connected to the second sub-operational amplifier unit;

[0101] The drain of the fifth PMOS transistor P5 and the drain of the sixth PMOS transistor P6 are respectively connected to the first sub-operational amplifier unit;

[0102] The drain of the fifth PMOS transistor P5 is connected to the drain of the first NMOS transistor N1;

[0103] The drain of the sixth PMOS transistor P6 is connected to the drain of the third PMOS transistor P3 and the drain of the second NMOS transistor N2.

[0104] Furthermore, the second sub-operational amplification unit specifically includes:

[0105] a seventh PMOS transistor P7, an eighth PMOS transistor P8, a third NMOS transistor N3, a fourth NMOS transistor N4, a fifth NMOS transistor N5, and a sixth NMOS transistor N6;

[0106] The gate of the seventh PMOS transistor P7 is connected to the gate of the eighth PMOS transistor P8;

[0107] The source of the seventh PMOS transistor P7 and the source of the eighth PMOS transistor P8 are connected to the power supply voltage VDD;

[0108] The drain of the seventh PMOS transistor P7 is grounded via a third polarized capacitor C3;

[0109] The drain of the seventh PMOS transistor P7 is connected to the gate of the fifth PMOS transistor P5 through a first switch;

[0110] The drain of the seventh PMOS transistor P7 is connected to the drain of the third NMOS transistor N3;

[0111] The drain of the eighth PMOS transistor P8 is connected to the drain of the fourth NMOS transistor N4;

[0112] The drain of the eighth PMOS transistor P8 and the drain of the fourth NMOS transistor N4 are grounded via a fourth polarized capacitor C4;

[0113] The drain of the eighth PMOS transistor P8 and the drain of the fourth NMOS transistor N4 are connected to the gate of the sixth NMOS transistor N6 through the switch A1;

[0114] The gate of the third NMOS transistor N3 and the gate of the fourth NMOS transistor N4 are connected to the power supply voltage VDD;

[0115] The source of the third NMOS transistor N3 is connected to the drain of the fifth NMOS transistor N5;

[0116] The source of the fourth NMOS transistor N4 is connected to the drain of the sixth NMOS transistor N6;

[0117] The source of the fifth NMOS transistor N5 and the source of the sixth NMOS transistor N6 are connected and grounded;

[0118] The gate of the first NMOS transistor N1 is connected to the gate of the fifth NMOS transistor N5 and to the gate of the sixth NMOS transistor N6 .

[0119] It should be noted that the first polarized capacitor C1 and the second polarized capacitor C2 act as storage capacitors, which are used to retain a certain amount of charge on the capacitors for a short period of time to form a certain voltage when the self-correcting operational amplifier circuit is powered off.

[0120] The third polarized capacitor and the fourth polarized capacitor play a role in fixing the unit gain bandwidth of the operational amplifier circuit.

[0121] Example 2:

[0122] like Figure 3 As shown:

[0123] The present disclosure also provides an analog-to-digital converter with adjustable precision, comprising:

[0124] A first analog-to-digital converter of a successive approximation SAR architecture, a second analog-to-digital converter of a sampling converter SD architecture, and a logic capacitor array;

[0125] The first analog-to-digital converter is connected to the second analog-to-digital converter;

[0126] The logic capacitor array is connected to the first analog-to-digital converter;

[0127] The first analog-to-digital converter and / or the second analog-to-digital converter has a self-calibrating comparator;

[0128] The second analog-to-digital converter comprises a self-correcting operational amplifier as described in the first embodiment;

[0129] The self-calibration comparator is composed of a self-calibration operational amplifier and a latch circuit as described in the first embodiment connected in series.

[0130] When users design sensor chips, they can disconnect the switch K1 to stop accessing the SD ADC circuit and thus save the overall power consumption of the circuit.

[0131] Specifically, the logic capacitor array includes a plurality of capacitors arranged in a binary format, and the capacitance values ​​thereof are 32C u1 , 16C u1 , 8C u1 、4C u1 , 2C u1 , 1C u1 , 1C u1 .

[0132] Specifically, the second analog-to-digital converter comprises a first operational amplifier and a second operational amplifier;

[0133] The first operational amplifier is connected to the second operational amplifier via a capacitor;

[0134] The second operational amplifier is connected to the self-calibration comparator;

[0135] The first operational amplifier is the self-correcting operational amplifier as described in the first embodiment.

[0136] The specific structure of the self-calibration comparator is as follows: Figure 6 shown.

[0137] It should be noted that:

[0138] like Figure 6 As shown, the circuit structure of the self-calibrating comparator is realized by adding a latch circuit in series on the basis of the circuit of the self-calibrating operational amplifier as described in Example 1. The latch circuit is a latch circuit and can be realized by conventional circuit structure design in this field. Figure 6 Only one optional implementation is shown, and those skilled in the art can make routine replacements, and the structure is also within the scope of protection of this disclosure.

[0139] Example 3:

[0140] like Figure 4 As shown:

[0141] The technical solution of the second embodiment of the present disclosure can also be improved as follows:

[0142] The precision-adjustable analog-to-digital converter further includes a capacitance-controlled switch;

[0143] The highest two capacitors in the logic capacitor array are connected to the first analog-to-digital converter by switching on and off a capacitor control switch.

[0144] That is Figure 4 As shown, the user can disconnect the capacitance control switch during use to make the highest two capacitors 32C in the logic capacitor array u1 and 16C u1 The circuit is open and the logic capacitor array is not connected. Users can adjust whether to connect these two highest load capacitors according to the requirements of the actual sensor chip design application scenario to effectively reduce the load capacitance of the SAR ADC, thereby effectively reducing the overall power consumption of the sensor design application scenario.

[0145] Example 4:

[0146] like Figure 5 As shown,

[0147] The technical solution of the second embodiment of the present disclosure can also be improved as follows:

[0148] The analog-to-digital converter with adjustable precision further includes a logic switch, which is used to short-circuit the first analog-to-digital converter of the successive approximation SAR architecture.

[0149] like Figure 5 As shown, when the logic switch is closed, the first ADC of the entire SAR architecture is connected, and the first ADC of the SAR architecture and the second ADC of the SD architecture are connected and work together. When the logic switch is open, the first ADC of the entire SAR architecture is not connected and the user's ADC needs are met by the improved second ADC of the SD architecture.

[0150] This solution disables the entire first analog-to-digital converter (SAR ADC) and allows the subsequent SD ADC to be used directly to meet the user's sensor chip design requirements. Because the SAR ADC is disabled, the total power consumption of the entire ADC is further reduced.

[0151] The above describes the embodiments of the present disclosure. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art may make various substitutions and modifications, which are intended to fall within the scope of the present disclosure.

Claims

1. A self-correcting operational amplifier, characterized in that include: a first sub-operational amplifier unit, a second sub-operational amplifier unit, and a third sub-operational amplifier unit; The first sub-operational amplifying unit is connected to the second sub-operational amplifying unit; The third sub-operational amplifier unit is connected between the first sub-operational amplifier unit and the second sub-operational amplifier unit; The second sub-operational amplifier unit and the third sub-operational amplifier unit are respectively grounded via a plurality of polarized capacitors; The first sub-operational amplifier unit, the second sub-operational amplifier unit and the third sub-operational amplifier unit are commonly connected to the power supply voltage; The first sub-operational amplification unit specifically includes: a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first NMOS transistor, and a second NMOS transistor; The source of the first PMOS transistor is connected to the source of the third PMOS transistor, and the source of the first PMOS transistor, the source of the third PMOS transistor and the drain of the second PMOS transistor are connected; The gate of the first PMOS tube is connected to an input voltage signal; The gate of the third PMOS tube is connected to the input voltage signal; The source of the second PMOS tube is connected to the power supply voltage; The drain of the first PMOS transistor is connected to the drain of the first NMOS transistor; The source of the first NMOS transistor and the source of the second NMOS transistor are connected and grounded together; The drain and gate of the first NMOS transistor are connected, the drain and gate of the second NMOS transistor are connected, and the drain of the first NMOS transistor and the source of the second NMOS transistor are respectively connected to the second sub-operational amplification unit, and the drain of the first NMOS transistor and the drain of the second NMOS transistor are respectively connected to the third sub-operational amplification unit; The drain of the third PMOS tube is connected to the third sub-operational amplifier unit; The drain of the third PMOS tube is connected to the second sub-operational amplifier unit; The drain of the third PMOS transistor is connected to the drain of the second NMOS transistor; The gate of the first NMOS transistor and the gate of the second NMOS transistor are respectively connected to the second sub-operational amplifier unit; The third sub-operational amplification unit specifically includes: a fourth PMOS transistor, a fifth PMOS transistor, and a sixth PMOS transistor; The source of the fifth PMOS tube is connected to the source of the sixth PMOS tube and is connected to the drain of the fourth PMOS tube; The source of the fourth PMOS tube is connected to the power supply voltage; The gate of the fifth PMOS tube is grounded via a first polarized capacitor; The gate of the fifth PMOS tube is connected to the second sub-operational amplifier unit through a switch; The gate of the sixth PMOS tube is grounded via a second polarized capacitor; The gate of the sixth PMOS tube is connected to the second sub-operational amplifier unit; The drain of the fifth PMOS tube and the drain of the sixth PMOS tube are respectively connected to the first sub-operational amplifier unit; The drain of the fifth PMOS transistor is connected to the drain of the first NMOS transistor; The drain of the sixth PMOS transistor is connected to the drain of the third PMOS transistor and the drain of the second NMOS transistor; The second sub-operational amplification unit specifically includes: a seventh PMOS transistor, an eighth PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor; The gate of the seventh PMOS transistor is connected to the gate of the eighth PMOS transistor; The source of the seventh PMOS transistor and the source of the eighth PMOS transistor are connected to the power supply voltage; The drain of the seventh PMOS transistor is connected to the gate of the fifth PMOS transistor through a first switch; The drain of the seventh PMOS transistor is connected to the drain of the third NMOS transistor; The drain of the eighth PMOS transistor is connected to the drain of the fourth NMOS transistor; The drain of the eighth PMOS transistor and the drain of the fourth NMOS transistor are grounded via a fourth polarized capacitor; The drain of the eighth PMOS transistor and the drain of the fourth NMOS transistor are connected to the gate of the sixth NMOS transistor through a switch; The gate of the third NMOS transistor and the gate of the fourth NMOS transistor are connected to the power supply voltage; The source of the third NMOS transistor is connected to the drain of the fifth NMOS transistor; The source of the fourth NMOS transistor is connected to the drain of the sixth NMOS transistor; The source of the fifth NMOS transistor and the source of the sixth NMOS transistor are connected and grounded; The gate of the first NMOS transistor is connected to the gate of the fifth NMOS transistor, and the gate of the second NMOS transistor is connected to the gate of the sixth NMOS transistor.

2. An analog-to-digital converter with adjustable precision, characterized in that: include: A first analog-to-digital converter of a successive approximation architecture, a second analog-to-digital converter of a Sigma-Delta architecture, and a logic capacitor array; The first analog-to-digital converter is connected to the second analog-to-digital converter; The logic capacitor array is connected to the first analog-to-digital converter; The first analog-to-digital converter and / or the second analog-to-digital converter has a self-calibrating comparator; The second analog-to-digital converter has a self-correcting operational amplifier as claimed in claim 1; The self-calibration comparator is composed of the self-calibration operational amplifier as claimed in claim 1 and a latch circuit connected in series.

3. The analog-to-digital converter according to claim 2, wherein: The highest two capacitors in the logic capacitor array are connected to the first analog-to-digital converter by switching on and off a capacitor control switch.

4. The analog-to-digital converter according to claim 2, wherein: The second analog-to-digital converter comprises a first operational amplifier and a second operational amplifier; The first operational amplifier is connected to the second operational amplifier via a capacitor; The second operational amplifier is connected to the self-calibration comparator; The first operational amplifier is a self-correcting operational amplifier as claimed in claim 1 .

5. The analog-to-digital converter according to claim 2, wherein: Also includes: A logic switch is used to short-circuit the first analog-to-digital converter of the successive approximation architecture.

6. An electronic device equipped with the analog-to-digital converter with adjustable precision as claimed in any one of claims 2 to 5.

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