A method for linear and stable output of clock signal optical receiver

Abstract

The present invention discloses a clock signal optical receiving linear amplitude-stabilized output device and output method, the device comprises an EDFA optical amplifier, a light detector, a clock signal amplifier, a coupler, a detector, a subtractor, a first integrator, a comparison calculation module, a second integrator and an ACC control module which are sequentially connected to form a closed loop, wherein the light detector is connected to a voltage follower and a 1kΩ bias resistor, the comparison calculation module is connected to the voltage follower and an initial optical power voltage setting module, the first integrator is connected to an amplitude setting voltage module via a subtractor, and the EDFA optical amplifier is connected to a clock optical transmitter via an optical fiber, and the length of the optical fiber is less than 100 km. This device has low cost, can ensure that the light detector is not saturated, can ensure the amplitude-stabilized output of the clock, and can also ensure that the electric amplifier works in a linear region, i.e., non-saturated. This method is simple and practical.

Description

Technical Field

[0001] The present invention relates to the technical field of radio frequency optical fiber transmission, and in particular to a clock signal optical receiving linear amplitude stabilization output device and output method. Background Art

[0002] With the development of radar and satellite signal receiving technology, these application scenarios require clock signals to ensure the consistency of system operation. The amplitude stability of the clock signal is very important to the system.

[0003] There are many ways to output clock amplitude stabilization, mainly using the clock signal amplifier saturation output method. Since the amplifier works in the nonlinear region, this method has nonlinear effects such as harmonic increase, which limits the application of steady-state output receivers in more scenarios. Summary of the invention

[0004] The purpose of the present invention is to provide a clock signal optical receiving linear stable amplitude output device and output method to address the deficiencies of the prior art. This device has low cost, can ensure that the optical detector is not saturated, can ensure the stable amplitude output of the clock, and can also ensure that the electric amplifier works in the linear region, that is, non-saturated. This method is simple and practical.

[0005] The technical solution for achieving the purpose of the present invention is:

[0006] A clock signal optical receiving linear amplitude stabilization output device comprises an EDFA optical amplifier, a light detector, a clock signal amplifier, a coupler, a detector, a subtractor, a first integrator, a comparison calculation module, a second integrator and an ACC control module which are sequentially connected to form a closed loop, wherein the light detector is connected to a voltage follower and a 1kΩ bias resistor, the comparison calculation module is connected to the voltage follower and an initial optical power voltage setting module, the first integrator is externally connected to an amplitude setting voltage module via a subtractor, and the EDFA optical amplifier is connected to a clock optical transmitter via an optical fiber, and the length of the optical fiber is less than 100km.

[0007] The coupler is a 20dB coupler.

[0008] The comparison and calculation module is provided with a first operational amplifier U1, resistors R1, R2, R3, R4 and Rf, wherein pin 8 of the first operational amplifier U1 is connected to +5V, pin 4 is connected to -5V, resistors R1, R2, and Rf are connected in parallel, and the parallel ends are connected to pin 2 of the operational amplifier U1, pin 1 of the first operational amplifier U1 is connected to the other end of the resistor Rf, resistors R3 and R4 are connected in parallel, and the parallel ends are connected to pin 3 of the first operational amplifier U1, and the other end of R4 is grounded.

[0009] The resistance value of R1 in the comparison and calculation module is 470 kΩ, and the resistance values ​​of Rf, R2, R3, and R4 are all 100 kΩ.

[0010] The first integrator is provided with a second operational amplifier U2, a resistor R6 and a capacitor C1, wherein pin 8 of the second operational amplifier is connected to +5V, pin 4 is connected to -5V, capacitor C1 is connected in parallel with resistor R5, and the parallel end is connected to pin 2 of the second operational amplifier U4, pin 1 of the second operational amplifier is connected to the other end of capacitor C1, and pin 3 of the second operational amplifier is grounded.

[0011] The capacitance of C1 in the first integrator is 10 μF, and the resistance of R5 is 100 kΩ.

[0012] The second integrator is provided with a third operational amplifier U3, a resistor R6 and a capacitor C2, wherein pin 8 of the third operational amplifier is connected to +5V, pin 4 is connected to -5V, capacitor C2 is connected in parallel with R6, and the parallel end is connected to pin 2 of the third operational amplifier U3, pin 1 of the third operational amplifier is connected to the other end of the capacitor C2, and pin 3 of the third operational amplifier is grounded.

[0013] The capacitance of C2 in the second integrator is 10 μF, and the resistance of R6 is 1 kΩ.

[0014] At the clock linear amplitude-stabilized optical receiver end, the EDFA input end is connected to the optical fiber receiving the clock modulated optical signal, the EDFA output end is connected to the optical input end of the optical detector, the RF output end of the optical detector is connected to the input end of the clock signal amplifier, the output end of the clock signal amplifier is connected to the input end of the coupler, the +5V power supply is connected to the bias leg of the optical detector through a 1kΩ resistor, the voltage bias end of the optical detector is connected to the input end of the voltage follower, the output end of the voltage follower is connected to the VT input end of the comparison calculation module, the -20dB output end of the coupler is connected to the input end of the detector, the output end of the detector is connected to an input end of the subtractor, the output end of the clock output amplitude setting voltage module is connected to the other input end of the subtractor, the output end of the subtractor is connected to the input end of the first integrator, the output end of the first integrator is connected to the VDI input end of the comparison calculation module, the output end of the initial received optical power voltage setting module is connected to the VF input end of the comparison calculation module, the VDO output end of the comparison calculation module is connected to the second integrator input end, the second integrator output end is connected to the input end of the ACC control module, and the output end of the ACC control module is connected to the EDFA.

[0015] An output method of a clock signal light receiving linear amplitude stabilization output device, comprising the above-mentioned clock signal light receiving linear amplitude stabilization output device, the method comprising the following steps:

[0016] 1) The clock linear amplitude stabilization optical receiving device receives the modulated optical signal sent by the clock signal optical transmitter and inputs the optical signal into the EDFA for optical amplification;

[0017] 2) The amplified light enters the photodetector for photoelectric demodulation into a clock electrical signal, and the +5V power supply provides a bias voltage to the photodetector through a 1kΩ bias resistor;

[0018] 3) The clock electrical signal is amplified by the clock signal amplifier and then output through a 20dB coupler;

[0019] 4) The detector bias voltage is input to the VT terminal of the comparison calculation module through the voltage follower. According to the working principle of the voltage follower, VT is the bias voltage of the photodetector;

[0020] 5) The 20dB coupler couples the clock electrical signal into the detector, detects the voltage value VR corresponding to the amplitude of the electrical signal at this time, and sends this voltage to one end of the subtractor; the amplitude setting voltage module sets the output amplitude reference voltage VS and sends it to the other end of the subtractor, the subtractor output voltage Δ = VS-VR, the first integrator integrates the subtractor output voltage Δ to obtain the output amplitude error cumulative value VDI;

[0021] 6) After the initial optical power voltage setting module sets the voltage, it inputs the voltage into the VF terminal of the comparison module. The comparison calculation module calculates VF, VT and VDI to obtain the received optical power error value VDO;

[0022] 7) The second integrator integrates VDO, and the ACC control module adjusts the EDFA pump laser bias current according to the integration result, thereby adjusting the EDFA output optical power.

[0023] Among them, when there is clock signal transmission in the system and VR≠VS, the received optical power error value VDO≠0V output by the comparison calculation module, that is, the received optical power error cumulative value VPI output by the second integrator will gradually increase (VDO<0V) or gradually decrease (VDO>0V), and the ACC control module adjusts the EDFA output optical power size according to the size of VPI until VR=VS; at this time, VPI no longer changes and is a stable value, and the working state of the ACC control module no longer changes, that is, the clock output amplitude no longer changes, thereby achieving the function of stable amplitude output; at this time, as long as the maximum linear output amplitude of the clock signal amplifier is greater than the signal output amplitude to be set, according to the operating principle of the device, the clock signal amplifier will always work in the linear area, that is, the device can achieve linear stable amplitude output.

[0024] Compared with the prior art, this technical solution has the following characteristics:

[0025] 1. An EDFA is added in front of the receiver optical detector. By detecting the detector optical power, the output optical power of the EDFA is controlled to ensure that the optical detector works in a non-saturated state;

[0026] 2. By adding a detector at the end of the receiver, the optical output amplitude of the EDFA is feedback-controlled, thereby adjusting the output optical power of the EDFA and ensuring the stability of the clock output amplitude.

[0027] 3. Adding a joint control mode to the circuit combines the above 1 and 2 functions to control the EDFA, which can not only ensure that the optical detector is not saturated, but also ensure the stable output of the clock, and at the same time ensure that the clock amplifier works in the linear region (non-saturated).

[0028] This device has low cost, can ensure that the light detector is not saturated, can ensure the clock output is stable, and can also ensure that the electric amplifier works in the linear region, that is, not saturated. This method is simple and practical. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 It is a schematic diagram of the principle block diagram of the embodiment device;

[0030] Figure 2 This is a schematic diagram of the principle of the comparison calculation module in the embodiment;

[0031] Figure 3 It is a schematic diagram of the decomposition 1 of the principle block diagram of the comparison calculation module in the embodiment;

[0032] Figure 4 It is a schematic diagram of decomposition 2 of the principle block diagram of the comparison calculation module in the embodiment;

[0033] Figure 5 is a schematic diagram of the first integrator in the embodiment;

[0034] Figure 6 Schematic diagram of the second integrator in the embodiment. DETAILED DESCRIPTION

[0035] The content of the present invention is further described below in conjunction with the drawings and embodiments, but the present invention is not limited thereto.

[0036] Example:

[0037] Reference Figure 1 A clock signal optical receiving linear amplitude stabilization output device comprises an EDFA optical amplifier, a light detector, a clock signal amplifier, a coupler, a detector, a subtractor, a first integrator, a comparison calculation module, a second integrator and an ACC control module which are sequentially connected to form a closed loop, wherein the light detector is connected to a voltage follower and a 1kΩ bias resistor, the comparison calculation module is connected to the voltage follower and an initial optical power voltage setting module, the first integrator is externally connected to an amplitude setting voltage module through a subtractor, and the EDFA optical amplifier is connected to a clock optical transmitter through an optical fiber, and the length of the optical fiber is less than 100KM.

[0038] The coupler is a 20dB coupler.

[0039] like Figure 2 As shown, the comparison and calculation module is provided with a first operational amplifier U1, resistors R1, R2, R3, R4 and Rf, wherein pin 8 of the first operational amplifier U1 is connected to +5V, pin 4 is connected to -5V, resistors R1, R2, and Rf are connected in parallel, and the parallel ends are connected to pin 2 of the operational amplifier U1, pin 1 of the first operational amplifier U1 is connected to the other end of the resistor Rf, resistors R3 and R4 are connected in parallel, and the parallel ends are connected to pin 3 of the first operational amplifier U1, and the other end of R4 is grounded.

[0040] In this example, the resistance value of R1 in the comparison calculation module is 470 kΩ, and the resistance values ​​of Rf, R2, R3, and R4 are all 100 kΩ.

[0041] like Figure 5 As shown, the first integrator is provided with a second operational amplifier U2, a resistor R5 and a capacitor C1, wherein the 8th pin of the second operational amplifier is connected to +5V, the 4th pin is connected to -5V, the capacitor C1 is connected in parallel with the resistor R5, and the parallel end is connected to the 2nd pin of the second operational amplifier U4, the 1st pin of the second operational amplifier is connected to the other end of the capacitor C1; the 3rd pin of the second operational amplifier is grounded.

[0042] In this example, the capacitance of C1 in the first integrator is 10 μF, and the resistance of R5 is 100 kΩ.

[0043] like Figure 6 As shown, the second integrator is provided with a third operational amplifier U3, a resistor R6 and a capacitor C2, wherein the 8th pin of the third operational amplifier is connected to +5V, the 4th pin is connected to -5V, the capacitor C2 is connected in parallel with R6, and the parallel end is connected to the 2nd pin of the third operational amplifier U3, the 1st pin of the third operational amplifier is connected to the other end of the capacitor C2, and the 3rd pin of the third operational amplifier is grounded.

[0044] In this example, the capacitance of C2 in the second integrator is 10 μF, and the resistance of R6 is 1 kΩ.

[0045] In this example, at the clock linear amplitude-stabilized optical receiver end, the EDFA input end is connected to the optical fiber that receives the clock modulated optical signal, the EDFA output end is connected to the optical input end of the optical detector, the RF output end of the optical detector is connected to the input end of the clock signal amplifier, the output end of the clock signal amplifier is connected to the input end of the coupler, the +5V power supply is connected to the bias leg of the optical detector through a 1kΩ resistor, the voltage bias end of the optical detector is connected to the input end of the voltage follower, the output end of the voltage follower is connected to the VT input end of the comparison calculation module, the -20dB output end of the coupler is connected to the input end of the detector, the output end of the detector is connected to one input end of the subtractor, the output end of the clock output amplitude setting voltage module is connected to the other input end of the subtractor, the output end of the subtractor is connected to the input end of the first integrator, the output end of the first integrator is connected to the VDI input end of the comparison calculation module, the output end of the initial received optical power voltage setting module is connected to the VF input end of the comparison calculation module, the VDO output end of the comparison calculation module is connected to the second integrator input end, the second integrator output end is connected to the input end of the ACC control module, and the output end of the ACC control module is connected to the EDFA.

[0046] An output method of a clock signal light receiving linear amplitude stabilization output device, comprising the above-mentioned clock signal light receiving linear amplitude stabilization output device, the method comprising the following steps:

[0047] 1) The clock linear amplitude stabilization optical receiving device receives the modulated optical signal sent by the clock optical transmitter and inputs the optical signal into the EDFA for optical amplification;

[0048] 2) The amplified light enters the photodetector for photoelectric demodulation into a clock electrical signal, and the +5V power supply provides a bias voltage to the photodetector through a 1kΩ bias resistor;

[0049] 3) The clock electrical signal is amplified by the clock signal amplifier and then output through a 20dB coupler;

[0050] 4) The detector bias voltage is input to the VT terminal of the comparison calculation module through the voltage follower. According to the working principle of the voltage follower, VT is the bias voltage of the photodetector;

[0051] 5) The 20dB coupler couples the clock electrical signal into the detector, detects the voltage value VR corresponding to the amplitude of the electrical signal at this time, and sends this voltage to one end of the subtractor; the amplitude setting voltage module sets the output amplitude reference voltage VS and sends it to the other end of the subtractor, the subtractor output voltage Δ = VS-VR, the first integrator integrates the subtractor output voltage Δ to obtain the output amplitude error cumulative value VDI;

[0052] 6) After the initial optical power voltage setting module sets the voltage, it inputs the voltage into the VF terminal of the comparison module. The comparison calculation module calculates VF, VT and VDI to obtain the received optical power error value VDO;

[0053] 7) The second integrator integrates VDO, and the ACC control module adjusts the EDFA pump laser bias current according to the integration result, thereby adjusting the EDFA output optical power.

[0054] Among them, when there is clock signal transmission in the system and VR≠VS, the received optical power error value VDO≠0V output by the comparison calculation module, that is, the received optical power error cumulative value VPI output by the second integrator will gradually increase (VDO<0V) or gradually decrease (VDO>0V), and the ACC control module adjusts the EDFA output optical power size according to the size of VPI until VR=VS; at this time, VPI no longer changes and is a stable value, and the working state of the ACC control module no longer changes, that is, the clock output amplitude no longer changes, thereby achieving the function of stable amplitude output; at this time, as long as the maximum linear output amplitude of the clock signal amplifier is greater than the signal output amplitude to be set, according to the operating principle of the device, the clock signal amplifier will always work in the linear area, that is, the device can achieve linear stable amplitude output.

[0055] In this example, the calculation and comparison process of the comparison calculation module is as follows: Figure 2 As shown, the superposition principle in the basis of analog electronic calculation is used to solve the addition and subtraction operation circuit. Figure 2 The circuit in can be decomposed into Figure 3 and Figure 4 The two circuits are solved separately. Figure 2 The output voltage of the circuit is equal to Figure 3 and Figure 4 The sum of the output voltages,

[0056] from Figure 3 The relationship can be obtained:

[0057] I1=I2+I3 (1),

[0058]

[0059] from Figure 4 The positive current relationship of the operational amplifier can be obtained as follows:

[0060] I4=I5 (3),

[0061]

[0062]

[0063]

[0064] from Figure 4 The negative current relationship of the operational amplifier can be obtained as follows:

[0065]

[0066]

[0067] Where R1 / / R2 is the parallel resistance of R1 and R2;

[0068] from Figure 3 and Figure 4 The output voltage of the comparison calculation module can be obtained:

[0069] VDO=VDO1+VDO2 (7),

[0070]

[0071] Will Figure 4 Substituting the resistance value in into formula (8) yields:

[0072] VDO=1.106VT-0.213VDI-VF (9),

[0073] Among them, VDI is the integral value of the first integrator. According to the principle diagram of the first integrator and the second integrator, it can be known that: under the condition of the same input signal, the integration speed of the second integrator is 100 times that of the first integrator. Therefore, when the second integrator and the first integrator work at the same time, the integrator value of the first integrator changes relatively slowly, thus ensuring that the entire system will not have self-oscillation.

[0074] In this example, the bias voltage of the actual test photodetector is 4.5V when the incident light power is -3dBm, and the detector output voltage is 1.7V when the 10MHz clock signal coupler outputs 10dBm. Therefore, VF=4.5V and VS=1.7V are set. At this time, formula (9) is expressed as:

[0075] VDO=1.106VT-0.213VDI-4.5 (10).

[0076] In formula (10), the voltage value VDI varies between -5V and 5V. According to the integration principle, when Δ=VS-VR is greater than 0, the value of VDI gradually changes from 0V to -5V; when Δ<0V, the value of VDI gradually changes from 0V to +5V.

[0077] According to the ACC module control mechanism, when the output voltage of the second integrator (VPI) changes, ACC adjusts the EDFA Bump current (the current increases as the output voltage of the second integrator decreases, and the current decreases as the output voltage of the second integrator increases). When the input voltage of the second integrator is VDO = 0V, the EDFA pump current no longer changes (the output optical power no longer changes). Therefore, the system is in a stable condition when there is a solution of VDO = 0V, that is:

[0078] 1.106VT-0.213VDI-4.5=0 (11),

[0079] The relationship between VT and VDI can be obtained as follows;

[0080] VDI≈5.192VT-21.126 (12),

[0081] Where VT is related to the EDFA output optical power range and the detector bias. According to the existing EDFA technology, a larger optical power adjustment range can be obtained. Therefore, only the detector linear bias voltage operating range can be considered. At present, the general detector bias voltage can work linearly in the range of 2.7V≤VT≤5V. In this example, 2.7V≤VT≤5V is taken. Substituting VT into formula (12), it can be obtained that the value range of VDI when the system works linearly should satisfy -4.512V≤VDI≤+4.834V, that is, there is a stable working point in this range. According to Figure 5 From the first integrator schematic diagram, we can see that the power supply voltage of the operational amplifier is ±5V. If a rail-to-rail output operational amplifier is used, the range of VDI is -5V≤VDI≤+5V; the VDI value includes all stable operating points, that is, the system can work stably.

[0082] After the system is in steady-state operation, VDO=0; when the amplitude of the clock signal of the input clock optical transmitter decreases, because the system is a linear system, the detector output voltage VR decreases, the subtractor output Δ=VS-VR>0, the first integrator integral value VDI decreases, the comparison calculation module output value VDO>0, the second integrator output value VPI decreases, the EDFA pump current increases (EDFApump current increases with decreasing voltage and decreases with increasing voltage), the EDFA output optical power increases, the detector output clock signal amplitude increases, the detector detection output voltage increases, and when it increases to Δ=VS-VR=0, the system stops adjusting and is in a stable state again. Because VS is a fixed value, the clock output power is also a fixed value, thereby achieving steady-amplitude output.

[0083] After the system is in steady-state operation, VDO=0; when the amplitude of the clock signal input to the clock optical transmitter increases, because the system is a linear system, the detector output voltage VR increases, the subtractor output Δ=VS-VR<0, the first integrator integral value VDI increases, the comparison calculation module output value VDO<0, the second integrator output value VPI increases, the EDFA pump current decreases, the EDFA output optical power decreases, the detector output clock signal amplitude decreases, and the detector detection output voltage decreases. When it decreases to Δ=VS-VR=0, the system stops adjusting and is in a stable state again. Because VS is a fixed value, the clock output power is also a fixed value, thereby achieving steady-amplitude output.

[0084] When the clock optical transmitter has no clock signal, the subtractor outputs Δ=VS-VR>0, and the integral value VDI of the first integrator continues to decrease to -5V. According to formula (12), the final detector voltage (VT) will be adjusted to 3.106V. Under this bias voltage, the detector is in the linear region, which can ensure that when the clock signal optical transmitter outputs the modulated light signal again, the detector can output the clock signal normally, thereby ensuring the normal operation of the system.

[0085] In this example, an analog operation circuit is established based on the adjustable output optical power function of EDFA, the law of change of detector bias voltage with received optical power, and the law of change of detector output voltage, which ensures that the optical detector and clock signal amplifier always remain in the linear working area and realizes the linear steady-amplitude output of the clock signal.

Claims

1. An output method of a clock signal light receiving linear amplitude stabilization output device, wherein the clock signal light receiving linear amplitude stabilization output device is used to implement the method, and the clock signal light receiving linear amplitude stabilization output device is: The device comprises an EDFA optical amplifier, a photodetector, a clock signal amplifier, a coupler, a detector, a subtractor, a first integrator, a comparison calculation module, a second integrator and an ACC control module which are sequentially connected to form a closed loop, wherein: The photodetector is connected to a voltage follower and a 1kΩ bias resistor, the comparison calculation module is connected to the voltage follower and the initial optical power voltage setting module, the first integrator is connected to an amplitude setting voltage module via a subtractor, the EDFA optical amplifier is connected to a clock optical transmitter via an optical fiber, and the length of the optical fiber is less than 100KM. The method comprises the following steps: 1) The clock linear amplitude-stabilized optical receiving device receives the modulated optical signal sent by the clock optical transmitter and inputs the optical signal into the EDFA for optical amplification; 2) The amplified light enters the photodetector for photoelectric demodulation into a clock electrical signal, and the +5V power supply provides a bias voltage to the photodetector through a 1kΩ bias resistor; 3) The clock electrical signal is amplified by the clock signal amplifier and then output through a 20dB coupler; 4) The detector bias voltage is input to the VT terminal of the comparison calculation module through the voltage follower. According to the working principle of the voltage follower, the value of the VT port is the bias voltage of the photodetector; 5) The 20dB coupler couples the clock electrical signal into the detector, detects the voltage value VR corresponding to the amplitude of the electrical signal at this time, and sends this voltage to one end of the subtractor; the amplitude setting voltage module sets the output amplitude reference voltage VS and sends it to the other end of the subtractor. The subtractor output voltage Δ=VS-VR. The first integrator integrates the subtractor output voltage Δ to obtain the output amplitude error cumulative value VDI; 6) After the initial optical power voltage setting module sets the voltage, it inputs the voltage into the VF terminal of the comparison module. The comparison calculation module calculates VF, VT and VDI to obtain the received optical power error value VDO; 7) The second integrator integrates VDO, and the ACC control module adjusts the EDFA pump laser bias current according to the integration result, thereby adjusting the EDFA output optical power. Among them, when there is clock signal transmission in the system and VR≠VS, the received optical power error value VDO≠0V output by the comparison calculation module, that is, the second integrator outputs the received optical power error cumulative value VPI which will gradually increase VDO<0V or gradually decrease VDO>0V, and the ACC control module adjusts the EDFA output optical power size according to the size of VPI until VR=VS, at which time VPI no longer changes and is a stable value, and the working state of the ACC control module no longer changes, that is, the clock output amplitude no longer changes, thereby achieving the function of stable amplitude output. At this time, as long as the maximum linear output amplitude of the clock signal amplifier is greater than the signal output amplitude to be set, according to the operating principle of the device, the clock signal amplifier will always work in the linear region, that is, the device can achieve linear stable amplitude output.

2. The output method of the clock signal optical receiving linear amplitude stabilization output device according to claim 1, characterized in that: The coupler is a 20dB coupler.

3. The output method of the clock signal optical receiving linear amplitude stabilization output device according to claim 1, characterized in that: The comparison and calculation module is provided with a first operational amplifier U1, resistors R1, R2, R3, R4 and Rf, wherein pin 8 of the first operational amplifier U1 is connected to +5V, pin 4 is connected to -5V, resistors R1, R2, and Rf are connected in parallel, and the parallel ends are connected to pin 2 of the operational amplifier U1, pin 1 of the first operational amplifier U1 is connected to the other end of the resistor Rf, resistors R3 and R4 are connected in parallel, and the parallel ends are connected to pin 3 of the first operational amplifier U1, and the other end of R4 is grounded.

4. The output method of the clock signal optical receiving linear amplitude stabilization output device according to claim 1, characterized in that: The resistance value of the resistor R1 in the comparison and calculation module is 470 kΩ, and the resistance values ​​of the resistors Rf, R2, R3, and R4 are all 100 kΩ.

5. The output method of the clock signal optical receiving linear amplitude stabilization output device according to claim 1, characterized in that: The first integrator is provided with a second operational amplifier U2, a resistor R5 and a capacitor C1, wherein pin 8 of the second operational amplifier is connected to +5V, pin 4 is connected to -5V, capacitor C1 is connected in parallel with resistor R5, and the parallel end is connected to pin 2 of the second operational amplifier U4, pin 1 of the second operational amplifier is connected to the other end of capacitor C1, and pin 3 of the second operational amplifier is grounded.

6. The output method of the clock signal optical receiving linear amplitude stabilization output device according to claim 1, characterized in that: The capacitance of C1 in the first integrator is 10 μF, and the resistance of R5 is 100 kΩ.

7. The output method of the clock signal optical receiving linear amplitude stabilization output device according to claim 1, characterized in that: The second integrator is provided with a third operational amplifier U3, a resistor R6 and a capacitor C2, wherein pin 8 of the third operational amplifier is connected to +5V, pin 4 is connected to -5V, capacitor C2 is connected in parallel with R6, and the parallel end is connected to pin 2 of the third operational amplifier U3, pin 1 of the third operational amplifier is connected to the other end of the capacitor C2, and pin 3 of the third operational amplifier is grounded.

8. The output method of the clock signal optical receiving linear amplitude stabilization output device according to claim 1, characterized in that: The capacitance of C2 in the second integrator is 10 μF, and the resistance of R6 is 1 kΩ.

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