Image sensor readout circuit

Abstract

The present invention provides an image sensor readout circuit, comprising a reference voltage input unit for inputting ramp signals and different reference voltages; a comparison unit, wherein one input end inputs pixel data, and the other input end is electrically connected to the reference voltage input unit to input ramp signals and reference voltages, and outputs high-bit readout data according to the signal comparison of the two input ends; a counting unit, which is electrically connected to the output end of the comparison unit to output low-bit readout data; a control logic unit, wherein the input end of the control logic unit is electrically connected to the output end of the comparison unit to obtain high-bit readout data and output it, and the output end of the control logic unit is electrically connected to the reference voltage input unit to control the reference voltage input unit to input different signals. The present invention greatly reduces the time required for readout, is conducive to improving the data output frame rate, and shortens the data readout cycle.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and in particular to an image sensor readout circuit. Background Art

[0002] CMOS image sensors (CIS) have been widely used in imaging fields such as video, surveillance, industrial manufacturing, automobiles, and home appliances. The mainstream CIS readout circuit structure is a readout circuit based on a column-level single-slope analog-to-digital converter (SS-ADC) to ensure that the CIS has sufficient conversion accuracy and speed under reasonable power consumption. The main disadvantage of this structure is that the counting cycle required for conversion is long, and its counting cycle increases exponentially with the ADC resolution. For example, a 12-bit SS-ADC requires 4095 counting cycles. In applications where the resolution and frame rate of CIS are high, the readout circuit structure based on the traditional SS-ADC can no longer meet such requirements.

[0003] Therefore, it is necessary to provide a new image sensor readout circuit to solve the above problems existing in the prior art. Summary of the invention

[0004] The object of the present invention is to provide an image sensor readout circuit, which greatly reduces the time required for readout, is conducive to improving the data output frame rate, and shortens the data readout cycle.

[0005] To achieve the above object, the image sensor readout circuit of the present invention includes:

[0006] A reference voltage input unit, used for inputting ramp signals and different reference voltages;

[0007] A comparison unit, wherein one input terminal is used to input pixel data, and the other input terminal is electrically connected to the reference voltage input unit to input the ramp signal and the reference voltage, and outputs high-bit readout data according to the comparison of the signals at the two input terminals;

[0008] A counting unit, electrically connected to the output terminal of the comparison unit to output low-bit read data;

[0009] A control logic unit, wherein the input end of the control logic unit is electrically connected to the output end of the comparison unit to obtain and output the high-bit read data, and the output end of the control logic unit is electrically connected to the reference voltage input unit to control the reference voltage input unit to input different signals.

[0010] The image sensor readout circuit of the present invention has the beneficial effect that after collecting pixel data, the reference voltage input unit is controlled by the control logic unit to input a ramp signal and different reference voltages, so that the comparison unit performs a successive approximation high-bit conversion on the pixel data based on the ramp signal and the reference voltage to output high-bit readout data, and the counting unit performs a column-level single-slope conversion on the remaining low-bit data to output low-bit readout data. Different conversion methods are used to read out the high-bit data and the low-bit data in the pixel data, respectively. Compared with the traditional column single-slope ADC, the pixel data readout time can be effectively shortened, which is beneficial to improving the frame rate and also beneficial to improving the data output frame rate of the CIS.

[0011] Optionally, the comparison unit includes a first capacitor, a second capacitor and a comparator, one end of the first capacitor is connected to the input end of the pixel data, the other end of the first capacitor is connected to the first input end of the comparator, one end of the second capacitor is connected to the output end of the reference voltage input unit, the other end of the second capacitor is connected to the second input end of the comparator, and the output end of the comparator is respectively connected to the counting unit and the control logic unit.

[0012] Optionally, the comparison unit also includes a first reset switch and a second reset switch, one end of the first reset switch is connected to the first input end, and the other end is connected to a reset end of the comparator; one end of the second reset switch is connected to the second input end, and the other end is connected to the other reset end of the comparator.

[0013] Optionally, the reference voltage input unit includes a reference voltage generating circuit and a combination switch, wherein one end of the reference voltage generating circuit inputs a reference current and the other end is grounded, the control logic module is connected to the combination switch to control the state of the combination switch, and the reference voltage generating circuit includes a plurality of resistors, voltage nodes are connected between adjacent resistors, and the combination switch includes a plurality of switches, each of the voltage nodes is connected to the second capacitor through the switch to input different reference voltages.

[0014] Optionally, the number of the switches is the same as the number of the voltage nodes.

[0015] Optionally, the reference voltage generating circuit includes a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor and a sixth resistor connected in sequence, the voltage nodes include a first node, a second node, a third node, a fourth node and a fifth node, one end of the first resistor inputs the reference current, and the other end is connected to the fifth node and the other end of the second resistor, the other end of the second resistor is connected to the fourth node and one end of the third resistor, the other end of the third resistor is connected to the third node and one end of the fourth resistor, the other end of the fourth resistor is connected to the second node and one end of the fifth resistor, the other end of the fifth resistor is connected to the first node and one end of the sixth resistor, and the other end of the sixth resistor is grounded.

[0016] Optionally, the second resistor, the third resistor, the fourth resistor, the fifth resistor and the sixth resistor are all of the same size.

[0017] Optionally, the number of switches is six, namely a ramp switch, a first switch, a second switch, a third switch, a fourth switch and a fifth switch, one end of the ramp switch is connected to the second capacitor, and the other end is connected to the ramp generator to input the ramp signal, the first node is connected to the second capacitor through the first switch, the second node is connected to the second capacitor through the second switch, the third node is connected to the second capacitor through the third switch, the fourth node is connected to the second capacitor through the fourth switch, and the fifth node is connected to the second capacitor through the fifth switch.

[0018] Optionally, the reference voltage generating circuit further includes a plurality of seventh resistors connected in series in sequence at the other end of the sixth resistor, one end of the last seventh resistor is grounded, and each of the seventh resistors is used to provide a different reference voltage.

[0019] Optionally, the image sensor readout circuit also includes a row selection decoding drive unit, a ramp generator and a timing control unit, the output end of the ramp generator is connected to the second capacitor to input the ramp signal, the output end of the timing control unit is connected to the input end of the ramp generator, and the timing control unit is connected to the input end of the row selection decoding drive unit, and the output end of the row selection decoding drive unit is connected to the pixel unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 A circuit diagram of a readout circuit in the prior art;

[0021] Figure 2 is a timing diagram of a readout circuit in the prior art;

[0022] Figure 3A circuit diagram of an image sensor readout circuit according to an embodiment of the present invention;

[0023] Figure 4 A circuit diagram of a reference voltage generating circuit in an image sensor readout circuit according to an embodiment of the present invention;

[0024] Figure 5 is a timing diagram of the image sensor readout circuit according to an embodiment of the present invention;

[0025] Figure 6 is a circuit diagram of a pixel circuit in a pixel unit according to an embodiment of the present invention;

[0026] Figure 7 For the embodiment of the present invention Figure 6 A timing diagram of the pixel circuit described in;

[0027] Figure 8 FIG. 4 is an overall circuit diagram of an image sensor readout circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0028] In order to make the purpose, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein should be understood by people with general skills in the field to which the present invention belongs. "Including" and similar words used in this article mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0029] In the prior art, the existing readout circuit generally includes a pixel array 101, a comparator 102, a counter 103, a ramp generator 104, a timing control 105, a row selection decoding driver 106 and an output signal processing 107. The pixel array 101 is composed of a plurality of pixel circuits P arranged in an array. The comparator 102 and the counter 103 form an analog-to-digital converter ADC. The pixel array 101 is read out row by row, and the specific order is ROW(0), ROW(1), ..., ROW(k-1), ROW(k). Each column of the pixel array 101 has an output bus, which are PIX_OUT(0), PIX_OUT(1), ...PIX_OUT(n-1), PIX_OUT(n). The PIX_OUT output is connected to the ADC. The comparator 102 compares the pixel output with the ramp signal RAMP, and the comparison result determines the size of the count value of the counter 103. The ADC judges the above-mentioned VRST and VSIG potentials respectively, and converts the VRST-VSIG difference into a digital quantity and outputs it to the system.

[0030] Specifically, the timing diagram is used for explanation. Figure 2 , Figure 2 for Figure 1 The working timing of the readout circuit shown is Figure 2 The Read phase of the timing. After entering the Read phase, the selection signal SEL is pulled "high", and the pixel unit is reset when the receiving signal RX is "high". After that, the receiving signal RX and the reset signal RST_CM change from "high" to "low", EN_CM is the comparator enable control signal, and EN_CM is also "high" to enable all comparators 102 in the ADC to enter the working state. The ADC working process consists of two processes: comparison and counting. First, when the ramp signal RAMP starts to decrease, the counter CNT starts counting until the comparator 103 signal flips from "low" to "high", then CNT stops counting and stores the current count value. To complete the analog-to-digital conversion of the pixel signal, the ADC needs to perform the above operation twice. The ramp signal RAMP will be generated twice as the ADC reference. The first ramp stage (that is, Figure 2 The ADC will determine and store the reset potential VRST, and the counter CNT will count and store the count value CN1 corresponding to the t1 period during the t1 period; the second ramp stage (i.e. Figure 2 The ADC will determine and store the reset potential VSIG, and the counter CNT will count and store the count value CN2 corresponding to the t2 period. Finally, the counter CNT will output the count difference ΔCN=CN2-CN1, which corresponds to the difference between VSIG and VRST.

[0031] In view of the problems existing in the prior art, an embodiment of the present invention provides an image sensor readout circuit, referring to Figure 3 ,include:

[0032] A reference voltage input unit 32, used for inputting ramp signals and different reference voltages;

[0033] A comparison unit 33, one input terminal of which inputs pixel data, and another input terminal of which is electrically connected to the reference voltage input unit 32 to input the ramp signal and the reference voltage, and outputs high-bit readout data according to the comparison of the signals at the two input terminals;

[0034] A counting unit 34, electrically connected to the output end of the comparing unit 33 to output low-bit read data;

[0035] A control logic unit 35, wherein the input end of the control logic unit 35 is electrically connected to the output end of the comparison unit 34 to obtain and output the high-bit read data, and the output end of the control logic unit 35 is electrically connected to the reference voltage input unit 32 to control the reference voltage input unit 32 to input different signals.

[0036] In the present solution, after the pixel data is collected, the reference voltage input unit 32 is controlled by the control logic unit 35 to input a ramp signal and different reference voltages, so that the comparison unit 33 performs a successive approximation of the high-bit conversion of the pixel data based on the ramp signal and the reference voltage to output the high-bit read data, while the counting unit 34 performs a column-level single-slope conversion on the remaining low-bit data to output the low-bit read data. Different conversion methods are used to read out the high-bit data and the low-bit data in the pixel data. Compared with the traditional column single-slope ADC, the pixel data read time can be effectively shortened, which is beneficial to improving the frame rate and also beneficial to improving the data output frame rate of the CIS.

[0037] In some embodiments, the comparison unit 33 includes a first capacitor 331, a second capacitor 332 and a comparator 333, one end of the first capacitor 331 is connected to the input end of the pixel data, the other end of the first capacitor 331 is connected to the first input end of the comparator 333, one end of the second capacitor 332 is connected to the output end of the reference voltage input unit 32, the other end of the second capacitor 332 is connected to the second input end of the comparator 333, and the output end of the comparator 333 is respectively connected to the counting unit 34 and the control logic unit 35.

[0038] In some embodiments, the comparison unit 33 further includes a first reset switch 334 and a second reset switch 335, wherein one end of the first reset switch 334 is connected to the first input end, and the other end is connected to a reset end of the comparator 333; one end of the second reset switch 335 is connected to the second input end, and the other end is connected to the other reset end of the comparator 333. By adding the first reset switch 334 and the second reset switch 335, it is convenient to reset the comparator 333 during the readout process.

[0039] In some embodiments, the reference voltage input unit 32 includes a reference voltage generating circuit 321 and a combination switch 322, one end of the reference voltage generating circuit 321 inputs a reference current IREF and the other end is grounded, the control logic module 35 is connected to the combination switch 322 to control the state of the combination switch 322, and the reference voltage generating circuit 321 includes a plurality of resistors, and voltage nodes are connected between adjacent resistors, and the combination switch 321 includes a plurality of switches, each of the voltage nodes is connected to the second capacitor 332 through the switch to input different reference voltages.

[0040] By inputting a reference current IREF into the reference voltage generating circuit 321, different reference voltages are output through the voltage nodes on the reference voltage generating circuit 321, and the control logic module 35 outputs a switch control signal to control the combination switch 322, so as to control the reference voltage output by the entire reference voltage generating circuit 321, so as to output different reference voltages to the comparator 333.

[0041] In some embodiments, the number of the switches is the same as the number of the voltage nodes, so that the reference voltage outputted by each voltage node is controlled by the switches.

[0042] In some embodiments, the number of resistors in the reference voltage generating circuit 321 is six, the number of voltage nodes is five, and the number of switches in the combination switch 322 is six.

[0043] Exemplary, reference Figure 4The reference voltage generating circuit 321 includes a first resistor 3211, a second resistor 3212, a third resistor 3213, a fourth resistor 3214, a fifth resistor 3215 and a sixth resistor 3216 connected in sequence, the voltage nodes include a first node 323, a second node 324, a third node 325, a fourth node 326 and a fifth node 327, one end of the first resistor 3211 inputs the reference current IREF, and the other end is connected to the fifth node 327 and the other end of the second resistor 3212, the other end of the second resistor 3212 is connected to the fourth node 326 and one end of the third resistor 3213, the other end of the third resistor 3213 is connected to the third node 325 and one end of the fourth resistor 3214, the other end of the fourth resistor 3214 is connected to the second node 324 and one end of the fifth resistor 3215, the other end of the fifth resistor 3215 is connected to the first node 323 and one end of the sixth resistor 3216, and the other end of the sixth resistor 3216 is grounded.

[0044] The reference current IREF flows through the reference voltage generating circuit 321 to generate the first reference voltage VB0, the second reference voltage VB1, the third reference voltage VB2, the fourth reference voltage VB3, and the fifth reference voltage VB4. Since the resistance of the first resistor 3211 is R1, and the other resistors, the second resistor 3212, the third resistor 3213, the fourth resistor 3214, the fifth resistor 3215, and the sixth resistor 3216, are all R, the difference between each adjacent reference voltage from VB0 to VB4 is equal. By setting the size of R1 and R, VB4-VB0=VREF can be made, and VREF is the reference reference voltage range in the successive approximation conversion stage.

[0045] In some embodiments, the second resistor 3212, the third resistor 3213, the fourth resistor 3214, the fifth resistor 3215 and the sixth resistor 3216 are all the same size, so that the differences between adjacent reference voltages output between the first node 323, the second node 324, the third node 325, the fourth node 326 and the fifth node 327 are the same.

[0046] In some other embodiments, the reference voltage generating circuit also includes a plurality of seventh resistors (not shown in the figure) connected in series at the other end of the sixth resistor, and one end of the last seventh resistor is grounded. Each of the seventh resistors is used to provide a different reference voltage so that the entire reference voltage generating circuit can generate different reference voltages as needed to meet different reference voltage usage requirements.

[0047] In some embodiments, the number of the switches is six, namely a ramp switch 3221, a first switch 3222, a second switch 3223, a third switch 3224, a fourth switch 3225 and a fifth switch 3226. One end of the ramp switch 3221 is connected to the second capacitor 332, and the other end is connected to the ramp generator to input the ramp signal. The first node 323 is connected to the second capacitor 332 through the first switch 3222, the second node 324 is connected to the second capacitor 332 through the second switch 3223, the third node 325 is connected to the second capacitor 332 through the third switch 3224, the fourth node 326 is connected to the second capacitor 332 through the fourth switch 3225, and the fifth node 327 is connected to the second capacitor 332 through the fifth switch 3226.

[0048] Among them, the control logic unit 35 outputs the switch control signal KS[5:0] to control the on and off of the ramp switch 3221, the first switch 3222, the second switch 3223, the third switch 3224, the fourth switch 3225 and the fifth switch 3226 according to the value of the output result CMO of the comparator 333, so as to output different reference voltages to the comparator 333.

[0049] In this embodiment, the counting unit 34 is a counter, the first input terminal of the comparator 333 is a positive input terminal IP, the second input terminal is a negative input terminal IN, the first capacitor 331 is denoted as C0, the second capacitor 332 is denoted as C1, C0=C1, the positive input terminal IP and the negative input terminal IN of the comparator 333 are respectively connected to the upper plates of the first capacitor 331 and the second capacitor 332. The lower plate of the first capacitor 331 is connected to the output terminal of the pixel acquisition unit 31, and the lower plate of the second capacitor 332 is respectively connected to the ramp generator, the first node 323, the second node 324, the third node 325, the fourth node 326 and the fifth node 327 through the ramp switch 3221, the first switch 3222, the second switch 3223, the third switch 3224, the fourth switch 3225 and the fifth switch 3226 to input the ramp signal RAMP, the first reference voltage VB0, the second reference voltage VB1, the third reference voltage VB2, the fourth reference voltage VB3 and the fifth reference voltage VB4. The comparator 333 outputs the comparison result CMO to the counter, controls the counter to count the result and finally outputs the data DATA to the system for subsequent data processing.

[0050] refer to Figure 5 , combined with Figure 5The timing sequence is used to illustrate the working process of the image sensor readout circuit in the present solution, taking a 12-bit resolution ADC as an example. The first reset switch 334 is recorded as Sk0, the second reset switch 335 is recorded as Sk1, the input pixel data is recorded as PIX_OUT, the ramp switch 3221, the first switch 3222, the second switch 3223, the third switch 3224, the fourth switch 3225 and the fifth switch 3226 are recorded as Sr, S0, S1, S2, S3 and S4 respectively, and the connection node between the second capacitor 332 and the ramp switch 3221, the first switch 3222, the second switch 3223, the third switch 3224, the fourth switch 3225 and the fifth switch 3226 is recorded as FB.

[0051] At time 0-t0, first, the control signals of Sk0 and Sk1 are set high to turn on the reset switches Sk0 and Sk1, and the comparator 333 is reset. At this time, the switches Sr, S0, S1, S3, and S4 are all turned off, S2 is turned on, and VB2 is connected to the FB point. From t0 to t3 is the successive approximation conversion stage. At time t0 to t1, VB2 is first connected to FB. At this time, the comparator 333 compares VB2 with PIX_OUT. If PIX_OUT is smaller than VB2, the output CMO of the comparator 333 is low potential. At this time, the control logic unit 35 outputs the highest bit DATA

[11] =0, and according to the CMO result, from time t1 to t2, S1 is turned on, and the other switches Sr, S0, S3, and S4 are turned off, so that the reference voltage VB1, which is one level lower than VB2, is connected to FB. If VB1 is still greater than PIX_OUT, the second highest bit DATA

[10] =0. From t2 to t3, S0 is turned on, and other switches Sr, S1, S3, and S4 are turned off, so that the reference voltage VB0, which is one level lower than VB1, is connected to FB. If PIX_OUT>VB0, then from t3 to t4, the reset switches Sk0 and Sk1 are set to high potential to reset the comparator 333, and FB is connected to VB1 (S1 is turned on, and other switches Sr, S0, S3, and S4 are turned off), and the ramp generator input reference is connected to VB1. From t4 to t5, the ramp generator will generate a RAMP signal with a range of VREF / 4 from high to low. Since FB is VB1 at the previous moment, RAMP will change linearly from VB1 to VB0. The counter is enabled and starts counting from time t4. When RAMP is less than PIX_OUT (tp), the CMO output changes from high to low, the counter stops counting, and sends the count value CNp from t4 to tp as the lower 10 bits of data to the system for subsequent data processing. That is, the output of DATA[9:0] is determined by the counter count value.

[0052] The above process is one possibility of the PIX_OUT potential. PIX_OUT may also fall between VB1 and VB2, VB2 and VB3, and VB3 and VB4, but the working principle is the same, that is, from t3 to t4 before the final single-slope A / D conversion, FB will be placed at a reference potential higher than PIX_OUT, and then the ramp signal will be connected from t4 to t5 for quantization of the lower 10 bits, which will not be repeated here.

[0053] Figure 5 The timing process is equivalent to an A / D conversion. Figure 2 The "VR" and "VS" processes of the prior art are two A / D conversions respectively, so Figure 1 The readout circuit operation sequence proposed in the above is equivalent to the "VR" and "VS" processes respectively. Figure 7 Timing process replacement. The traditional pure single slope A / D conversion takes the longest time. Figure 2 "VS" stage, Figure 7 The timing sequence can significantly shorten the time of the “VS” phase in the conventional readout circuit timing sequence.

[0054] Specifically, the time required for each bit conversion of the successive approximation A / D quantization depends on the comparator judgment delay, reference establishment and switch switching speed. Generally, the time required for each bit is about 100ns to 500ns, so the time required to process the upper two bits is 1μs, plus the time required for two resets of 1μs, then the time required for the successive approximation stage conversion is 2μs, and if the counter clock is 200MHz in the single slope A / D conversion stage, the time required for the lower 10 bits to convert is 5.12μs, and the time required for the entire 12-bit ADC conversion is 7.121μs. If the 12 bits are completely converted by the single slope A / D method, it will take 20.48μs (that is, Figure 2 “VS” phase time). Figure 2 If the "VR" stage is replaced with the proposed timing, the conversion time can be shortened accordingly, but the shortening ratio is smaller than that of "VS". The conversion time of the readout circuit proposed in this scheme is at least 13μs shorter than the conversion time of the traditional readout circuit.

[0055] If CIS is in 1080p / 30fps output mode, the traditional readout circuit has a line read cycle of about 30μs, while the readout circuit proposed in this solution has a line read cycle of about 17μs, and the data frame rate of the same frame output can be increased to 52fps. It can be seen that the successive approximation conversion method for high bits can significantly shorten the conversion cycle, and the more bits of successive approximation conversion, the shorter the overall ADC conversion time.

[0056] Exemplarily, the choice is to select 1 to 3 high bits for successive approximation conversion, and the remaining low bits adopt single-slope A / D conversion to effectively shorten the A / D conversion time, that is, the operation time of the multi-segment readout circuit, which is beneficial to improving the CIS frame rate.

[0057] In some embodiments, reference Figure 6 The pixel unit 36 ​​includes a plurality of pixel circuits 361 arranged in an array. The pixel circuit 361 includes a photosensitive diode 3611, a charge transfer tube 3612, a reset tube 3613, a row selection tube 3614 and an amplifier tube 3615. The anode of the photosensitive diode 3611 is grounded, the cathode of the photosensitive diode 3611 is connected to the source of the charge transfer tube 3612, the drain of the charge transfer tube 3612 and the source of the reset tube 3613 are both connected to the gate of the amplifier tube 3615, the drain of the reset tube 3613 and the drain of the amplifier tube 3615 are both connected to the working voltage, the gate of the charge transfer tube 3612 inputs a sending signal TX, the gate of the reset tube 3613 inputs a receiving signal RX, the gate of the row selection tube 3614 inputs a selection signal SEL, the source of the row selection tube 3614 is connected to a current source, and the source of the row selection tube 3614 is connected to the input end of the pixel data.

[0058] Among them, the photosensitive diode 3611 is used for light sensing and generates photoelectrons proportional to the light intensity. The function of the charge transfer tube 3612 is to transfer the photoelectrons in the photosensitive diode 3611. When TX is a high voltage, the charge transfer tube 3612 is turned on, and the photoelectrons in the photosensitive diode 3611 are transferred to the floating node FD. The function of the reset tube 3613 is to reset the floating node FD when RX is a high potential. When SEL is a high potential and the row selection tube 3614 is turned on, the amplifier tube 3615, the row selection tube 3614 and the current source to the ground form a path. At this time, the amplifier tube 3615 is essentially a source follower, following the change in the potential of the floating node FD and finally output by PIX_OUT.

[0059] For example, in order to specifically describe the working process of the pixel circuit 361, the operation timing is described in conjunction with reference to Figure 7, the working process of the pixel circuit 361 is divided into reset (Rst), exposure (Exp), and signal reading (Read). In the Rst stage, TX and RX are "high", the charge transfer tube 3612 and the reset tube 3613 are both turned on, FD is reset and its potential is pulled up to VDD. After that, RX and TX are "low", entering the Exp stage, the photodiode 3611 senses light and accumulates electrons. Entering the Read stage, SEL is "high", RX is first "high" to reset FD, RX is then pulled "low", and TX remains "low". At this time, the amplifier tube 3615 is controlled by the FD potential and outputs the reset potential VRST through PIX_OUT. After that, TX pulls "high" to transfer the electrons on the photodiode 3611 to FD. At this time, the amplifier tube 3615 is controlled by the FD potential and outputs the integral potential VSIG through PIX_OUT. The VRST and VSIG potentials are read by the subsequent image reading circuit and converted into digital quantities, and then subtracted to obtain the digital quantity actually corresponding to the photoelectrons on the photodiode 3611. If the ADC conversion accuracy is 12 bits and the ADC reference voltage range is VREF, the final output is DOUT = (VRST-VSIG) × 2 12 / VREF.

[0060] It should be noted that in this embodiment, the CIS standard four-tube pixel unit circuit structure is used for explanation, but this solution can adopt either a four-tube pixel unit or a pixel unit of other structures. The working process of the pixel units of other structures is similar and will not be repeated here.

[0061] In some embodiments, reference Figure 8 The image sensor readout circuit also includes a row selection decoding driving unit 37, a ramp generator 38 and a timing control unit 39, the output end of the ramp generator 38 is connected to the second capacitor 331 to input the ramp signal, the output end of the timing control unit 39 is connected to the input end of the ramp generator 38, and the timing control unit 39 is connected to the input end of the row selection decoding driving unit 37, and the output end of the row selection decoding driving unit 37 is connected to the pixel unit 39.

[0062] Although the embodiments of the present invention are described in detail above, it is obvious to those skilled in the art that various modifications and variations can be made to these embodiments. However, it should be understood that such modifications and variations are within the scope and spirit of the present invention as described in the claims. Moreover, the present invention described herein may have other embodiments and may be implemented or realized in a variety of ways.

Claims

1. An image sensor readout circuit, characterized in that: include: A reference voltage input unit, used for inputting ramp signals and different reference voltages; A comparison unit, wherein one input terminal inputs pixel data, and the other input terminal is electrically connected to the reference voltage input unit to input the ramp signal and the reference voltage, and outputs high-bit readout data according to the comparison of the signals at the two input terminals; A counting unit, electrically connected to the output terminal of the comparison unit to output low-bit read data; a control logic unit, wherein an input end of the control logic unit is electrically connected to an output end of the comparison unit to obtain and output the high-bit read data, and an output end of the control logic unit is electrically connected to the reference voltage input unit to control the reference voltage input unit to input different signals; The comparison unit includes a first capacitor, a second capacitor and a comparator, one end of the first capacitor is connected to the input end of the pixel data, the other end of the first capacitor is connected to the first input end of the comparator, one end of the second capacitor is connected to the output end of the reference voltage input unit, the other end of the second capacitor is connected to the second input end of the comparator, and the output end of the comparator is connected to the counting unit and the control logic unit respectively; The reference voltage input unit includes a reference voltage generating circuit and a combination switch, one end of the reference voltage generating circuit inputs a reference current and the other end is grounded, the control logic unit is connected to the combination switch to control the state of the combination switch, and the reference voltage generating circuit includes a plurality of resistors, and voltage nodes are connected between adjacent resistors, and the combination switch includes a plurality of switches, each of the voltage nodes is connected to the second capacitor through the switch to input different reference voltages.

2. The image sensor readout circuit according to claim 1, characterized in that: The comparison unit also includes a first reset switch and a second reset switch, wherein one end of the first reset switch is connected to the first input end, and the other end is connected to a reset end of the comparator; one end of the second reset switch is connected to the second input end, and the other end is connected to the other reset end of the comparator.

3. The image sensor readout circuit according to claim 1, characterized in that: The number of the switches is the same as the number of the voltage nodes.

4. The image sensor readout circuit according to claim 1, characterized in that: The reference voltage generating circuit includes a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor and a sixth resistor connected in sequence, the voltage nodes include a first node, a second node, a third node, a fourth node and a fifth node, one end of the first resistor inputs the reference current, and the other end is connected to the fifth node and the other end of the second resistor, the other end of the second resistor is connected to the fourth node and one end of the third resistor, the other end of the third resistor is connected to the third node and one end of the fourth resistor, the other end of the fourth resistor is connected to the second node and one end of the fifth resistor, the other end of the fifth resistor is connected to the first node and one end of the sixth resistor, and the other end of the sixth resistor is grounded.

5. The image sensor readout circuit according to claim 4, characterized in that: The second resistor, the third resistor, the fourth resistor, the fifth resistor and the sixth resistor are all the same in size.

6. The image sensor readout circuit according to claim 4, characterized in that: There are six switches, namely a ramp switch, a first switch, a second switch, a third switch, a fourth switch and a fifth switch. One end of the ramp switch is connected to the second capacitor, and the other end is connected to the ramp generator to input the ramp signal. The first node is connected to the second capacitor through the first switch, the second node is connected to the second capacitor through the second switch, the third node is connected to the second capacitor through the third switch, the fourth node is connected to the second capacitor through the fourth switch, and the fifth node is connected to the second capacitor through the fifth switch.

7. The image sensor readout circuit according to claim 4, characterized in that: The reference voltage generating circuit also includes a plurality of seventh resistors connected in series at the other end of the sixth resistor, one end of the last seventh resistor is grounded, and each of the seventh resistors is used to provide a different reference voltage.

8. The image sensor readout circuit according to claim 1, characterized in that: The image sensor readout circuit also includes a row selection decoding driving unit, a ramp generator and a timing control unit, the output end of the ramp generator is connected to the second capacitor to input the ramp signal, the output end of the timing control unit is connected to the input end of the ramp generator, and the timing control unit is connected to the input end of the row selection decoding driving unit, and the output end of the row selection decoding driving unit is connected to the pixel unit.

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